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rt2x00: Invert scheduled packet_filter check
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2500pci.c
CommitLineData
95ea3627 1/*
811aa9ca 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2500pci
23 Abstract: rt2500pci device specific routines.
24 Supported chipsets: RT2560.
25 */
26
95ea3627
ID		 27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h>
34
35#include "rt2x00.h"
36#include "rt2x00pci.h"
37#include "rt2500pci.h"
38
39/*
40 * Register access.
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
51 */
0e14f6d3 52static u32 rt2500pci_bbp_check(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 53{
54 u32 reg;
55 unsigned int i;
56
57 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
59 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
60 break;
61 udelay(REGISTER_BUSY_DELAY);
62 }
63
64 return reg;
65}
66
0e14f6d3 67static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 68 const unsigned int word, const u8 value)
69{
70 u32 reg;
71
72 /*
73 * Wait until the BBP becomes ready.
74 */
75 reg = rt2500pci_bbp_check(rt2x00dev);
76 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
77 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
78 return;
79 }
80
81 /*
82 * Write the data into the BBP.
83 */
84 reg = 0;
85 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
86 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
87 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
88 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
89
90 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
91}
92
0e14f6d3 93static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 94 const unsigned int word, u8 *value)
95{
96 u32 reg;
97
98 /*
99 * Wait until the BBP becomes ready.
100 */
101 reg = rt2500pci_bbp_check(rt2x00dev);
102 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
103 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
104 return;
105 }
106
107 /*
108 * Write the request into the BBP.
109 */
110 reg = 0;
111 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
112 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
113 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
114
115 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
116
117 /*
118 * Wait until the BBP becomes ready.
119 */
120 reg = rt2500pci_bbp_check(rt2x00dev);
121 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
122 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
123 *value = 0xff;
124 return;
125 }
126
127 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
128}
129
0e14f6d3 130static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 131 const unsigned int word, const u32 value)
132{
133 u32 reg;
134 unsigned int i;
135
136 if (!word)
137 return;
138
139 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
140 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
141 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
142 goto rf_write;
143 udelay(REGISTER_BUSY_DELAY);
144 }
145
146 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
147 return;
148
149rf_write:
150 reg = 0;
151 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
152 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
153 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
154 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
155
156 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
157 rt2x00_rf_write(rt2x00dev, word, value);
158}
159
160static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
161{
162 struct rt2x00_dev *rt2x00dev = eeprom->data;
163 u32 reg;
164
165 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
166
167 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
168 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
169 eeprom->reg_data_clock =
170 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
171 eeprom->reg_chip_select =
172 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
173}
174
175static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
176{
177 struct rt2x00_dev *rt2x00dev = eeprom->data;
178 u32 reg = 0;
179
180 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
181 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
182 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
183 !!eeprom->reg_data_clock);
184 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
185 !!eeprom->reg_chip_select);
186
187 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
188}
189
190#ifdef CONFIG_RT2X00_LIB_DEBUGFS
191#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
192
0e14f6d3 193static void rt2500pci_read_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 194 const unsigned int word, u32 *data)
195{
196 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
197}
198
0e14f6d3 199static void rt2500pci_write_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 200 const unsigned int word, u32 data)
201{
202 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
203}
204
205static const struct rt2x00debug rt2500pci_rt2x00debug = {
206 .owner = THIS_MODULE,
207 .csr = {
208 .read = rt2500pci_read_csr,
209 .write = rt2500pci_write_csr,
210 .word_size = sizeof(u32),
211 .word_count = CSR_REG_SIZE / sizeof(u32),
212 },
213 .eeprom = {
214 .read = rt2x00_eeprom_read,
215 .write = rt2x00_eeprom_write,
216 .word_size = sizeof(u16),
217 .word_count = EEPROM_SIZE / sizeof(u16),
218 },
219 .bbp = {
220 .read = rt2500pci_bbp_read,
221 .write = rt2500pci_bbp_write,
222 .word_size = sizeof(u8),
223 .word_count = BBP_SIZE / sizeof(u8),
224 },
225 .rf = {
226 .read = rt2x00_rf_read,
227 .write = rt2500pci_rf_write,
228 .word_size = sizeof(u32),
229 .word_count = RF_SIZE / sizeof(u32),
230 },
231};
232#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
233
234#ifdef CONFIG_RT2500PCI_RFKILL
235static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
236{
237 u32 reg;
238
239 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
240 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
241}
81873e9c
ID		 242#else
243#define rt2500pci_rfkill_poll NULL
dcf5475b 244#endif /* CONFIG_RT2500PCI_RFKILL */
95ea3627 245
a9450b70
ID		 246#ifdef CONFIG_RT2500PCI_LEDS
247static void rt2500pci_led_brightness(struct led_classdev *led_cdev,
248 enum led_brightness brightness)
249{
250 struct rt2x00_led *led =
251 container_of(led_cdev, struct rt2x00_led, led_dev);
252 unsigned int enabled = brightness != LED_OFF;
253 unsigned int activity =
254 led->rt2x00dev->led_flags & LED_SUPPORT_ACTIVITY;
255 u32 reg;
256
257 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
258
259 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC) {
260 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
261 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled && activity);
262 }
263
264 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
265}
266#else
267#define rt2500pci_led_brightness NULL
268#endif /* CONFIG_RT2500PCI_LEDS */
269
95ea3627
ID		 270/*
271 * Configuration handlers.
272 */
3a643d24
ID		 273static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
274 const unsigned int filter_flags)
275{
276 u32 reg;
277
278 /*
279 * Start configuration steps.
280 * Note that the version error will always be dropped
281 * and broadcast frames will always be accepted since
282 * there is no filter for it at this time.
283 */
284 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
285 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
286 !(filter_flags & FIF_FCSFAIL));
287 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
288 !(filter_flags & FIF_PLCPFAIL));
289 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
290 !(filter_flags & FIF_CONTROL));
291 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
292 !(filter_flags & FIF_PROMISC_IN_BSS));
293 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
294 !(filter_flags & FIF_PROMISC_IN_BSS));
295 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
296 rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
297 !(filter_flags & FIF_ALLMULTI));
298 rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
299 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
300}
301
6bb40dd1
ID		 302static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
303 struct rt2x00_intf *intf,
304 struct rt2x00intf_conf *conf,
305 const unsigned int flags)
95ea3627 306{
181d6902 307 struct data_queue *queue =
5957da4c 308 rt2x00queue_get_queue(rt2x00dev, RT2X00_BCN_QUEUE_BEACON);
6bb40dd1 309 unsigned int bcn_preload;
95ea3627
ID		 310 u32 reg;
311
6bb40dd1 312 if (flags & CONFIG_UPDATE_TYPE) {
6bb40dd1
ID		 313 /*
314 * Enable beacon config
315 */
316 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
317 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
318 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
319 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
320 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
95ea3627 321
6bb40dd1
ID		 322 /*
323 * Enable synchronisation.
324 */
325 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
fd3c91c5 326 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
6bb40dd1 327 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
fd3c91c5 328 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
6bb40dd1
ID		 329 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
330 }
331
332 if (flags & CONFIG_UPDATE_MAC)
333 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
334 conf->mac, sizeof(conf->mac));
335
336 if (flags & CONFIG_UPDATE_BSSID)
337 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
338 conf->bssid, sizeof(conf->bssid));
95ea3627
ID		 339}
340
3a643d24
ID		 341static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
342 struct rt2x00lib_erp *erp)
95ea3627 343{
5c58ee51 344 int preamble_mask;
95ea3627 345 u32 reg;
95ea3627 346
5c58ee51
ID		 347 /*
348 * When short preamble is enabled, we should set bit 0x08
349 */
72810379 350 preamble_mask = erp->short_preamble << 3;
95ea3627
ID		 351
352 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
72810379
ID		 353 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
354 erp->ack_timeout);
355 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
356 erp->ack_consume_time);
95ea3627
ID		 357 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
358
95ea3627 359 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
5c58ee51 360 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble_mask);
95ea3627
ID		 361 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
362 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
363 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
364
365 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
5c58ee51 366 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
95ea3627
ID		 367 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
368 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
369 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
370
371 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
5c58ee51 372 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
95ea3627
ID		 373 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
374 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
375 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
376
377 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
5c58ee51 378 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
95ea3627
ID		 379 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
380 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
381 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
382}
383
384static void rt2500pci_config_phymode(struct rt2x00_dev *rt2x00dev,
5c58ee51 385 const int basic_rate_mask)
95ea3627 386{
5c58ee51 387 rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
95ea3627
ID		 388}
389
390static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
5c58ee51 391 struct rf_channel *rf, const int txpower)
95ea3627 392{
95ea3627
ID		 393 u8 r70;
394
95ea3627
ID		 395 /*
396 * Set TXpower.
397 */
5c58ee51 398 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
95ea3627
ID		 399
400 /*
401 * Switch on tuning bits.
402 * For RT2523 devices we do not need to update the R1 register.
403 */
404 if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
5c58ee51
ID		 405 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
406 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
95ea3627
ID		 407
408 /*
409 * For RT2525 we should first set the channel to half band higher.
410 */
411 if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
412 static const u32 vals[] = {
413 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
414 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
415 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
416 0x00080d2e, 0x00080d3a
417 };
418
5c58ee51
ID		 419 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
420 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
421 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
422 if (rf->rf4)
423 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
95ea3627
ID		 424 }
425
5c58ee51
ID		 426 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
427 rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
428 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
429 if (rf->rf4)
430 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
95ea3627
ID		 431
432 /*
433 * Channel 14 requires the Japan filter bit to be set.
434 */
435 r70 = 0x46;
5c58ee51 436 rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
95ea3627
ID		 437 rt2500pci_bbp_write(rt2x00dev, 70, r70);
438
439 msleep(1);
440
441 /*
442 * Switch off tuning bits.
443 * For RT2523 devices we do not need to update the R1 register.
444 */
445 if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
5c58ee51
ID		 446 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
447 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
95ea3627
ID		 448 }
449
5c58ee51
ID		 450 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
451 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 452
453 /*
454 * Clear false CRC during channel switch.
455 */
5c58ee51 456 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
95ea3627
ID		 457}
458
459static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
460 const int txpower)
461{
462 u32 rf3;
463
464 rt2x00_rf_read(rt2x00dev, 3, &rf3);
465 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
466 rt2500pci_rf_write(rt2x00dev, 3, rf3);
467}
468
469static void rt2500pci_config_antenna(struct rt2x00_dev *rt2x00dev,
addc81bd 470 struct antenna_setup *ant)
95ea3627
ID		 471{
472 u32 reg;
473 u8 r14;
474 u8 r2;
475
a4fe07d9
ID		 476 /*
477 * We should never come here because rt2x00lib is supposed
478 * to catch this and send us the correct antenna explicitely.
479 */
480 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
481 ant->tx == ANTENNA_SW_DIVERSITY);
482
95ea3627
ID		 483 rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
484 rt2500pci_bbp_read(rt2x00dev, 14, &r14);
485 rt2500pci_bbp_read(rt2x00dev, 2, &r2);
486
487 /*
488 * Configure the TX antenna.
489 */
addc81bd 490 switch (ant->tx) {
95ea3627
ID		 491 case ANTENNA_A:
492 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
493 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
494 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
495 break;
496 case ANTENNA_B:
a4fe07d9 497 default:
95ea3627
ID		 498 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
499 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
500 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
501 break;
502 }
503
504 /*
505 * Configure the RX antenna.
506 */
addc81bd 507 switch (ant->rx) {
95ea3627
ID		 508 case ANTENNA_A:
509 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
510 break;
511 case ANTENNA_B:
a4fe07d9 512 default:
95ea3627
ID		 513 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
514 break;
515 }
516
517 /*
518 * RT2525E and RT5222 need to flip TX I/Q
519 */
520 if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
521 rt2x00_rf(&rt2x00dev->chip, RF5222)) {
522 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
523 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
524 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
525
526 /*
527 * RT2525E does not need RX I/Q Flip.
528 */
529 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
530 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
531 } else {
532 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
533 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
534 }
535
536 rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
537 rt2500pci_bbp_write(rt2x00dev, 14, r14);
538 rt2500pci_bbp_write(rt2x00dev, 2, r2);
539}
540
541static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 542 struct rt2x00lib_conf *libconf)
95ea3627
ID		 543{
544 u32 reg;
545
546 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
5c58ee51 547 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
95ea3627
ID		 548 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
549
550 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
5c58ee51
ID		 551 rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
552 rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
95ea3627
ID		 553 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
554
555 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
5c58ee51
ID		 556 rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
557 rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
95ea3627
ID		 558 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
559
560 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
561 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
562 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
563 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
564
565 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
5c58ee51
ID		 566 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
567 libconf->conf->beacon_int * 16);
568 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
569 libconf->conf->beacon_int * 16);
95ea3627
ID		 570 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
571}
572
573static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 574 struct rt2x00lib_conf *libconf,
575 const unsigned int flags)
95ea3627 576{
95ea3627 577 if (flags & CONFIG_UPDATE_PHYMODE)
5c58ee51 578 rt2500pci_config_phymode(rt2x00dev, libconf->basic_rates);
95ea3627 579 if (flags & CONFIG_UPDATE_CHANNEL)
5c58ee51
ID		 580 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
581 libconf->conf->power_level);
95ea3627 582 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
5c58ee51
ID		 583 rt2500pci_config_txpower(rt2x00dev,
584 libconf->conf->power_level);
95ea3627 585 if (flags & CONFIG_UPDATE_ANTENNA)
addc81bd 586 rt2500pci_config_antenna(rt2x00dev, &libconf->ant);
95ea3627 587 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
5c58ee51 588 rt2500pci_config_duration(rt2x00dev, libconf);
95ea3627
ID		 589}
590
95ea3627
ID		 591/*
592 * Link tuning
593 */
ebcf26da
ID		 594static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
595 struct link_qual *qual)
95ea3627
ID		 596{
597 u32 reg;
598
599 /*
600 * Update FCS error count from register.
601 */
602 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
ebcf26da 603 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
95ea3627
ID		 604
605 /*
606 * Update False CCA count from register.
607 */
608 rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
ebcf26da 609 qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
95ea3627
ID		 610}
611
612static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
613{
614 rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
615 rt2x00dev->link.vgc_level = 0x48;
616}
617
618static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
619{
620 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
621 u8 r17;
622
623 /*
624 * To prevent collisions with MAC ASIC on chipsets
625 * up to version C the link tuning should halt after 20
6bb40dd1 626 * seconds while being associated.
95ea3627 627 */
755a957d 628 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
6bb40dd1 629 rt2x00dev->intf_associated &&
95ea3627
ID		 630 rt2x00dev->link.count > 20)
631 return;
632
633 rt2500pci_bbp_read(rt2x00dev, 17, &r17);
634
635 /*
636 * Chipset versions C and lower should directly continue
6bb40dd1
ID		 637 * to the dynamic CCA tuning. Chipset version D and higher
638 * should go straight to dynamic CCA tuning when they
639 * are not associated.
95ea3627 640 */
6bb40dd1
ID		 641 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D ||
642 !rt2x00dev->intf_associated)
95ea3627
ID		 643 goto dynamic_cca_tune;
644
645 /*
646 * A too low RSSI will cause too much false CCA which will
647 * then corrupt the R17 tuning. To remidy this the tuning should
648 * be stopped (While making sure the R17 value will not exceed limits)
649 */
650 if (rssi < -80 && rt2x00dev->link.count > 20) {
651 if (r17 >= 0x41) {
652 r17 = rt2x00dev->link.vgc_level;
653 rt2500pci_bbp_write(rt2x00dev, 17, r17);
654 }
655 return;
656 }
657
658 /*
659 * Special big-R17 for short distance
660 */
661 if (rssi >= -58) {
662 if (r17 != 0x50)
663 rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
664 return;
665 }
666
667 /*
668 * Special mid-R17 for middle distance
669 */
670 if (rssi >= -74) {
671 if (r17 != 0x41)
672 rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
673 return;
674 }
675
676 /*
677 * Leave short or middle distance condition, restore r17
678 * to the dynamic tuning range.
679 */
680 if (r17 >= 0x41) {
681 rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
682 return;
683 }
684
685dynamic_cca_tune:
686
687 /*
688 * R17 is inside the dynamic tuning range,
689 * start tuning the link based on the false cca counter.
690 */
ebcf26da 691 if (rt2x00dev->link.qual.false_cca > 512 && r17 < 0x40) {
95ea3627
ID		 692 rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
693 rt2x00dev->link.vgc_level = r17;
ebcf26da 694 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > 0x32) {
95ea3627
ID		 695 rt2500pci_bbp_write(rt2x00dev, 17, --r17);
696 rt2x00dev->link.vgc_level = r17;
697 }
698}
699
700/*
701 * Initialization functions.
702 */
837e7f24 703static void rt2500pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
181d6902 704 struct queue_entry *entry)
95ea3627 705{
181d6902 706 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
95ea3627
ID		 707 u32 word;
708
181d6902 709 rt2x00_desc_read(priv_rx->desc, 1, &word);
30b3a23c 710 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma);
181d6902 711 rt2x00_desc_write(priv_rx->desc, 1, word);
95ea3627 712
181d6902 713 rt2x00_desc_read(priv_rx->desc, 0, &word);
837e7f24 714 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
181d6902 715 rt2x00_desc_write(priv_rx->desc, 0, word);
95ea3627
ID		 716}
717
837e7f24 718static void rt2500pci_init_txentry(struct rt2x00_dev *rt2x00dev,
181d6902 719 struct queue_entry *entry)
95ea3627 720{
181d6902 721 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
95ea3627
ID		 722 u32 word;
723
181d6902 724 rt2x00_desc_read(priv_tx->desc, 1, &word);
30b3a23c 725 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->data_dma);
181d6902 726 rt2x00_desc_write(priv_tx->desc, 1, word);
95ea3627 727
181d6902 728 rt2x00_desc_read(priv_tx->desc, 0, &word);
837e7f24
ID		 729 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
730 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
181d6902 731 rt2x00_desc_write(priv_tx->desc, 0, word);
95ea3627
ID		 732}
733
181d6902 734static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 735{
181d6902
ID		 736 struct queue_entry_priv_pci_rx *priv_rx;
737 struct queue_entry_priv_pci_tx *priv_tx;
95ea3627
ID		 738 u32 reg;
739
95ea3627
ID		 740 /*
741 * Initialize registers.
742 */
743 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
181d6902
ID		 744 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
745 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
746 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
747 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
95ea3627
ID		 748 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
749
181d6902 750 priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 751 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
30b3a23c
ID		 752 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
753 priv_tx->desc_dma);
95ea3627
ID		 754 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
755
181d6902 756 priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 757 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
30b3a23c
ID		 758 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
759 priv_tx->desc_dma);
95ea3627
ID		 760 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
761
181d6902 762 priv_tx = rt2x00dev->bcn[1].entries[0].priv_data;
95ea3627 763 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
30b3a23c
ID		 764 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
765 priv_tx->desc_dma);
95ea3627
ID		 766 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
767
181d6902 768 priv_tx = rt2x00dev->bcn[0].entries[0].priv_data;
95ea3627 769 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
30b3a23c
ID		 770 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
771 priv_tx->desc_dma);
95ea3627
ID		 772 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
773
774 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
775 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
181d6902 776 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
95ea3627
ID		 777 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
778
181d6902 779 priv_rx = rt2x00dev->rx->entries[0].priv_data;
95ea3627 780 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
dac37d72 781 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, priv_rx->desc_dma);
95ea3627
ID		 782 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
783
784 return 0;
785}
786
787static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
788{
789 u32 reg;
790
791 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
792 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
793 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
794 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
795
796 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
797 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
798 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
799 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
800 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
801
802 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
803 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
804 rt2x00dev->rx->data_size / 128);
805 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
806
807 /*
808 * Always use CWmin and CWmax set in descriptor.
809 */
810 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
811 rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
812 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
813
a9450b70
ID		 814 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
815 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
816 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
817 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
818
95ea3627
ID		 819 rt2x00pci_register_write(rt2x00dev, CNT3, 0);
820
821 rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
822 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
823 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
824 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
825 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
826 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
827 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
828 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
829 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
830 rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
831
832 rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
833 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
834 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
835 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
836 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
837 rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
838
839 rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
840 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
841 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
842 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
843 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
844 rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
845
846 rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
847 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
848 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
849 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
850 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
851 rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
852
853 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
854 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
855 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
856 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
857 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
858 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
859 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
860 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
861 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
862 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
863
864 rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
865 rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
866 rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
867 rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
868 rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
869 rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
870 rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
871 rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
872 rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
873
874 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
875
876 rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
877 rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
878
879 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
880 return -EBUSY;
881
882 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
883 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
884
885 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
886 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
887 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
888
889 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
890 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
891 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
892 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
893 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
894 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
895 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
896 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
897
898 rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
899
900 rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
901
902 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
903 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
904 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
905 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
906 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
907
908 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
909 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
910 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
911 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
912
913 /*
914 * We must clear the FCS and FIFO error count.
915 * These registers are cleared on read,
916 * so we may pass a useless variable to store the value.
917 */
918 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
919 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
920
921 return 0;
922}
923
924static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
925{
926 unsigned int i;
927 u16 eeprom;
928 u8 reg_id;
929 u8 value;
930
931 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
932 rt2500pci_bbp_read(rt2x00dev, 0, &value);
933 if ((value != 0xff) && (value != 0x00))
934 goto continue_csr_init;
935 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
936 udelay(REGISTER_BUSY_DELAY);
937 }
938
939 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
940 return -EACCES;
941
942continue_csr_init:
943 rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
944 rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
945 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
946 rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
947 rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
948 rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
949 rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
950 rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
951 rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
952 rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
953 rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
954 rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
955 rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
956 rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
957 rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
958 rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
959 rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
960 rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
961 rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
962 rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
963 rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
964 rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
965 rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
966 rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
967 rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
968 rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
969 rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
970 rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
971 rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
972 rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
973
95ea3627
ID		 974 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
975 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
976
977 if (eeprom != 0xffff && eeprom != 0x0000) {
978 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
979 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 980 rt2500pci_bbp_write(rt2x00dev, reg_id, value);
981 }
982 }
95ea3627
ID		 983
984 return 0;
985}
986
987/*
988 * Device state switch handlers.
989 */
990static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
991 enum dev_state state)
992{
993 u32 reg;
994
995 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
996 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
997 state == STATE_RADIO_RX_OFF);
998 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
999}
1000
1001static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1002 enum dev_state state)
1003{
1004 int mask = (state == STATE_RADIO_IRQ_OFF);
1005 u32 reg;
1006
1007 /*
1008 * When interrupts are being enabled, the interrupt registers
1009 * should clear the register to assure a clean state.
1010 */
1011 if (state == STATE_RADIO_IRQ_ON) {
1012 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1013 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1014 }
1015
1016 /*
1017 * Only toggle the interrupts bits we are going to use.
1018 * Non-checked interrupt bits are disabled by default.
1019 */
1020 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1021 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1022 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1023 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1024 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1025 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1026 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1027}
1028
1029static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1030{
1031 /*
1032 * Initialize all registers.
1033 */
181d6902 1034 if (rt2500pci_init_queues(rt2x00dev) ||
95ea3627
ID		 1035 rt2500pci_init_registers(rt2x00dev) ||
1036 rt2500pci_init_bbp(rt2x00dev)) {
1037 ERROR(rt2x00dev, "Register initialization failed.\n");
1038 return -EIO;
1039 }
1040
1041 /*
1042 * Enable interrupts.
1043 */
1044 rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1045
95ea3627
ID		 1046 return 0;
1047}
1048
1049static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1050{
1051 u32 reg;
1052
95ea3627
ID		 1053 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1054
1055 /*
1056 * Disable synchronisation.
1057 */
1058 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1059
1060 /*
1061 * Cancel RX and TX.
1062 */
1063 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1064 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1065 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1066
1067 /*
1068 * Disable interrupts.
1069 */
1070 rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1071}
1072
1073static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1074 enum dev_state state)
1075{
1076 u32 reg;
1077 unsigned int i;
1078 char put_to_sleep;
1079 char bbp_state;
1080 char rf_state;
1081
1082 put_to_sleep = (state != STATE_AWAKE);
1083
1084 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1085 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1086 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1087 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1088 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1089 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1090
1091 /*
1092 * Device is not guaranteed to be in the requested state yet.
1093 * We must wait until the register indicates that the
1094 * device has entered the correct state.
1095 */
1096 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1097 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1098 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1099 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1100 if (bbp_state == state && rf_state == state)
1101 return 0;
1102 msleep(10);
1103 }
1104
1105 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1106 "current device state: bbp %d and rf %d.\n",
1107 state, bbp_state, rf_state);
1108
1109 return -EBUSY;
1110}
1111
1112static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1113 enum dev_state state)
1114{
1115 int retval = 0;
1116
1117 switch (state) {
1118 case STATE_RADIO_ON:
1119 retval = rt2500pci_enable_radio(rt2x00dev);
1120 break;
1121 case STATE_RADIO_OFF:
1122 rt2500pci_disable_radio(rt2x00dev);
1123 break;
1124 case STATE_RADIO_RX_ON:
61667d8d
ID		 1125 case STATE_RADIO_RX_ON_LINK:
1126 rt2500pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1127 break;
95ea3627 1128 case STATE_RADIO_RX_OFF:
61667d8d
ID		 1129 case STATE_RADIO_RX_OFF_LINK:
1130 rt2500pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
95ea3627
ID		 1131 break;
1132 case STATE_DEEP_SLEEP:
1133 case STATE_SLEEP:
1134 case STATE_STANDBY:
1135 case STATE_AWAKE:
1136 retval = rt2500pci_set_state(rt2x00dev, state);
1137 break;
1138 default:
1139 retval = -ENOTSUPP;
1140 break;
1141 }
1142
1143 return retval;
1144}
1145
1146/*
1147 * TX descriptor initialization
1148 */
1149static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 1150 struct sk_buff *skb,
181d6902 1151 struct txentry_desc *txdesc,
95ea3627
ID		 1152 struct ieee80211_tx_control *control)
1153{
181d6902 1154 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
dd3193e1 1155 __le32 *txd = skbdesc->desc;
95ea3627
ID		 1156 u32 word;
1157
1158 /*
1159 * Start writing the descriptor words.
1160 */
1161 rt2x00_desc_read(txd, 2, &word);
1162 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
181d6902
ID		 1163 rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
1164 rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
1165 rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
95ea3627
ID		 1166 rt2x00_desc_write(txd, 2, word);
1167
1168 rt2x00_desc_read(txd, 3, &word);
181d6902
ID		 1169 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1170 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1171 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low);
1172 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1173 rt2x00_desc_write(txd, 3, word);
1174
1175 rt2x00_desc_read(txd, 10, &word);
1176 rt2x00_set_field32(&word, TXD_W10_RTS,
181d6902 1177 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
95ea3627
ID		 1178 rt2x00_desc_write(txd, 10, word);
1179
1180 rt2x00_desc_read(txd, 0, &word);
1181 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1182 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1183 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1184 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1185 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1186 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1187 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1188 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1189 rt2x00_set_field32(&word, TXD_W0_OFDM,
181d6902 1190 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
95ea3627 1191 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
181d6902 1192 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627
ID		 1193 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1194 !!(control->flags &
1195 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
dd3193e1 1196 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
95ea3627
ID		 1197 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1198 rt2x00_desc_write(txd, 0, word);
1199}
1200
1201/*
1202 * TX data initialization
1203 */
1204static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
5957da4c 1205 const unsigned int queue)
95ea3627
ID		 1206{
1207 u32 reg;
1208
5957da4c 1209 if (queue == RT2X00_BCN_QUEUE_BEACON) {
95ea3627
ID		 1210 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1211 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
8af244cc
ID		 1212 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1213 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
95ea3627
ID		 1214 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1215 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1216 }
1217 return;
1218 }
1219
1220 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
ddc827f9
ID		 1221 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO,
1222 (queue == IEEE80211_TX_QUEUE_DATA0));
1223 rt2x00_set_field32(&reg, TXCSR0_KICK_TX,
1224 (queue == IEEE80211_TX_QUEUE_DATA1));
1225 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM,
5957da4c 1226 (queue == RT2X00_BCN_QUEUE_ATIM));
95ea3627
ID		 1227 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1228}
1229
1230/*
1231 * RX control handlers
1232 */
181d6902
ID		 1233static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1234 struct rxdone_entry_desc *rxdesc)
95ea3627 1235{
181d6902 1236 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
95ea3627
ID		 1237 u32 word0;
1238 u32 word2;
1239
181d6902
ID		 1240 rt2x00_desc_read(priv_rx->desc, 0, &word0);
1241 rt2x00_desc_read(priv_rx->desc, 2, &word2);
95ea3627 1242
181d6902 1243 rxdesc->flags = 0;
4150c572 1244 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1245 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
4150c572 1246 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
181d6902
ID		 1247 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1248
89993890
ID		 1249 /*
1250 * Obtain the status about this packet.
1251 * When frame was received with an OFDM bitrate,
1252 * the signal is the PLCP value. If it was received with
1253 * a CCK bitrate the signal is the rate in 100kbit/s.
1254 */
181d6902
ID		 1255 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1256 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1257 entry->queue->rt2x00dev->rssi_offset;
181d6902 1258 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02
ID		 1259
1260 rxdesc->dev_flags = 0;
1261 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1262 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1263 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1264 rxdesc->dev_flags |= RXDONE_MY_BSS;
95ea3627
ID		 1265}
1266
1267/*
1268 * Interrupt functions.
1269 */
181d6902
ID		 1270static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1271 const enum ieee80211_tx_queue queue_idx)
95ea3627 1272{
181d6902
ID		 1273 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1274 struct queue_entry_priv_pci_tx *priv_tx;
1275 struct queue_entry *entry;
1276 struct txdone_entry_desc txdesc;
95ea3627 1277 u32 word;
95ea3627 1278
181d6902
ID		 1279 while (!rt2x00queue_empty(queue)) {
1280 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1281 priv_tx = entry->priv_data;
1282 rt2x00_desc_read(priv_tx->desc, 0, &word);
95ea3627
ID		 1283
1284 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1285 !rt2x00_get_field32(word, TXD_W0_VALID))
1286 break;
1287
1288 /*
1289 * Obtain the status about this packet.
1290 */
181d6902
ID		 1291 txdesc.status = rt2x00_get_field32(word, TXD_W0_RESULT);
1292 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
95ea3627 1293
181d6902 1294 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
95ea3627 1295 }
95ea3627
ID		 1296}
1297
1298static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1299{
1300 struct rt2x00_dev *rt2x00dev = dev_instance;
1301 u32 reg;
1302
1303 /*
1304 * Get the interrupt sources & saved to local variable.
1305 * Write register value back to clear pending interrupts.
1306 */
1307 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1308 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1309
1310 if (!reg)
1311 return IRQ_NONE;
1312
1313 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1314 return IRQ_HANDLED;
1315
1316 /*
1317 * Handle interrupts, walk through all bits
1318 * and run the tasks, the bits are checked in order of
1319 * priority.
1320 */
1321
1322 /*
1323 * 1 - Beacon timer expired interrupt.
1324 */
1325 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1326 rt2x00lib_beacondone(rt2x00dev);
1327
1328 /*
1329 * 2 - Rx ring done interrupt.
1330 */
1331 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1332 rt2x00pci_rxdone(rt2x00dev);
1333
1334 /*
1335 * 3 - Atim ring transmit done interrupt.
1336 */
1337 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
5957da4c 1338 rt2500pci_txdone(rt2x00dev, RT2X00_BCN_QUEUE_ATIM);
95ea3627
ID		 1339
1340 /*
1341 * 4 - Priority ring transmit done interrupt.
1342 */
1343 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1344 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1345
1346 /*
1347 * 5 - Tx ring transmit done interrupt.
1348 */
1349 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1350 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1351
1352 return IRQ_HANDLED;
1353}
1354
1355/*
1356 * Device probe functions.
1357 */
1358static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1359{
1360 struct eeprom_93cx6 eeprom;
1361 u32 reg;
1362 u16 word;
1363 u8 *mac;
1364
1365 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1366
1367 eeprom.data = rt2x00dev;
1368 eeprom.register_read = rt2500pci_eepromregister_read;
1369 eeprom.register_write = rt2500pci_eepromregister_write;
1370 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1371 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1372 eeprom.reg_data_in = 0;
1373 eeprom.reg_data_out = 0;
1374 eeprom.reg_data_clock = 0;
1375 eeprom.reg_chip_select = 0;
1376
1377 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1378 EEPROM_SIZE / sizeof(u16));
1379
1380 /*
1381 * Start validation of the data that has been read.
1382 */
1383 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1384 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1385 DECLARE_MAC_BUF(macbuf);
1386
95ea3627 1387 random_ether_addr(mac);
0795af57
JP		 1388 EEPROM(rt2x00dev, "MAC: %s\n",
1389 print_mac(macbuf, mac));
95ea3627
ID		 1390 }
1391
1392 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1393 if (word == 0xffff) {
1394 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1395 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1396 ANTENNA_SW_DIVERSITY);
1397 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1398 ANTENNA_SW_DIVERSITY);
1399 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1400 LED_MODE_DEFAULT);
95ea3627
ID		 1401 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1402 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1403 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1404 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1405 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1406 }
1407
1408 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1409 if (word == 0xffff) {
1410 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1411 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1412 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1413 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1414 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1415 }
1416
1417 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1418 if (word == 0xffff) {
1419 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1420 DEFAULT_RSSI_OFFSET);
1421 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1422 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1423 }
1424
1425 return 0;
1426}
1427
1428static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1429{
1430 u32 reg;
1431 u16 value;
1432 u16 eeprom;
1433
1434 /*
1435 * Read EEPROM word for configuration.
1436 */
1437 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1438
1439 /*
1440 * Identify RF chipset.
1441 */
1442 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1443 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1444 rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
1445
1446 if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1447 !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1448 !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1449 !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1450 !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1451 !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1452 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1453 return -ENODEV;
1454 }
1455
1456 /*
1457 * Identify default antenna configuration.
1458 */
addc81bd 1459 rt2x00dev->default_ant.tx =
95ea3627 1460 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1461 rt2x00dev->default_ant.rx =
95ea3627
ID		 1462 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1463
1464 /*
1465 * Store led mode, for correct led behaviour.
1466 */
a9450b70
ID		 1467#ifdef CONFIG_RT2500PCI_LEDS
1468 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1469
1470 switch (value) {
1471 case LED_MODE_ASUS:
1472 case LED_MODE_ALPHA:
1473 case LED_MODE_DEFAULT:
1474 rt2x00dev->led_flags = LED_SUPPORT_RADIO;
1475 break;
1476 case LED_MODE_TXRX_ACTIVITY:
1477 rt2x00dev->led_flags =
1478 LED_SUPPORT_RADIO | LED_SUPPORT_ACTIVITY;
1479 break;
1480 case LED_MODE_SIGNAL_STRENGTH:
1481 rt2x00dev->led_flags = LED_SUPPORT_RADIO;
1482 break;
1483 }
1484#endif /* CONFIG_RT2500PCI_LEDS */
95ea3627
ID		 1485
1486 /*
1487 * Detect if this device has an hardware controlled radio.
1488 */
81873e9c 1489#ifdef CONFIG_RT2500PCI_RFKILL
95ea3627 1490 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 1491 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
81873e9c 1492#endif /* CONFIG_RT2500PCI_RFKILL */
95ea3627
ID		 1493
1494 /*
1495 * Check if the BBP tuning should be enabled.
1496 */
1497 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1498
1499 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1500 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1501
1502 /*
1503 * Read the RSSI <-> dBm offset information.
1504 */
1505 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1506 rt2x00dev->rssi_offset =
1507 rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1508
1509 return 0;
1510}
1511
1512/*
1513 * RF value list for RF2522
1514 * Supports: 2.4 GHz
1515 */
1516static const struct rf_channel rf_vals_bg_2522[] = {
1517 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
1518 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
1519 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
1520 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
1521 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
1522 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
1523 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
1524 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
1525 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
1526 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1527 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1528 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1529 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1530 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1531};
1532
1533/*
1534 * RF value list for RF2523
1535 * Supports: 2.4 GHz
1536 */
1537static const struct rf_channel rf_vals_bg_2523[] = {
1538 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1539 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1540 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1541 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1542 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1543 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1544 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1545 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1546 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1547 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1548 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1549 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1550 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1551 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1552};
1553
1554/*
1555 * RF value list for RF2524
1556 * Supports: 2.4 GHz
1557 */
1558static const struct rf_channel rf_vals_bg_2524[] = {
1559 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1560 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1561 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1562 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1563 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1564 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1565 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1566 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1567 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1568 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1569 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1570 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1571 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1572 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1573};
1574
1575/*
1576 * RF value list for RF2525
1577 * Supports: 2.4 GHz
1578 */
1579static const struct rf_channel rf_vals_bg_2525[] = {
1580 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1581 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1582 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1583 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1584 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1585 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1586 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1587 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1588 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1589 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1590 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1591 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1592 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1593 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1594};
1595
1596/*
1597 * RF value list for RF2525e
1598 * Supports: 2.4 GHz
1599 */
1600static const struct rf_channel rf_vals_bg_2525e[] = {
1601 { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1602 { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1603 { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1604 { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1605 { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1606 { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1607 { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1608 { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1609 { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1610 { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1611 { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1612 { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1613 { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1614 { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1615};
1616
1617/*
1618 * RF value list for RF5222
1619 * Supports: 2.4 GHz & 5.2 GHz
1620 */
1621static const struct rf_channel rf_vals_5222[] = {
1622 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1623 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1624 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1625 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1626 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1627 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1628 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1629 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1630 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1631 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1632 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1633 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1634 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1635 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1636
1637 /* 802.11 UNI / HyperLan 2 */
1638 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1639 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1640 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1641 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1642 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1643 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1644 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1645 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1646
1647 /* 802.11 HyperLan 2 */
1648 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1649 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1650 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1651 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1652 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1653 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1654 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1655 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1656 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1657 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1658
1659 /* 802.11 UNII */
1660 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1661 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1662 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1663 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1664 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1665};
1666
1667static void rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1668{
1669 struct hw_mode_spec *spec = &rt2x00dev->spec;
1670 u8 *txpower;
1671 unsigned int i;
1672
1673 /*
1674 * Initialize all hw fields.
1675 */
4150c572 1676 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
95ea3627
ID		 1677 rt2x00dev->hw->extra_tx_headroom = 0;
1678 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1679 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1680 rt2x00dev->hw->queues = 2;
1681
1682 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1683 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1684 rt2x00_eeprom_addr(rt2x00dev,
1685 EEPROM_MAC_ADDR_0));
1686
1687 /*
1688 * Convert tx_power array in eeprom.
1689 */
1690 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1691 for (i = 0; i < 14; i++)
1692 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1693
1694 /*
1695 * Initialize hw_mode information.
1696 */
31562e80
ID		 1697 spec->supported_bands = SUPPORT_BAND_2GHZ;
1698 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627
ID		 1699 spec->tx_power_a = NULL;
1700 spec->tx_power_bg = txpower;
1701 spec->tx_power_default = DEFAULT_TXPOWER;
1702
1703 if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1704 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1705 spec->channels = rf_vals_bg_2522;
1706 } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1707 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1708 spec->channels = rf_vals_bg_2523;
1709 } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1710 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1711 spec->channels = rf_vals_bg_2524;
1712 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1713 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1714 spec->channels = rf_vals_bg_2525;
1715 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1716 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1717 spec->channels = rf_vals_bg_2525e;
1718 } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
31562e80 1719 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 1720 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1721 spec->channels = rf_vals_5222;
95ea3627
ID		 1722 }
1723}
1724
1725static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1726{
1727 int retval;
1728
1729 /*
1730 * Allocate eeprom data.
1731 */
1732 retval = rt2500pci_validate_eeprom(rt2x00dev);
1733 if (retval)
1734 return retval;
1735
1736 retval = rt2500pci_init_eeprom(rt2x00dev);
1737 if (retval)
1738 return retval;
1739
1740 /*
1741 * Initialize hw specifications.
1742 */
1743 rt2500pci_probe_hw_mode(rt2x00dev);
1744
1745 /*
181d6902 1746 * This device requires the atim queue
95ea3627 1747 */
181d6902 1748 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
95ea3627
ID		 1749
1750 /*
1751 * Set the rssi offset.
1752 */
1753 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1754
1755 return 0;
1756}
1757
1758/*
1759 * IEEE80211 stack callback functions.
1760 */
1761static int rt2500pci_set_retry_limit(struct ieee80211_hw *hw,
1762 u32 short_retry, u32 long_retry)
1763{
1764 struct rt2x00_dev *rt2x00dev = hw->priv;
1765 u32 reg;
1766
1767 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1768 rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1769 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1770 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1771
1772 return 0;
1773}
1774
1775static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1776{
1777 struct rt2x00_dev *rt2x00dev = hw->priv;
1778 u64 tsf;
1779 u32 reg;
1780
1781 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1782 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1783 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1784 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1785
1786 return tsf;
1787}
1788
5957da4c
ID		 1789static int rt2500pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1790 struct ieee80211_tx_control *control)
1791{
1792 struct rt2x00_dev *rt2x00dev = hw->priv;
1793 struct rt2x00_intf *intf = vif_to_intf(control->vif);
1794 struct queue_entry_priv_pci_tx *priv_tx;
1795 struct skb_frame_desc *skbdesc;
8af244cc 1796 u32 reg;
5957da4c
ID		 1797
1798 if (unlikely(!intf->beacon))
1799 return -ENOBUFS;
1800
1801 priv_tx = intf->beacon->priv_data;
1802
1803 /*
1804 * Fill in skb descriptor
1805 */
1806 skbdesc = get_skb_frame_desc(skb);
1807 memset(skbdesc, 0, sizeof(*skbdesc));
baf26a7e 1808 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
5957da4c
ID		 1809 skbdesc->data = skb->data;
1810 skbdesc->data_len = skb->len;
1811 skbdesc->desc = priv_tx->desc;
1812 skbdesc->desc_len = intf->beacon->queue->desc_size;
1813 skbdesc->entry = intf->beacon;
1814
8af244cc
ID		 1815 /*
1816 * Disable beaconing while we are reloading the beacon data,
1817 * otherwise we might be sending out invalid data.
1818 */
1819 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1820 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1821 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1822 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1823 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1824
5957da4c
ID		 1825 /*
1826 * mac80211 doesn't provide the control->queue variable
1827 * for beacons. Set our own queue identification so
1828 * it can be used during descriptor initialization.
1829 */
1830 control->queue = RT2X00_BCN_QUEUE_BEACON;
1831 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
1832
1833 /*
1834 * Enable beacon generation.
1835 * Write entire beacon with descriptor to register,
1836 * and kick the beacon generator.
1837 */
1838 memcpy(priv_tx->data, skb->data, skb->len);
1839 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);
1840
1841 return 0;
1842}
1843
95ea3627
ID		 1844static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1845{
1846 struct rt2x00_dev *rt2x00dev = hw->priv;
1847 u32 reg;
1848
1849 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1850 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1851}
1852
1853static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1854 .tx = rt2x00mac_tx,
4150c572
JB		 1855 .start = rt2x00mac_start,
1856 .stop = rt2x00mac_stop,
95ea3627
ID		 1857 .add_interface = rt2x00mac_add_interface,
1858 .remove_interface = rt2x00mac_remove_interface,
1859 .config = rt2x00mac_config,
1860 .config_interface = rt2x00mac_config_interface,
3a643d24 1861 .configure_filter = rt2x00mac_configure_filter,
95ea3627
ID		 1862 .get_stats = rt2x00mac_get_stats,
1863 .set_retry_limit = rt2500pci_set_retry_limit,
471b3efd 1864 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627
ID		 1865 .conf_tx = rt2x00mac_conf_tx,
1866 .get_tx_stats = rt2x00mac_get_tx_stats,
1867 .get_tsf = rt2500pci_get_tsf,
5957da4c 1868 .beacon_update = rt2500pci_beacon_update,
95ea3627
ID		 1869 .tx_last_beacon = rt2500pci_tx_last_beacon,
1870};
1871
1872static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1873 .irq_handler = rt2500pci_interrupt,
1874 .probe_hw = rt2500pci_probe_hw,
1875 .initialize = rt2x00pci_initialize,
1876 .uninitialize = rt2x00pci_uninitialize,
837e7f24
ID		 1877 .init_rxentry = rt2500pci_init_rxentry,
1878 .init_txentry = rt2500pci_init_txentry,
95ea3627 1879 .set_device_state = rt2500pci_set_device_state,
95ea3627 1880 .rfkill_poll = rt2500pci_rfkill_poll,
95ea3627
ID		 1881 .link_stats = rt2500pci_link_stats,
1882 .reset_tuner = rt2500pci_reset_tuner,
1883 .link_tuner = rt2500pci_link_tuner,
a9450b70 1884 .led_brightness = rt2500pci_led_brightness,
95ea3627
ID		 1885 .write_tx_desc = rt2500pci_write_tx_desc,
1886 .write_tx_data = rt2x00pci_write_tx_data,
1887 .kick_tx_queue = rt2500pci_kick_tx_queue,
1888 .fill_rxdone = rt2500pci_fill_rxdone,
3a643d24 1889 .config_filter = rt2500pci_config_filter,
6bb40dd1 1890 .config_intf = rt2500pci_config_intf,
72810379 1891 .config_erp = rt2500pci_config_erp,
95ea3627
ID		 1892 .config = rt2500pci_config,
1893};
1894
181d6902
ID		 1895static const struct data_queue_desc rt2500pci_queue_rx = {
1896 .entry_num = RX_ENTRIES,
1897 .data_size = DATA_FRAME_SIZE,
1898 .desc_size = RXD_DESC_SIZE,
1899 .priv_size = sizeof(struct queue_entry_priv_pci_rx),
1900};
1901
1902static const struct data_queue_desc rt2500pci_queue_tx = {
1903 .entry_num = TX_ENTRIES,
1904 .data_size = DATA_FRAME_SIZE,
1905 .desc_size = TXD_DESC_SIZE,
1906 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1907};
1908
1909static const struct data_queue_desc rt2500pci_queue_bcn = {
1910 .entry_num = BEACON_ENTRIES,
1911 .data_size = MGMT_FRAME_SIZE,
1912 .desc_size = TXD_DESC_SIZE,
1913 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1914};
1915
1916static const struct data_queue_desc rt2500pci_queue_atim = {
1917 .entry_num = ATIM_ENTRIES,
1918 .data_size = DATA_FRAME_SIZE,
1919 .desc_size = TXD_DESC_SIZE,
1920 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1921};
1922
95ea3627 1923static const struct rt2x00_ops rt2500pci_ops = {
2360157c 1924 .name = KBUILD_MODNAME,
6bb40dd1
ID		 1925 .max_sta_intf = 1,
1926 .max_ap_intf = 1,
95ea3627
ID		 1927 .eeprom_size = EEPROM_SIZE,
1928 .rf_size = RF_SIZE,
181d6902
ID		 1929 .rx = &rt2500pci_queue_rx,
1930 .tx = &rt2500pci_queue_tx,
1931 .bcn = &rt2500pci_queue_bcn,
1932 .atim = &rt2500pci_queue_atim,
95ea3627
ID		 1933 .lib = &rt2500pci_rt2x00_ops,
1934 .hw = &rt2500pci_mac80211_ops,
1935#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1936 .debugfs = &rt2500pci_rt2x00debug,
1937#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1938};
1939
1940/*
1941 * RT2500pci module information.
1942 */
1943static struct pci_device_id rt2500pci_device_table[] = {
1944 { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1945 { 0, }
1946};
1947
1948MODULE_AUTHOR(DRV_PROJECT);
1949MODULE_VERSION(DRV_VERSION);
1950MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1951MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1952MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1953MODULE_LICENSE("GPL");
1954
1955static struct pci_driver rt2500pci_driver = {
2360157c 1956 .name = KBUILD_MODNAME,
95ea3627
ID		 1957 .id_table = rt2500pci_device_table,
1958 .probe = rt2x00pci_probe,
1959 .remove = __devexit_p(rt2x00pci_remove),
1960 .suspend = rt2x00pci_suspend,
1961 .resume = rt2x00pci_resume,
1962};
1963
1964static int __init rt2500pci_init(void)
1965{
1966 return pci_register_driver(&rt2500pci_driver);
1967}
1968
1969static void __exit rt2500pci_exit(void)
1970{
1971 pci_unregister_driver(&rt2500pci_driver);
1972}
1973
1974module_init(rt2500pci_init);
1975module_exit(rt2500pci_exit);
Linux kernel - Deliverables
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