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rt2x00: Filter ACK_CTS based on FIF_CONTROL
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2500pci.c
CommitLineData
95ea3627 1/*
811aa9ca 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2500pci
23 Abstract: rt2500pci device specific routines.
24 Supported chipsets: RT2560.
25 */
26
95ea3627
ID		 27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h>
34
35#include "rt2x00.h"
36#include "rt2x00pci.h"
37#include "rt2500pci.h"
38
39/*
40 * Register access.
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
51 */
0e14f6d3 52static u32 rt2500pci_bbp_check(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 53{
54 u32 reg;
55 unsigned int i;
56
57 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
59 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
60 break;
61 udelay(REGISTER_BUSY_DELAY);
62 }
63
64 return reg;
65}
66
0e14f6d3 67static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 68 const unsigned int word, const u8 value)
69{
70 u32 reg;
71
72 /*
73 * Wait until the BBP becomes ready.
74 */
75 reg = rt2500pci_bbp_check(rt2x00dev);
76 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
77 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
78 return;
79 }
80
81 /*
82 * Write the data into the BBP.
83 */
84 reg = 0;
85 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
86 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
87 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
88 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
89
90 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
91}
92
0e14f6d3 93static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 94 const unsigned int word, u8 *value)
95{
96 u32 reg;
97
98 /*
99 * Wait until the BBP becomes ready.
100 */
101 reg = rt2500pci_bbp_check(rt2x00dev);
102 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
103 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
104 return;
105 }
106
107 /*
108 * Write the request into the BBP.
109 */
110 reg = 0;
111 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
112 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
113 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
114
115 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
116
117 /*
118 * Wait until the BBP becomes ready.
119 */
120 reg = rt2500pci_bbp_check(rt2x00dev);
121 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
122 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
123 *value = 0xff;
124 return;
125 }
126
127 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
128}
129
0e14f6d3 130static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 131 const unsigned int word, const u32 value)
132{
133 u32 reg;
134 unsigned int i;
135
136 if (!word)
137 return;
138
139 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
140 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
141 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
142 goto rf_write;
143 udelay(REGISTER_BUSY_DELAY);
144 }
145
146 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
147 return;
148
149rf_write:
150 reg = 0;
151 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
152 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
153 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
154 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
155
156 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
157 rt2x00_rf_write(rt2x00dev, word, value);
158}
159
160static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
161{
162 struct rt2x00_dev *rt2x00dev = eeprom->data;
163 u32 reg;
164
165 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
166
167 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
168 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
169 eeprom->reg_data_clock =
170 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
171 eeprom->reg_chip_select =
172 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
173}
174
175static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
176{
177 struct rt2x00_dev *rt2x00dev = eeprom->data;
178 u32 reg = 0;
179
180 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
181 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
182 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
183 !!eeprom->reg_data_clock);
184 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
185 !!eeprom->reg_chip_select);
186
187 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
188}
189
190#ifdef CONFIG_RT2X00_LIB_DEBUGFS
191#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
192
0e14f6d3 193static void rt2500pci_read_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 194 const unsigned int word, u32 *data)
195{
196 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
197}
198
0e14f6d3 199static void rt2500pci_write_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 200 const unsigned int word, u32 data)
201{
202 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
203}
204
205static const struct rt2x00debug rt2500pci_rt2x00debug = {
206 .owner = THIS_MODULE,
207 .csr = {
208 .read = rt2500pci_read_csr,
209 .write = rt2500pci_write_csr,
210 .word_size = sizeof(u32),
211 .word_count = CSR_REG_SIZE / sizeof(u32),
212 },
213 .eeprom = {
214 .read = rt2x00_eeprom_read,
215 .write = rt2x00_eeprom_write,
216 .word_size = sizeof(u16),
217 .word_count = EEPROM_SIZE / sizeof(u16),
218 },
219 .bbp = {
220 .read = rt2500pci_bbp_read,
221 .write = rt2500pci_bbp_write,
222 .word_size = sizeof(u8),
223 .word_count = BBP_SIZE / sizeof(u8),
224 },
225 .rf = {
226 .read = rt2x00_rf_read,
227 .write = rt2500pci_rf_write,
228 .word_size = sizeof(u32),
229 .word_count = RF_SIZE / sizeof(u32),
230 },
231};
232#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
233
234#ifdef CONFIG_RT2500PCI_RFKILL
235static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
236{
237 u32 reg;
238
239 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
240 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
241}
81873e9c
ID		 242#else
243#define rt2500pci_rfkill_poll NULL
dcf5475b 244#endif /* CONFIG_RT2500PCI_RFKILL */
95ea3627 245
a9450b70
ID		 246#ifdef CONFIG_RT2500PCI_LEDS
247static void rt2500pci_led_brightness(struct led_classdev *led_cdev,
248 enum led_brightness brightness)
249{
250 struct rt2x00_led *led =
251 container_of(led_cdev, struct rt2x00_led, led_dev);
252 unsigned int enabled = brightness != LED_OFF;
253 unsigned int activity =
254 led->rt2x00dev->led_flags & LED_SUPPORT_ACTIVITY;
255 u32 reg;
256
257 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
258
259 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC) {
260 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
261 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled && activity);
262 }
263
264 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
265}
266#else
267#define rt2500pci_led_brightness NULL
268#endif /* CONFIG_RT2500PCI_LEDS */
269
95ea3627
ID		 270/*
271 * Configuration handlers.
272 */
6bb40dd1
ID		 273static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
274 struct rt2x00_intf *intf,
275 struct rt2x00intf_conf *conf,
276 const unsigned int flags)
95ea3627 277{
181d6902 278 struct data_queue *queue =
5957da4c 279 rt2x00queue_get_queue(rt2x00dev, RT2X00_BCN_QUEUE_BEACON);
6bb40dd1 280 unsigned int bcn_preload;
95ea3627
ID		 281 u32 reg;
282
6bb40dd1
ID		 283 if (flags & CONFIG_UPDATE_TYPE) {
284 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
95ea3627 285
6bb40dd1
ID		 286 /*
287 * Enable beacon config
288 */
289 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
290 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
291 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
292 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
293 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
95ea3627 294
6bb40dd1
ID		 295 /*
296 * Enable synchronisation.
297 */
298 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
299 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
300 rt2x00_set_field32(&reg, CSR14_TBCN,
301 (conf->sync == TSF_SYNC_BEACON));
302 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
303 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
304 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
305 }
306
307 if (flags & CONFIG_UPDATE_MAC)
308 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
309 conf->mac, sizeof(conf->mac));
310
311 if (flags & CONFIG_UPDATE_BSSID)
312 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
313 conf->bssid, sizeof(conf->bssid));
95ea3627
ID		 314}
315
6bb40dd1
ID		 316static int rt2500pci_config_preamble(struct rt2x00_dev *rt2x00dev,
317 const int short_preamble,
318 const int ack_timeout,
319 const int ack_consume_time)
95ea3627 320{
5c58ee51 321 int preamble_mask;
95ea3627 322 u32 reg;
95ea3627 323
5c58ee51
ID		 324 /*
325 * When short preamble is enabled, we should set bit 0x08
326 */
327 preamble_mask = short_preamble << 3;
95ea3627
ID		 328
329 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
5c58ee51
ID		 330 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, ack_timeout);
331 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, ack_consume_time);
95ea3627
ID		 332 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
333
95ea3627 334 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
5c58ee51 335 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble_mask);
95ea3627
ID		 336 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
337 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
338 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
339
340 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
5c58ee51 341 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
95ea3627
ID		 342 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
343 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
344 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
345
346 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
5c58ee51 347 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
95ea3627
ID		 348 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
349 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
350 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
351
352 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
5c58ee51 353 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
95ea3627
ID		 354 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
355 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
356 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
6bb40dd1
ID		 357
358 return 0;
95ea3627
ID		 359}
360
361static void rt2500pci_config_phymode(struct rt2x00_dev *rt2x00dev,
5c58ee51 362 const int basic_rate_mask)
95ea3627 363{
5c58ee51 364 rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
95ea3627
ID		 365}
366
367static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
5c58ee51 368 struct rf_channel *rf, const int txpower)
95ea3627 369{
95ea3627
ID		 370 u8 r70;
371
95ea3627
ID		 372 /*
373 * Set TXpower.
374 */
5c58ee51 375 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
95ea3627
ID		 376
377 /*
378 * Switch on tuning bits.
379 * For RT2523 devices we do not need to update the R1 register.
380 */
381 if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
5c58ee51
ID		 382 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
383 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
95ea3627
ID		 384
385 /*
386 * For RT2525 we should first set the channel to half band higher.
387 */
388 if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
389 static const u32 vals[] = {
390 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
391 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
392 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
393 0x00080d2e, 0x00080d3a
394 };
395
5c58ee51
ID		 396 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
397 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
398 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
399 if (rf->rf4)
400 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
95ea3627
ID		 401 }
402
5c58ee51
ID		 403 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
404 rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
405 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
406 if (rf->rf4)
407 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
95ea3627
ID		 408
409 /*
410 * Channel 14 requires the Japan filter bit to be set.
411 */
412 r70 = 0x46;
5c58ee51 413 rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
95ea3627
ID		 414 rt2500pci_bbp_write(rt2x00dev, 70, r70);
415
416 msleep(1);
417
418 /*
419 * Switch off tuning bits.
420 * For RT2523 devices we do not need to update the R1 register.
421 */
422 if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
5c58ee51
ID		 423 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
424 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
95ea3627
ID		 425 }
426
5c58ee51
ID		 427 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
428 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 429
430 /*
431 * Clear false CRC during channel switch.
432 */
5c58ee51 433 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
95ea3627
ID		 434}
435
436static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
437 const int txpower)
438{
439 u32 rf3;
440
441 rt2x00_rf_read(rt2x00dev, 3, &rf3);
442 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
443 rt2500pci_rf_write(rt2x00dev, 3, rf3);
444}
445
446static void rt2500pci_config_antenna(struct rt2x00_dev *rt2x00dev,
addc81bd 447 struct antenna_setup *ant)
95ea3627
ID		 448{
449 u32 reg;
450 u8 r14;
451 u8 r2;
452
453 rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
454 rt2500pci_bbp_read(rt2x00dev, 14, &r14);
455 rt2500pci_bbp_read(rt2x00dev, 2, &r2);
456
457 /*
458 * Configure the TX antenna.
459 */
addc81bd 460 switch (ant->tx) {
95ea3627
ID		 461 case ANTENNA_A:
462 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
463 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
464 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
465 break;
39e75857
ID		 466 case ANTENNA_HW_DIVERSITY:
467 case ANTENNA_SW_DIVERSITY:
468 /*
469 * NOTE: We should never come here because rt2x00lib is
470 * supposed to catch this and send us the correct antenna
471 * explicitely. However we are nog going to bug about this.
472 * Instead, just default to antenna B.
473 */
95ea3627
ID		 474 case ANTENNA_B:
475 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
476 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
477 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
478 break;
479 }
480
481 /*
482 * Configure the RX antenna.
483 */
addc81bd 484 switch (ant->rx) {
95ea3627
ID		 485 case ANTENNA_A:
486 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
487 break;
39e75857
ID		 488 case ANTENNA_HW_DIVERSITY:
489 case ANTENNA_SW_DIVERSITY:
490 /*
491 * NOTE: We should never come here because rt2x00lib is
492 * supposed to catch this and send us the correct antenna
493 * explicitely. However we are nog going to bug about this.
494 * Instead, just default to antenna B.
495 */
95ea3627
ID		 496 case ANTENNA_B:
497 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
498 break;
499 }
500
501 /*
502 * RT2525E and RT5222 need to flip TX I/Q
503 */
504 if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
505 rt2x00_rf(&rt2x00dev->chip, RF5222)) {
506 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
507 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
508 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
509
510 /*
511 * RT2525E does not need RX I/Q Flip.
512 */
513 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
514 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
515 } else {
516 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
517 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
518 }
519
520 rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
521 rt2500pci_bbp_write(rt2x00dev, 14, r14);
522 rt2500pci_bbp_write(rt2x00dev, 2, r2);
523}
524
525static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 526 struct rt2x00lib_conf *libconf)
95ea3627
ID		 527{
528 u32 reg;
529
530 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
5c58ee51 531 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
95ea3627
ID		 532 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
533
534 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
5c58ee51
ID		 535 rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
536 rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
95ea3627
ID		 537 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
538
539 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
5c58ee51
ID		 540 rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
541 rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
95ea3627
ID		 542 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
543
544 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
545 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
546 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
547 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
548
549 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
5c58ee51
ID		 550 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
551 libconf->conf->beacon_int * 16);
552 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
553 libconf->conf->beacon_int * 16);
95ea3627
ID		 554 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
555}
556
557static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 558 struct rt2x00lib_conf *libconf,
559 const unsigned int flags)
95ea3627 560{
95ea3627 561 if (flags & CONFIG_UPDATE_PHYMODE)
5c58ee51 562 rt2500pci_config_phymode(rt2x00dev, libconf->basic_rates);
95ea3627 563 if (flags & CONFIG_UPDATE_CHANNEL)
5c58ee51
ID		 564 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
565 libconf->conf->power_level);
95ea3627 566 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
5c58ee51
ID		 567 rt2500pci_config_txpower(rt2x00dev,
568 libconf->conf->power_level);
95ea3627 569 if (flags & CONFIG_UPDATE_ANTENNA)
addc81bd 570 rt2500pci_config_antenna(rt2x00dev, &libconf->ant);
95ea3627 571 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
5c58ee51 572 rt2500pci_config_duration(rt2x00dev, libconf);
95ea3627
ID		 573}
574
95ea3627
ID		 575/*
576 * Link tuning
577 */
ebcf26da
ID		 578static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
579 struct link_qual *qual)
95ea3627
ID		 580{
581 u32 reg;
582
583 /*
584 * Update FCS error count from register.
585 */
586 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
ebcf26da 587 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
95ea3627
ID		 588
589 /*
590 * Update False CCA count from register.
591 */
592 rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
ebcf26da 593 qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
95ea3627
ID		 594}
595
596static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
597{
598 rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
599 rt2x00dev->link.vgc_level = 0x48;
600}
601
602static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
603{
604 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
605 u8 r17;
606
607 /*
608 * To prevent collisions with MAC ASIC on chipsets
609 * up to version C the link tuning should halt after 20
6bb40dd1 610 * seconds while being associated.
95ea3627 611 */
755a957d 612 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
6bb40dd1 613 rt2x00dev->intf_associated &&
95ea3627
ID		 614 rt2x00dev->link.count > 20)
615 return;
616
617 rt2500pci_bbp_read(rt2x00dev, 17, &r17);
618
619 /*
620 * Chipset versions C and lower should directly continue
6bb40dd1
ID		 621 * to the dynamic CCA tuning. Chipset version D and higher
622 * should go straight to dynamic CCA tuning when they
623 * are not associated.
95ea3627 624 */
6bb40dd1
ID		 625 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D ||
626 !rt2x00dev->intf_associated)
95ea3627
ID		 627 goto dynamic_cca_tune;
628
629 /*
630 * A too low RSSI will cause too much false CCA which will
631 * then corrupt the R17 tuning. To remidy this the tuning should
632 * be stopped (While making sure the R17 value will not exceed limits)
633 */
634 if (rssi < -80 && rt2x00dev->link.count > 20) {
635 if (r17 >= 0x41) {
636 r17 = rt2x00dev->link.vgc_level;
637 rt2500pci_bbp_write(rt2x00dev, 17, r17);
638 }
639 return;
640 }
641
642 /*
643 * Special big-R17 for short distance
644 */
645 if (rssi >= -58) {
646 if (r17 != 0x50)
647 rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
648 return;
649 }
650
651 /*
652 * Special mid-R17 for middle distance
653 */
654 if (rssi >= -74) {
655 if (r17 != 0x41)
656 rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
657 return;
658 }
659
660 /*
661 * Leave short or middle distance condition, restore r17
662 * to the dynamic tuning range.
663 */
664 if (r17 >= 0x41) {
665 rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
666 return;
667 }
668
669dynamic_cca_tune:
670
671 /*
672 * R17 is inside the dynamic tuning range,
673 * start tuning the link based on the false cca counter.
674 */
ebcf26da 675 if (rt2x00dev->link.qual.false_cca > 512 && r17 < 0x40) {
95ea3627
ID		 676 rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
677 rt2x00dev->link.vgc_level = r17;
ebcf26da 678 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > 0x32) {
95ea3627
ID		 679 rt2500pci_bbp_write(rt2x00dev, 17, --r17);
680 rt2x00dev->link.vgc_level = r17;
681 }
682}
683
684/*
685 * Initialization functions.
686 */
837e7f24 687static void rt2500pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
181d6902 688 struct queue_entry *entry)
95ea3627 689{
181d6902 690 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
95ea3627
ID		 691 u32 word;
692
181d6902
ID		 693 rt2x00_desc_read(priv_rx->desc, 1, &word);
694 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->dma);
695 rt2x00_desc_write(priv_rx->desc, 1, word);
95ea3627 696
181d6902 697 rt2x00_desc_read(priv_rx->desc, 0, &word);
837e7f24 698 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
181d6902 699 rt2x00_desc_write(priv_rx->desc, 0, word);
95ea3627
ID		 700}
701
837e7f24 702static void rt2500pci_init_txentry(struct rt2x00_dev *rt2x00dev,
181d6902 703 struct queue_entry *entry)
95ea3627 704{
181d6902 705 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
95ea3627
ID		 706 u32 word;
707
181d6902
ID		 708 rt2x00_desc_read(priv_tx->desc, 1, &word);
709 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->dma);
710 rt2x00_desc_write(priv_tx->desc, 1, word);
95ea3627 711
181d6902 712 rt2x00_desc_read(priv_tx->desc, 0, &word);
837e7f24
ID		 713 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
714 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
181d6902 715 rt2x00_desc_write(priv_tx->desc, 0, word);
95ea3627
ID		 716}
717
181d6902 718static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 719{
181d6902
ID		 720 struct queue_entry_priv_pci_rx *priv_rx;
721 struct queue_entry_priv_pci_tx *priv_tx;
95ea3627
ID		 722 u32 reg;
723
95ea3627
ID		 724 /*
725 * Initialize registers.
726 */
727 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
181d6902
ID		 728 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
729 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
730 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
731 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
95ea3627
ID		 732 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
733
181d6902 734 priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 735 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
181d6902 736 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER, priv_tx->dma);
95ea3627
ID		 737 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
738
181d6902 739 priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 740 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
181d6902 741 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER, priv_tx->dma);
95ea3627
ID		 742 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
743
181d6902 744 priv_tx = rt2x00dev->bcn[1].entries[0].priv_data;
95ea3627 745 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
181d6902 746 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER, priv_tx->dma);
95ea3627
ID		 747 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
748
181d6902 749 priv_tx = rt2x00dev->bcn[0].entries[0].priv_data;
95ea3627 750 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
181d6902 751 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER, priv_tx->dma);
95ea3627
ID		 752 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
753
754 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
755 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
181d6902 756 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
95ea3627
ID		 757 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
758
181d6902 759 priv_rx = rt2x00dev->rx->entries[0].priv_data;
95ea3627 760 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
181d6902 761 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, priv_tx->dma);
95ea3627
ID		 762 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
763
764 return 0;
765}
766
767static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
768{
769 u32 reg;
770
771 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
772 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
773 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
774 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
775
776 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
777 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
778 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
779 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
780 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
781
782 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
783 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
784 rt2x00dev->rx->data_size / 128);
785 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
786
787 /*
788 * Always use CWmin and CWmax set in descriptor.
789 */
790 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
791 rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
792 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
793
a9450b70
ID		 794 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
795 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
796 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
797 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
798
95ea3627
ID		 799 rt2x00pci_register_write(rt2x00dev, CNT3, 0);
800
801 rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
802 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
803 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
804 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
805 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
806 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
807 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
808 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
809 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
810 rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
811
812 rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
813 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
814 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
815 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
816 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
817 rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
818
819 rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
820 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
821 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
822 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
823 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
824 rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
825
826 rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
827 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
828 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
829 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
830 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
831 rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
832
833 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
834 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
835 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
836 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
837 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
838 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
839 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
840 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
841 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
842 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
843
844 rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
845 rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
846 rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
847 rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
848 rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
849 rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
850 rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
851 rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
852 rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
853
854 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
855
856 rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
857 rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
858
859 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
860 return -EBUSY;
861
862 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
863 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
864
865 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
866 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
867 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
868
869 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
870 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
871 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
872 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
873 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
874 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
875 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
876 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
877
878 rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
879
880 rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
881
882 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
883 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
884 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
885 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
886 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
887
888 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
889 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
890 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
891 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
892
893 /*
894 * We must clear the FCS and FIFO error count.
895 * These registers are cleared on read,
896 * so we may pass a useless variable to store the value.
897 */
898 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
899 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
900
901 return 0;
902}
903
904static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
905{
906 unsigned int i;
907 u16 eeprom;
908 u8 reg_id;
909 u8 value;
910
911 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
912 rt2500pci_bbp_read(rt2x00dev, 0, &value);
913 if ((value != 0xff) && (value != 0x00))
914 goto continue_csr_init;
915 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
916 udelay(REGISTER_BUSY_DELAY);
917 }
918
919 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
920 return -EACCES;
921
922continue_csr_init:
923 rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
924 rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
925 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
926 rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
927 rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
928 rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
929 rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
930 rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
931 rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
932 rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
933 rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
934 rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
935 rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
936 rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
937 rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
938 rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
939 rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
940 rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
941 rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
942 rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
943 rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
944 rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
945 rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
946 rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
947 rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
948 rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
949 rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
950 rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
951 rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
952 rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
953
95ea3627
ID		 954 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
955 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
956
957 if (eeprom != 0xffff && eeprom != 0x0000) {
958 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
959 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 960 rt2500pci_bbp_write(rt2x00dev, reg_id, value);
961 }
962 }
95ea3627
ID		 963
964 return 0;
965}
966
967/*
968 * Device state switch handlers.
969 */
970static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
971 enum dev_state state)
972{
973 u32 reg;
974
975 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
976 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
977 state == STATE_RADIO_RX_OFF);
978 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
979}
980
981static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
982 enum dev_state state)
983{
984 int mask = (state == STATE_RADIO_IRQ_OFF);
985 u32 reg;
986
987 /*
988 * When interrupts are being enabled, the interrupt registers
989 * should clear the register to assure a clean state.
990 */
991 if (state == STATE_RADIO_IRQ_ON) {
992 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
993 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
994 }
995
996 /*
997 * Only toggle the interrupts bits we are going to use.
998 * Non-checked interrupt bits are disabled by default.
999 */
1000 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1001 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1002 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1003 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1004 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1005 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1006 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1007}
1008
1009static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1010{
1011 /*
1012 * Initialize all registers.
1013 */
181d6902 1014 if (rt2500pci_init_queues(rt2x00dev) ||
95ea3627
ID		 1015 rt2500pci_init_registers(rt2x00dev) ||
1016 rt2500pci_init_bbp(rt2x00dev)) {
1017 ERROR(rt2x00dev, "Register initialization failed.\n");
1018 return -EIO;
1019 }
1020
1021 /*
1022 * Enable interrupts.
1023 */
1024 rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1025
95ea3627
ID		 1026 return 0;
1027}
1028
1029static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1030{
1031 u32 reg;
1032
95ea3627
ID		 1033 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1034
1035 /*
1036 * Disable synchronisation.
1037 */
1038 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1039
1040 /*
1041 * Cancel RX and TX.
1042 */
1043 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1044 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1045 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1046
1047 /*
1048 * Disable interrupts.
1049 */
1050 rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1051}
1052
1053static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1054 enum dev_state state)
1055{
1056 u32 reg;
1057 unsigned int i;
1058 char put_to_sleep;
1059 char bbp_state;
1060 char rf_state;
1061
1062 put_to_sleep = (state != STATE_AWAKE);
1063
1064 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1065 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1066 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1067 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1068 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1069 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1070
1071 /*
1072 * Device is not guaranteed to be in the requested state yet.
1073 * We must wait until the register indicates that the
1074 * device has entered the correct state.
1075 */
1076 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1077 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1078 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1079 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1080 if (bbp_state == state && rf_state == state)
1081 return 0;
1082 msleep(10);
1083 }
1084
1085 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1086 "current device state: bbp %d and rf %d.\n",
1087 state, bbp_state, rf_state);
1088
1089 return -EBUSY;
1090}
1091
1092static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1093 enum dev_state state)
1094{
1095 int retval = 0;
1096
1097 switch (state) {
1098 case STATE_RADIO_ON:
1099 retval = rt2500pci_enable_radio(rt2x00dev);
1100 break;
1101 case STATE_RADIO_OFF:
1102 rt2500pci_disable_radio(rt2x00dev);
1103 break;
1104 case STATE_RADIO_RX_ON:
61667d8d
ID		 1105 case STATE_RADIO_RX_ON_LINK:
1106 rt2500pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1107 break;
95ea3627 1108 case STATE_RADIO_RX_OFF:
61667d8d
ID		 1109 case STATE_RADIO_RX_OFF_LINK:
1110 rt2500pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
95ea3627
ID		 1111 break;
1112 case STATE_DEEP_SLEEP:
1113 case STATE_SLEEP:
1114 case STATE_STANDBY:
1115 case STATE_AWAKE:
1116 retval = rt2500pci_set_state(rt2x00dev, state);
1117 break;
1118 default:
1119 retval = -ENOTSUPP;
1120 break;
1121 }
1122
1123 return retval;
1124}
1125
1126/*
1127 * TX descriptor initialization
1128 */
1129static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 1130 struct sk_buff *skb,
181d6902 1131 struct txentry_desc *txdesc,
95ea3627
ID		 1132 struct ieee80211_tx_control *control)
1133{
181d6902 1134 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
dd3193e1 1135 __le32 *txd = skbdesc->desc;
95ea3627
ID		 1136 u32 word;
1137
1138 /*
1139 * Start writing the descriptor words.
1140 */
1141 rt2x00_desc_read(txd, 2, &word);
1142 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
181d6902
ID		 1143 rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
1144 rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
1145 rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
95ea3627
ID		 1146 rt2x00_desc_write(txd, 2, word);
1147
1148 rt2x00_desc_read(txd, 3, &word);
181d6902
ID		 1149 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1150 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1151 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low);
1152 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1153 rt2x00_desc_write(txd, 3, word);
1154
1155 rt2x00_desc_read(txd, 10, &word);
1156 rt2x00_set_field32(&word, TXD_W10_RTS,
181d6902 1157 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
95ea3627
ID		 1158 rt2x00_desc_write(txd, 10, word);
1159
1160 rt2x00_desc_read(txd, 0, &word);
1161 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1162 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1163 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1164 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1165 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1166 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1167 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1168 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1169 rt2x00_set_field32(&word, TXD_W0_OFDM,
181d6902 1170 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
95ea3627 1171 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
181d6902 1172 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627
ID		 1173 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1174 !!(control->flags &
1175 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
dd3193e1 1176 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
95ea3627
ID		 1177 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1178 rt2x00_desc_write(txd, 0, word);
1179}
1180
1181/*
1182 * TX data initialization
1183 */
1184static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
5957da4c 1185 const unsigned int queue)
95ea3627
ID		 1186{
1187 u32 reg;
1188
5957da4c 1189 if (queue == RT2X00_BCN_QUEUE_BEACON) {
95ea3627
ID		 1190 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1191 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1192 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1193 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1194 }
1195 return;
1196 }
1197
1198 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
ddc827f9
ID		 1199 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO,
1200 (queue == IEEE80211_TX_QUEUE_DATA0));
1201 rt2x00_set_field32(&reg, TXCSR0_KICK_TX,
1202 (queue == IEEE80211_TX_QUEUE_DATA1));
1203 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM,
5957da4c 1204 (queue == RT2X00_BCN_QUEUE_ATIM));
95ea3627
ID		 1205 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1206}
1207
1208/*
1209 * RX control handlers
1210 */
181d6902
ID		 1211static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1212 struct rxdone_entry_desc *rxdesc)
95ea3627 1213{
181d6902 1214 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
95ea3627
ID		 1215 u32 word0;
1216 u32 word2;
1217
181d6902
ID		 1218 rt2x00_desc_read(priv_rx->desc, 0, &word0);
1219 rt2x00_desc_read(priv_rx->desc, 2, &word2);
95ea3627 1220
181d6902 1221 rxdesc->flags = 0;
4150c572 1222 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1223 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
4150c572 1224 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
181d6902
ID		 1225 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1226
1227 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1228 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1229 entry->queue->rt2x00dev->rssi_offset;
1230 rxdesc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1231 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1232 rxdesc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
95ea3627
ID		 1233}
1234
1235/*
1236 * Interrupt functions.
1237 */
181d6902
ID		 1238static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1239 const enum ieee80211_tx_queue queue_idx)
95ea3627 1240{
181d6902
ID		 1241 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1242 struct queue_entry_priv_pci_tx *priv_tx;
1243 struct queue_entry *entry;
1244 struct txdone_entry_desc txdesc;
95ea3627 1245 u32 word;
95ea3627 1246
181d6902
ID		 1247 while (!rt2x00queue_empty(queue)) {
1248 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1249 priv_tx = entry->priv_data;
1250 rt2x00_desc_read(priv_tx->desc, 0, &word);
95ea3627
ID		 1251
1252 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1253 !rt2x00_get_field32(word, TXD_W0_VALID))
1254 break;
1255
1256 /*
1257 * Obtain the status about this packet.
1258 */
181d6902
ID		 1259 txdesc.status = rt2x00_get_field32(word, TXD_W0_RESULT);
1260 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
95ea3627 1261
181d6902 1262 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
95ea3627 1263 }
95ea3627
ID		 1264}
1265
1266static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1267{
1268 struct rt2x00_dev *rt2x00dev = dev_instance;
1269 u32 reg;
1270
1271 /*
1272 * Get the interrupt sources & saved to local variable.
1273 * Write register value back to clear pending interrupts.
1274 */
1275 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1276 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1277
1278 if (!reg)
1279 return IRQ_NONE;
1280
1281 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1282 return IRQ_HANDLED;
1283
1284 /*
1285 * Handle interrupts, walk through all bits
1286 * and run the tasks, the bits are checked in order of
1287 * priority.
1288 */
1289
1290 /*
1291 * 1 - Beacon timer expired interrupt.
1292 */
1293 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1294 rt2x00lib_beacondone(rt2x00dev);
1295
1296 /*
1297 * 2 - Rx ring done interrupt.
1298 */
1299 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1300 rt2x00pci_rxdone(rt2x00dev);
1301
1302 /*
1303 * 3 - Atim ring transmit done interrupt.
1304 */
1305 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
5957da4c 1306 rt2500pci_txdone(rt2x00dev, RT2X00_BCN_QUEUE_ATIM);
95ea3627
ID		 1307
1308 /*
1309 * 4 - Priority ring transmit done interrupt.
1310 */
1311 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1312 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1313
1314 /*
1315 * 5 - Tx ring transmit done interrupt.
1316 */
1317 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1318 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1319
1320 return IRQ_HANDLED;
1321}
1322
1323/*
1324 * Device probe functions.
1325 */
1326static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1327{
1328 struct eeprom_93cx6 eeprom;
1329 u32 reg;
1330 u16 word;
1331 u8 *mac;
1332
1333 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1334
1335 eeprom.data = rt2x00dev;
1336 eeprom.register_read = rt2500pci_eepromregister_read;
1337 eeprom.register_write = rt2500pci_eepromregister_write;
1338 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1339 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1340 eeprom.reg_data_in = 0;
1341 eeprom.reg_data_out = 0;
1342 eeprom.reg_data_clock = 0;
1343 eeprom.reg_chip_select = 0;
1344
1345 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1346 EEPROM_SIZE / sizeof(u16));
1347
1348 /*
1349 * Start validation of the data that has been read.
1350 */
1351 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1352 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1353 DECLARE_MAC_BUF(macbuf);
1354
95ea3627 1355 random_ether_addr(mac);
0795af57
JP		 1356 EEPROM(rt2x00dev, "MAC: %s\n",
1357 print_mac(macbuf, mac));
95ea3627
ID		 1358 }
1359
1360 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1361 if (word == 0xffff) {
1362 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1363 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1364 ANTENNA_SW_DIVERSITY);
1365 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1366 ANTENNA_SW_DIVERSITY);
1367 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1368 LED_MODE_DEFAULT);
95ea3627
ID		 1369 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1370 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1371 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1372 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1373 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1374 }
1375
1376 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1377 if (word == 0xffff) {
1378 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1379 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1380 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1381 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1382 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1383 }
1384
1385 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1386 if (word == 0xffff) {
1387 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1388 DEFAULT_RSSI_OFFSET);
1389 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1390 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1391 }
1392
1393 return 0;
1394}
1395
1396static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1397{
1398 u32 reg;
1399 u16 value;
1400 u16 eeprom;
1401
1402 /*
1403 * Read EEPROM word for configuration.
1404 */
1405 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1406
1407 /*
1408 * Identify RF chipset.
1409 */
1410 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1411 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1412 rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
1413
1414 if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1415 !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1416 !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1417 !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1418 !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1419 !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1420 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1421 return -ENODEV;
1422 }
1423
1424 /*
1425 * Identify default antenna configuration.
1426 */
addc81bd 1427 rt2x00dev->default_ant.tx =
95ea3627 1428 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1429 rt2x00dev->default_ant.rx =
95ea3627
ID		 1430 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1431
1432 /*
1433 * Store led mode, for correct led behaviour.
1434 */
a9450b70
ID		 1435#ifdef CONFIG_RT2500PCI_LEDS
1436 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1437
1438 switch (value) {
1439 case LED_MODE_ASUS:
1440 case LED_MODE_ALPHA:
1441 case LED_MODE_DEFAULT:
1442 rt2x00dev->led_flags = LED_SUPPORT_RADIO;
1443 break;
1444 case LED_MODE_TXRX_ACTIVITY:
1445 rt2x00dev->led_flags =
1446 LED_SUPPORT_RADIO | LED_SUPPORT_ACTIVITY;
1447 break;
1448 case LED_MODE_SIGNAL_STRENGTH:
1449 rt2x00dev->led_flags = LED_SUPPORT_RADIO;
1450 break;
1451 }
1452#endif /* CONFIG_RT2500PCI_LEDS */
95ea3627
ID		 1453
1454 /*
1455 * Detect if this device has an hardware controlled radio.
1456 */
81873e9c 1457#ifdef CONFIG_RT2500PCI_RFKILL
95ea3627 1458 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 1459 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
81873e9c 1460#endif /* CONFIG_RT2500PCI_RFKILL */
95ea3627
ID		 1461
1462 /*
1463 * Check if the BBP tuning should be enabled.
1464 */
1465 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1466
1467 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1468 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1469
1470 /*
1471 * Read the RSSI <-> dBm offset information.
1472 */
1473 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1474 rt2x00dev->rssi_offset =
1475 rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1476
1477 return 0;
1478}
1479
1480/*
1481 * RF value list for RF2522
1482 * Supports: 2.4 GHz
1483 */
1484static const struct rf_channel rf_vals_bg_2522[] = {
1485 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
1486 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
1487 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
1488 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
1489 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
1490 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
1491 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
1492 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
1493 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
1494 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1495 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1496 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1497 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1498 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1499};
1500
1501/*
1502 * RF value list for RF2523
1503 * Supports: 2.4 GHz
1504 */
1505static const struct rf_channel rf_vals_bg_2523[] = {
1506 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1507 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1508 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1509 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1510 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1511 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1512 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1513 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1514 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1515 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1516 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1517 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1518 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1519 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1520};
1521
1522/*
1523 * RF value list for RF2524
1524 * Supports: 2.4 GHz
1525 */
1526static const struct rf_channel rf_vals_bg_2524[] = {
1527 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1528 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1529 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1530 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1531 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1532 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1533 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1534 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1535 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1536 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1537 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1538 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1539 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1540 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1541};
1542
1543/*
1544 * RF value list for RF2525
1545 * Supports: 2.4 GHz
1546 */
1547static const struct rf_channel rf_vals_bg_2525[] = {
1548 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1549 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1550 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1551 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1552 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1553 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1554 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1555 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1556 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1557 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1558 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1559 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1560 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1561 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1562};
1563
1564/*
1565 * RF value list for RF2525e
1566 * Supports: 2.4 GHz
1567 */
1568static const struct rf_channel rf_vals_bg_2525e[] = {
1569 { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1570 { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1571 { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1572 { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1573 { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1574 { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1575 { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1576 { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1577 { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1578 { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1579 { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1580 { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1581 { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1582 { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1583};
1584
1585/*
1586 * RF value list for RF5222
1587 * Supports: 2.4 GHz & 5.2 GHz
1588 */
1589static const struct rf_channel rf_vals_5222[] = {
1590 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1591 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1592 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1593 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1594 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1595 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1596 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1597 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1598 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1599 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1600 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1601 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1602 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1603 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1604
1605 /* 802.11 UNI / HyperLan 2 */
1606 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1607 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1608 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1609 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1610 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1611 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1612 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1613 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1614
1615 /* 802.11 HyperLan 2 */
1616 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1617 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1618 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1619 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1620 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1621 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1622 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1623 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1624 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1625 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1626
1627 /* 802.11 UNII */
1628 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1629 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1630 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1631 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1632 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1633};
1634
1635static void rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1636{
1637 struct hw_mode_spec *spec = &rt2x00dev->spec;
1638 u8 *txpower;
1639 unsigned int i;
1640
1641 /*
1642 * Initialize all hw fields.
1643 */
4150c572 1644 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
95ea3627
ID		 1645 rt2x00dev->hw->extra_tx_headroom = 0;
1646 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1647 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1648 rt2x00dev->hw->queues = 2;
1649
1650 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1651 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1652 rt2x00_eeprom_addr(rt2x00dev,
1653 EEPROM_MAC_ADDR_0));
1654
1655 /*
1656 * Convert tx_power array in eeprom.
1657 */
1658 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1659 for (i = 0; i < 14; i++)
1660 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1661
1662 /*
1663 * Initialize hw_mode information.
1664 */
1665 spec->num_modes = 2;
1666 spec->num_rates = 12;
1667 spec->tx_power_a = NULL;
1668 spec->tx_power_bg = txpower;
1669 spec->tx_power_default = DEFAULT_TXPOWER;
1670
1671 if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1672 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1673 spec->channels = rf_vals_bg_2522;
1674 } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1675 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1676 spec->channels = rf_vals_bg_2523;
1677 } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1678 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1679 spec->channels = rf_vals_bg_2524;
1680 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1681 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1682 spec->channels = rf_vals_bg_2525;
1683 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1684 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1685 spec->channels = rf_vals_bg_2525e;
1686 } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1687 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1688 spec->channels = rf_vals_5222;
1689 spec->num_modes = 3;
1690 }
1691}
1692
1693static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1694{
1695 int retval;
1696
1697 /*
1698 * Allocate eeprom data.
1699 */
1700 retval = rt2500pci_validate_eeprom(rt2x00dev);
1701 if (retval)
1702 return retval;
1703
1704 retval = rt2500pci_init_eeprom(rt2x00dev);
1705 if (retval)
1706 return retval;
1707
1708 /*
1709 * Initialize hw specifications.
1710 */
1711 rt2500pci_probe_hw_mode(rt2x00dev);
1712
1713 /*
181d6902 1714 * This device requires the atim queue
95ea3627 1715 */
181d6902 1716 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
95ea3627
ID		 1717
1718 /*
1719 * Set the rssi offset.
1720 */
1721 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1722
1723 return 0;
1724}
1725
1726/*
1727 * IEEE80211 stack callback functions.
1728 */
4150c572
JB		 1729static void rt2500pci_configure_filter(struct ieee80211_hw *hw,
1730 unsigned int changed_flags,
1731 unsigned int *total_flags,
1732 int mc_count,
1733 struct dev_addr_list *mc_list)
1734{
1735 struct rt2x00_dev *rt2x00dev = hw->priv;
4150c572
JB		 1736 u32 reg;
1737
1738 /*
1739 * Mask off any flags we are going to ignore from
1740 * the total_flags field.
1741 */
1742 *total_flags &=
1743 FIF_ALLMULTI |
1744 FIF_FCSFAIL |
1745 FIF_PLCPFAIL |
1746 FIF_CONTROL |
1747 FIF_OTHER_BSS |
1748 FIF_PROMISC_IN_BSS;
1749
1750 /*
1751 * Apply some rules to the filters:
1752 * - Some filters imply different filters to be set.
1753 * - Some things we can't filter out at all.
4150c572
JB		 1754 */
1755 if (mc_count)
1756 *total_flags |= FIF_ALLMULTI;
5886d0db
ID		 1757 if (*total_flags & FIF_OTHER_BSS ||
1758 *total_flags & FIF_PROMISC_IN_BSS)
4150c572 1759 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
4150c572
JB		 1760
1761 /*
1762 * Check if there is any work left for us.
1763 */
3c4f2085 1764 if (rt2x00dev->packet_filter == *total_flags)
4150c572 1765 return;
3c4f2085 1766 rt2x00dev->packet_filter = *total_flags;
4150c572
JB		 1767
1768 /*
1769 * Start configuration steps.
1770 * Note that the version error will always be dropped
1771 * and broadcast frames will always be accepted since
1772 * there is no filter for it at this time.
1773 */
1774 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1775 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
1776 !(*total_flags & FIF_FCSFAIL));
1777 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
1778 !(*total_flags & FIF_PLCPFAIL));
1779 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
1780 !(*total_flags & FIF_CONTROL));
1781 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
1782 !(*total_flags & FIF_PROMISC_IN_BSS));
1783 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
1784 !(*total_flags & FIF_PROMISC_IN_BSS));
1785 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
1786 rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
1787 !(*total_flags & FIF_ALLMULTI));
1788 rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
1789 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1790}
1791
95ea3627
ID		 1792static int rt2500pci_set_retry_limit(struct ieee80211_hw *hw,
1793 u32 short_retry, u32 long_retry)
1794{
1795 struct rt2x00_dev *rt2x00dev = hw->priv;
1796 u32 reg;
1797
1798 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1799 rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1800 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1801 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1802
1803 return 0;
1804}
1805
1806static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1807{
1808 struct rt2x00_dev *rt2x00dev = hw->priv;
1809 u64 tsf;
1810 u32 reg;
1811
1812 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1813 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1814 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1815 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1816
1817 return tsf;
1818}
1819
1820static void rt2500pci_reset_tsf(struct ieee80211_hw *hw)
1821{
1822 struct rt2x00_dev *rt2x00dev = hw->priv;
1823
1824 rt2x00pci_register_write(rt2x00dev, CSR16, 0);
1825 rt2x00pci_register_write(rt2x00dev, CSR17, 0);
1826}
1827
5957da4c
ID		 1828static int rt2500pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1829 struct ieee80211_tx_control *control)
1830{
1831 struct rt2x00_dev *rt2x00dev = hw->priv;
1832 struct rt2x00_intf *intf = vif_to_intf(control->vif);
1833 struct queue_entry_priv_pci_tx *priv_tx;
1834 struct skb_frame_desc *skbdesc;
1835
1836 if (unlikely(!intf->beacon))
1837 return -ENOBUFS;
1838
1839 priv_tx = intf->beacon->priv_data;
1840
1841 /*
1842 * Fill in skb descriptor
1843 */
1844 skbdesc = get_skb_frame_desc(skb);
1845 memset(skbdesc, 0, sizeof(*skbdesc));
baf26a7e 1846 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
5957da4c
ID		 1847 skbdesc->data = skb->data;
1848 skbdesc->data_len = skb->len;
1849 skbdesc->desc = priv_tx->desc;
1850 skbdesc->desc_len = intf->beacon->queue->desc_size;
1851 skbdesc->entry = intf->beacon;
1852
1853 /*
1854 * mac80211 doesn't provide the control->queue variable
1855 * for beacons. Set our own queue identification so
1856 * it can be used during descriptor initialization.
1857 */
1858 control->queue = RT2X00_BCN_QUEUE_BEACON;
1859 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
1860
1861 /*
1862 * Enable beacon generation.
1863 * Write entire beacon with descriptor to register,
1864 * and kick the beacon generator.
1865 */
1866 memcpy(priv_tx->data, skb->data, skb->len);
1867 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);
1868
1869 return 0;
1870}
1871
95ea3627
ID		 1872static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1873{
1874 struct rt2x00_dev *rt2x00dev = hw->priv;
1875 u32 reg;
1876
1877 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1878 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1879}
1880
1881static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1882 .tx = rt2x00mac_tx,
4150c572
JB		 1883 .start = rt2x00mac_start,
1884 .stop = rt2x00mac_stop,
95ea3627
ID		 1885 .add_interface = rt2x00mac_add_interface,
1886 .remove_interface = rt2x00mac_remove_interface,
1887 .config = rt2x00mac_config,
1888 .config_interface = rt2x00mac_config_interface,
4150c572 1889 .configure_filter = rt2500pci_configure_filter,
95ea3627
ID		 1890 .get_stats = rt2x00mac_get_stats,
1891 .set_retry_limit = rt2500pci_set_retry_limit,
471b3efd 1892 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627
ID		 1893 .conf_tx = rt2x00mac_conf_tx,
1894 .get_tx_stats = rt2x00mac_get_tx_stats,
1895 .get_tsf = rt2500pci_get_tsf,
1896 .reset_tsf = rt2500pci_reset_tsf,
5957da4c 1897 .beacon_update = rt2500pci_beacon_update,
95ea3627
ID		 1898 .tx_last_beacon = rt2500pci_tx_last_beacon,
1899};
1900
1901static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1902 .irq_handler = rt2500pci_interrupt,
1903 .probe_hw = rt2500pci_probe_hw,
1904 .initialize = rt2x00pci_initialize,
1905 .uninitialize = rt2x00pci_uninitialize,
837e7f24
ID		 1906 .init_rxentry = rt2500pci_init_rxentry,
1907 .init_txentry = rt2500pci_init_txentry,
95ea3627 1908 .set_device_state = rt2500pci_set_device_state,
95ea3627 1909 .rfkill_poll = rt2500pci_rfkill_poll,
95ea3627
ID		 1910 .link_stats = rt2500pci_link_stats,
1911 .reset_tuner = rt2500pci_reset_tuner,
1912 .link_tuner = rt2500pci_link_tuner,
a9450b70 1913 .led_brightness = rt2500pci_led_brightness,
95ea3627
ID		 1914 .write_tx_desc = rt2500pci_write_tx_desc,
1915 .write_tx_data = rt2x00pci_write_tx_data,
1916 .kick_tx_queue = rt2500pci_kick_tx_queue,
1917 .fill_rxdone = rt2500pci_fill_rxdone,
6bb40dd1 1918 .config_intf = rt2500pci_config_intf,
5c58ee51 1919 .config_preamble = rt2500pci_config_preamble,
95ea3627
ID		 1920 .config = rt2500pci_config,
1921};
1922
181d6902
ID		 1923static const struct data_queue_desc rt2500pci_queue_rx = {
1924 .entry_num = RX_ENTRIES,
1925 .data_size = DATA_FRAME_SIZE,
1926 .desc_size = RXD_DESC_SIZE,
1927 .priv_size = sizeof(struct queue_entry_priv_pci_rx),
1928};
1929
1930static const struct data_queue_desc rt2500pci_queue_tx = {
1931 .entry_num = TX_ENTRIES,
1932 .data_size = DATA_FRAME_SIZE,
1933 .desc_size = TXD_DESC_SIZE,
1934 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1935};
1936
1937static const struct data_queue_desc rt2500pci_queue_bcn = {
1938 .entry_num = BEACON_ENTRIES,
1939 .data_size = MGMT_FRAME_SIZE,
1940 .desc_size = TXD_DESC_SIZE,
1941 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1942};
1943
1944static const struct data_queue_desc rt2500pci_queue_atim = {
1945 .entry_num = ATIM_ENTRIES,
1946 .data_size = DATA_FRAME_SIZE,
1947 .desc_size = TXD_DESC_SIZE,
1948 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1949};
1950
95ea3627 1951static const struct rt2x00_ops rt2500pci_ops = {
2360157c 1952 .name = KBUILD_MODNAME,
6bb40dd1
ID		 1953 .max_sta_intf = 1,
1954 .max_ap_intf = 1,
95ea3627
ID		 1955 .eeprom_size = EEPROM_SIZE,
1956 .rf_size = RF_SIZE,
181d6902
ID		 1957 .rx = &rt2500pci_queue_rx,
1958 .tx = &rt2500pci_queue_tx,
1959 .bcn = &rt2500pci_queue_bcn,
1960 .atim = &rt2500pci_queue_atim,
95ea3627
ID		 1961 .lib = &rt2500pci_rt2x00_ops,
1962 .hw = &rt2500pci_mac80211_ops,
1963#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1964 .debugfs = &rt2500pci_rt2x00debug,
1965#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1966};
1967
1968/*
1969 * RT2500pci module information.
1970 */
1971static struct pci_device_id rt2500pci_device_table[] = {
1972 { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1973 { 0, }
1974};
1975
1976MODULE_AUTHOR(DRV_PROJECT);
1977MODULE_VERSION(DRV_VERSION);
1978MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1979MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1980MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1981MODULE_LICENSE("GPL");
1982
1983static struct pci_driver rt2500pci_driver = {
2360157c 1984 .name = KBUILD_MODNAME,
95ea3627
ID		 1985 .id_table = rt2500pci_device_table,
1986 .probe = rt2x00pci_probe,
1987 .remove = __devexit_p(rt2x00pci_remove),
1988 .suspend = rt2x00pci_suspend,
1989 .resume = rt2x00pci_resume,
1990};
1991
1992static int __init rt2500pci_init(void)
1993{
1994 return pci_register_driver(&rt2500pci_driver);
1995}
1996
1997static void __exit rt2500pci_exit(void)
1998{
1999 pci_unregister_driver(&rt2500pci_driver);
2000}
2001
2002module_init(rt2500pci_init);
2003module_exit(rt2500pci_exit);
Linux kernel - Deliverables
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