projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
rt2800: initialize BBP_R83 on all subroutines (except 5592)
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
CommitLineData
89297425 1/*
96481b20 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
a5ea2f02 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 6
9c9a0d14 7 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32/*
33 Module: rt2800lib
34 Abstract: rt2800 generic device routines.
35 */
36
f31c9a8c 37#include <linux/crc-ccitt.h>
89297425
BZ		 38#include <linux/kernel.h>
39#include <linux/module.h>
5a0e3ad6 40#include <linux/slab.h>
89297425
BZ		 41
42#include "rt2x00.h"
43#include "rt2800lib.h"
44#include "rt2800.h"
45
89297425
BZ		 46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60#define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64#define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66#define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
baff8006
HS		 70static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71{
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
75 return false;
76
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
81 return true;
82
ec9c4989 83 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
baff8006
HS		 84 return false;
85}
86
fcf51541
BZ		 87static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
89297425
BZ		 89{
90 u32 reg;
91
92 mutex_lock(&rt2x00dev->csr_mutex);
93
94 /*
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
97 */
98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
efc7d36f 104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 105
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107 }
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110}
89297425 111
fcf51541
BZ		 112static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
89297425
BZ		 114{
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
126 */
127 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 reg = 0;
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
efc7d36f 132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142}
89297425 143
fcf51541
BZ		 144static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
89297425
BZ		 146{
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166}
89297425 167
fcf51541
BZ		 168static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
89297425
BZ		 170{
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197}
89297425 198
fcf51541
BZ		 199static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
89297425
BZ		 201{
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222}
89297425 223
16ebd608
WH		 224static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
225{
226 u32 reg;
227 int i, count;
228
229 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
230 if (rt2x00_get_field32(reg, WLAN_EN))
231 return 0;
232
233 rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
234 rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
235 rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
236 rt2x00_set_field32(&reg, WLAN_EN, 1);
237 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
238
239 udelay(REGISTER_BUSY_DELAY);
240
241 count = 0;
242 do {
243 /*
244 * Check PLL_LD & XTAL_RDY.
245 */
246 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
247 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
248 if (rt2x00_get_field32(reg, PLL_LD) &&
249 rt2x00_get_field32(reg, XTAL_RDY))
250 break;
251 udelay(REGISTER_BUSY_DELAY);
252 }
253
254 if (i >= REGISTER_BUSY_COUNT) {
255
256 if (count >= 10)
257 return -EIO;
258
259 rt2800_register_write(rt2x00dev, 0x58, 0x018);
260 udelay(REGISTER_BUSY_DELAY);
261 rt2800_register_write(rt2x00dev, 0x58, 0x418);
262 udelay(REGISTER_BUSY_DELAY);
263 rt2800_register_write(rt2x00dev, 0x58, 0x618);
264 udelay(REGISTER_BUSY_DELAY);
265 count++;
266 } else {
267 count = 0;
268 }
269
270 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
271 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
272 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
273 rt2x00_set_field32(&reg, WLAN_RESET, 1);
274 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
275 udelay(10);
276 rt2x00_set_field32(&reg, WLAN_RESET, 0);
277 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
278 udelay(10);
279 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
280 } while (count != 0);
281
282 return 0;
283}
284
89297425
BZ		 285void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
286 const u8 command, const u8 token,
287 const u8 arg0, const u8 arg1)
288{
289 u32 reg;
290
ee303e54 291 /*
cea90e55 292 * SOC devices don't support MCU requests.
ee303e54 293 */
cea90e55 294 if (rt2x00_is_soc(rt2x00dev))
ee303e54 295 return;
89297425
BZ		 296
297 mutex_lock(&rt2x00dev->csr_mutex);
298
299 /*
300 * Wait until the MCU becomes available, afterwards we
301 * can safely write the new data into the register.
302 */
303 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
304 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
305 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
306 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
307 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
308 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
309
310 reg = 0;
311 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
312 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
313 }
314
315 mutex_unlock(&rt2x00dev->csr_mutex);
316}
317EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 318
5ffddc49
ID		 319int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
320{
321 unsigned int i = 0;
322 u32 reg;
323
324 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
325 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
326 if (reg && reg != ~0)
327 return 0;
328 msleep(1);
329 }
330
ec9c4989 331 rt2x00_err(rt2x00dev, "Unstable hardware\n");
5ffddc49
ID		 332 return -EBUSY;
333}
334EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
335
67a4c1e2
GW		 336int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
337{
338 unsigned int i;
339 u32 reg;
340
08e53100
HS		 341 /*
342 * Some devices are really slow to respond here. Wait a whole second
343 * before timing out.
344 */
67a4c1e2
GW		 345 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
346 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
347 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
348 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
349 return 0;
350
08e53100 351 msleep(10);
67a4c1e2
GW		 352 }
353
ec9c4989 354 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
67a4c1e2
GW		 355 return -EACCES;
356}
357EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
358
f7b395e9
JK		 359void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
360{
361 u32 reg;
362
363 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
364 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
365 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
366 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
367 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
368 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
369 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
370}
371EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
372
f31c9a8c
ID		 373static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
374{
375 u16 fw_crc;
376 u16 crc;
377
378 /*
379 * The last 2 bytes in the firmware array are the crc checksum itself,
380 * this means that we should never pass those 2 bytes to the crc
381 * algorithm.
382 */
383 fw_crc = (data[len - 2] << 8 | data[len - 1]);
384
385 /*
386 * Use the crc ccitt algorithm.
387 * This will return the same value as the legacy driver which
388 * used bit ordering reversion on the both the firmware bytes
389 * before input input as well as on the final output.
390 * Obviously using crc ccitt directly is much more efficient.
391 */
392 crc = crc_ccitt(~0, data, len - 2);
393
394 /*
395 * There is a small difference between the crc-itu-t + bitrev and
396 * the crc-ccitt crc calculation. In the latter method the 2 bytes
397 * will be swapped, use swab16 to convert the crc to the correct
398 * value.
399 */
400 crc = swab16(crc);
401
402 return fw_crc == crc;
403}
404
405int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
406 const u8 *data, const size_t len)
407{
408 size_t offset = 0;
409 size_t fw_len;
410 bool multiple;
411
412 /*
413 * PCI(e) & SOC devices require firmware with a length
414 * of 8kb. USB devices require firmware files with a length
415 * of 4kb. Certain USB chipsets however require different firmware,
416 * which Ralink only provides attached to the original firmware
417 * file. Thus for USB devices, firmware files have a length
a89534ed
WH		 418 * which is a multiple of 4kb. The firmware for rt3290 chip also
419 * have a length which is a multiple of 4kb.
f31c9a8c 420 */
a89534ed 421 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
f31c9a8c 422 fw_len = 4096;
a89534ed 423 else
f31c9a8c 424 fw_len = 8192;
f31c9a8c 425
a89534ed 426 multiple = true;
f31c9a8c
ID		 427 /*
428 * Validate the firmware length
429 */
430 if (len != fw_len && (!multiple || (len % fw_len) != 0))
431 return FW_BAD_LENGTH;
432
433 /*
434 * Check if the chipset requires one of the upper parts
435 * of the firmware.
436 */
437 if (rt2x00_is_usb(rt2x00dev) &&
438 !rt2x00_rt(rt2x00dev, RT2860) &&
439 !rt2x00_rt(rt2x00dev, RT2872) &&
440 !rt2x00_rt(rt2x00dev, RT3070) &&
441 ((len / fw_len) == 1))
442 return FW_BAD_VERSION;
443
444 /*
445 * 8kb firmware files must be checked as if it were
446 * 2 separate firmware files.
447 */
448 while (offset < len) {
449 if (!rt2800_check_firmware_crc(data + offset, fw_len))
450 return FW_BAD_CRC;
451
452 offset += fw_len;
453 }
454
455 return FW_OK;
456}
457EXPORT_SYMBOL_GPL(rt2800_check_firmware);
458
459int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
460 const u8 *data, const size_t len)
461{
462 unsigned int i;
463 u32 reg;
16ebd608
WH		 464 int retval;
465
466 if (rt2x00_rt(rt2x00dev, RT3290)) {
467 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
468 if (retval)
469 return -EBUSY;
470 }
f31c9a8c
ID		 471
472 /*
b9eca242
ID		 473 * If driver doesn't wake up firmware here,
474 * rt2800_load_firmware will hang forever when interface is up again.
f31c9a8c 475 */
b9eca242 476 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
f31c9a8c 477
f31c9a8c
ID		 478 /*
479 * Wait for stable hardware.
480 */
5ffddc49 481 if (rt2800_wait_csr_ready(rt2x00dev))
f31c9a8c 482 return -EBUSY;
f31c9a8c 483
adde5882 484 if (rt2x00_is_pci(rt2x00dev)) {
a89534ed
WH		 485 if (rt2x00_rt(rt2x00dev, RT3290) ||
486 rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884
JL		 487 rt2x00_rt(rt2x00dev, RT5390) ||
488 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 489 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
490 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
491 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
492 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
493 }
f31c9a8c 494 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
adde5882 495 }
f31c9a8c 496
b7e1d225
JK		 497 rt2800_disable_wpdma(rt2x00dev);
498
f31c9a8c
ID		 499 /*
500 * Write firmware to the device.
501 */
502 rt2800_drv_write_firmware(rt2x00dev, data, len);
503
504 /*
505 * Wait for device to stabilize.
506 */
507 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
508 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
509 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
510 break;
511 msleep(1);
512 }
513
514 if (i == REGISTER_BUSY_COUNT) {
ec9c4989 515 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
f31c9a8c
ID		 516 return -EBUSY;
517 }
518
4ed1dd2a
SG		 519 /*
520 * Disable DMA, will be reenabled later when enabling
521 * the radio.
522 */
f7b395e9 523 rt2800_disable_wpdma(rt2x00dev);
4ed1dd2a 524
f31c9a8c
ID		 525 /*
526 * Initialize firmware.
527 */
528 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
529 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
8756130b 530 if (rt2x00_is_usb(rt2x00dev)) {
0c17cf96 531 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
8756130b
SG		 532 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
533 }
f31c9a8c
ID		 534 msleep(1);
535
536 return 0;
537}
538EXPORT_SYMBOL_GPL(rt2800_load_firmware);
539
0c5879bc
ID		 540void rt2800_write_tx_data(struct queue_entry *entry,
541 struct txentry_desc *txdesc)
59679b91 542{
0c5879bc 543 __le32 *txwi = rt2800_drv_get_txwi(entry);
59679b91 544 u32 word;
557985ae 545 int i;
59679b91
GW		 546
547 /*
548 * Initialize TX Info descriptor
549 */
550 rt2x00_desc_read(txwi, 0, &word);
551 rt2x00_set_field32(&word, TXWI_W0_FRAG,
552 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
84804cdc
ID		 553 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
554 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
59679b91
GW		 555 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
556 rt2x00_set_field32(&word, TXWI_W0_TS,
557 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
558 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
559 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
26a1d07f
HS		 560 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
561 txdesc->u.ht.mpdu_density);
562 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
563 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
59679b91
GW		 564 rt2x00_set_field32(&word, TXWI_W0_BW,
565 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
566 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
567 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
26a1d07f 568 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
59679b91
GW		 569 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
570 rt2x00_desc_write(txwi, 0, word);
571
572 rt2x00_desc_read(txwi, 1, &word);
573 rt2x00_set_field32(&word, TXWI_W1_ACK,
574 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
575 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
576 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
26a1d07f 577 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
59679b91
GW		 578 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
579 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
a2b1328a 580 txdesc->key_idx : txdesc->u.ht.wcid);
59679b91
GW		 581 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
582 txdesc->length);
2b23cdaa 583 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
bc8a979e 584 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
59679b91
GW		 585 rt2x00_desc_write(txwi, 1, word);
586
587 /*
557985ae
SG		 588 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
589 * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
59679b91
GW		 590 * When TXD_W3_WIV is set to 1 it will use the IV data
591 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
592 * crypto entry in the registers should be used to encrypt the frame.
557985ae
SG		 593 *
594 * Nulify all remaining words as well, we don't know how to program them.
59679b91 595 */
557985ae
SG		 596 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
597 _rt2x00_desc_write(txwi, i, 0);
59679b91 598}
0c5879bc 599EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
59679b91 600
ff6133be 601static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
2de64dd2 602{
7fc41755
LT		 603 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
604 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
605 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
74861922
ID		 606 u16 eeprom;
607 u8 offset0;
608 u8 offset1;
609 u8 offset2;
610
e5ef5bad 611 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
74861922
ID		 612 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
613 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
614 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
615 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
616 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
617 } else {
618 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
619 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
620 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
621 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
622 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
623 }
624
625 /*
626 * Convert the value from the descriptor into the RSSI value
627 * If the value in the descriptor is 0, it is considered invalid
628 * and the default (extremely low) rssi value is assumed
629 */
630 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
631 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
632 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
633
634 /*
635 * mac80211 only accepts a single RSSI value. Calculating the
636 * average doesn't deliver a fair answer either since -60:-60 would
637 * be considered equally good as -50:-70 while the second is the one
638 * which gives less energy...
639 */
640 rssi0 = max(rssi0, rssi1);
7fc41755 641 return (int)max(rssi0, rssi2);
74861922
ID		 642}
643
644void rt2800_process_rxwi(struct queue_entry *entry,
645 struct rxdone_entry_desc *rxdesc)
646{
647 __le32 *rxwi = (__le32 *) entry->skb->data;
2de64dd2
GW		 648 u32 word;
649
650 rt2x00_desc_read(rxwi, 0, &word);
651
652 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
653 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
654
655 rt2x00_desc_read(rxwi, 1, &word);
656
657 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
658 rxdesc->flags |= RX_FLAG_SHORT_GI;
659
660 if (rt2x00_get_field32(word, RXWI_W1_BW))
661 rxdesc->flags |= RX_FLAG_40MHZ;
662
663 /*
664 * Detect RX rate, always use MCS as signal type.
665 */
666 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
667 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
668 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
669
670 /*
671 * Mask of 0x8 bit to remove the short preamble flag.
672 */
673 if (rxdesc->rate_mode == RATE_MODE_CCK)
674 rxdesc->signal &= ~0x8;
675
676 rt2x00_desc_read(rxwi, 2, &word);
677
74861922
ID		 678 /*
679 * Convert descriptor AGC value to RSSI value.
680 */
681 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
f0bda571
SG		 682 /*
683 * Remove RXWI descriptor from start of the buffer.
684 */
685 skb_pull(entry->skb, entry->queue->winfo_size);
2de64dd2
GW		 686}
687EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
688
31937c42 689void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
14433331
HS		 690{
691 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b34793ee 692 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
14433331
HS		 693 struct txdone_entry_desc txdesc;
694 u32 word;
695 u16 mcs, real_mcs;
b34793ee 696 int aggr, ampdu;
14433331
HS		 697
698 /*
699 * Obtain the status about this packet.
700 */
701 txdesc.flags = 0;
14433331 702 rt2x00_desc_read(txwi, 0, &word);
b34793ee 703
14433331 704 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
b34793ee
HS		 705 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
706
14433331 707 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
b34793ee
HS		 708 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
709
710 /*
711 * If a frame was meant to be sent as a single non-aggregated MPDU
712 * but ended up in an aggregate the used tx rate doesn't correlate
713 * with the one specified in the TXWI as the whole aggregate is sent
714 * with the same rate.
715 *
716 * For example: two frames are sent to rt2x00, the first one sets
717 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
718 * and requests MCS15. If the hw aggregates both frames into one
719 * AMDPU the tx status for both frames will contain MCS7 although
720 * the frame was sent successfully.
721 *
722 * Hence, replace the requested rate with the real tx rate to not
723 * confuse the rate control algortihm by providing clearly wrong
724 * data.
725 */
5356d963 726 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
b34793ee
HS		 727 skbdesc->tx_rate_idx = real_mcs;
728 mcs = real_mcs;
729 }
14433331 730
f16d2db7
HS		 731 if (aggr == 1 || ampdu == 1)
732 __set_bit(TXDONE_AMPDU, &txdesc.flags);
733
14433331
HS		 734 /*
735 * Ralink has a retry mechanism using a global fallback
736 * table. We setup this fallback table to try the immediate
737 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
738 * always contains the MCS used for the last transmission, be
739 * it successful or not.
740 */
741 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
742 /*
743 * Transmission succeeded. The number of retries is
744 * mcs - real_mcs
745 */
746 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
747 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
748 } else {
749 /*
750 * Transmission failed. The number of retries is
751 * always 7 in this case (for a total number of 8
752 * frames sent).
753 */
754 __set_bit(TXDONE_FAILURE, &txdesc.flags);
755 txdesc.retry = rt2x00dev->long_retry;
756 }
757
758 /*
759 * the frame was retried at least once
760 * -> hw used fallback rates
761 */
762 if (txdesc.retry)
763 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
764
765 rt2x00lib_txdone(entry, &txdesc);
766}
767EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
768
f0194b2d
GW		 769void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
770{
771 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
772 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
773 unsigned int beacon_base;
739fd940 774 unsigned int padding_len;
d76dfc61 775 u32 orig_reg, reg;
f0bda571 776 const int txwi_desc_size = entry->queue->winfo_size;
f0194b2d
GW		 777
778 /*
779 * Disable beaconing while we are reloading the beacon data,
780 * otherwise we might be sending out invalid data.
781 */
782 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
d76dfc61 783 orig_reg = reg;
f0194b2d
GW		 784 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
785 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
786
787 /*
788 * Add space for the TXWI in front of the skb.
789 */
f0bda571 790 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
f0194b2d
GW		 791
792 /*
793 * Register descriptor details in skb frame descriptor.
794 */
795 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
796 skbdesc->desc = entry->skb->data;
f0bda571 797 skbdesc->desc_len = txwi_desc_size;
f0194b2d
GW		 798
799 /*
800 * Add the TXWI for the beacon to the skb.
801 */
0c5879bc 802 rt2800_write_tx_data(entry, txdesc);
f0194b2d
GW		 803
804 /*
805 * Dump beacon to userspace through debugfs.
806 */
807 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
808
809 /*
739fd940 810 * Write entire beacon with TXWI and padding to register.
f0194b2d 811 */
739fd940 812 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
d76dfc61 813 if (padding_len && skb_pad(entry->skb, padding_len)) {
ec9c4989 814 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
d76dfc61
SF		 815 /* skb freed by skb_pad() on failure */
816 entry->skb = NULL;
817 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
818 return;
819 }
820
f0194b2d 821 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
739fd940
WK		 822 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
823 entry->skb->len + padding_len);
f0194b2d
GW		 824
825 /*
826 * Enable beaconing again.
827 */
f0194b2d
GW		 828 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
829 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
830
831 /*
832 * Clean up beacon skb.
833 */
834 dev_kfree_skb_any(entry->skb);
835 entry->skb = NULL;
836}
50e888ea 837EXPORT_SYMBOL_GPL(rt2800_write_beacon);
f0194b2d 838
69cf36a4
HS		 839static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
840 unsigned int beacon_base)
fdb87251
HS		 841{
842 int i;
0879f875 843 const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
fdb87251
HS		 844
845 /*
846 * For the Beacon base registers we only need to clear
847 * the whole TXWI which (when set to 0) will invalidate
848 * the entire beacon.
849 */
f0bda571 850 for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
fdb87251
HS		 851 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
852}
853
69cf36a4
HS		 854void rt2800_clear_beacon(struct queue_entry *entry)
855{
856 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
857 u32 reg;
858
859 /*
860 * Disable beaconing while we are reloading the beacon data,
861 * otherwise we might be sending out invalid data.
862 */
863 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
864 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
865 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
866
867 /*
868 * Clear beacon.
869 */
870 rt2800_clear_beacon_register(rt2x00dev,
871 HW_BEACON_OFFSET(entry->entry_idx));
872
873 /*
874 * Enabled beaconing again.
875 */
876 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
877 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
878}
879EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
880
f4450616
BZ		 881#ifdef CONFIG_RT2X00_LIB_DEBUGFS
882const struct rt2x00debug rt2800_rt2x00debug = {
883 .owner = THIS_MODULE,
884 .csr = {
885 .read = rt2800_register_read,
886 .write = rt2800_register_write,
887 .flags = RT2X00DEBUGFS_OFFSET,
888 .word_base = CSR_REG_BASE,
889 .word_size = sizeof(u32),
890 .word_count = CSR_REG_SIZE / sizeof(u32),
891 },
892 .eeprom = {
893 .read = rt2x00_eeprom_read,
894 .write = rt2x00_eeprom_write,
895 .word_base = EEPROM_BASE,
896 .word_size = sizeof(u16),
897 .word_count = EEPROM_SIZE / sizeof(u16),
898 },
899 .bbp = {
900 .read = rt2800_bbp_read,
901 .write = rt2800_bbp_write,
902 .word_base = BBP_BASE,
903 .word_size = sizeof(u8),
904 .word_count = BBP_SIZE / sizeof(u8),
905 },
906 .rf = {
907 .read = rt2x00_rf_read,
908 .write = rt2800_rf_write,
909 .word_base = RF_BASE,
910 .word_size = sizeof(u32),
911 .word_count = RF_SIZE / sizeof(u32),
912 },
f2bd7f16
AA		 913 .rfcsr = {
914 .read = rt2800_rfcsr_read,
915 .write = rt2800_rfcsr_write,
916 .word_base = RFCSR_BASE,
917 .word_size = sizeof(u8),
918 .word_count = RFCSR_SIZE / sizeof(u8),
919 },
f4450616
BZ		 920};
921EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
922#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
923
924int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
925{
926 u32 reg;
927
a89534ed
WH		 928 if (rt2x00_rt(rt2x00dev, RT3290)) {
929 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
930 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
931 } else {
99bdf51a
GW		 932 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
933 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
a89534ed 934 }
f4450616
BZ		 935}
936EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
937
938#ifdef CONFIG_RT2X00_LIB_LEDS
939static void rt2800_brightness_set(struct led_classdev *led_cdev,
940 enum led_brightness brightness)
941{
942 struct rt2x00_led *led =
943 container_of(led_cdev, struct rt2x00_led, led_dev);
944 unsigned int enabled = brightness != LED_OFF;
945 unsigned int bg_mode =
946 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
947 unsigned int polarity =
948 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
949 EEPROM_FREQ_LED_POLARITY);
950 unsigned int ledmode =
951 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
952 EEPROM_FREQ_LED_MODE);
44704e5d 953 u32 reg;
f4450616 954
44704e5d
LE		 955 /* Check for SoC (SOC devices don't support MCU requests) */
956 if (rt2x00_is_soc(led->rt2x00dev)) {
957 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
958
959 /* Set LED Polarity */
960 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
961
962 /* Set LED Mode */
963 if (led->type == LED_TYPE_RADIO) {
964 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
965 enabled ? 3 : 0);
966 } else if (led->type == LED_TYPE_ASSOC) {
967 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
968 enabled ? 3 : 0);
969 } else if (led->type == LED_TYPE_QUALITY) {
970 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
971 enabled ? 3 : 0);
972 }
973
974 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
975
976 } else {
977 if (led->type == LED_TYPE_RADIO) {
978 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
979 enabled ? 0x20 : 0);
980 } else if (led->type == LED_TYPE_ASSOC) {
981 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
982 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
983 } else if (led->type == LED_TYPE_QUALITY) {
984 /*
985 * The brightness is divided into 6 levels (0 - 5),
986 * The specs tell us the following levels:
987 * 0, 1 ,3, 7, 15, 31
988 * to determine the level in a simple way we can simply
989 * work with bitshifting:
990 * (1 << level) - 1
991 */
992 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
993 (1 << brightness / (LED_FULL / 6)) - 1,
994 polarity);
995 }
f4450616
BZ		 996 }
997}
998
b3579d6a 999static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 1000 struct rt2x00_led *led, enum led_type type)
1001{
1002 led->rt2x00dev = rt2x00dev;
1003 led->type = type;
1004 led->led_dev.brightness_set = rt2800_brightness_set;
f4450616
BZ		 1005 led->flags = LED_INITIALIZED;
1006}
f4450616
BZ		 1007#endif /* CONFIG_RT2X00_LIB_LEDS */
1008
1009/*
1010 * Configuration handlers.
1011 */
a2b1328a
HS		 1012static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1013 const u8 *address,
1014 int wcid)
f4450616
BZ		 1015{
1016 struct mac_wcid_entry wcid_entry;
a2b1328a
HS		 1017 u32 offset;
1018
1019 offset = MAC_WCID_ENTRY(wcid);
1020
1021 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1022 if (address)
1023 memcpy(wcid_entry.mac, address, ETH_ALEN);
1024
1025 rt2800_register_multiwrite(rt2x00dev, offset,
1026 &wcid_entry, sizeof(wcid_entry));
1027}
1028
1029static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1030{
1031 u32 offset;
1032 offset = MAC_WCID_ATTR_ENTRY(wcid);
1033 rt2800_register_write(rt2x00dev, offset, 0);
1034}
1035
1036static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1037 int wcid, u32 bssidx)
1038{
1039 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1040 u32 reg;
1041
1042 /*
1043 * The BSS Idx numbers is split in a main value of 3 bits,
1044 * and a extended field for adding one additional bit to the value.
1045 */
1046 rt2800_register_read(rt2x00dev, offset, &reg);
1047 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1048 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1049 (bssidx & 0x8) >> 3);
1050 rt2800_register_write(rt2x00dev, offset, reg);
1051}
1052
1053static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1054 struct rt2x00lib_crypto *crypto,
1055 struct ieee80211_key_conf *key)
1056{
f4450616
BZ		 1057 struct mac_iveiv_entry iveiv_entry;
1058 u32 offset;
1059 u32 reg;
1060
1061 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1062
e4a0ab34
ID		 1063 if (crypto->cmd == SET_KEY) {
1064 rt2800_register_read(rt2x00dev, offset, &reg);
1065 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1066 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1067 /*
1068 * Both the cipher as the BSS Idx numbers are split in a main
1069 * value of 3 bits, and a extended field for adding one additional
1070 * bit to the value.
1071 */
1072 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1073 (crypto->cipher & 0x7));
1074 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1075 (crypto->cipher & 0x8) >> 3);
e4a0ab34
ID		 1076 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1077 rt2800_register_write(rt2x00dev, offset, reg);
1078 } else {
a2b1328a
HS		 1079 /* Delete the cipher without touching the bssidx */
1080 rt2800_register_read(rt2x00dev, offset, &reg);
1081 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1082 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1083 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1084 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1085 rt2800_register_write(rt2x00dev, offset, reg);
e4a0ab34 1086 }
f4450616
BZ		 1087
1088 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1089
1090 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1091 if ((crypto->cipher == CIPHER_TKIP) ||
1092 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1093 (crypto->cipher == CIPHER_AES))
1094 iveiv_entry.iv[3] |= 0x20;
1095 iveiv_entry.iv[3] |= key->keyidx << 6;
1096 rt2800_register_multiwrite(rt2x00dev, offset,
1097 &iveiv_entry, sizeof(iveiv_entry));
f4450616
BZ		 1098}
1099
1100int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1101 struct rt2x00lib_crypto *crypto,
1102 struct ieee80211_key_conf *key)
1103{
1104 struct hw_key_entry key_entry;
1105 struct rt2x00_field32 field;
1106 u32 offset;
1107 u32 reg;
1108
1109 if (crypto->cmd == SET_KEY) {
1110 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1111
1112 memcpy(key_entry.key, crypto->key,
1113 sizeof(key_entry.key));
1114 memcpy(key_entry.tx_mic, crypto->tx_mic,
1115 sizeof(key_entry.tx_mic));
1116 memcpy(key_entry.rx_mic, crypto->rx_mic,
1117 sizeof(key_entry.rx_mic));
1118
1119 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1120 rt2800_register_multiwrite(rt2x00dev, offset,
1121 &key_entry, sizeof(key_entry));
1122 }
1123
1124 /*
1125 * The cipher types are stored over multiple registers
1126 * starting with SHARED_KEY_MODE_BASE each word will have
1127 * 32 bits and contains the cipher types for 2 bssidx each.
1128 * Using the correct defines correctly will cause overhead,
1129 * so just calculate the correct offset.
1130 */
1131 field.bit_offset = 4 * (key->hw_key_idx % 8);
1132 field.bit_mask = 0x7 << field.bit_offset;
1133
1134 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1135
1136 rt2800_register_read(rt2x00dev, offset, &reg);
1137 rt2x00_set_field32(&reg, field,
1138 (crypto->cmd == SET_KEY) * crypto->cipher);
1139 rt2800_register_write(rt2x00dev, offset, reg);
1140
1141 /*
1142 * Update WCID information
1143 */
a2b1328a
HS		 1144 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1145 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1146 crypto->bssidx);
1147 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1148
1149 return 0;
1150}
1151EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1152
a2b1328a 1153static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1ed3811c 1154{
a2b1328a 1155 struct mac_wcid_entry wcid_entry;
1ed3811c 1156 int idx;
a2b1328a 1157 u32 offset;
1ed3811c
HS		 1158
1159 /*
a2b1328a
HS		 1160 * Search for the first free WCID entry and return the corresponding
1161 * index.
1ed3811c
HS		 1162 *
1163 * Make sure the WCID starts _after_ the last possible shared key
1164 * entry (>32).
1165 *
1166 * Since parts of the pairwise key table might be shared with
1167 * the beacon frame buffers 6 & 7 we should only write into the
1168 * first 222 entries.
1169 */
1170 for (idx = 33; idx <= 222; idx++) {
a2b1328a
HS		 1171 offset = MAC_WCID_ENTRY(idx);
1172 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1173 sizeof(wcid_entry));
1174 if (is_broadcast_ether_addr(wcid_entry.mac))
1ed3811c
HS		 1175 return idx;
1176 }
a2b1328a
HS		 1177
1178 /*
1179 * Use -1 to indicate that we don't have any more space in the WCID
1180 * table.
1181 */
1ed3811c
HS		 1182 return -1;
1183}
1184
f4450616
BZ		 1185int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1186 struct rt2x00lib_crypto *crypto,
1187 struct ieee80211_key_conf *key)
1188{
1189 struct hw_key_entry key_entry;
1190 u32 offset;
1191
1192 if (crypto->cmd == SET_KEY) {
a2b1328a
HS		 1193 /*
1194 * Allow key configuration only for STAs that are
1195 * known by the hw.
1196 */
1197 if (crypto->wcid < 0)
f4450616 1198 return -ENOSPC;
a2b1328a 1199 key->hw_key_idx = crypto->wcid;
f4450616
BZ		 1200
1201 memcpy(key_entry.key, crypto->key,
1202 sizeof(key_entry.key));
1203 memcpy(key_entry.tx_mic, crypto->tx_mic,
1204 sizeof(key_entry.tx_mic));
1205 memcpy(key_entry.rx_mic, crypto->rx_mic,
1206 sizeof(key_entry.rx_mic));
1207
1208 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1209 rt2800_register_multiwrite(rt2x00dev, offset,
1210 &key_entry, sizeof(key_entry));
1211 }
1212
1213 /*
1214 * Update WCID information
1215 */
a2b1328a 1216 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1217
1218 return 0;
1219}
1220EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1221
a2b1328a
HS		 1222int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1223 struct ieee80211_sta *sta)
1224{
1225 int wcid;
1226 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1227
1228 /*
1229 * Find next free WCID.
1230 */
1231 wcid = rt2800_find_wcid(rt2x00dev);
1232
1233 /*
1234 * Store selected wcid even if it is invalid so that we can
1235 * later decide if the STA is uploaded into the hw.
1236 */
1237 sta_priv->wcid = wcid;
1238
1239 /*
1240 * No space left in the device, however, we can still communicate
1241 * with the STA -> No error.
1242 */
1243 if (wcid < 0)
1244 return 0;
1245
1246 /*
1247 * Clean up WCID attributes and write STA address to the device.
1248 */
1249 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1250 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1251 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1252 rt2x00lib_get_bssidx(rt2x00dev, vif));
1253 return 0;
1254}
1255EXPORT_SYMBOL_GPL(rt2800_sta_add);
1256
1257int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1258{
1259 /*
1260 * Remove WCID entry, no need to clean the attributes as they will
1261 * get renewed when the WCID is reused.
1262 */
1263 rt2800_config_wcid(rt2x00dev, NULL, wcid);
1264
1265 return 0;
1266}
1267EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1268
f4450616
BZ		 1269void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1270 const unsigned int filter_flags)
1271{
1272 u32 reg;
1273
1274 /*
1275 * Start configuration steps.
1276 * Note that the version error will always be dropped
1277 * and broadcast frames will always be accepted since
1278 * there is no filter for it at this time.
1279 */
1280 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1281 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1282 !(filter_flags & FIF_FCSFAIL));
1283 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1284 !(filter_flags & FIF_PLCPFAIL));
1285 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1286 !(filter_flags & FIF_PROMISC_IN_BSS));
1287 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1288 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1289 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1290 !(filter_flags & FIF_ALLMULTI));
1291 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1292 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1293 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1294 !(filter_flags & FIF_CONTROL));
1295 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1296 !(filter_flags & FIF_CONTROL));
1297 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1298 !(filter_flags & FIF_CONTROL));
1299 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1300 !(filter_flags & FIF_CONTROL));
1301 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1302 !(filter_flags & FIF_CONTROL));
1303 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1304 !(filter_flags & FIF_PSPOLL));
84e9e8eb 1305 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
48839938
HS		 1306 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1307 !(filter_flags & FIF_CONTROL));
f4450616
BZ		 1308 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1309 !(filter_flags & FIF_CONTROL));
1310 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1311}
1312EXPORT_SYMBOL_GPL(rt2800_config_filter);
1313
1314void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1315 struct rt2x00intf_conf *conf, const unsigned int flags)
1316{
f4450616 1317 u32 reg;
fa8b4b22 1318 bool update_bssid = false;
f4450616
BZ		 1319
1320 if (flags & CONFIG_UPDATE_TYPE) {
f4450616
BZ		 1321 /*
1322 * Enable synchronisation.
1323 */
1324 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
f4450616 1325 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
f4450616 1326 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
15a533c4
HS		 1327
1328 if (conf->sync == TSF_SYNC_AP_NONE) {
1329 /*
1330 * Tune beacon queue transmit parameters for AP mode
1331 */
1332 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1333 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1334 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1335 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1336 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1337 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1338 } else {
1339 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1340 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1341 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1342 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1343 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1344 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1345 }
f4450616
BZ		 1346 }
1347
1348 if (flags & CONFIG_UPDATE_MAC) {
fa8b4b22
HS		 1349 if (flags & CONFIG_UPDATE_TYPE &&
1350 conf->sync == TSF_SYNC_AP_NONE) {
1351 /*
1352 * The BSSID register has to be set to our own mac
1353 * address in AP mode.
1354 */
1355 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1356 update_bssid = true;
1357 }
1358
c600c826
ID		 1359 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1360 reg = le32_to_cpu(conf->mac[1]);
1361 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1362 conf->mac[1] = cpu_to_le32(reg);
1363 }
f4450616
BZ		 1364
1365 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1366 conf->mac, sizeof(conf->mac));
1367 }
1368
fa8b4b22 1369 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
c600c826
ID		 1370 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1371 reg = le32_to_cpu(conf->bssid[1]);
1372 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1373 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1374 conf->bssid[1] = cpu_to_le32(reg);
1375 }
f4450616
BZ		 1376
1377 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1378 conf->bssid, sizeof(conf->bssid));
1379 }
1380}
1381EXPORT_SYMBOL_GPL(rt2800_config_intf);
1382
87c1915d
HS		 1383static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1384 struct rt2x00lib_erp *erp)
1385{
1386 bool any_sta_nongf = !!(erp->ht_opmode &
1387 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1388 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1389 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1390 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1391 u32 reg;
1392
1393 /* default protection rate for HT20: OFDM 24M */
1394 mm20_rate = gf20_rate = 0x4004;
1395
1396 /* default protection rate for HT40: duplicate OFDM 24M */
1397 mm40_rate = gf40_rate = 0x4084;
1398
1399 switch (protection) {
1400 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1401 /*
1402 * All STAs in this BSS are HT20/40 but there might be
1403 * STAs not supporting greenfield mode.
1404 * => Disable protection for HT transmissions.
1405 */
1406 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1407
1408 break;
1409 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1410 /*
1411 * All STAs in this BSS are HT20 or HT20/40 but there
1412 * might be STAs not supporting greenfield mode.
1413 * => Protect all HT40 transmissions.
1414 */
1415 mm20_mode = gf20_mode = 0;
1416 mm40_mode = gf40_mode = 2;
1417
1418 break;
1419 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1420 /*
1421 * Nonmember protection:
1422 * According to 802.11n we _should_ protect all
1423 * HT transmissions (but we don't have to).
1424 *
1425 * But if cts_protection is enabled we _shall_ protect
1426 * all HT transmissions using a CCK rate.
1427 *
1428 * And if any station is non GF we _shall_ protect
1429 * GF transmissions.
1430 *
1431 * We decide to protect everything
1432 * -> fall through to mixed mode.
1433 */
1434 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1435 /*
1436 * Legacy STAs are present
1437 * => Protect all HT transmissions.
1438 */
1439 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1440
1441 /*
1442 * If erp protection is needed we have to protect HT
1443 * transmissions with CCK 11M long preamble.
1444 */
1445 if (erp->cts_protection) {
1446 /* don't duplicate RTS/CTS in CCK mode */
1447 mm20_rate = mm40_rate = 0x0003;
1448 gf20_rate = gf40_rate = 0x0003;
1449 }
1450 break;
6403eab1 1451 }
87c1915d
HS		 1452
1453 /* check for STAs not supporting greenfield mode */
1454 if (any_sta_nongf)
1455 gf20_mode = gf40_mode = 2;
1456
1457 /* Update HT protection config */
1458 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1459 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1460 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1461 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1462
1463 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1464 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1465 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1466 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1467
1468 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1469 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1470 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1471 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1472
1473 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1474 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1475 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1476 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1477}
1478
02044643
HS		 1479void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1480 u32 changed)
f4450616
BZ		 1481{
1482 u32 reg;
1483
02044643
HS		 1484 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1485 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1486 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1487 !!erp->short_preamble);
1488 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1489 !!erp->short_preamble);
1490 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1491 }
f4450616 1492
02044643
HS		 1493 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1494 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1495 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1496 erp->cts_protection ? 2 : 0);
1497 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1498 }
f4450616 1499
02044643
HS		 1500 if (changed & BSS_CHANGED_BASIC_RATES) {
1501 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1502 erp->basic_rates);
1503 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1504 }
f4450616 1505
02044643
HS		 1506 if (changed & BSS_CHANGED_ERP_SLOT) {
1507 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1508 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1509 erp->slot_time);
1510 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
f4450616 1511
02044643
HS		 1512 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1513 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1514 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1515 }
f4450616 1516
02044643
HS		 1517 if (changed & BSS_CHANGED_BEACON_INT) {
1518 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1519 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1520 erp->beacon_int * 16);
1521 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1522 }
87c1915d
HS		 1523
1524 if (changed & BSS_CHANGED_HT)
1525 rt2800_config_ht_opmode(rt2x00dev, erp);
f4450616
BZ		 1526}
1527EXPORT_SYMBOL_GPL(rt2800_config_erp);
1528
872834df
GW		 1529static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1530{
1531 u32 reg;
1532 u16 eeprom;
1533 u8 led_ctrl, led_g_mode, led_r_mode;
1534
1535 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1536 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1537 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1538 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1539 } else {
1540 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1541 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1542 }
1543 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1544
1545 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1546 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1547 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1548 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1549 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1550 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1551 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1552 if (led_ctrl == 0 || led_ctrl > 0x40) {
1553 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1554 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1555 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1556 } else {
1557 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1558 (led_g_mode << 2) | led_r_mode, 1);
1559 }
1560 }
1561}
1562
d96aa640
RJH		 1563static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1564 enum antenna ant)
1565{
1566 u32 reg;
1567 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1568 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1569
1570 if (rt2x00_is_pci(rt2x00dev)) {
1571 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1572 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1573 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1574 } else if (rt2x00_is_usb(rt2x00dev))
1575 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1576 eesk_pin, 0);
1577
99bdf51a
GW		 1578 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1579 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1580 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1581 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
d96aa640
RJH		 1582}
1583
f4450616
BZ		 1584void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1585{
1586 u8 r1;
1587 u8 r3;
d96aa640 1588 u16 eeprom;
f4450616
BZ		 1589
1590 rt2800_bbp_read(rt2x00dev, 1, &r1);
1591 rt2800_bbp_read(rt2x00dev, 3, &r3);
1592
872834df
GW		 1593 if (rt2x00_rt(rt2x00dev, RT3572) &&
1594 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1595 rt2800_config_3572bt_ant(rt2x00dev);
1596
f4450616
BZ		 1597 /*
1598 * Configure the TX antenna.
1599 */
d96aa640 1600 switch (ant->tx_chain_num) {
f4450616
BZ		 1601 case 1:
1602 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1603 break;
1604 case 2:
872834df
GW		 1605 if (rt2x00_rt(rt2x00dev, RT3572) &&
1606 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1607 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1608 else
1609 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
f4450616
BZ		 1610 break;
1611 case 3:
e22557f2 1612 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1613 break;
1614 }
1615
1616 /*
1617 * Configure the RX antenna.
1618 */
d96aa640 1619 switch (ant->rx_chain_num) {
f4450616 1620 case 1:
d96aa640
RJH		 1621 if (rt2x00_rt(rt2x00dev, RT3070) ||
1622 rt2x00_rt(rt2x00dev, RT3090) ||
03839951 1623 rt2x00_rt(rt2x00dev, RT3352) ||
d96aa640
RJH		 1624 rt2x00_rt(rt2x00dev, RT3390)) {
1625 rt2x00_eeprom_read(rt2x00dev,
1626 EEPROM_NIC_CONF1, &eeprom);
1627 if (rt2x00_get_field16(eeprom,
1628 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1629 rt2800_set_ant_diversity(rt2x00dev,
1630 rt2x00dev->default_ant.rx);
1631 }
f4450616
BZ		 1632 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1633 break;
1634 case 2:
872834df
GW		 1635 if (rt2x00_rt(rt2x00dev, RT3572) &&
1636 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1637 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1638 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1639 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1640 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1641 } else {
1642 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1643 }
f4450616
BZ		 1644 break;
1645 case 3:
1646 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1647 break;
1648 }
1649
1650 rt2800_bbp_write(rt2x00dev, 3, r3);
1651 rt2800_bbp_write(rt2x00dev, 1, r1);
1652}
1653EXPORT_SYMBOL_GPL(rt2800_config_ant);
1654
1655static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1656 struct rt2x00lib_conf *libconf)
1657{
1658 u16 eeprom;
1659 short lna_gain;
1660
1661 if (libconf->rf.channel <= 14) {
1662 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1663 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1664 } else if (libconf->rf.channel <= 64) {
1665 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1666 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1667 } else if (libconf->rf.channel <= 128) {
1668 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1669 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1670 } else {
1671 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1672 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1673 }
1674
1675 rt2x00dev->lna_gain = lna_gain;
1676}
1677
06855ef4
GW		 1678static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1679 struct ieee80211_conf *conf,
1680 struct rf_channel *rf,
1681 struct channel_info *info)
f4450616
BZ		 1682{
1683 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1684
d96aa640 1685 if (rt2x00dev->default_ant.tx_chain_num == 1)
f4450616
BZ		 1686 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1687
d96aa640 1688 if (rt2x00dev->default_ant.rx_chain_num == 1) {
f4450616
BZ		 1689 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1690 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
d96aa640 1691 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
f4450616
BZ		 1692 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1693
1694 if (rf->channel > 14) {
1695 /*
1696 * When TX power is below 0, we should increase it by 7 to
25985edc 1697 * make it a positive value (Minimum value is -7).
f4450616
BZ		 1698 * However this means that values between 0 and 7 have
1699 * double meaning, and we should set a 7DBm boost flag.
1700 */
1701 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
8d1331b3 1702 (info->default_power1 >= 0));
f4450616 1703
8d1331b3
ID		 1704 if (info->default_power1 < 0)
1705 info->default_power1 += 7;
f4450616 1706
8d1331b3 1707 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
f4450616
BZ		 1708
1709 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
8d1331b3 1710 (info->default_power2 >= 0));
f4450616 1711
8d1331b3
ID		 1712 if (info->default_power2 < 0)
1713 info->default_power2 += 7;
f4450616 1714
8d1331b3 1715 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
f4450616 1716 } else {
8d1331b3
ID		 1717 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1718 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
f4450616
BZ		 1719 }
1720
1721 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1722
1723 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1724 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1725 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1726 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1727
1728 udelay(200);
1729
1730 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1731 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1732 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1733 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1734
1735 udelay(200);
1736
1737 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1738 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1739 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1740 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1741}
1742
06855ef4
GW		 1743static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1744 struct ieee80211_conf *conf,
1745 struct rf_channel *rf,
1746 struct channel_info *info)
f4450616 1747{
3a1c0128 1748 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
f1f12f98 1749 u8 rfcsr, calib_tx, calib_rx;
f4450616
BZ		 1750
1751 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
7f4666ab
SG		 1752
1753 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1754 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
1755 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
f4450616
BZ		 1756
1757 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 1758 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 1759 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1760
1761 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
8d1331b3 1762 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
f4450616
BZ		 1763 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1764
5a673964 1765 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
8d1331b3 1766 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
5a673964 1767 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
e3bab197
SG		 1768
1769 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1770 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
7ad63035
GW		 1771 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
1772 rt2x00dev->default_ant.rx_chain_num <= 1);
1773 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
1774 rt2x00dev->default_ant.rx_chain_num <= 2);
e3bab197 1775 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
7ad63035
GW		 1776 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
1777 rt2x00dev->default_ant.tx_chain_num <= 1);
1778 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
1779 rt2x00dev->default_ant.tx_chain_num <= 2);
e3bab197 1780 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5a673964 1781
3e0c7643
SG		 1782 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1783 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1784 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1785 msleep(1);
1786 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1787 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1788
f4450616
BZ		 1789 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1790 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1791 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1792
f1f12f98
SG		 1793 if (rt2x00_rt(rt2x00dev, RT3390)) {
1794 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
1795 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
1796 } else {
3a1c0128
GW		 1797 if (conf_is_ht40(conf)) {
1798 calib_tx = drv_data->calibration_bw40;
1799 calib_rx = drv_data->calibration_bw40;
1800 } else {
1801 calib_tx = drv_data->calibration_bw20;
1802 calib_rx = drv_data->calibration_bw20;
1803 }
f1f12f98
SG		 1804 }
1805
1806 rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
1807 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
1808 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
1809
1810 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
1811 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
1812 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
f4450616 1813
71976907 1814 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 1815 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 1816 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
3e0c7643
SG		 1817
1818 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1819 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1820 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1821 msleep(1);
1822 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1823 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
f4450616
BZ		 1824}
1825
872834df
GW		 1826static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1827 struct ieee80211_conf *conf,
1828 struct rf_channel *rf,
1829 struct channel_info *info)
1830{
3a1c0128 1831 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
872834df
GW		 1832 u8 rfcsr;
1833 u32 reg;
1834
1835 if (rf->channel <= 14) {
5d137dff
GW		 1836 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
1837 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
872834df
GW		 1838 } else {
1839 rt2800_bbp_write(rt2x00dev, 25, 0x09);
1840 rt2800_bbp_write(rt2x00dev, 26, 0xff);
1841 }
1842
1843 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1844 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1845
1846 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1847 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1848 if (rf->channel <= 14)
1849 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
1850 else
1851 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
1852 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1853
1854 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
1855 if (rf->channel <= 14)
1856 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
1857 else
1858 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
1859 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
1860
1861 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1862 if (rf->channel <= 14) {
1863 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
1864 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
569ffa56 1865 info->default_power1);
872834df
GW		 1866 } else {
1867 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
1868 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1869 (info->default_power1 & 0x3) |
1870 ((info->default_power1 & 0xC) << 1));
1871 }
1872 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1873
1874 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1875 if (rf->channel <= 14) {
1876 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
1877 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
569ffa56 1878 info->default_power2);
872834df
GW		 1879 } else {
1880 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
1881 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1882 (info->default_power2 & 0x3) |
1883 ((info->default_power2 & 0xC) << 1));
1884 }
1885 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1886
1887 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
872834df
GW		 1888 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1889 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1890 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1891 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
0cd461ef
GW		 1892 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1893 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
872834df
GW		 1894 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1895 if (rf->channel <= 14) {
1896 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1897 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1898 }
1899 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1900 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1901 } else {
1902 switch (rt2x00dev->default_ant.tx_chain_num) {
1903 case 1:
1904 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1905 case 2:
1906 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1907 break;
1908 }
1909
1910 switch (rt2x00dev->default_ant.rx_chain_num) {
1911 case 1:
1912 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1913 case 2:
1914 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1915 break;
1916 }
1917 }
1918 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1919
1920 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1921 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1922 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1923
3a1c0128
GW		 1924 if (conf_is_ht40(conf)) {
1925 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
1926 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
1927 } else {
1928 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
1929 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
1930 }
872834df
GW		 1931
1932 if (rf->channel <= 14) {
1933 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
1934 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
1935 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1936 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
1937 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
77c06c2c
GW		 1938 rfcsr = 0x4c;
1939 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1940 drv_data->txmixer_gain_24g);
1941 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
872834df
GW		 1942 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1943 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
1944 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
1945 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
1946 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1947 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1948 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
1949 } else {
58b8ae14
GW		 1950 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1951 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
1952 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
1953 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
1954 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
1955 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
872834df
GW		 1956 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1957 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1958 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1959 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
77c06c2c
GW		 1960 rfcsr = 0x7a;
1961 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1962 drv_data->txmixer_gain_5g);
1963 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
872834df
GW		 1964 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1965 if (rf->channel <= 64) {
1966 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
1967 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
1968 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1969 } else if (rf->channel <= 128) {
1970 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
1971 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
1972 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1973 } else {
1974 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
1975 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
1976 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1977 }
1978 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
1979 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
1980 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
1981 }
1982
99bdf51a
GW		 1983 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1984 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
872834df 1985 if (rf->channel <= 14)
99bdf51a 1986 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
872834df 1987 else
99bdf51a
GW		 1988 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
1989 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
872834df
GW		 1990
1991 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1992 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1993 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1994}
60687ba7 1995
7573cb5b 1996#define POWER_BOUND 0x27
8f821098 1997#define POWER_BOUND_5G 0x2b
7573cb5b 1998#define FREQ_OFFSET_BOUND 0x5f
60687ba7 1999
0c9e5fb9
SG		 2000static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev)
2001{
2002 u8 rfcsr;
2003
2004 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2005 if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
2006 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
2007 else
2008 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2009 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2010}
2011
a89534ed
WH		 2012static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2013 struct ieee80211_conf *conf,
2014 struct rf_channel *rf,
2015 struct channel_info *info)
2016{
2017 u8 rfcsr;
2018
2019 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2020 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2021 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2022 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2023 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2024
2025 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
7573cb5b
SG		 2026 if (info->default_power1 > POWER_BOUND)
2027 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
a89534ed
WH		 2028 else
2029 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2030 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2031
0c9e5fb9 2032 rt2800_adjust_freq_offset(rt2x00dev);
a89534ed
WH		 2033
2034 if (rf->channel <= 14) {
2035 if (rf->channel == 6)
2036 rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2037 else
2038 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2039
2040 if (rf->channel >= 1 && rf->channel <= 6)
2041 rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2042 else if (rf->channel >= 7 && rf->channel <= 11)
2043 rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2044 else if (rf->channel >= 12 && rf->channel <= 14)
2045 rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2046 }
2047}
2048
03839951
DG		 2049static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2050 struct ieee80211_conf *conf,
2051 struct rf_channel *rf,
2052 struct channel_info *info)
2053{
2054 u8 rfcsr;
2055
2056 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2057 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2058
2059 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2060 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2061 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2062
2063 if (info->default_power1 > POWER_BOUND)
2064 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2065 else
2066 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2067
2068 if (info->default_power2 > POWER_BOUND)
2069 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2070 else
2071 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2072
0c9e5fb9 2073 rt2800_adjust_freq_offset(rt2x00dev);
03839951
DG		 2074
2075 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2076 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2077 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2078
2079 if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2080 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2081 else
2082 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2083
2084 if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2085 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2086 else
2087 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2088
2089 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2090 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2091
2092 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2093
2094 rt2800_rfcsr_write(rt2x00dev, 31, 80);
2095}
2096
60687ba7 2097static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
adde5882
GJ		 2098 struct ieee80211_conf *conf,
2099 struct rf_channel *rf,
2100 struct channel_info *info)
2101{
2102 u8 rfcsr;
adde5882
GJ		 2103
2104 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2105 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2106 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2107 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2108 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2109
2110 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
7573cb5b
SG		 2111 if (info->default_power1 > POWER_BOUND)
2112 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
adde5882
GJ		 2113 else
2114 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2115 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2116
cff3d1f0
ZL		 2117 if (rt2x00_rt(rt2x00dev, RT5392)) {
2118 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
7573cb5b
SG		 2119 if (info->default_power1 > POWER_BOUND)
2120 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
cff3d1f0
ZL		 2121 else
2122 rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2123 info->default_power2);
2124 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2125 }
2126
adde5882 2127 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
cff3d1f0
ZL		 2128 if (rt2x00_rt(rt2x00dev, RT5392)) {
2129 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2130 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2131 }
adde5882
GJ		 2132 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2133 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2134 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2135 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2136 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2137
0c9e5fb9 2138 rt2800_adjust_freq_offset(rt2x00dev);
adde5882 2139
adde5882
GJ		 2140 if (rf->channel <= 14) {
2141 int idx = rf->channel-1;
2142
fdbc7b0a 2143 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
adde5882
GJ		 2144 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2145 /* r55/r59 value array of channel 1~14 */
2146 static const char r55_bt_rev[] = {0x83, 0x83,
2147 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2148 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2149 static const char r59_bt_rev[] = {0x0e, 0x0e,
2150 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2151 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2152
2153 rt2800_rfcsr_write(rt2x00dev, 55,
2154 r55_bt_rev[idx]);
2155 rt2800_rfcsr_write(rt2x00dev, 59,
2156 r59_bt_rev[idx]);
2157 } else {
2158 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2159 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2160 0x88, 0x88, 0x86, 0x85, 0x84};
2161
2162 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2163 }
2164 } else {
2165 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2166 static const char r55_nonbt_rev[] = {0x23, 0x23,
2167 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2168 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2169 static const char r59_nonbt_rev[] = {0x07, 0x07,
2170 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2171 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2172
2173 rt2800_rfcsr_write(rt2x00dev, 55,
2174 r55_nonbt_rev[idx]);
2175 rt2800_rfcsr_write(rt2x00dev, 59,
2176 r59_nonbt_rev[idx]);
2ed71884 2177 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
e6d227b9 2178 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 2179 static const char r59_non_bt[] = {0x8f, 0x8f,
2180 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2181 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2182
2183 rt2800_rfcsr_write(rt2x00dev, 59,
2184 r59_non_bt[idx]);
2185 }
2186 }
2187 }
60687ba7
RST		 2188}
2189
8f821098
SG		 2190static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2191 struct ieee80211_conf *conf,
2192 struct rf_channel *rf,
2193 struct channel_info *info)
2194{
2195 u8 rfcsr, ep_reg;
d5ae7a6b 2196 u32 reg;
8f821098
SG		 2197 int power_bound;
2198
2199 /* TODO */
2200 const bool is_11b = false;
2201 const bool is_type_ep = false;
2202
d5ae7a6b
SG		 2203 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2204 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
2205 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
2206 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
8f821098
SG		 2207
2208 /* Order of values on rf_channel entry: N, K, mod, R */
2209 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2210
2211 rt2800_rfcsr_read(rt2x00dev, 9, &rfcsr);
2212 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2213 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2214 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2215 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2216
2217 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2218 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2219 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2220 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2221
2222 if (rf->channel <= 14) {
2223 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2224 /* FIXME: RF11 owerwrite ? */
2225 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2226 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2227 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2228 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2229 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2230 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2231 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2232 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2233 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2234 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2235 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2236 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2237 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2238 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2239 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2240 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2241 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2242 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2243 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2244 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2245 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2246 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2247 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2248 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2249 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2250 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2251 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2252 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2253
2254 /* TODO RF27 <- tssi */
2255
2256 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2257 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2258 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2259
2260 if (is_11b) {
2261 /* CCK */
2262 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2263 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2264 if (is_type_ep)
2265 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2266 else
2267 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2268 } else {
2269 /* OFDM */
2270 if (is_type_ep)
2271 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2272 else
2273 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2274 }
2275
2276 power_bound = POWER_BOUND;
2277 ep_reg = 0x2;
2278 } else {
2279 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2280 /* FIMXE: RF11 overwrite */
2281 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2282 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
2283 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2284 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
2285 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
2286 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
2287 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
2288 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
2289 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
2290 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
2291 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
2292 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
2293 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
2294 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
2295
2296 /* TODO RF27 <- tssi */
2297
2298 if (rf->channel >= 36 && rf->channel <= 64) {
2299
2300 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
2301 rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
2302 rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
2303 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
2304 if (rf->channel <= 50)
2305 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
2306 else if (rf->channel >= 52)
2307 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
2308 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
2309 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
2310 rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
2311 rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
2312 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
2313 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
2314 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
2315 if (rf->channel <= 50) {
2316 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
2317 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
2318 } else if (rf->channel >= 52) {
2319 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
2320 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2321 }
2322
2323 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2324 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
2325 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2326
2327 } else if (rf->channel >= 100 && rf->channel <= 165) {
2328
2329 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
2330 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2331 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2332 if (rf->channel <= 153) {
2333 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
2334 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
2335 } else if (rf->channel >= 155) {
2336 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
2337 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
2338 }
2339 if (rf->channel <= 138) {
2340 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
2341 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
2342 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
2343 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
2344 } else if (rf->channel >= 140) {
2345 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
2346 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
2347 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
2348 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
2349 }
2350 if (rf->channel <= 124)
2351 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
2352 else if (rf->channel >= 126)
2353 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
2354 if (rf->channel <= 138)
2355 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2356 else if (rf->channel >= 140)
2357 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2358 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
2359 if (rf->channel <= 138)
2360 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
2361 else if (rf->channel >= 140)
2362 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
2363 if (rf->channel <= 128)
2364 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2365 else if (rf->channel >= 130)
2366 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
2367 if (rf->channel <= 116)
2368 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
2369 else if (rf->channel >= 118)
2370 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2371 if (rf->channel <= 138)
2372 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
2373 else if (rf->channel >= 140)
2374 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
2375 if (rf->channel <= 116)
2376 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
2377 else if (rf->channel >= 118)
2378 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2379 }
2380
2381 power_bound = POWER_BOUND_5G;
2382 ep_reg = 0x3;
2383 }
2384
2385 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2386 if (info->default_power1 > power_bound)
2387 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
2388 else
2389 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2390 if (is_type_ep)
2391 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
2392 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2393
2394 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2395 if (info->default_power1 > power_bound)
2396 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
2397 else
2398 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
2399 if (is_type_ep)
2400 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
2401 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2402
2403 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2404 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2405 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2406
2407 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
2408 rt2x00dev->default_ant.tx_chain_num >= 1);
2409 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2410 rt2x00dev->default_ant.tx_chain_num == 2);
2411 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2412
2413 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
2414 rt2x00dev->default_ant.rx_chain_num >= 1);
2415 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2416 rt2x00dev->default_ant.rx_chain_num == 2);
2417 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2418
2419 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2420 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
2421
2422 if (conf_is_ht40(conf))
2423 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
2424 else
2425 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
2426
2427 if (!is_11b) {
2428 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2429 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
2430 }
2431
2432 /* TODO proper frequency adjustment */
0c9e5fb9 2433 rt2800_adjust_freq_offset(rt2x00dev);
8f821098
SG		 2434
2435 /* TODO merge with others */
2436 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2437 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2438 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
6803141b
SG		 2439
2440 /* BBP settings */
2441 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2442 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2443 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2444
2445 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
2446 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
2447 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
2448 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
2449
2450 /* GLRT band configuration */
2451 rt2800_bbp_write(rt2x00dev, 195, 128);
2452 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
2453 rt2800_bbp_write(rt2x00dev, 195, 129);
2454 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
2455 rt2800_bbp_write(rt2x00dev, 195, 130);
2456 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
2457 rt2800_bbp_write(rt2x00dev, 195, 131);
2458 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
2459 rt2800_bbp_write(rt2x00dev, 195, 133);
2460 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
2461 rt2800_bbp_write(rt2x00dev, 195, 124);
2462 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
8f821098
SG		 2463}
2464
5bc2dd06
SG		 2465static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
2466 const unsigned int word,
2467 const u8 value)
2468{
2469 u8 chain, reg;
2470
2471 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
2472 rt2800_bbp_read(rt2x00dev, 27, &reg);
2473 rt2x00_set_field8(&reg, BBP27_RX_CHAIN_SEL, chain);
2474 rt2800_bbp_write(rt2x00dev, 27, reg);
2475
2476 rt2800_bbp_write(rt2x00dev, word, value);
2477 }
2478}
2479
8756130b
SG		 2480static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
2481{
2482 u8 cal;
2483
415e3f2f 2484 /* TX0 IQ Gain */
8756130b 2485 rt2800_bbp_write(rt2x00dev, 158, 0x2c);
415e3f2f
SG		 2486 if (channel <= 14)
2487 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
2488 else if (channel >= 36 && channel <= 64)
2489 cal = rt2x00_eeprom_byte(rt2x00dev,
2490 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
2491 else if (channel >= 100 && channel <= 138)
2492 cal = rt2x00_eeprom_byte(rt2x00dev,
2493 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
2494 else if (channel >= 140 && channel <= 165)
2495 cal = rt2x00_eeprom_byte(rt2x00dev,
2496 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
2497 else
2498 cal = 0;
8756130b
SG		 2499 rt2800_bbp_write(rt2x00dev, 159, cal);
2500
415e3f2f 2501 /* TX0 IQ Phase */
8756130b 2502 rt2800_bbp_write(rt2x00dev, 158, 0x2d);
415e3f2f
SG		 2503 if (channel <= 14)
2504 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
2505 else if (channel >= 36 && channel <= 64)
2506 cal = rt2x00_eeprom_byte(rt2x00dev,
2507 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
2508 else if (channel >= 100 && channel <= 138)
2509 cal = rt2x00_eeprom_byte(rt2x00dev,
2510 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
2511 else if (channel >= 140 && channel <= 165)
2512 cal = rt2x00_eeprom_byte(rt2x00dev,
2513 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
2514 else
2515 cal = 0;
8756130b
SG		 2516 rt2800_bbp_write(rt2x00dev, 159, cal);
2517
415e3f2f 2518 /* TX1 IQ Gain */
8756130b 2519 rt2800_bbp_write(rt2x00dev, 158, 0x4a);
415e3f2f
SG		 2520 if (channel <= 14)
2521 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
2522 else if (channel >= 36 && channel <= 64)
2523 cal = rt2x00_eeprom_byte(rt2x00dev,
2524 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
2525 else if (channel >= 100 && channel <= 138)
2526 cal = rt2x00_eeprom_byte(rt2x00dev,
2527 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
2528 else if (channel >= 140 && channel <= 165)
2529 cal = rt2x00_eeprom_byte(rt2x00dev,
2530 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
2531 else
2532 cal = 0;
8756130b
SG		 2533 rt2800_bbp_write(rt2x00dev, 159, cal);
2534
415e3f2f 2535 /* TX1 IQ Phase */
8756130b 2536 rt2800_bbp_write(rt2x00dev, 158, 0x4b);
415e3f2f
SG		 2537 if (channel <= 14)
2538 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
2539 else if (channel >= 36 && channel <= 64)
2540 cal = rt2x00_eeprom_byte(rt2x00dev,
2541 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
2542 else if (channel >= 100 && channel <= 138)
2543 cal = rt2x00_eeprom_byte(rt2x00dev,
2544 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
2545 else if (channel >= 140 && channel <= 165)
2546 cal = rt2x00_eeprom_byte(rt2x00dev,
2547 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
2548 else
2549 cal = 0;
8756130b
SG		 2550 rt2800_bbp_write(rt2x00dev, 159, cal);
2551
415e3f2f
SG		 2552 /* FIXME: possible RX0, RX1 callibration ? */
2553
8756130b
SG		 2554 /* RF IQ compensation control */
2555 rt2800_bbp_write(rt2x00dev, 158, 0x04);
2556 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
2557 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
2558
2559 /* RF IQ imbalance compensation control */
2560 rt2800_bbp_write(rt2x00dev, 158, 0x03);
415e3f2f
SG		 2561 cal = rt2x00_eeprom_byte(rt2x00dev,
2562 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
8756130b
SG		 2563 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
2564}
2565
f4450616
BZ		 2566static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2567 struct ieee80211_conf *conf,
2568 struct rf_channel *rf,
2569 struct channel_info *info)
2570{
2571 u32 reg;
2572 unsigned int tx_pin;
a89534ed 2573 u8 bbp, rfcsr;
f4450616 2574
46323e11 2575 if (rf->channel <= 14) {
8d1331b3
ID		 2576 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
2577 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
46323e11 2578 } else {
8d1331b3
ID		 2579 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
2580 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
46323e11
ID		 2581 }
2582
5aa57015
GW		 2583 switch (rt2x00dev->chip.rf) {
2584 case RF2020:
2585 case RF3020:
2586 case RF3021:
2587 case RF3022:
2588 case RF3320:
06855ef4 2589 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
5aa57015
GW		 2590 break;
2591 case RF3052:
872834df 2592 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
5aa57015 2593 break;
a89534ed
WH		 2594 case RF3290:
2595 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
2596 break;
03839951
DG		 2597 case RF3322:
2598 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
2599 break;
ccf91bd6 2600 case RF5360:
5aa57015 2601 case RF5370:
2ed71884 2602 case RF5372:
5aa57015 2603 case RF5390:
cff3d1f0 2604 case RF5392:
adde5882 2605 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
5aa57015 2606 break;
8f821098
SG		 2607 case RF5592:
2608 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
2609 break;
5aa57015 2610 default:
06855ef4 2611 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
5aa57015 2612 }
f4450616 2613
a89534ed 2614 if (rt2x00_rf(rt2x00dev, RF3290) ||
03839951 2615 rt2x00_rf(rt2x00dev, RF3322) ||
a89534ed
WH		 2616 rt2x00_rf(rt2x00dev, RF5360) ||
2617 rt2x00_rf(rt2x00dev, RF5370) ||
2618 rt2x00_rf(rt2x00dev, RF5372) ||
2619 rt2x00_rf(rt2x00dev, RF5390) ||
2620 rt2x00_rf(rt2x00dev, RF5392)) {
2621 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2622 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
2623 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
2624 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2625
2626 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
d6d82020 2627 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
a89534ed
WH		 2628 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2629 }
2630
f4450616
BZ		 2631 /*
2632 * Change BBP settings
2633 */
03839951
DG		 2634 if (rt2x00_rt(rt2x00dev, RT3352)) {
2635 rt2800_bbp_write(rt2x00dev, 27, 0x0);
cf193f6d 2636 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
03839951 2637 rt2800_bbp_write(rt2x00dev, 27, 0x20);
cf193f6d 2638 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
03839951
DG		 2639 } else {
2640 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2641 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2642 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2643 rt2800_bbp_write(rt2x00dev, 86, 0);
2644 }
f4450616
BZ		 2645
2646 if (rf->channel <= 14) {
2ed71884 2647 if (!rt2x00_rt(rt2x00dev, RT5390) &&
e6d227b9 2648 !rt2x00_rt(rt2x00dev, RT5392)) {
7dab73b3
ID		 2649 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
2650 &rt2x00dev->cap_flags)) {
adde5882
GJ		 2651 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2652 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2653 } else {
2654 rt2800_bbp_write(rt2x00dev, 82, 0x84);
2655 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2656 }
f4450616
BZ		 2657 }
2658 } else {
872834df
GW		 2659 if (rt2x00_rt(rt2x00dev, RT3572))
2660 rt2800_bbp_write(rt2x00dev, 82, 0x94);
2661 else
2662 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
f4450616 2663
7dab73b3 2664 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
f4450616
BZ		 2665 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2666 else
2667 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2668 }
2669
2670 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 2671 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 2672 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
2673 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
2674 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
2675
872834df
GW		 2676 if (rt2x00_rt(rt2x00dev, RT3572))
2677 rt2800_rfcsr_write(rt2x00dev, 8, 0);
2678
f4450616
BZ		 2679 tx_pin = 0;
2680
2681 /* Turn on unused PA or LNA when not using 1T or 1R */
d96aa640 2682 if (rt2x00dev->default_ant.tx_chain_num == 2) {
65f31b5e
GW		 2683 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
2684 rf->channel > 14);
2685 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
2686 rf->channel <= 14);
f4450616
BZ		 2687 }
2688
2689 /* Turn on unused PA or LNA when not using 1T or 1R */
d96aa640 2690 if (rt2x00dev->default_ant.rx_chain_num == 2) {
f4450616
BZ		 2691 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
2692 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
2693 }
2694
2695 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
2696 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
2697 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
2698 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
8f96e91f
GW		 2699 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
2700 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2701 else
2702 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
2703 rf->channel <= 14);
f4450616
BZ		 2704 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
2705
2706 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2707
872834df
GW		 2708 if (rt2x00_rt(rt2x00dev, RT3572))
2709 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
2710
6803141b
SG		 2711 if (rt2x00_rt(rt2x00dev, RT5592)) {
2712 rt2800_bbp_write(rt2x00dev, 195, 141);
2713 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
2714
8ba0ebf3
SG		 2715 /* AGC init */
2716 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain;
2717 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
2718
8756130b 2719 rt2800_iq_calibrate(rt2x00dev, rf->channel);
6803141b
SG		 2720 }
2721
f4450616
BZ		 2722 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2723 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
2724 rt2800_bbp_write(rt2x00dev, 4, bbp);
2725
2726 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 2727 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 2728 rt2800_bbp_write(rt2x00dev, 3, bbp);
2729
8d0c9b65 2730 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 2731 if (conf_is_ht40(conf)) {
2732 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
2733 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2734 rt2800_bbp_write(rt2x00dev, 73, 0x16);
2735 } else {
2736 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2737 rt2800_bbp_write(rt2x00dev, 70, 0x08);
2738 rt2800_bbp_write(rt2x00dev, 73, 0x11);
2739 }
2740 }
2741
2742 msleep(1);
977206d7
HS		 2743
2744 /*
2745 * Clear channel statistic counters
2746 */
2747 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
2748 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
2749 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
03839951
DG		 2750
2751 /*
2752 * Clear update flag
2753 */
2754 if (rt2x00_rt(rt2x00dev, RT3352)) {
2755 rt2800_bbp_read(rt2x00dev, 49, &bbp);
2756 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
2757 rt2800_bbp_write(rt2x00dev, 49, bbp);
2758 }
f4450616
BZ		 2759}
2760
9e33a355
HS		 2761static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
2762{
2763 u8 tssi_bounds[9];
2764 u8 current_tssi;
2765 u16 eeprom;
2766 u8 step;
2767 int i;
2768
2769 /*
2770 * Read TSSI boundaries for temperature compensation from
2771 * the EEPROM.
2772 *
2773 * Array idx 0 1 2 3 4 5 6 7 8
2774 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
2775 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2776 */
2777 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2778 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
2779 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2780 EEPROM_TSSI_BOUND_BG1_MINUS4);
2781 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2782 EEPROM_TSSI_BOUND_BG1_MINUS3);
2783
2784 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
2785 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2786 EEPROM_TSSI_BOUND_BG2_MINUS2);
2787 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2788 EEPROM_TSSI_BOUND_BG2_MINUS1);
2789
2790 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
2791 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2792 EEPROM_TSSI_BOUND_BG3_REF);
2793 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2794 EEPROM_TSSI_BOUND_BG3_PLUS1);
2795
2796 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
2797 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2798 EEPROM_TSSI_BOUND_BG4_PLUS2);
2799 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2800 EEPROM_TSSI_BOUND_BG4_PLUS3);
2801
2802 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
2803 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2804 EEPROM_TSSI_BOUND_BG5_PLUS4);
2805
2806 step = rt2x00_get_field16(eeprom,
2807 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
2808 } else {
2809 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
2810 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2811 EEPROM_TSSI_BOUND_A1_MINUS4);
2812 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2813 EEPROM_TSSI_BOUND_A1_MINUS3);
2814
2815 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
2816 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2817 EEPROM_TSSI_BOUND_A2_MINUS2);
2818 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2819 EEPROM_TSSI_BOUND_A2_MINUS1);
2820
2821 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
2822 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2823 EEPROM_TSSI_BOUND_A3_REF);
2824 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2825 EEPROM_TSSI_BOUND_A3_PLUS1);
2826
2827 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
2828 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2829 EEPROM_TSSI_BOUND_A4_PLUS2);
2830 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2831 EEPROM_TSSI_BOUND_A4_PLUS3);
2832
2833 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
2834 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2835 EEPROM_TSSI_BOUND_A5_PLUS4);
2836
2837 step = rt2x00_get_field16(eeprom,
2838 EEPROM_TSSI_BOUND_A5_AGC_STEP);
2839 }
2840
2841 /*
2842 * Check if temperature compensation is supported.
2843 */
bf7e1abe 2844 if (tssi_bounds[4] == 0xff || step == 0xff)
9e33a355
HS		 2845 return 0;
2846
2847 /*
2848 * Read current TSSI (BBP 49).
2849 */
2850 rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
2851
2852 /*
2853 * Compare TSSI value (BBP49) with the compensation boundaries
2854 * from the EEPROM and increase or decrease tx power.
2855 */
2856 for (i = 0; i <= 3; i++) {
2857 if (current_tssi > tssi_bounds[i])
2858 break;
2859 }
2860
2861 if (i == 4) {
2862 for (i = 8; i >= 5; i--) {
2863 if (current_tssi < tssi_bounds[i])
2864 break;
2865 }
2866 }
2867
2868 return (i - 4) * step;
2869}
2870
e90c54b2
RJH		 2871static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
2872 enum ieee80211_band band)
2873{
2874 u16 eeprom;
2875 u8 comp_en;
2876 u8 comp_type;
75faae8b 2877 int comp_value = 0;
e90c54b2
RJH		 2878
2879 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
2880
75faae8b
HS		 2881 /*
2882 * HT40 compensation not required.
2883 */
2884 if (eeprom == 0xffff ||
2885 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
e90c54b2
RJH		 2886 return 0;
2887
2888 if (band == IEEE80211_BAND_2GHZ) {
2889 comp_en = rt2x00_get_field16(eeprom,
2890 EEPROM_TXPOWER_DELTA_ENABLE_2G);
2891 if (comp_en) {
2892 comp_type = rt2x00_get_field16(eeprom,
2893 EEPROM_TXPOWER_DELTA_TYPE_2G);
2894 comp_value = rt2x00_get_field16(eeprom,
2895 EEPROM_TXPOWER_DELTA_VALUE_2G);
2896 if (!comp_type)
2897 comp_value = -comp_value;
2898 }
2899 } else {
2900 comp_en = rt2x00_get_field16(eeprom,
2901 EEPROM_TXPOWER_DELTA_ENABLE_5G);
2902 if (comp_en) {
2903 comp_type = rt2x00_get_field16(eeprom,
2904 EEPROM_TXPOWER_DELTA_TYPE_5G);
2905 comp_value = rt2x00_get_field16(eeprom,
2906 EEPROM_TXPOWER_DELTA_VALUE_5G);
2907 if (!comp_type)
2908 comp_value = -comp_value;
2909 }
2910 }
2911
2912 return comp_value;
2913}
2914
1e4cf249
SG		 2915static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
2916 int power_level, int max_power)
2917{
2918 int delta;
2919
2920 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags))
2921 return 0;
2922
2923 /*
2924 * XXX: We don't know the maximum transmit power of our hardware since
2925 * the EEPROM doesn't expose it. We only know that we are calibrated
2926 * to 100% tx power.
2927 *
2928 * Hence, we assume the regulatory limit that cfg80211 calulated for
2929 * the current channel is our maximum and if we are requested to lower
2930 * the value we just reduce our tx power accordingly.
2931 */
2932 delta = power_level - max_power;
2933 return min(delta, 0);
2934}
2935
fa71a160
HS		 2936static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
2937 enum ieee80211_band band, int power_level,
2938 u8 txpower, int delta)
e90c54b2 2939{
e90c54b2
RJH		 2940 u16 eeprom;
2941 u8 criterion;
2942 u8 eirp_txpower;
2943 u8 eirp_txpower_criterion;
2944 u8 reg_limit;
e90c54b2 2945
7dab73b3 2946 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
e90c54b2
RJH		 2947 /*
2948 * Check if eirp txpower exceed txpower_limit.
2949 * We use OFDM 6M as criterion and its eirp txpower
2950 * is stored at EEPROM_EIRP_MAX_TX_POWER.
2951 * .11b data rate need add additional 4dbm
2952 * when calculating eirp txpower.
2953 */
d9bceaeb
SG		 2954 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + 1,
2955 &eeprom);
2956 criterion = rt2x00_get_field16(eeprom,
2957 EEPROM_TXPOWER_BYRATE_RATE0);
e90c54b2 2958
d9bceaeb
SG		 2959 rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
2960 &eeprom);
e90c54b2
RJH		 2961
2962 if (band == IEEE80211_BAND_2GHZ)
2963 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2964 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2965 else
2966 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2967 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2968
2969 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2af242e1 2970 (is_rate_b ? 4 : 0) + delta;
e90c54b2
RJH		 2971
2972 reg_limit = (eirp_txpower > power_level) ?
2973 (eirp_txpower - power_level) : 0;
2974 } else
2975 reg_limit = 0;
2976
19f3fa24
SG		 2977 txpower = max(0, txpower + delta - reg_limit);
2978 return min_t(u8, txpower, 0xc);
e90c54b2
RJH		 2979}
2980
7a66205a
SG		 2981/*
2982 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
2983 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
2984 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
2985 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
2986 * Reference per rate transmit power values are located in the EEPROM at
2987 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
2988 * current conditions (i.e. band, bandwidth, temperature, user settings).
2989 */
f4450616 2990static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
146c3b0c 2991 struct ieee80211_channel *chan,
9e33a355 2992 int power_level)
f4450616 2993{
cee2c731 2994 u8 txpower, r1;
5e846004 2995 u16 eeprom;
cee2c731
SG		 2996 u32 reg, offset;
2997 int i, is_rate_b, delta, power_ctrl;
146c3b0c 2998 enum ieee80211_band band = chan->band;
2af242e1
HS		 2999
3000 /*
7a66205a
SG		 3001 * Calculate HT40 compensation. For 40MHz we need to add or subtract
3002 * value read from EEPROM (different for 2GHz and for 5GHz).
2af242e1
HS		 3003 */
3004 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
f4450616 3005
9e33a355 3006 /*
7a66205a
SG		 3007 * Calculate temperature compensation. Depends on measurement of current
3008 * TSSI (Transmitter Signal Strength Indication) we know TX power (due
3009 * to temperature or maybe other factors) is smaller or bigger than
3010 * expected. We adjust it, based on TSSI reference and boundaries values
3011 * provided in EEPROM.
9e33a355
HS		 3012 */
3013 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
f4450616 3014
1e4cf249 3015 /*
7a66205a
SG		 3016 * Decrease power according to user settings, on devices with unknown
3017 * maximum tx power. For other devices we take user power_level into
3018 * consideration on rt2800_compensate_txpower().
1e4cf249
SG		 3019 */
3020 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
3021 chan->max_power);
3022
5e846004 3023 /*
cee2c731
SG		 3024 * BBP_R1 controls TX power for all rates, it allow to set the following
3025 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
3026 *
3027 * TODO: we do not use +6 dBm option to do not increase power beyond
3028 * regulatory limit, however this could be utilized for devices with
3029 * CAPABILITY_POWER_LIMIT.
5e846004 3030 */
f4450616 3031 rt2800_bbp_read(rt2x00dev, 1, &r1);
cee2c731
SG		 3032 if (delta <= -12) {
3033 power_ctrl = 2;
3034 delta += 12;
3035 } else if (delta <= -6) {
3036 power_ctrl = 1;
3037 delta += 6;
3038 } else {
3039 power_ctrl = 0;
3040 }
3041 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
f4450616 3042 rt2800_bbp_write(rt2x00dev, 1, r1);
5e846004
HS		 3043 offset = TX_PWR_CFG_0;
3044
3045 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
3046 /* just to be safe */
3047 if (offset > TX_PWR_CFG_4)
3048 break;
3049
3050 rt2800_register_read(rt2x00dev, offset, &reg);
3051
3052 /* read the next four txpower values */
3053 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
3054 &eeprom);
3055
e90c54b2
RJH		 3056 is_rate_b = i ? 0 : 1;
3057 /*
3058 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
5e846004 3059 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
e90c54b2
RJH		 3060 * TX_PWR_CFG_4: unknown
3061 */
5e846004
HS		 3062 txpower = rt2x00_get_field16(eeprom,
3063 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 3064 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 3065 power_level, txpower, delta);
e90c54b2 3066 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
5e846004 3067
e90c54b2
RJH		 3068 /*
3069 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
5e846004 3070 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
e90c54b2
RJH		 3071 * TX_PWR_CFG_4: unknown
3072 */
5e846004
HS		 3073 txpower = rt2x00_get_field16(eeprom,
3074 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 3075 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 3076 power_level, txpower, delta);
e90c54b2 3077 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
5e846004 3078
e90c54b2
RJH		 3079 /*
3080 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
5e846004 3081 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
e90c54b2
RJH		 3082 * TX_PWR_CFG_4: unknown
3083 */
5e846004
HS		 3084 txpower = rt2x00_get_field16(eeprom,
3085 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 3086 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 3087 power_level, txpower, delta);
e90c54b2 3088 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
5e846004 3089
e90c54b2
RJH		 3090 /*
3091 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
5e846004 3092 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
e90c54b2
RJH		 3093 * TX_PWR_CFG_4: unknown
3094 */
5e846004
HS		 3095 txpower = rt2x00_get_field16(eeprom,
3096 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 3097 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 3098 power_level, txpower, delta);
e90c54b2 3099 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
5e846004
HS		 3100
3101 /* read the next four txpower values */
3102 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
3103 &eeprom);
3104
e90c54b2
RJH		 3105 is_rate_b = 0;
3106 /*
3107 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
5e846004 3108 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 3109 * TX_PWR_CFG_4: unknown
3110 */
5e846004
HS		 3111 txpower = rt2x00_get_field16(eeprom,
3112 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 3113 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 3114 power_level, txpower, delta);
e90c54b2 3115 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
5e846004 3116
e90c54b2
RJH		 3117 /*
3118 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
5e846004 3119 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 3120 * TX_PWR_CFG_4: unknown
3121 */
5e846004
HS		 3122 txpower = rt2x00_get_field16(eeprom,
3123 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 3124 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 3125 power_level, txpower, delta);
e90c54b2 3126 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
5e846004 3127
e90c54b2
RJH		 3128 /*
3129 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
5e846004 3130 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 3131 * TX_PWR_CFG_4: unknown
3132 */
5e846004
HS		 3133 txpower = rt2x00_get_field16(eeprom,
3134 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 3135 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 3136 power_level, txpower, delta);
e90c54b2 3137 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
5e846004 3138
e90c54b2
RJH		 3139 /*
3140 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
5e846004 3141 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 3142 * TX_PWR_CFG_4: unknown
3143 */
5e846004
HS		 3144 txpower = rt2x00_get_field16(eeprom,
3145 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 3146 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 3147 power_level, txpower, delta);
e90c54b2 3148 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
5e846004
HS		 3149
3150 rt2800_register_write(rt2x00dev, offset, reg);
3151
3152 /* next TX_PWR_CFG register */
3153 offset += 4;
3154 }
f4450616
BZ		 3155}
3156
9e33a355
HS		 3157void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
3158{
675a0b04 3159 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
9e33a355
HS		 3160 rt2x00dev->tx_power);
3161}
3162EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
3163
2e9c43dd
JL		 3164void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
3165{
3166 u32 tx_pin;
3167 u8 rfcsr;
3168
3169 /*
3170 * A voltage-controlled oscillator(VCO) is an electronic oscillator
3171 * designed to be controlled in oscillation frequency by a voltage
3172 * input. Maybe the temperature will affect the frequency of
3173 * oscillation to be shifted. The VCO calibration will be called
3174 * periodically to adjust the frequency to be precision.
3175 */
3176
3177 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
3178 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
3179 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3180
3181 switch (rt2x00dev->chip.rf) {
3182 case RF2020:
3183 case RF3020:
3184 case RF3021:
3185 case RF3022:
3186 case RF3320:
3187 case RF3052:
3188 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
3189 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
3190 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
3191 break;
a89534ed 3192 case RF3290:
ccf91bd6 3193 case RF5360:
2e9c43dd
JL		 3194 case RF5370:
3195 case RF5372:
3196 case RF5390:
cff3d1f0 3197 case RF5392:
2e9c43dd 3198 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
d6d82020 3199 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2e9c43dd
JL		 3200 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3201 break;
3202 default:
3203 return;
3204 }
3205
3206 mdelay(1);
3207
3208 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
3209 if (rt2x00dev->rf_channel <= 14) {
3210 switch (rt2x00dev->default_ant.tx_chain_num) {
3211 case 3:
3212 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
3213 /* fall through */
3214 case 2:
3215 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
3216 /* fall through */
3217 case 1:
3218 default:
3219 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3220 break;
3221 }
3222 } else {
3223 switch (rt2x00dev->default_ant.tx_chain_num) {
3224 case 3:
3225 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
3226 /* fall through */
3227 case 2:
3228 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
3229 /* fall through */
3230 case 1:
3231 default:
3232 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
3233 break;
3234 }
3235 }
3236 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3237
3238}
3239EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
3240
f4450616
BZ		 3241static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
3242 struct rt2x00lib_conf *libconf)
3243{
3244 u32 reg;
3245
3246 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
3247 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
3248 libconf->conf->short_frame_max_tx_count);
3249 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
3250 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 3251 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
3252}
3253
3254static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
3255 struct rt2x00lib_conf *libconf)
3256{
3257 enum dev_state state =
3258 (libconf->conf->flags & IEEE80211_CONF_PS) ?
3259 STATE_SLEEP : STATE_AWAKE;
3260 u32 reg;
3261
3262 if (state == STATE_SLEEP) {
3263 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
3264
3265 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
3266 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
3267 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
3268 libconf->conf->listen_interval - 1);
3269 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
3270 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
3271
3272 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
3273 } else {
f4450616
BZ		 3274 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
3275 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
3276 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
3277 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
3278 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 3279
3280 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 3281 }
3282}
3283
3284void rt2800_config(struct rt2x00_dev *rt2x00dev,
3285 struct rt2x00lib_conf *libconf,
3286 const unsigned int flags)
3287{
3288 /* Always recalculate LNA gain before changing configuration */
3289 rt2800_config_lna_gain(rt2x00dev, libconf);
3290
e90c54b2 3291 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
f4450616
BZ		 3292 rt2800_config_channel(rt2x00dev, libconf->conf,
3293 &libconf->rf, &libconf->channel);
675a0b04 3294 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
9e33a355 3295 libconf->conf->power_level);
e90c54b2 3296 }
f4450616 3297 if (flags & IEEE80211_CONF_CHANGE_POWER)
675a0b04 3298 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
9e33a355 3299 libconf->conf->power_level);
f4450616
BZ		 3300 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3301 rt2800_config_retry_limit(rt2x00dev, libconf);
3302 if (flags & IEEE80211_CONF_CHANGE_PS)
3303 rt2800_config_ps(rt2x00dev, libconf);
3304}
3305EXPORT_SYMBOL_GPL(rt2800_config);
3306
3307/*
3308 * Link tuning
3309 */
3310void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
3311{
3312 u32 reg;
3313
3314 /*
3315 * Update FCS error count from register.
3316 */
3317 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3318 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
3319}
3320EXPORT_SYMBOL_GPL(rt2800_link_stats);
3321
3322static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
3323{
8c6728b0
GW		 3324 u8 vgc;
3325
f4450616 3326 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
d5385bfc 3327 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 3328 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 3329 rt2x00_rt(rt2x00dev, RT3090) ||
a89534ed 3330 rt2x00_rt(rt2x00dev, RT3290) ||
adde5882 3331 rt2x00_rt(rt2x00dev, RT3390) ||
d961e447 3332 rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884 3333 rt2x00_rt(rt2x00dev, RT5390) ||
3d81535e
SG		 3334 rt2x00_rt(rt2x00dev, RT5392) ||
3335 rt2x00_rt(rt2x00dev, RT5592))
8c6728b0
GW		 3336 vgc = 0x1c + (2 * rt2x00dev->lna_gain);
3337 else
3338 vgc = 0x2e + rt2x00dev->lna_gain;
3339 } else { /* 5GHZ band */
d961e447
GW		 3340 if (rt2x00_rt(rt2x00dev, RT3572))
3341 vgc = 0x22 + (rt2x00dev->lna_gain * 5) / 3;
3d81535e
SG		 3342 else if (rt2x00_rt(rt2x00dev, RT5592))
3343 vgc = 0x24 + (2 * rt2x00dev->lna_gain);
d961e447
GW		 3344 else {
3345 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3346 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
3347 else
3348 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
3349 }
f4450616
BZ		 3350 }
3351
8c6728b0 3352 return vgc;
f4450616
BZ		 3353}
3354
3355static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
3356 struct link_qual *qual, u8 vgc_level)
3357{
3358 if (qual->vgc_level != vgc_level) {
3d81535e
SG		 3359 if (rt2x00_rt(rt2x00dev, RT5592)) {
3360 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
3361 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
3362 } else
3363 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
f4450616
BZ		 3364 qual->vgc_level = vgc_level;
3365 qual->vgc_level_reg = vgc_level;
3366 }
3367}
3368
3369void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
3370{
3371 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
3372}
3373EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
3374
3375void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
3376 const u32 count)
3377{
3d81535e
SG		 3378 u8 vgc;
3379
8d0c9b65 3380 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616 3381 return;
f4450616 3382 /*
3d81535e
SG		 3383 * When RSSI is better then -80 increase VGC level with 0x10, except
3384 * for rt5592 chip.
f4450616 3385 */
3d81535e
SG		 3386
3387 vgc = rt2800_get_default_vgc(rt2x00dev);
3388
3389 if (rt2x00_rt(rt2x00dev, RT5592) && qual->rssi > -65)
3390 vgc += 0x20;
3391 else if (qual->rssi > -80)
3392 vgc += 0x10;
3393
3394 rt2800_set_vgc(rt2x00dev, qual, vgc);
f4450616
BZ		 3395}
3396EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 3397
3398/*
3399 * Initialization functions.
3400 */
b9a07ae9 3401static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 3402{
3403 u32 reg;
d5385bfc 3404 u16 eeprom;
fcf51541 3405 unsigned int i;
e3a896b9 3406 int ret;
fcf51541 3407
f7b395e9 3408 rt2800_disable_wpdma(rt2x00dev);
a9dce149 3409
e3a896b9
GW		 3410 ret = rt2800_drv_init_registers(rt2x00dev);
3411 if (ret)
3412 return ret;
fcf51541
BZ		 3413
3414 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
3415 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
3416 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
3417 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
3418 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
3419 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
3420
3421 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
3422 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
3423 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
3424 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
3425 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
3426 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
3427
3428 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
3429 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
3430
3431 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
3432
3433 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
8544df32 3434 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
fcf51541
BZ		 3435 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
3436 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
3437 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
3438 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
3439 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
3440 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
3441
a9dce149
GW		 3442 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
3443
3444 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
3445 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
3446 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
3447 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
3448
a89534ed
WH		 3449 if (rt2x00_rt(rt2x00dev, RT3290)) {
3450 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
3451 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
3452 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
3453 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
3454 }
3455
3456 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
3457 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
3458 rt2x00_set_field32(&reg, LDO0_EN, 1);
3459 rt2x00_set_field32(&reg, LDO_BGSEL, 3);
3460 rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
3461 }
3462
3463 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
3464 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
3465 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
3466 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
3467 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
3468
3469 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
3470 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
3471 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
3472
3473 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
3474 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
3475 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
3476 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
3477 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
3478 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
3479
3480 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
3481 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
3482 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
3483 }
3484
64522957 3485 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 3486 rt2x00_rt(rt2x00dev, RT3090) ||
a89534ed 3487 rt2x00_rt(rt2x00dev, RT3290) ||
cc78e904 3488 rt2x00_rt(rt2x00dev, RT3390)) {
a89534ed
WH		 3489
3490 if (rt2x00_rt(rt2x00dev, RT3290))
3491 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
3492 0x00000404);
3493 else
3494 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
3495 0x00000400);
3496
fcf51541 3497 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 3498 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 3499 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3500 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
38c8a566
RJH		 3501 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3502 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 3503 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
3504 0x0000002c);
3505 else
3506 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
3507 0x0000000f);
3508 } else {
3509 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3510 }
d5385bfc 3511 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 3512 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 3513
3514 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3515 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3516 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
3517 } else {
3518 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3519 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3520 }
c295a81d
HS		 3521 } else if (rt2800_is_305x_soc(rt2x00dev)) {
3522 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3523 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
961636ba 3524 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
03839951
DG		 3525 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
3526 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
3527 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3528 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
872834df
GW		 3529 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3530 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3531 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2ed71884 3532 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
7641328d
SG		 3533 rt2x00_rt(rt2x00dev, RT5392) ||
3534 rt2x00_rt(rt2x00dev, RT5592)) {
adde5882
GJ		 3535 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
3536 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3537 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
fcf51541
BZ		 3538 } else {
3539 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
3540 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3541 }
3542
3543 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
3544 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
3545 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
3546 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
3547 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
3548 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
3549 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
3550 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
3551 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
3552 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
3553
3554 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
3555 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 3556 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 3557 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
3558 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
3559
3560 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
3561 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 3562 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 3563 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 3564 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 3565 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
3566 else
3567 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
3568 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
3569 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
3570 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
3571
a9dce149
GW		 3572 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
3573 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
3574 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
3575 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
3576 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
3577 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
3578 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
3579 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
3580 rt2800_register_write(rt2x00dev, LED_CFG, reg);
3581
fcf51541
BZ		 3582 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
3583
a9dce149
GW		 3584 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
3585 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
3586 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
3587 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
3588 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
3589 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
3590 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
3591 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
3592
fcf51541
BZ		 3593 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
3594 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 3595 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 3596 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
3597 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 3598 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 3599 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
3600 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
3601 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
3602
3603 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 3604 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541 3605 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 3606 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 3607 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3608 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3609 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 3610 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 3611 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 3612 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3613 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 3614 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3615
3616 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 3617 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541 3618 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 3619 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 3620 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3621 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3622 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 3623 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 3624 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 3625 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3626 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 3627 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3628
3629 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3630 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
3631 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 3632 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 3633 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3634 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3635 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3636 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3637 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3638 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 3639 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 3640 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3641
3642 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3643 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
d13a97f0 3644 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 3645 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 3646 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3647 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3648 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3649 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
3650 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3651 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 3652 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 3653 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3654
3655 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3656 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
3657 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 3658 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 3659 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3660 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3661 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3662 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3663 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3664 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 3665 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 3666 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3667
3668 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3669 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
3670 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 3671 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 3672 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3673 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3674 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3675 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
3676 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3677 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 3678 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 3679 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3680
cea90e55 3681 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 3682 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
3683
3684 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3685 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
3686 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
3687 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
3688 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
3689 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
3690 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
3691 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
3692 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
3693 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
3694 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3695 }
3696
961621ab
HS		 3697 /*
3698 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
3699 * although it is reserved.
3700 */
3701 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
3702 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
3703 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
3704 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
3705 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
3706 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
3707 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
3708 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
3709 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
3710 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
3711 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
3712 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
3713
7641328d
SG		 3714 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
3715 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
fcf51541
BZ		 3716
3717 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3718 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
3719 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
3720 IEEE80211_MAX_RTS_THRESHOLD);
3721 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
3722 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3723
3724 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 3725
a21c2ab4
HS		 3726 /*
3727 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
3728 * time should be set to 16. However, the original Ralink driver uses
3729 * 16 for both and indeed using a value of 10 for CCK SIFS results in
3730 * connection problems with 11g + CTS protection. Hence, use the same
3731 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
3732 */
a9dce149 3733 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 3734 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
3735 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 3736 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
3737 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
3738 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
3739 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
3740
fcf51541
BZ		 3741 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
3742
3743 /*
3744 * ASIC will keep garbage value after boot, clear encryption keys.
3745 */
3746 for (i = 0; i < 4; i++)
3747 rt2800_register_write(rt2x00dev,
3748 SHARED_KEY_MODE_ENTRY(i), 0);
3749
3750 for (i = 0; i < 256; i++) {
d7d259d3
HS		 3751 rt2800_config_wcid(rt2x00dev, NULL, i);
3752 rt2800_delete_wcid_attr(rt2x00dev, i);
fcf51541
BZ		 3753 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
3754 }
3755
3756 /*
3757 * Clear all beacons
fcf51541 3758 */
69cf36a4
HS		 3759 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
3760 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
3761 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
3762 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
3763 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
3764 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
3765 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
3766 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
fcf51541 3767
cea90e55 3768 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 3769 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3770 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
3771 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
c6fcc0e5
RJH		 3772 } else if (rt2x00_is_pcie(rt2x00dev)) {
3773 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3774 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
3775 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 3776 }
3777
3778 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
3779 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
3780 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
3781 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
3782 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
3783 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
3784 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
3785 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
3786 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
3787 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
3788
3789 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
3790 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
3791 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
3792 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
3793 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
3794 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
3795 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
3796 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
3797 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
3798 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
3799
3800 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
3801 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
3802 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
3803 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
3804 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
3805 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
3806 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
3807 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
3808 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
3809 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
3810
3811 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
3812 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
3813 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
3814 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
3815 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
3816 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
3817
47ee3eb1
HS		 3818 /*
3819 * Do not force the BA window size, we use the TXWI to set it
3820 */
3821 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
3822 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
3823 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
3824 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
3825
fcf51541
BZ		 3826 /*
3827 * We must clear the error counters.
3828 * These registers are cleared on read,
3829 * so we may pass a useless variable to store the value.
3830 */
3831 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3832 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
3833 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
3834 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
3835 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
3836 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
3837
9f926fb5
HS		 3838 /*
3839 * Setup leadtime for pre tbtt interrupt to 6ms
3840 */
3841 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
3842 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
3843 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
3844
977206d7
HS		 3845 /*
3846 * Set up channel statistics timer
3847 */
3848 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
3849 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
3850 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
3851 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
3852 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
3853 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
3854 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
3855
fcf51541
BZ		 3856 return 0;
3857}
fcf51541
BZ		 3858
3859static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
3860{
3861 unsigned int i;
3862 u32 reg;
3863
3864 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3865 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
3866 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
3867 return 0;
3868
3869 udelay(REGISTER_BUSY_DELAY);
3870 }
3871
ec9c4989 3872 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
fcf51541
BZ		 3873 return -EACCES;
3874}
3875
3876static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
3877{
3878 unsigned int i;
3879 u8 value;
3880
3881 /*
3882 * BBP was enabled after firmware was loaded,
3883 * but we need to reactivate it now.
3884 */
3885 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
3886 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
3887 msleep(1);
3888
3889 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3890 rt2800_bbp_read(rt2x00dev, 0, &value);
3891 if ((value != 0xff) && (value != 0x00))
3892 return 0;
3893 udelay(REGISTER_BUSY_DELAY);
3894 }
3895
ec9c4989 3896 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
fcf51541
BZ		 3897 return -EACCES;
3898}
3899
a7bbbe5c
SG		 3900static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
3901{
3902 u8 value;
3903
3904 rt2800_bbp_read(rt2x00dev, 4, &value);
3905 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
3906 rt2800_bbp_write(rt2x00dev, 4, value);
3907}
3908
c2675487
SG		 3909static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
3910{
3911 rt2800_bbp_write(rt2x00dev, 142, 1);
3912 rt2800_bbp_write(rt2x00dev, 143, 57);
3913}
3914
a7bbbe5c
SG		 3915static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
3916{
3917 const u8 glrt_table[] = {
3918 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
3919 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
3920 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
3921 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
3922 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
3923 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
3924 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
3925 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
3926 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */
3927 };
3928 int i;
3929
3930 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
3931 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
3932 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
3933 }
3934};
3935
624708b8 3936static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
a4969d0d
SG		 3937{
3938 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
3939 rt2800_bbp_write(rt2x00dev, 66, 0x38);
3940 rt2800_bbp_write(rt2x00dev, 68, 0x0B);
3941 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3942 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3943 rt2800_bbp_write(rt2x00dev, 73, 0x10);
3944 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3945 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3946 rt2800_bbp_write(rt2x00dev, 83, 0x6A);
3947 rt2800_bbp_write(rt2x00dev, 84, 0x99);
3948 rt2800_bbp_write(rt2x00dev, 86, 0x00);
3949 rt2800_bbp_write(rt2x00dev, 91, 0x04);
3950 rt2800_bbp_write(rt2x00dev, 92, 0x00);
3951 rt2800_bbp_write(rt2x00dev, 103, 0x00);
3952 rt2800_bbp_write(rt2x00dev, 105, 0x05);
3953 rt2800_bbp_write(rt2x00dev, 106, 0x35);
3954}
3955
dae62957
SG		 3956static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
3957{
b2f8e0bd 3958 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 3959
3960 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
3961 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 3962
3963 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3964 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 3965
3966 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 3967
3968 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
3969 rt2800_bbp_write(rt2x00dev, 80, 0x08);
fa1e3424
SG		 3970
3971 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 3972
3973 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
dae62957
SG		 3974}
3975
39ab3e8b
SG		 3976static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
3977{
e379de12
SG		 3978 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
3979 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 3980
3981 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3982 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3983 rt2800_bbp_write(rt2x00dev, 73, 0x12);
3984 } else {
3985 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3986 rt2800_bbp_write(rt2x00dev, 73, 0x10);
3987 }
8d97be38
SG		 3988
3989 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 3990
3991 rt2800_bbp_write(rt2x00dev, 81, 0x37);
fa1e3424
SG		 3992
3993 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 3994
3995 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
39ab3e8b
SG		 3996}
3997
3998static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
3999{
e379de12
SG		 4000 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4001 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 4002
4003 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4004 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 4005
4006 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 4007
4008 rt2800_bbp_write(rt2x00dev, 79, 0x13);
4009 rt2800_bbp_write(rt2x00dev, 80, 0x05);
4010 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 4011
4012 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 4013
4014 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
39ab3e8b
SG		 4015}
4016
4017static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
4018{
c3223573 4019 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
b2f8e0bd
SG		 4020
4021 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 4022
4023 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4024 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 4025
4026 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142
SG		 4027
4028 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4029 rt2800_bbp_write(rt2x00dev, 73, 0x13);
4030 rt2800_bbp_write(rt2x00dev, 75, 0x46);
4031 rt2800_bbp_write(rt2x00dev, 76, 0x28);
4032
4033 rt2800_bbp_write(rt2x00dev, 77, 0x58);
8d97be38
SG		 4034
4035 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 4036
4037 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
4038 rt2800_bbp_write(rt2x00dev, 79, 0x18);
4039 rt2800_bbp_write(rt2x00dev, 80, 0x09);
4040 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 4041
4042 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 4043
4044 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
39ab3e8b
SG		 4045}
4046
4047static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
4048{
29f3a58b
SG		 4049 rt2800_bbp_write(rt2x00dev, 3, 0x00);
4050 rt2800_bbp_write(rt2x00dev, 4, 0x50);
b2f8e0bd
SG		 4051
4052 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3420f797
SG		 4053
4054 rt2800_bbp_write(rt2x00dev, 47, 0x48);
e379de12
SG		 4055
4056 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4057 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 4058
4059 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142
SG		 4060
4061 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4062 rt2800_bbp_write(rt2x00dev, 73, 0x13);
4063 rt2800_bbp_write(rt2x00dev, 75, 0x46);
4064 rt2800_bbp_write(rt2x00dev, 76, 0x28);
4065
4066 rt2800_bbp_write(rt2x00dev, 77, 0x59);
8d97be38
SG		 4067
4068 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 4069
4070 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
4071 rt2800_bbp_write(rt2x00dev, 80, 0x08);
4072 rt2800_bbp_write(rt2x00dev, 81, 0x37);
fa1e3424
SG		 4073
4074 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 4075
4076 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
39ab3e8b
SG		 4077}
4078
4079static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
4080{
e379de12
SG		 4081 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4082 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 4083
4084 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4085 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 4086
4087 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 4088
4089 rt2800_bbp_write(rt2x00dev, 79, 0x13);
4090 rt2800_bbp_write(rt2x00dev, 80, 0x05);
4091 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 4092
4093 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 4094
4095 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
39ab3e8b
SG		 4096}
4097
4098static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
4099{
b2f8e0bd 4100 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 4101
4102 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4103 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 4104
4105 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4106 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 4107
4108 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 4109
4110 rt2800_bbp_write(rt2x00dev, 79, 0x13);
4111 rt2800_bbp_write(rt2x00dev, 80, 0x05);
4112 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 4113
4114 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 4115
4116 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
39ab3e8b
SG		 4117}
4118
4119static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
4120{
c3223573 4121 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
b2f8e0bd
SG		 4122
4123 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 4124
4125 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4126 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 4127
4128 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142
SG		 4129
4130 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4131 rt2800_bbp_write(rt2x00dev, 73, 0x13);
4132 rt2800_bbp_write(rt2x00dev, 75, 0x46);
4133 rt2800_bbp_write(rt2x00dev, 76, 0x28);
4134
4135 rt2800_bbp_write(rt2x00dev, 77, 0x59);
8d97be38
SG		 4136
4137 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 4138
4139 rt2800_bbp_write(rt2x00dev, 79, 0x13);
4140 rt2800_bbp_write(rt2x00dev, 80, 0x05);
4141 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 4142
4143 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 4144
4145 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
39ab3e8b
SG		 4146}
4147
a7bbbe5c
SG		 4148static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
4149{
4150 int ant, div_mode;
4151 u16 eeprom;
4152 u8 value;
4153
624708b8 4154 rt2800_init_bbp_early(rt2x00dev);
a4969d0d 4155
a7bbbe5c
SG		 4156 rt2800_bbp_read(rt2x00dev, 105, &value);
4157 rt2x00_set_field8(&value, BBP105_MLD,
4158 rt2x00dev->default_ant.rx_chain_num == 2);
4159 rt2800_bbp_write(rt2x00dev, 105, value);
4160
4161 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
4162
4163 rt2800_bbp_write(rt2x00dev, 20, 0x06);
4164 rt2800_bbp_write(rt2x00dev, 31, 0x08);
4165 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
4166 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
4167 rt2800_bbp_write(rt2x00dev, 69, 0x1A);
4168 rt2800_bbp_write(rt2x00dev, 70, 0x05);
4169 rt2800_bbp_write(rt2x00dev, 73, 0x13);
4170 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
4171 rt2800_bbp_write(rt2x00dev, 75, 0x4F);
4172 rt2800_bbp_write(rt2x00dev, 76, 0x28);
4173 rt2800_bbp_write(rt2x00dev, 77, 0x59);
4174 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
4175 rt2800_bbp_write(rt2x00dev, 86, 0x38);
4176 rt2800_bbp_write(rt2x00dev, 88, 0x90);
4177 rt2800_bbp_write(rt2x00dev, 91, 0x04);
4178 rt2800_bbp_write(rt2x00dev, 92, 0x02);
4179 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
4180 rt2800_bbp_write(rt2x00dev, 98, 0x12);
4181 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
4182 rt2800_bbp_write(rt2x00dev, 104, 0x92);
4183 /* FIXME BBP105 owerwrite */
4184 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
4185 rt2800_bbp_write(rt2x00dev, 106, 0x35);
4186 rt2800_bbp_write(rt2x00dev, 128, 0x12);
4187 rt2800_bbp_write(rt2x00dev, 134, 0xD0);
4188 rt2800_bbp_write(rt2x00dev, 135, 0xF6);
4189 rt2800_bbp_write(rt2x00dev, 137, 0x0F);
4190
4191 /* Initialize GLRT (Generalized Likehood Radio Test) */
4192 rt2800_init_bbp_5592_glrt(rt2x00dev);
4193
4194 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
4195
4196 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4197 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
4198 ant = (div_mode == 3) ? 1 : 0;
4199 rt2800_bbp_read(rt2x00dev, 152, &value);
4200 if (ant == 0) {
4201 /* Main antenna */
4202 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
4203 } else {
4204 /* Auxiliary antenna */
4205 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
4206 }
4207 rt2800_bbp_write(rt2x00dev, 152, value);
4208
4209 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
4210 rt2800_bbp_read(rt2x00dev, 254, &value);
4211 rt2x00_set_field8(&value, BBP254_BIT7, 1);
4212 rt2800_bbp_write(rt2x00dev, 254, value);
4213 }
4214
c2675487
SG		 4215 rt2800_init_freq_calibration(rt2x00dev);
4216
a7bbbe5c 4217 rt2800_bbp_write(rt2x00dev, 84, 0x19);
6e04f253
SG		 4218 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
4219 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
a7bbbe5c
SG		 4220}
4221
a1ef5039 4222static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 4223{
4224 unsigned int i;
4225 u16 eeprom;
4226 u8 reg_id;
4227 u8 value;
4228
dae62957
SG		 4229 if (rt2800_is_305x_soc(rt2x00dev))
4230 rt2800_init_bbp_305x_soc(rt2x00dev);
4231
39ab3e8b
SG		 4232 switch (rt2x00dev->chip.rt) {
4233 case RT2860:
4234 case RT2872:
4235 case RT2883:
4236 rt2800_init_bbp_28xx(rt2x00dev);
4237 break;
4238 case RT3070:
4239 case RT3071:
4240 case RT3090:
4241 rt2800_init_bbp_30xx(rt2x00dev);
4242 break;
4243 case RT3290:
4244 rt2800_init_bbp_3290(rt2x00dev);
4245 break;
4246 case RT3352:
4247 rt2800_init_bbp_3352(rt2x00dev);
4248 break;
4249 case RT3390:
4250 rt2800_init_bbp_3390(rt2x00dev);
4251 break;
4252 case RT3572:
4253 rt2800_init_bbp_3572(rt2x00dev);
4254 break;
4255 case RT5390:
4256 case RT5392:
4257 rt2800_init_bbp_53xx(rt2x00dev);
4258 break;
4259 case RT5592:
a7bbbe5c 4260 rt2800_init_bbp_5592(rt2x00dev);
a1ef5039 4261 return;
a7bbbe5c
SG		 4262 }
4263
5ed8f458 4264 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
a9dce149 4265 rt2800_bbp_write(rt2x00dev, 84, 0x19);
a89534ed 4266 else if (rt2x00_rt(rt2x00dev, RT3290) ||
e6d227b9
GJ		 4267 rt2x00_rt(rt2x00dev, RT5390) ||
4268 rt2x00_rt(rt2x00dev, RT5392))
adde5882 4269 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
a9dce149
GW		 4270 else
4271 rt2800_bbp_write(rt2x00dev, 84, 0x99);
4272
a89534ed 4273 if (rt2x00_rt(rt2x00dev, RT3290) ||
03839951 4274 rt2x00_rt(rt2x00dev, RT3352) ||
a89534ed
WH		 4275 rt2x00_rt(rt2x00dev, RT5390) ||
4276 rt2x00_rt(rt2x00dev, RT5392))
adde5882
GJ		 4277 rt2800_bbp_write(rt2x00dev, 86, 0x38);
4278 else
4279 rt2800_bbp_write(rt2x00dev, 86, 0x00);
60687ba7 4280
03839951
DG		 4281 if (rt2x00_rt(rt2x00dev, RT3352) ||
4282 rt2x00_rt(rt2x00dev, RT5392))
2ed71884
JL		 4283 rt2800_bbp_write(rt2x00dev, 88, 0x90);
4284
fcf51541 4285 rt2800_bbp_write(rt2x00dev, 91, 0x04);
60687ba7 4286
a89534ed 4287 if (rt2x00_rt(rt2x00dev, RT3290) ||
03839951 4288 rt2x00_rt(rt2x00dev, RT3352) ||
a89534ed
WH		 4289 rt2x00_rt(rt2x00dev, RT5390) ||
4290 rt2x00_rt(rt2x00dev, RT5392))
adde5882
GJ		 4291 rt2800_bbp_write(rt2x00dev, 92, 0x02);
4292 else
4293 rt2800_bbp_write(rt2x00dev, 92, 0x00);
8cdd15e0 4294
2ed71884
JL		 4295 if (rt2x00_rt(rt2x00dev, RT5392)) {
4296 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
4297 rt2800_bbp_write(rt2x00dev, 98, 0x12);
4298 }
4299
d5385bfc 4300 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 4301 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904 4302 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
baff8006 4303 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
a89534ed 4304 rt2x00_rt(rt2x00dev, RT3290) ||
03839951 4305 rt2x00_rt(rt2x00dev, RT3352) ||
872834df 4306 rt2x00_rt(rt2x00dev, RT3572) ||
adde5882 4307 rt2x00_rt(rt2x00dev, RT5390) ||
2ed71884 4308 rt2x00_rt(rt2x00dev, RT5392) ||
baff8006 4309 rt2800_is_305x_soc(rt2x00dev))
8cdd15e0
GW		 4310 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4311 else
4312 rt2800_bbp_write(rt2x00dev, 103, 0x00);
4313
a89534ed 4314 if (rt2x00_rt(rt2x00dev, RT3290) ||
03839951 4315 rt2x00_rt(rt2x00dev, RT3352) ||
a89534ed
WH		 4316 rt2x00_rt(rt2x00dev, RT5390) ||
4317 rt2x00_rt(rt2x00dev, RT5392))
adde5882 4318 rt2800_bbp_write(rt2x00dev, 104, 0x92);
60687ba7 4319
baff8006
HS		 4320 if (rt2800_is_305x_soc(rt2x00dev))
4321 rt2800_bbp_write(rt2x00dev, 105, 0x01);
a89534ed
WH		 4322 else if (rt2x00_rt(rt2x00dev, RT3290))
4323 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
03839951
DG		 4324 else if (rt2x00_rt(rt2x00dev, RT3352))
4325 rt2800_bbp_write(rt2x00dev, 105, 0x34);
2ed71884 4326 else if (rt2x00_rt(rt2x00dev, RT5390) ||
e6d227b9 4327 rt2x00_rt(rt2x00dev, RT5392))
adde5882 4328 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
baff8006
HS		 4329 else
4330 rt2800_bbp_write(rt2x00dev, 105, 0x05);
60687ba7 4331
a89534ed
WH		 4332 if (rt2x00_rt(rt2x00dev, RT3290) ||
4333 rt2x00_rt(rt2x00dev, RT5390))
adde5882 4334 rt2800_bbp_write(rt2x00dev, 106, 0x03);
03839951
DG		 4335 else if (rt2x00_rt(rt2x00dev, RT3352))
4336 rt2800_bbp_write(rt2x00dev, 106, 0x05);
2ed71884
JL		 4337 else if (rt2x00_rt(rt2x00dev, RT5392))
4338 rt2800_bbp_write(rt2x00dev, 106, 0x12);
adde5882
GJ		 4339 else
4340 rt2800_bbp_write(rt2x00dev, 106, 0x35);
60687ba7 4341
03839951
DG		 4342 if (rt2x00_rt(rt2x00dev, RT3352))
4343 rt2800_bbp_write(rt2x00dev, 120, 0x50);
4344
a89534ed
WH		 4345 if (rt2x00_rt(rt2x00dev, RT3290) ||
4346 rt2x00_rt(rt2x00dev, RT5390) ||
4347 rt2x00_rt(rt2x00dev, RT5392))
adde5882 4348 rt2800_bbp_write(rt2x00dev, 128, 0x12);
fcf51541 4349
2ed71884
JL		 4350 if (rt2x00_rt(rt2x00dev, RT5392)) {
4351 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
4352 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
4353 }
4354
03839951
DG		 4355 if (rt2x00_rt(rt2x00dev, RT3352))
4356 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
4357
64522957 4358 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 4359 rt2x00_rt(rt2x00dev, RT3090) ||
adde5882 4360 rt2x00_rt(rt2x00dev, RT3390) ||
872834df 4361 rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884
JL		 4362 rt2x00_rt(rt2x00dev, RT5390) ||
4363 rt2x00_rt(rt2x00dev, RT5392)) {
d5385bfc 4364 rt2800_bbp_read(rt2x00dev, 138, &value);
fcf51541 4365
38c8a566
RJH		 4366 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4367 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
d5385bfc 4368 value |= 0x20;
38c8a566 4369 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
d5385bfc 4370 value &= ~0x02;
fcf51541 4371
d5385bfc 4372 rt2800_bbp_write(rt2x00dev, 138, value);
fcf51541
BZ		 4373 }
4374
a89534ed
WH		 4375 if (rt2x00_rt(rt2x00dev, RT3290)) {
4376 rt2800_bbp_write(rt2x00dev, 67, 0x24);
4377 rt2800_bbp_write(rt2x00dev, 143, 0x04);
4378 rt2800_bbp_write(rt2x00dev, 142, 0x99);
4379 rt2800_bbp_write(rt2x00dev, 150, 0x30);
4380 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
4381 rt2800_bbp_write(rt2x00dev, 152, 0x20);
4382 rt2800_bbp_write(rt2x00dev, 153, 0x34);
4383 rt2800_bbp_write(rt2x00dev, 154, 0x40);
4384 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
4385 rt2800_bbp_write(rt2x00dev, 253, 0x04);
4386
4387 rt2800_bbp_read(rt2x00dev, 47, &value);
4388 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
4389 rt2800_bbp_write(rt2x00dev, 47, value);
4390
4391 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
4392 rt2800_bbp_read(rt2x00dev, 3, &value);
4393 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
4394 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
4395 rt2800_bbp_write(rt2x00dev, 3, value);
4396 }
4397
03839951
DG		 4398 if (rt2x00_rt(rt2x00dev, RT3352)) {
4399 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
4400 /* Set ITxBF timeout to 0x9c40=1000msec */
4401 rt2800_bbp_write(rt2x00dev, 179, 0x02);
4402 rt2800_bbp_write(rt2x00dev, 180, 0x00);
4403 rt2800_bbp_write(rt2x00dev, 182, 0x40);
4404 rt2800_bbp_write(rt2x00dev, 180, 0x01);
4405 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
4406 rt2800_bbp_write(rt2x00dev, 179, 0x00);
4407 /* Reprogram the inband interface to put right values in RXWI */
4408 rt2800_bbp_write(rt2x00dev, 142, 0x04);
4409 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
4410 rt2800_bbp_write(rt2x00dev, 142, 0x06);
4411 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
4412 rt2800_bbp_write(rt2x00dev, 142, 0x07);
4413 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
4414 rt2800_bbp_write(rt2x00dev, 142, 0x08);
4415 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
4416
4417 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
4418 }
4419
2ed71884 4420 if (rt2x00_rt(rt2x00dev, RT5390) ||
e6d227b9 4421 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 4422 int ant, div_mode;
4423
4424 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4425 div_mode = rt2x00_get_field16(eeprom,
4426 EEPROM_NIC_CONF1_ANT_DIVERSITY);
4427 ant = (div_mode == 3) ? 1 : 0;
4428
4429 /* check if this is a Bluetooth combo card */
fdbc7b0a 4430 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
adde5882
GJ		 4431 u32 reg;
4432
99bdf51a
GW		 4433 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
4434 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
4435 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
4436 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
4437 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
adde5882 4438 if (ant == 0)
99bdf51a 4439 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
adde5882 4440 else if (ant == 1)
99bdf51a
GW		 4441 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
4442 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
adde5882
GJ		 4443 }
4444
0586a11b
AA		 4445 /* This chip has hardware antenna diversity*/
4446 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
4447 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
4448 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
4449 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
4450 }
4451
adde5882
GJ		 4452 rt2800_bbp_read(rt2x00dev, 152, &value);
4453 if (ant == 0)
4454 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
4455 else
4456 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
4457 rt2800_bbp_write(rt2x00dev, 152, value);
4458
c2675487 4459 rt2800_init_freq_calibration(rt2x00dev);
adde5882 4460 }
fcf51541
BZ		 4461
4462 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
4463 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
4464
4465 if (eeprom != 0xffff && eeprom != 0x0000) {
4466 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
4467 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
4468 rt2800_bbp_write(rt2x00dev, reg_id, value);
4469 }
4470 }
fcf51541 4471}
fcf51541 4472
d9517f2f
SG		 4473static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
4474{
4475 u32 reg;
4476
4477 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
4478 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
4479 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
4480}
4481
c5b3c350
SG		 4482static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
4483 u8 filter_target)
fcf51541
BZ		 4484{
4485 unsigned int i;
4486 u8 bbp;
4487 u8 rfcsr;
4488 u8 passband;
4489 u8 stopband;
4490 u8 overtuned = 0;
c5b3c350 4491 u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
fcf51541
BZ		 4492
4493 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
4494
4495 rt2800_bbp_read(rt2x00dev, 4, &bbp);
4496 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
4497 rt2800_bbp_write(rt2x00dev, 4, bbp);
4498
80d184e6
RJH		 4499 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
4500 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
4501 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
4502
fcf51541
BZ		 4503 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
4504 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
4505 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
4506
4507 /*
4508 * Set power & frequency of passband test tone
4509 */
4510 rt2800_bbp_write(rt2x00dev, 24, 0);
4511
4512 for (i = 0; i < 100; i++) {
4513 rt2800_bbp_write(rt2x00dev, 25, 0x90);
4514 msleep(1);
4515
4516 rt2800_bbp_read(rt2x00dev, 55, &passband);
4517 if (passband)
4518 break;
4519 }
4520
4521 /*
4522 * Set power & frequency of stopband test tone
4523 */
4524 rt2800_bbp_write(rt2x00dev, 24, 0x06);
4525
4526 for (i = 0; i < 100; i++) {
4527 rt2800_bbp_write(rt2x00dev, 25, 0x90);
4528 msleep(1);
4529
4530 rt2800_bbp_read(rt2x00dev, 55, &stopband);
4531
4532 if ((passband - stopband) <= filter_target) {
4533 rfcsr24++;
4534 overtuned += ((passband - stopband) == filter_target);
4535 } else
4536 break;
4537
4538 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
4539 }
4540
4541 rfcsr24 -= !!overtuned;
4542
4543 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
4544 return rfcsr24;
4545}
4546
ce94ede9
SG		 4547static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
4548 const unsigned int rf_reg)
4549{
4550 u8 rfcsr;
4551
4552 rt2800_rfcsr_read(rt2x00dev, rf_reg, &rfcsr);
4553 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
4554 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
4555 msleep(1);
4556 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
4557 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
4558}
4559
c5b3c350
SG		 4560static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
4561{
4562 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
4563 u8 filter_tgt_bw20;
4564 u8 filter_tgt_bw40;
4565 u8 rfcsr, bbp;
4566
4567 /*
4568 * TODO: sync filter_tgt values with vendor driver
4569 */
4570 if (rt2x00_rt(rt2x00dev, RT3070)) {
4571 filter_tgt_bw20 = 0x16;
4572 filter_tgt_bw40 = 0x19;
4573 } else {
4574 filter_tgt_bw20 = 0x13;
4575 filter_tgt_bw40 = 0x15;
4576 }
4577
4578 drv_data->calibration_bw20 =
4579 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
4580 drv_data->calibration_bw40 =
4581 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
4582
4583 /*
4584 * Save BBP 25 & 26 values for later use in channel switching (for 3052)
4585 */
4586 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
4587 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
4588
4589 /*
4590 * Set back to initial state
4591 */
4592 rt2800_bbp_write(rt2x00dev, 24, 0);
4593
4594 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
4595 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
4596 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
4597
4598 /*
4599 * Set BBP back to BW20
4600 */
4601 rt2800_bbp_read(rt2x00dev, 4, &bbp);
4602 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
4603 rt2800_bbp_write(rt2x00dev, 4, bbp);
4604}
4605
da8064c2
SG		 4606static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
4607{
4608 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
4609 u8 min_gain, rfcsr, bbp;
4610 u16 eeprom;
4611
4612 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
4613
4614 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
4615 if (rt2x00_rt(rt2x00dev, RT3070) ||
4616 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4617 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4618 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
4619 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags))
4620 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
4621 }
4622
4623 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
4624 if (drv_data->txmixer_gain_24g >= min_gain) {
4625 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
4626 drv_data->txmixer_gain_24g);
4627 }
4628
4629 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
4630
4631 if (rt2x00_rt(rt2x00dev, RT3090)) {
4632 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
4633 rt2800_bbp_read(rt2x00dev, 138, &bbp);
4634 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4635 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4636 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
4637 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4638 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
4639 rt2800_bbp_write(rt2x00dev, 138, bbp);
4640 }
4641
4642 if (rt2x00_rt(rt2x00dev, RT3070)) {
4643 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
4644 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
4645 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
4646 else
4647 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
4648 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
4649 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
4650 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
4651 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
4652 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4653 rt2x00_rt(rt2x00dev, RT3090) ||
4654 rt2x00_rt(rt2x00dev, RT3390)) {
4655 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
4656 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
4657 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
4658 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
4659 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
4660 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
4661 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
4662
4663 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
4664 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
4665 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
4666
4667 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
4668 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
4669 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
4670
4671 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
4672 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
4673 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
4674 }
4675}
4676
f7df8fe5
SG		 4677static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
4678{
4679 u8 reg;
4680 u16 eeprom;
4681
4682 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
4683 rt2800_bbp_read(rt2x00dev, 138, &reg);
4684 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4685 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4686 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
4687 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4688 rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
4689 rt2800_bbp_write(rt2x00dev, 138, reg);
4690
4691 rt2800_rfcsr_read(rt2x00dev, 38, &reg);
4692 rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
4693 rt2800_rfcsr_write(rt2x00dev, 38, reg);
4694
4695 rt2800_rfcsr_read(rt2x00dev, 39, &reg);
4696 rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
4697 rt2800_rfcsr_write(rt2x00dev, 39, reg);
4698
4699 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
4700
4701 rt2800_rfcsr_read(rt2x00dev, 30, &reg);
4702 rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
4703 rt2800_rfcsr_write(rt2x00dev, 30, reg);
4704}
4705
d5374ef1
SG		 4706static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
4707{
ce94ede9
SG		 4708 rt2800_rf_init_calibration(rt2x00dev, 30);
4709
d5374ef1
SG		 4710 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
4711 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
4712 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
4713 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
4714 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
4715 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
4716 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
4717 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
4718 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
4719 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
4720 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
4721 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
4722 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
4723 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
4724 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
4725 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
4726 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
4727 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
4728 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
4729 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4730 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
4731 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
4732 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4733 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
4734 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
4735 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
4736 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
4737 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
4738 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
4739 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
4740 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
4741 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
4742}
4743
4744static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
4745{
c9a221b2
SG		 4746 u8 rfcsr;
4747 u16 eeprom;
4748 u32 reg;
4749
ce94ede9
SG		 4750 /* XXX vendor driver do this only for 3070 */
4751 rt2800_rf_init_calibration(rt2x00dev, 30);
4752
d5374ef1
SG		 4753 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
4754 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
4755 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
4756 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
4757 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
4758 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
4759 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
4760 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
4761 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
4762 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
4763 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
4764 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
4765 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
4766 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4767 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
4768 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
4769 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
4770 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
4771 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
c9a221b2
SG		 4772
4773 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4774 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4775 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4776 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4777 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4778 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4779 rt2x00_rt(rt2x00dev, RT3090)) {
4780 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
4781
4782 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
4783 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
4784 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
4785
4786 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4787 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4788 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4789 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
4790 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4791 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
4792 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4793 else
4794 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
4795 }
4796 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4797
4798 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
4799 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
4800 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
4801 }
c5b3c350
SG		 4802
4803 rt2800_rx_filter_calibration(rt2x00dev);
5de5a1f4
SG		 4804
4805 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
4806 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4807 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
4808 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 4809
4810 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 4811 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 4812}
4813
4814static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
4815{
f9cdcbb1
SG		 4816 u8 rfcsr;
4817
ce94ede9
SG		 4818 rt2800_rf_init_calibration(rt2x00dev, 2);
4819
d5374ef1
SG		 4820 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
4821 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4822 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
4823 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
4824 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
4825 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
4826 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
4827 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
4828 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
4829 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
4830 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
4831 rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
4832 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
4833 rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
4834 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
4835 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
4836 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4837 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4838 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4839 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4840 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4841 rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
4842 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4843 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
4844 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
4845 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
4846 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
4847 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
4848 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
4849 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
4850 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
4851 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
4852 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
4853 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
4854 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
4855 rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
4856 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
4857 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
4858 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
4859 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
4860 rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
4861 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
4862 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
4863 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
4864 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
4865 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
f9cdcbb1
SG		 4866
4867 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
4868 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
4869 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
d9517f2f
SG		 4870
4871 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 4872 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 4873}
4874
4875static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
4876{
ce94ede9
SG		 4877 rt2800_rf_init_calibration(rt2x00dev, 30);
4878
d5374ef1
SG		 4879 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
4880 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
4881 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
4882 rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
4883 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
4884 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
4885 rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
4886 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4887 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
4888 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
4889 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
4890 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
4891 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
4892 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
4893 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
4894 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4895 rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
4896 rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
4897 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4898 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4899 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
4900 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4901 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
4902 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
4903 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4904 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
4905 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
4906 rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
4907 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
4908 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4909 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4910 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4911 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4912 rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
4913 rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
4914 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
4915 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
4916 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
4917 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
4918 rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
4919 rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
4920 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
4921 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
4922 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
4923 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
4924 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
4925 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
4926 rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
4927 rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
4928 rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
4929 rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
4930 rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
4931 rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
4932 rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
4933 rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
4934 rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
4935 rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
4936 rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
4937 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
4938 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
4939 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
4940 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
4941 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
c5b3c350
SG		 4942
4943 rt2800_rx_filter_calibration(rt2x00dev);
d9517f2f 4944 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 4945 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 4946}
4947
4948static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
4949{
2971e66f
SG		 4950 u32 reg;
4951
ce94ede9
SG		 4952 rt2800_rf_init_calibration(rt2x00dev, 30);
4953
d5374ef1
SG		 4954 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
4955 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
4956 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
4957 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
4958 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
4959 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
4960 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
4961 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
4962 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
4963 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
4964 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
4965 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
4966 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
4967 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
4968 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
4969 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
4970 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
4971 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
4972 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
4973 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
4974 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
4975 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
4976 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4977 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
4978 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
4979 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
4980 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
4981 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
4982 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
4983 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
4984 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
4985 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
2971e66f
SG		 4986
4987 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
4988 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
4989 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
c5b3c350
SG		 4990
4991 rt2800_rx_filter_calibration(rt2x00dev);
5de5a1f4
SG		 4992
4993 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
4994 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 4995
4996 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 4997 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 4998}
4999
5000static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
5001{
87d91db9
SG		 5002 u8 rfcsr;
5003 u32 reg;
5004
ce94ede9
SG		 5005 rt2800_rf_init_calibration(rt2x00dev, 30);
5006
d5374ef1
SG		 5007 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
5008 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
5009 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
5010 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
5011 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
5012 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
5013 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
5014 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
5015 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
5016 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
5017 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
5018 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
5019 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
5020 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
5021 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
5022 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
5023 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
5024 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
5025 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
5026 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
5027 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
5028 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
5029 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
5030 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
5031 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
5032 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
5033 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
5034 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
5035 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
5036 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
5037 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
87d91db9
SG		 5038
5039 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
5040 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
5041 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
5042
5043 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
5044 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
5045 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
5046 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
5047 msleep(1);
5048 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
5049 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
5050 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
5051 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
c5b3c350
SG		 5052
5053 rt2800_rx_filter_calibration(rt2x00dev);
d9517f2f 5054 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 5055 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 5056}
5057
5058static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
5059{
ce94ede9
SG		 5060 rt2800_rf_init_calibration(rt2x00dev, 2);
5061
d5374ef1
SG		 5062 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
5063 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
5064 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
5065 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
5066 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
5067 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
5068 else
5069 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
5070 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
5071 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
5072 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
5073 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
5074 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
5075 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
5076 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
5077 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
5078 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
5079 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
5080
5081 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
5082 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
5083 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
5084 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
5085 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
5086 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
5087 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
5088 else
5089 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
5090 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
5091 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
5092 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
5093 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
5094
5095 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
5096 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
5097 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
5098 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
5099 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
5100 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
5101 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
5102 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
5103 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
5104 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
5105
5106 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
5107 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
5108 else
5109 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
5110 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
5111 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
5112 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
5113 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
5114 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
5115 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
5116 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
5117 else
5118 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
5119 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
5120 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
5121 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
5122
5123 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
5124 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
5125 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
5126 else
5127 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
5128 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
5129 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
5130 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
5131 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
5132 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
5133 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
5134
5135 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
5136 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
5137 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
5138 else
5139 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
5140 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
5141 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
f7df8fe5
SG		 5142
5143 rt2800_normal_mode_setup_5xxx(rt2x00dev);
d9517f2f
SG		 5144
5145 rt2800_led_open_drain_enable(rt2x00dev);
d5374ef1
SG		 5146}
5147
5148static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
5149{
ce94ede9
SG		 5150 rt2800_rf_init_calibration(rt2x00dev, 2);
5151
d5374ef1
SG		 5152 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
5153 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
5154 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
5155 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
5156 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
5157 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
5158 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
5159 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
5160 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
5161 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
5162 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
5163 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
5164 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
5165 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
5166 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
5167 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
5168 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
5169 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
5170 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
5171 rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
5172 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
5173 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
5174 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
5175 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
5176 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
5177 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
5178 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
5179 rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
5180 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
5181 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
5182 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
5183 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
5184 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
5185 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
5186 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
5187 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
5188 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
5189 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
5190 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
5191 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
5192 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
5193 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
5194 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
5195 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
5196 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
5197 rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
5198 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
5199 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
5200 rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
5201 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
5202 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
5203 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
5204 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
5205 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
5206 rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
5207 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
5208 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
5209 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
5210 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
f7df8fe5
SG		 5211
5212 rt2800_normal_mode_setup_5xxx(rt2x00dev);
d9517f2f
SG		 5213
5214 rt2800_led_open_drain_enable(rt2x00dev);
d5374ef1
SG		 5215}
5216
0c9e5fb9
SG		 5217static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
5218{
ce94ede9
SG		 5219 rt2800_rf_init_calibration(rt2x00dev, 30);
5220
0c9e5fb9
SG		 5221 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
5222 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
5223 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
5224 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
5225 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
5226 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
5227 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
5228 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
5229 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
5230 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
5231 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
5232 rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
5233 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
5234 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
5235 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
5236 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
5237 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
5238 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
5239 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
5240 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
5241 rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
5242 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
5243
5244 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
5245 msleep(1);
5246
5247 rt2800_adjust_freq_offset(rt2x00dev);
c630ccf1 5248
c630ccf1
SG		 5249 /* Enable DC filter */
5250 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
5251 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5252
f7df8fe5 5253 rt2800_normal_mode_setup_5xxx(rt2x00dev);
5de5a1f4
SG		 5254
5255 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
5256 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 5257
5258 rt2800_led_open_drain_enable(rt2x00dev);
0c9e5fb9
SG		 5259}
5260
074f2529 5261static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
fcf51541 5262{
d5374ef1
SG		 5263 if (rt2800_is_305x_soc(rt2x00dev)) {
5264 rt2800_init_rfcsr_305x_soc(rt2x00dev);
074f2529 5265 return;
d5374ef1
SG		 5266 }
5267
5268 switch (rt2x00dev->chip.rt) {
5269 case RT3070:
5270 case RT3071:
5271 case RT3090:
5272 rt2800_init_rfcsr_30xx(rt2x00dev);
5273 break;
5274 case RT3290:
5275 rt2800_init_rfcsr_3290(rt2x00dev);
5276 break;
5277 case RT3352:
5278 rt2800_init_rfcsr_3352(rt2x00dev);
5279 break;
5280 case RT3390:
5281 rt2800_init_rfcsr_3390(rt2x00dev);
5282 break;
5283 case RT3572:
5284 rt2800_init_rfcsr_3572(rt2x00dev);
5285 break;
5286 case RT5390:
5287 rt2800_init_rfcsr_5390(rt2x00dev);
5288 break;
5289 case RT5392:
5290 rt2800_init_rfcsr_5392(rt2x00dev);
5291 break;
0c9e5fb9
SG		 5292 case RT5592:
5293 rt2800_init_rfcsr_5592(rt2x00dev);
074f2529 5294 break;
8cdd15e0 5295 }
fcf51541 5296}
b9a07ae9
ID		 5297
5298int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
5299{
5300 u32 reg;
5301 u16 word;
5302
5303 /*
5304 * Initialize all registers.
5305 */
5306 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
c630ccf1 5307 rt2800_init_registers(rt2x00dev)))
b9a07ae9
ID		 5308 return -EIO;
5309
5310 /*
5311 * Send signal to firmware during boot time.
5312 */
c630ccf1
SG		 5313 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
5314 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
5315 if (rt2x00_is_usb(rt2x00dev)) {
5316 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
5317 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
5318 }
5319 msleep(1);
5320
a1ef5039
SG		 5321 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
5322 rt2800_wait_bbp_ready(rt2x00dev)))
c630ccf1 5323 return -EIO;
b9a07ae9 5324
a1ef5039 5325 rt2800_init_bbp(rt2x00dev);
074f2529
SG		 5326 rt2800_init_rfcsr(rt2x00dev);
5327
b9a07ae9
ID		 5328 if (rt2x00_is_usb(rt2x00dev) &&
5329 (rt2x00_rt(rt2x00dev, RT3070) ||
5330 rt2x00_rt(rt2x00dev, RT3071) ||
5331 rt2x00_rt(rt2x00dev, RT3572))) {
5332 udelay(200);
5333 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
5334 udelay(10);
5335 }
5336
5337 /*
5338 * Enable RX.
5339 */
5340 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5341 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
5342 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
5343 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5344
5345 udelay(50);
5346
5347 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
5348 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
5349 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
5350 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
5351 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
5352 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
5353
5354 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5355 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
5356 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
5357 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5358
5359 /*
5360 * Initialize LED control
5361 */
38c8a566
RJH		 5362 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
5363 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
b9a07ae9
ID		 5364 word & 0xff, (word >> 8) & 0xff);
5365
38c8a566
RJH		 5366 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
5367 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
b9a07ae9
ID		 5368 word & 0xff, (word >> 8) & 0xff);
5369
38c8a566
RJH		 5370 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
5371 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
b9a07ae9
ID		 5372 word & 0xff, (word >> 8) & 0xff);
5373
5374 return 0;
5375}
5376EXPORT_SYMBOL_GPL(rt2800_enable_radio);
5377
5378void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
5379{
5380 u32 reg;
5381
f7b395e9 5382 rt2800_disable_wpdma(rt2x00dev);
b9a07ae9
ID		 5383
5384 /* Wait for DMA, ignore error */
5385 rt2800_wait_wpdma_ready(rt2x00dev);
5386
5387 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5388 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
5389 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
5390 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
b9a07ae9
ID		 5391}
5392EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2ce33995 5393
30e84034
BZ		 5394int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
5395{
5396 u32 reg;
a89534ed 5397 u16 efuse_ctrl_reg;
30e84034 5398
a89534ed
WH		 5399 if (rt2x00_rt(rt2x00dev, RT3290))
5400 efuse_ctrl_reg = EFUSE_CTRL_3290;
5401 else
5402 efuse_ctrl_reg = EFUSE_CTRL;
30e84034 5403
a89534ed 5404 rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
30e84034
BZ		 5405 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
5406}
5407EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
5408
5409static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
5410{
5411 u32 reg;
a89534ed
WH		 5412 u16 efuse_ctrl_reg;
5413 u16 efuse_data0_reg;
5414 u16 efuse_data1_reg;
5415 u16 efuse_data2_reg;
5416 u16 efuse_data3_reg;
5417
5418 if (rt2x00_rt(rt2x00dev, RT3290)) {
5419 efuse_ctrl_reg = EFUSE_CTRL_3290;
5420 efuse_data0_reg = EFUSE_DATA0_3290;
5421 efuse_data1_reg = EFUSE_DATA1_3290;
5422 efuse_data2_reg = EFUSE_DATA2_3290;
5423 efuse_data3_reg = EFUSE_DATA3_3290;
5424 } else {
5425 efuse_ctrl_reg = EFUSE_CTRL;
5426 efuse_data0_reg = EFUSE_DATA0;
5427 efuse_data1_reg = EFUSE_DATA1;
5428 efuse_data2_reg = EFUSE_DATA2;
5429 efuse_data3_reg = EFUSE_DATA3;
5430 }
31a4cf1f
GW		 5431 mutex_lock(&rt2x00dev->csr_mutex);
5432
a89534ed 5433 rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
30e84034
BZ		 5434 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
5435 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
5436 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
a89534ed 5437 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
30e84034
BZ		 5438
5439 /* Wait until the EEPROM has been loaded */
a89534ed 5440 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
30e84034 5441 /* Apparently the data is read from end to start */
a89534ed 5442 rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
daabead1 5443 /* The returned value is in CPU order, but eeprom is le */
68fa64ef 5444 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
a89534ed 5445 rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
daabead1 5446 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
a89534ed 5447 rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
daabead1 5448 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
a89534ed 5449 rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
daabead1 5450 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
31a4cf1f
GW		 5451
5452 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 5453}
5454
a02308e9 5455int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
30e84034
BZ		 5456{
5457 unsigned int i;
5458
5459 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
5460 rt2800_efuse_read(rt2x00dev, i);
a02308e9
GJ		 5461
5462 return 0;
30e84034
BZ		 5463}
5464EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
5465
ad417a53 5466static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
38bd7b8a 5467{
77c06c2c 5468 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
38bd7b8a
BZ		 5469 u16 word;
5470 u8 *mac;
5471 u8 default_lna_gain;
a02308e9 5472 int retval;
38bd7b8a 5473
ad417a53
GW		 5474 /*
5475 * Read the EEPROM.
5476 */
a02308e9
GJ		 5477 retval = rt2800_read_eeprom(rt2x00dev);
5478 if (retval)
5479 return retval;
ad417a53 5480
38bd7b8a
BZ		 5481 /*
5482 * Start validation of the data that has been read.
5483 */
5484 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
5485 if (!is_valid_ether_addr(mac)) {
f4f7f414 5486 eth_random_addr(mac);
ec9c4989 5487 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
38bd7b8a
BZ		 5488 }
5489
38c8a566 5490 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
38bd7b8a 5491 if (word == 0xffff) {
38c8a566
RJH		 5492 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
5493 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
5494 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
5495 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
ec9c4989 5496 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 5497 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 5498 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 5499 /*
5500 * There is a max of 2 RX streams for RT28x0 series
5501 */
38c8a566
RJH		 5502 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
5503 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
5504 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a
BZ		 5505 }
5506
38c8a566 5507 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
38bd7b8a 5508 if (word == 0xffff) {
38c8a566
RJH		 5509 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
5510 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
5511 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
5512 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
5513 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
5514 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
5515 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
5516 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
5517 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
5518 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
5519 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
5520 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
5521 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
5522 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
5523 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
5524 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
ec9c4989 5525 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
38bd7b8a
BZ		 5526 }
5527
5528 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
5529 if ((word & 0x00ff) == 0x00ff) {
5530 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
ec2d1791 5531 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
ec9c4989 5532 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
ec2d1791
GW		 5533 }
5534 if ((word & 0xff00) == 0xff00) {
38bd7b8a
BZ		 5535 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
5536 LED_MODE_TXRX_ACTIVITY);
5537 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
5538 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
38c8a566
RJH		 5539 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
5540 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
5541 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
ec9c4989 5542 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
38bd7b8a
BZ		 5543 }
5544
5545 /*
5546 * During the LNA validation we are going to use
5547 * lna0 as correct value. Note that EEPROM_LNA
5548 * is never validated.
5549 */
5550 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
5551 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
5552
5553 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
5554 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
5555 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
5556 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
5557 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
5558 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
5559
77c06c2c
GW		 5560 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
5561 if ((word & 0x00ff) != 0x00ff) {
5562 drv_data->txmixer_gain_24g =
5563 rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
5564 } else {
5565 drv_data->txmixer_gain_24g = 0;
5566 }
5567
38bd7b8a
BZ		 5568 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
5569 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
5570 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
5571 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
5572 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
5573 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
5574 default_lna_gain);
5575 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
5576
77c06c2c
GW		 5577 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
5578 if ((word & 0x00ff) != 0x00ff) {
5579 drv_data->txmixer_gain_5g =
5580 rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
5581 } else {
5582 drv_data->txmixer_gain_5g = 0;
5583 }
5584
38bd7b8a
BZ		 5585 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
5586 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
5587 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
5588 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
5589 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
5590 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
5591
5592 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
5593 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
5594 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
5595 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
5596 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
5597 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
5598 default_lna_gain);
5599 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
5600
5601 return 0;
5602}
38bd7b8a 5603
ad417a53 5604static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
38bd7b8a 5605{
38bd7b8a
BZ		 5606 u16 value;
5607 u16 eeprom;
86868b26 5608 u16 rf;
38bd7b8a 5609
86868b26
GJ		 5610 /*
5611 * Read EEPROM word for configuration.
5612 */
5613 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5614
5615 /*
5616 * Identify RF chipset by EEPROM value
5617 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
5618 * RT53xx: defined in "EEPROM_CHIP_ID" field
5619 */
5620 if (rt2x00_rt(rt2x00dev, RT3290) ||
5621 rt2x00_rt(rt2x00dev, RT5390) ||
5622 rt2x00_rt(rt2x00dev, RT5392))
5623 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf);
5624 else
5625 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
5626
5627 switch (rf) {
d331eb51
LF		 5628 case RF2820:
5629 case RF2850:
5630 case RF2720:
5631 case RF2750:
5632 case RF3020:
5633 case RF2020:
5634 case RF3021:
5635 case RF3022:
5636 case RF3052:
a89534ed 5637 case RF3290:
d331eb51 5638 case RF3320:
03839951 5639 case RF3322:
ccf91bd6 5640 case RF5360:
d331eb51 5641 case RF5370:
2ed71884 5642 case RF5372:
d331eb51 5643 case RF5390:
cff3d1f0 5644 case RF5392:
b8863f8b 5645 case RF5592:
d331eb51
LF		 5646 break;
5647 default:
ec9c4989
JP		 5648 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
5649 rf);
38bd7b8a
BZ		 5650 return -ENODEV;
5651 }
5652
86868b26
GJ		 5653 rt2x00_set_rf(rt2x00dev, rf);
5654
38bd7b8a
BZ		 5655 /*
5656 * Identify default antenna configuration.
5657 */
d96aa640 5658 rt2x00dev->default_ant.tx_chain_num =
38c8a566 5659 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
d96aa640 5660 rt2x00dev->default_ant.rx_chain_num =
38c8a566 5661 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
38bd7b8a 5662
d96aa640
RJH		 5663 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
5664
5665 if (rt2x00_rt(rt2x00dev, RT3070) ||
5666 rt2x00_rt(rt2x00dev, RT3090) ||
03839951 5667 rt2x00_rt(rt2x00dev, RT3352) ||
d96aa640
RJH		 5668 rt2x00_rt(rt2x00dev, RT3390)) {
5669 value = rt2x00_get_field16(eeprom,
5670 EEPROM_NIC_CONF1_ANT_DIVERSITY);
5671 switch (value) {
5672 case 0:
5673 case 1:
5674 case 2:
5675 rt2x00dev->default_ant.tx = ANTENNA_A;
5676 rt2x00dev->default_ant.rx = ANTENNA_A;
5677 break;
5678 case 3:
5679 rt2x00dev->default_ant.tx = ANTENNA_A;
5680 rt2x00dev->default_ant.rx = ANTENNA_B;
5681 break;
5682 }
5683 } else {
5684 rt2x00dev->default_ant.tx = ANTENNA_A;
5685 rt2x00dev->default_ant.rx = ANTENNA_A;
5686 }
5687
0586a11b
AA		 5688 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
5689 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
5690 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
5691 }
5692
38bd7b8a 5693 /*
9328fdac 5694 * Determine external LNA informations.
38bd7b8a 5695 */
38c8a566 5696 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
7dab73b3 5697 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
38c8a566 5698 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
7dab73b3 5699 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
38bd7b8a
BZ		 5700
5701 /*
5702 * Detect if this device has an hardware controlled radio.
5703 */
38c8a566 5704 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
7dab73b3 5705 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
38bd7b8a 5706
fdbc7b0a
GW		 5707 /*
5708 * Detect if this device has Bluetooth co-existence.
5709 */
5710 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
5711 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
5712
9328fdac
GW		 5713 /*
5714 * Read frequency offset and RF programming sequence.
5715 */
5716 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
5717 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
5718
38bd7b8a
BZ		 5719 /*
5720 * Store led settings, for correct led behaviour.
5721 */
5722#ifdef CONFIG_RT2X00_LIB_LEDS
5723 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
5724 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
5725 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
5726
9328fdac 5727 rt2x00dev->led_mcu_reg = eeprom;
38bd7b8a
BZ		 5728#endif /* CONFIG_RT2X00_LIB_LEDS */
5729
e90c54b2
RJH		 5730 /*
5731 * Check if support EIRP tx power limit feature.
5732 */
5733 rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
5734
5735 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
5736 EIRP_MAX_TX_POWER_LIMIT)
7dab73b3 5737 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
e90c54b2 5738
38bd7b8a
BZ		 5739 return 0;
5740}
38bd7b8a 5741
4da2933f 5742/*
55f9321a 5743 * RF value list for rt28xx
4da2933f
BZ		 5744 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
5745 */
5746static const struct rf_channel rf_vals[] = {
5747 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
5748 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
5749 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
5750 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
5751 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
5752 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
5753 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
5754 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
5755 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
5756 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
5757 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
5758 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
5759 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
5760 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
5761
5762 /* 802.11 UNI / HyperLan 2 */
5763 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
5764 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
5765 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
5766 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
5767 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
5768 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
5769 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
5770 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
5771 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
5772 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
5773 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
5774 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
5775
5776 /* 802.11 HyperLan 2 */
5777 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
5778 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
5779 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
5780 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
5781 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
5782 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
5783 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
5784 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
5785 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
5786 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
5787 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
5788 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
5789 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
5790 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
5791 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
5792 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
5793
5794 /* 802.11 UNII */
5795 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
5796 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
5797 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
5798 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
5799 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
5800 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
5801 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
5802 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
5803 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
5804 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
5805 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
5806
5807 /* 802.11 Japan */
5808 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
5809 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
5810 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
5811 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
5812 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
5813 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
5814 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
5815};
5816
5817/*
55f9321a
ID		 5818 * RF value list for rt3xxx
5819 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4da2933f 5820 */
55f9321a 5821static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 5822 {1, 241, 2, 2 },
5823 {2, 241, 2, 7 },
5824 {3, 242, 2, 2 },
5825 {4, 242, 2, 7 },
5826 {5, 243, 2, 2 },
5827 {6, 243, 2, 7 },
5828 {7, 244, 2, 2 },
5829 {8, 244, 2, 7 },
5830 {9, 245, 2, 2 },
5831 {10, 245, 2, 7 },
5832 {11, 246, 2, 2 },
5833 {12, 246, 2, 7 },
5834 {13, 247, 2, 2 },
5835 {14, 248, 2, 4 },
55f9321a
ID		 5836
5837 /* 802.11 UNI / HyperLan 2 */
5838 {36, 0x56, 0, 4},
5839 {38, 0x56, 0, 6},
5840 {40, 0x56, 0, 8},
5841 {44, 0x57, 0, 0},
5842 {46, 0x57, 0, 2},
5843 {48, 0x57, 0, 4},
5844 {52, 0x57, 0, 8},
5845 {54, 0x57, 0, 10},
5846 {56, 0x58, 0, 0},
5847 {60, 0x58, 0, 4},
5848 {62, 0x58, 0, 6},
5849 {64, 0x58, 0, 8},
5850
5851 /* 802.11 HyperLan 2 */
5852 {100, 0x5b, 0, 8},
5853 {102, 0x5b, 0, 10},
5854 {104, 0x5c, 0, 0},
5855 {108, 0x5c, 0, 4},
5856 {110, 0x5c, 0, 6},
5857 {112, 0x5c, 0, 8},
5858 {116, 0x5d, 0, 0},
5859 {118, 0x5d, 0, 2},
5860 {120, 0x5d, 0, 4},
5861 {124, 0x5d, 0, 8},
5862 {126, 0x5d, 0, 10},
5863 {128, 0x5e, 0, 0},
5864 {132, 0x5e, 0, 4},
5865 {134, 0x5e, 0, 6},
5866 {136, 0x5e, 0, 8},
5867 {140, 0x5f, 0, 0},
5868
5869 /* 802.11 UNII */
5870 {149, 0x5f, 0, 9},
5871 {151, 0x5f, 0, 11},
5872 {153, 0x60, 0, 1},
5873 {157, 0x60, 0, 5},
5874 {159, 0x60, 0, 7},
5875 {161, 0x60, 0, 9},
5876 {165, 0x61, 0, 1},
5877 {167, 0x61, 0, 3},
5878 {169, 0x61, 0, 5},
5879 {171, 0x61, 0, 7},
5880 {173, 0x61, 0, 9},
4da2933f
BZ		 5881};
5882
7848b231
SG		 5883static const struct rf_channel rf_vals_5592_xtal20[] = {
5884 /* Channel, N, K, mod, R */
5885 {1, 482, 4, 10, 3},
5886 {2, 483, 4, 10, 3},
5887 {3, 484, 4, 10, 3},
5888 {4, 485, 4, 10, 3},
5889 {5, 486, 4, 10, 3},
5890 {6, 487, 4, 10, 3},
5891 {7, 488, 4, 10, 3},
5892 {8, 489, 4, 10, 3},
5893 {9, 490, 4, 10, 3},
5894 {10, 491, 4, 10, 3},
5895 {11, 492, 4, 10, 3},
5896 {12, 493, 4, 10, 3},
5897 {13, 494, 4, 10, 3},
5898 {14, 496, 8, 10, 3},
5899 {36, 172, 8, 12, 1},
5900 {38, 173, 0, 12, 1},
5901 {40, 173, 4, 12, 1},
5902 {42, 173, 8, 12, 1},
5903 {44, 174, 0, 12, 1},
5904 {46, 174, 4, 12, 1},
5905 {48, 174, 8, 12, 1},
5906 {50, 175, 0, 12, 1},
5907 {52, 175, 4, 12, 1},
5908 {54, 175, 8, 12, 1},
5909 {56, 176, 0, 12, 1},
5910 {58, 176, 4, 12, 1},
5911 {60, 176, 8, 12, 1},
5912 {62, 177, 0, 12, 1},
5913 {64, 177, 4, 12, 1},
5914 {100, 183, 4, 12, 1},
5915 {102, 183, 8, 12, 1},
5916 {104, 184, 0, 12, 1},
5917 {106, 184, 4, 12, 1},
5918 {108, 184, 8, 12, 1},
5919 {110, 185, 0, 12, 1},
5920 {112, 185, 4, 12, 1},
5921 {114, 185, 8, 12, 1},
5922 {116, 186, 0, 12, 1},
5923 {118, 186, 4, 12, 1},
5924 {120, 186, 8, 12, 1},
5925 {122, 187, 0, 12, 1},
5926 {124, 187, 4, 12, 1},
5927 {126, 187, 8, 12, 1},
5928 {128, 188, 0, 12, 1},
5929 {130, 188, 4, 12, 1},
5930 {132, 188, 8, 12, 1},
5931 {134, 189, 0, 12, 1},
5932 {136, 189, 4, 12, 1},
5933 {138, 189, 8, 12, 1},
5934 {140, 190, 0, 12, 1},
5935 {149, 191, 6, 12, 1},
5936 {151, 191, 10, 12, 1},
5937 {153, 192, 2, 12, 1},
5938 {155, 192, 6, 12, 1},
5939 {157, 192, 10, 12, 1},
5940 {159, 193, 2, 12, 1},
5941 {161, 193, 6, 12, 1},
5942 {165, 194, 2, 12, 1},
5943 {184, 164, 0, 12, 1},
5944 {188, 164, 4, 12, 1},
5945 {192, 165, 8, 12, 1},
5946 {196, 166, 0, 12, 1},
5947};
5948
5949static const struct rf_channel rf_vals_5592_xtal40[] = {
5950 /* Channel, N, K, mod, R */
5951 {1, 241, 2, 10, 3},
5952 {2, 241, 7, 10, 3},
5953 {3, 242, 2, 10, 3},
5954 {4, 242, 7, 10, 3},
5955 {5, 243, 2, 10, 3},
5956 {6, 243, 7, 10, 3},
5957 {7, 244, 2, 10, 3},
5958 {8, 244, 7, 10, 3},
5959 {9, 245, 2, 10, 3},
5960 {10, 245, 7, 10, 3},
5961 {11, 246, 2, 10, 3},
5962 {12, 246, 7, 10, 3},
5963 {13, 247, 2, 10, 3},
5964 {14, 248, 4, 10, 3},
5965 {36, 86, 4, 12, 1},
5966 {38, 86, 6, 12, 1},
5967 {40, 86, 8, 12, 1},
5968 {42, 86, 10, 12, 1},
5969 {44, 87, 0, 12, 1},
5970 {46, 87, 2, 12, 1},
5971 {48, 87, 4, 12, 1},
5972 {50, 87, 6, 12, 1},
5973 {52, 87, 8, 12, 1},
5974 {54, 87, 10, 12, 1},
5975 {56, 88, 0, 12, 1},
5976 {58, 88, 2, 12, 1},
5977 {60, 88, 4, 12, 1},
5978 {62, 88, 6, 12, 1},
5979 {64, 88, 8, 12, 1},
5980 {100, 91, 8, 12, 1},
5981 {102, 91, 10, 12, 1},
5982 {104, 92, 0, 12, 1},
5983 {106, 92, 2, 12, 1},
5984 {108, 92, 4, 12, 1},
5985 {110, 92, 6, 12, 1},
5986 {112, 92, 8, 12, 1},
5987 {114, 92, 10, 12, 1},
5988 {116, 93, 0, 12, 1},
5989 {118, 93, 2, 12, 1},
5990 {120, 93, 4, 12, 1},
5991 {122, 93, 6, 12, 1},
5992 {124, 93, 8, 12, 1},
5993 {126, 93, 10, 12, 1},
5994 {128, 94, 0, 12, 1},
5995 {130, 94, 2, 12, 1},
5996 {132, 94, 4, 12, 1},
5997 {134, 94, 6, 12, 1},
5998 {136, 94, 8, 12, 1},
5999 {138, 94, 10, 12, 1},
6000 {140, 95, 0, 12, 1},
6001 {149, 95, 9, 12, 1},
6002 {151, 95, 11, 12, 1},
6003 {153, 96, 1, 12, 1},
6004 {155, 96, 3, 12, 1},
6005 {157, 96, 5, 12, 1},
6006 {159, 96, 7, 12, 1},
6007 {161, 96, 9, 12, 1},
6008 {165, 97, 1, 12, 1},
6009 {184, 82, 0, 12, 1},
6010 {188, 82, 4, 12, 1},
6011 {192, 82, 8, 12, 1},
6012 {196, 83, 0, 12, 1},
6013};
6014
ad417a53 6015static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4da2933f 6016{
4da2933f
BZ		 6017 struct hw_mode_spec *spec = &rt2x00dev->spec;
6018 struct channel_info *info;
8d1331b3
ID		 6019 char *default_power1;
6020 char *default_power2;
4da2933f
BZ		 6021 unsigned int i;
6022 u16 eeprom;
7848b231 6023 u32 reg;
4da2933f 6024
93b6bd26
GW		 6025 /*
6026 * Disable powersaving as default on PCI devices.
6027 */
cea90e55 6028 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
93b6bd26
GW		 6029 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
6030
4da2933f
BZ		 6031 /*
6032 * Initialize all hw fields.
6033 */
6034 rt2x00dev->hw->flags =
4da2933f
BZ		 6035 IEEE80211_HW_SIGNAL_DBM |
6036 IEEE80211_HW_SUPPORTS_PS |
1df90809 6037 IEEE80211_HW_PS_NULLFUNC_STACK |
9d4f09b8 6038 IEEE80211_HW_AMPDU_AGGREGATION |
84e9e8eb 6039 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
9d4f09b8 6040
5a5b6ed6
HS		 6041 /*
6042 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
6043 * unless we are capable of sending the buffered frames out after the
6044 * DTIM transmission using rt2x00lib_beacondone. This will send out
6045 * multicast and broadcast traffic immediately instead of buffering it
6046 * infinitly and thus dropping it after some time.
6047 */
6048 if (!rt2x00_is_usb(rt2x00dev))
6049 rt2x00dev->hw->flags |=
6050 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
4da2933f 6051
4da2933f
BZ		 6052 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
6053 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
6054 rt2x00_eeprom_addr(rt2x00dev,
6055 EEPROM_MAC_ADDR_0));
6056
3f2bee24
HS		 6057 /*
6058 * As rt2800 has a global fallback table we cannot specify
6059 * more then one tx rate per frame but since the hw will
6060 * try several rates (based on the fallback table) we should
ba3b9e5e 6061 * initialize max_report_rates to the maximum number of rates
3f2bee24
HS		 6062 * we are going to try. Otherwise mac80211 will truncate our
6063 * reported tx rates and the rc algortihm will end up with
6064 * incorrect data.
6065 */
ba3b9e5e
HS		 6066 rt2x00dev->hw->max_rates = 1;
6067 rt2x00dev->hw->max_report_rates = 7;
3f2bee24
HS		 6068 rt2x00dev->hw->max_rate_tries = 1;
6069
38c8a566 6070 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4da2933f
BZ		 6071
6072 /*
6073 * Initialize hw_mode information.
6074 */
6075 spec->supported_bands = SUPPORT_BAND_2GHZ;
6076 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
6077
5122d898 6078 if (rt2x00_rf(rt2x00dev, RF2820) ||
55f9321a 6079 rt2x00_rf(rt2x00dev, RF2720)) {
4da2933f
BZ		 6080 spec->num_channels = 14;
6081 spec->channels = rf_vals;
55f9321a
ID		 6082 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
6083 rt2x00_rf(rt2x00dev, RF2750)) {
4da2933f
BZ		 6084 spec->supported_bands |= SUPPORT_BAND_5GHZ;
6085 spec->num_channels = ARRAY_SIZE(rf_vals);
6086 spec->channels = rf_vals;
5122d898
GW		 6087 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
6088 rt2x00_rf(rt2x00dev, RF2020) ||
6089 rt2x00_rf(rt2x00dev, RF3021) ||
f93bc9b3 6090 rt2x00_rf(rt2x00dev, RF3022) ||
a89534ed 6091 rt2x00_rf(rt2x00dev, RF3290) ||
adde5882 6092 rt2x00_rf(rt2x00dev, RF3320) ||
03839951 6093 rt2x00_rf(rt2x00dev, RF3322) ||
ccf91bd6 6094 rt2x00_rf(rt2x00dev, RF5360) ||
aca355b9 6095 rt2x00_rf(rt2x00dev, RF5370) ||
2ed71884 6096 rt2x00_rf(rt2x00dev, RF5372) ||
cff3d1f0
ZL		 6097 rt2x00_rf(rt2x00dev, RF5390) ||
6098 rt2x00_rf(rt2x00dev, RF5392)) {
55f9321a
ID		 6099 spec->num_channels = 14;
6100 spec->channels = rf_vals_3x;
6101 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
6102 spec->supported_bands |= SUPPORT_BAND_5GHZ;
6103 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
6104 spec->channels = rf_vals_3x;
7848b231
SG		 6105 } else if (rt2x00_rf(rt2x00dev, RF5592)) {
6106 spec->supported_bands |= SUPPORT_BAND_5GHZ;
6107
6108 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, &reg);
6109 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
6110 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
6111 spec->channels = rf_vals_5592_xtal40;
6112 } else {
6113 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
6114 spec->channels = rf_vals_5592_xtal20;
6115 }
4da2933f
BZ		 6116 }
6117
53216d6a
SG		 6118 if (WARN_ON_ONCE(!spec->channels))
6119 return -ENODEV;
6120
4da2933f
BZ		 6121 /*
6122 * Initialize HT information.
6123 */
5122d898 6124 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 6125 spec->ht.ht_supported = true;
6126 else
6127 spec->ht.ht_supported = false;
6128
4da2933f 6129 spec->ht.cap =
06443e46 6130 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 6131 IEEE80211_HT_CAP_GRN_FLD |
6132 IEEE80211_HT_CAP_SGI_20 |
aa674631 6133 IEEE80211_HT_CAP_SGI_40;
22cabaa6 6134
38c8a566 6135 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
22cabaa6
HS		 6136 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
6137
aa674631 6138 spec->ht.cap |=
38c8a566 6139 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
aa674631
ID		 6140 IEEE80211_HT_CAP_RX_STBC_SHIFT;
6141
4da2933f
BZ		 6142 spec->ht.ampdu_factor = 3;
6143 spec->ht.ampdu_density = 4;
6144 spec->ht.mcs.tx_params =
6145 IEEE80211_HT_MCS_TX_DEFINED |
6146 IEEE80211_HT_MCS_TX_RX_DIFF |
38c8a566 6147 ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
4da2933f
BZ		 6148 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
6149
38c8a566 6150 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
4da2933f
BZ		 6151 case 3:
6152 spec->ht.mcs.rx_mask[2] = 0xff;
6153 case 2:
6154 spec->ht.mcs.rx_mask[1] = 0xff;
6155 case 1:
6156 spec->ht.mcs.rx_mask[0] = 0xff;
6157 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
6158 break;
6159 }
6160
6161 /*
6162 * Create channel information array
6163 */
baeb2ffa 6164 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4da2933f
BZ		 6165 if (!info)
6166 return -ENOMEM;
6167
6168 spec->channels_info = info;
6169
8d1331b3
ID		 6170 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
6171 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4da2933f
BZ		 6172
6173 for (i = 0; i < 14; i++) {
e90c54b2
RJH		 6174 info[i].default_power1 = default_power1[i];
6175 info[i].default_power2 = default_power2[i];
4da2933f
BZ		 6176 }
6177
6178 if (spec->num_channels > 14) {
8d1331b3
ID		 6179 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
6180 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4da2933f
BZ		 6181
6182 for (i = 14; i < spec->num_channels; i++) {
e90c54b2
RJH		 6183 info[i].default_power1 = default_power1[i];
6184 info[i].default_power2 = default_power2[i];
4da2933f
BZ		 6185 }
6186 }
6187
2e9c43dd
JL		 6188 switch (rt2x00dev->chip.rf) {
6189 case RF2020:
6190 case RF3020:
6191 case RF3021:
6192 case RF3022:
6193 case RF3320:
6194 case RF3052:
a89534ed 6195 case RF3290:
ccf91bd6 6196 case RF5360:
2e9c43dd
JL		 6197 case RF5370:
6198 case RF5372:
6199 case RF5390:
cff3d1f0 6200 case RF5392:
2e9c43dd
JL		 6201 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
6202 break;
6203 }
6204
4da2933f
BZ		 6205 return 0;
6206}
ad417a53 6207
cbafb601
GJ		 6208static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
6209{
6210 u32 reg;
6211 u32 rt;
6212 u32 rev;
6213
6214 if (rt2x00_rt(rt2x00dev, RT3290))
6215 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
6216 else
6217 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
6218
6219 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
6220 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
6221
6222 switch (rt) {
6223 case RT2860:
6224 case RT2872:
6225 case RT2883:
6226 case RT3070:
6227 case RT3071:
6228 case RT3090:
6229 case RT3290:
6230 case RT3352:
6231 case RT3390:
6232 case RT3572:
6233 case RT5390:
6234 case RT5392:
6235 case RT5592:
6236 break;
6237 default:
ec9c4989
JP		 6238 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
6239 rt, rev);
cbafb601
GJ		 6240 return -ENODEV;
6241 }
6242
6243 rt2x00_set_rt(rt2x00dev, rt, rev);
6244
6245 return 0;
6246}
6247
ad417a53
GW		 6248int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
6249{
6250 int retval;
6251 u32 reg;
6252
cbafb601
GJ		 6253 retval = rt2800_probe_rt(rt2x00dev);
6254 if (retval)
6255 return retval;
6256
ad417a53
GW		 6257 /*
6258 * Allocate eeprom data.
6259 */
6260 retval = rt2800_validate_eeprom(rt2x00dev);
6261 if (retval)
6262 return retval;
6263
6264 retval = rt2800_init_eeprom(rt2x00dev);
6265 if (retval)
6266 return retval;
6267
6268 /*
6269 * Enable rfkill polling by setting GPIO direction of the
6270 * rfkill switch GPIO pin correctly.
6271 */
6272 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
6273 rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
6274 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
6275
6276 /*
6277 * Initialize hw specifications.
6278 */
6279 retval = rt2800_probe_hw_mode(rt2x00dev);
6280 if (retval)
6281 return retval;
6282
6283 /*
6284 * Set device capabilities.
6285 */
6286 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
6287 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
6288 if (!rt2x00_is_usb(rt2x00dev))
6289 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
6290
6291 /*
6292 * Set device requirements.
6293 */
6294 if (!rt2x00_is_soc(rt2x00dev))
6295 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
6296 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
6297 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
6298 if (!rt2800_hwcrypt_disabled(rt2x00dev))
6299 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
6300 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
6301 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
6302 if (rt2x00_is_usb(rt2x00dev))
6303 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
6304 else {
6305 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
6306 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
6307 }
6308
6309 /*
6310 * Set the rssi offset.
6311 */
6312 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
6313
6314 return 0;
6315}
6316EXPORT_SYMBOL_GPL(rt2800_probe_hw);
4da2933f 6317
2ce33995
BZ		 6318/*
6319 * IEEE80211 stack callback functions.
6320 */
e783619e
HS		 6321void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
6322 u16 *iv16)
2ce33995
BZ		 6323{
6324 struct rt2x00_dev *rt2x00dev = hw->priv;
6325 struct mac_iveiv_entry iveiv_entry;
6326 u32 offset;
6327
6328 offset = MAC_IVEIV_ENTRY(hw_key_idx);
6329 rt2800_register_multiread(rt2x00dev, offset,
6330 &iveiv_entry, sizeof(iveiv_entry));
6331
855da5e0
JL		 6332 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
6333 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995 6334}
e783619e 6335EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
2ce33995 6336
e783619e 6337int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2ce33995
BZ		 6338{
6339 struct rt2x00_dev *rt2x00dev = hw->priv;
6340 u32 reg;
6341 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
6342
6343 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
6344 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
6345 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
6346
6347 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
6348 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
6349 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
6350
6351 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
6352 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
6353 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
6354
6355 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
6356 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
6357 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
6358
6359 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
6360 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
6361 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
6362
6363 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
6364 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
6365 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
6366
6367 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
6368 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
6369 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
6370
6371 return 0;
6372}
e783619e 6373EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2ce33995 6374
8a3a3c85
EP		 6375int rt2800_conf_tx(struct ieee80211_hw *hw,
6376 struct ieee80211_vif *vif, u16 queue_idx,
e783619e 6377 const struct ieee80211_tx_queue_params *params)
2ce33995
BZ		 6378{
6379 struct rt2x00_dev *rt2x00dev = hw->priv;
6380 struct data_queue *queue;
6381 struct rt2x00_field32 field;
6382 int retval;
6383 u32 reg;
6384 u32 offset;
6385
6386 /*
6387 * First pass the configuration through rt2x00lib, that will
6388 * update the queue settings and validate the input. After that
6389 * we are free to update the registers based on the value
6390 * in the queue parameter.
6391 */
8a3a3c85 6392 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
2ce33995
BZ		 6393 if (retval)
6394 return retval;
6395
6396 /*
6397 * We only need to perform additional register initialization
6398 * for WMM queues/
6399 */
6400 if (queue_idx >= 4)
6401 return 0;
6402
11f818e0 6403 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2ce33995
BZ		 6404
6405 /* Update WMM TXOP register */
6406 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
6407 field.bit_offset = (queue_idx & 1) * 16;
6408 field.bit_mask = 0xffff << field.bit_offset;
6409
6410 rt2800_register_read(rt2x00dev, offset, &reg);
6411 rt2x00_set_field32(&reg, field, queue->txop);
6412 rt2800_register_write(rt2x00dev, offset, reg);
6413
6414 /* Update WMM registers */
6415 field.bit_offset = queue_idx * 4;
6416 field.bit_mask = 0xf << field.bit_offset;
6417
6418 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
6419 rt2x00_set_field32(&reg, field, queue->aifs);
6420 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
6421
6422 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
6423 rt2x00_set_field32(&reg, field, queue->cw_min);
6424 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
6425
6426 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
6427 rt2x00_set_field32(&reg, field, queue->cw_max);
6428 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
6429
6430 /* Update EDCA registers */
6431 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
6432
6433 rt2800_register_read(rt2x00dev, offset, &reg);
6434 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
6435 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
6436 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
6437 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
6438 rt2800_register_write(rt2x00dev, offset, reg);
6439
6440 return 0;
6441}
e783619e 6442EXPORT_SYMBOL_GPL(rt2800_conf_tx);
2ce33995 6443
37a41b4a 6444u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2ce33995
BZ		 6445{
6446 struct rt2x00_dev *rt2x00dev = hw->priv;
6447 u64 tsf;
6448 u32 reg;
6449
6450 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
6451 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
6452 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
6453 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
6454
6455 return tsf;
6456}
e783619e 6457EXPORT_SYMBOL_GPL(rt2800_get_tsf);
2ce33995 6458
e783619e
HS		 6459int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6460 enum ieee80211_ampdu_mlme_action action,
0b01f030
JB		 6461 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
6462 u8 buf_size)
1df90809 6463{
af35323d 6464 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
1df90809
HS		 6465 int ret = 0;
6466
af35323d
HS		 6467 /*
6468 * Don't allow aggregation for stations the hardware isn't aware
6469 * of because tx status reports for frames to an unknown station
6470 * always contain wcid=255 and thus we can't distinguish between
6471 * multiple stations which leads to unwanted situations when the
6472 * hw reorders frames due to aggregation.
6473 */
6474 if (sta_priv->wcid < 0)
6475 return 1;
6476
1df90809
HS		 6477 switch (action) {
6478 case IEEE80211_AMPDU_RX_START:
6479 case IEEE80211_AMPDU_RX_STOP:
58ed826e
HS		 6480 /*
6481 * The hw itself takes care of setting up BlockAck mechanisms.
6482 * So, we only have to allow mac80211 to nagotiate a BlockAck
6483 * agreement. Once that is done, the hw will BlockAck incoming
6484 * AMPDUs without further setup.
6485 */
1df90809
HS		 6486 break;
6487 case IEEE80211_AMPDU_TX_START:
6488 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
6489 break;
18b559d5
JB		 6490 case IEEE80211_AMPDU_TX_STOP_CONT:
6491 case IEEE80211_AMPDU_TX_STOP_FLUSH:
6492 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
1df90809
HS		 6493 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
6494 break;
6495 case IEEE80211_AMPDU_TX_OPERATIONAL:
6496 break;
6497 default:
ec9c4989
JP		 6498 rt2x00_warn((struct rt2x00_dev *)hw->priv,
6499 "Unknown AMPDU action\n");
1df90809
HS		 6500 }
6501
6502 return ret;
6503}
e783619e 6504EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
a5ea2f02 6505
977206d7
HS		 6506int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
6507 struct survey_info *survey)
6508{
6509 struct rt2x00_dev *rt2x00dev = hw->priv;
6510 struct ieee80211_conf *conf = &hw->conf;
6511 u32 idle, busy, busy_ext;
6512
6513 if (idx != 0)
6514 return -ENOENT;
6515
675a0b04 6516 survey->channel = conf->chandef.chan;
977206d7
HS		 6517
6518 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
6519 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
6520 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
6521
6522 if (idle || busy) {
6523 survey->filled = SURVEY_INFO_CHANNEL_TIME |
6524 SURVEY_INFO_CHANNEL_TIME_BUSY |
6525 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
6526
6527 survey->channel_time = (idle + busy) / 1000;
6528 survey->channel_time_busy = busy / 1000;
6529 survey->channel_time_ext_busy = busy_ext / 1000;
6530 }
6531
9931df26
HS		 6532 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
6533 survey->filled |= SURVEY_INFO_IN_USE;
6534
977206d7
HS		 6535 return 0;
6536
6537}
6538EXPORT_SYMBOL_GPL(rt2800_get_survey);
6539
a5ea2f02
ID		 6540MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
6541MODULE_VERSION(DRV_VERSION);
6542MODULE_DESCRIPTION("Ralink RT2800 library");
6543MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.828499 seconds and 5 git commands to generate.