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Update e-mail address for Andrea Merello (resubmit)
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
CommitLineData
89297425 1/*
96481b20 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
a5ea2f02 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 6
9c9a0d14 7 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32/*
33 Module: rt2800lib
34 Abstract: rt2800 generic device routines.
35 */
36
f31c9a8c 37#include <linux/crc-ccitt.h>
89297425
BZ		 38#include <linux/kernel.h>
39#include <linux/module.h>
5a0e3ad6 40#include <linux/slab.h>
89297425
BZ		 41
42#include "rt2x00.h"
43#include "rt2800lib.h"
44#include "rt2800.h"
45
89297425
BZ		 46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60#define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64#define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66#define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
baff8006
HS		 70static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71{
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
75 return false;
76
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
81 return true;
82
ec9c4989 83 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
baff8006
HS		 84 return false;
85}
86
fcf51541
BZ		 87static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
89297425
BZ		 89{
90 u32 reg;
91
92 mutex_lock(&rt2x00dev->csr_mutex);
93
94 /*
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
97 */
98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
efc7d36f 104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 105
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107 }
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110}
89297425 111
fcf51541
BZ		 112static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
89297425
BZ		 114{
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
126 */
127 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 reg = 0;
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
efc7d36f 132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142}
89297425 143
fcf51541
BZ		 144static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
89297425
BZ		 146{
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166}
89297425 167
fcf51541
BZ		 168static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
89297425
BZ		 170{
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197}
89297425 198
fcf51541
BZ		 199static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
89297425
BZ		 201{
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222}
89297425 223
379448fe
GJ		 224static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
225 [EEPROM_CHIP_ID] = 0x0000,
226 [EEPROM_VERSION] = 0x0001,
227 [EEPROM_MAC_ADDR_0] = 0x0002,
228 [EEPROM_MAC_ADDR_1] = 0x0003,
229 [EEPROM_MAC_ADDR_2] = 0x0004,
230 [EEPROM_NIC_CONF0] = 0x001a,
231 [EEPROM_NIC_CONF1] = 0x001b,
232 [EEPROM_FREQ] = 0x001d,
233 [EEPROM_LED_AG_CONF] = 0x001e,
234 [EEPROM_LED_ACT_CONF] = 0x001f,
235 [EEPROM_LED_POLARITY] = 0x0020,
236 [EEPROM_NIC_CONF2] = 0x0021,
237 [EEPROM_LNA] = 0x0022,
238 [EEPROM_RSSI_BG] = 0x0023,
239 [EEPROM_RSSI_BG2] = 0x0024,
240 [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */
241 [EEPROM_RSSI_A] = 0x0025,
242 [EEPROM_RSSI_A2] = 0x0026,
243 [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */
244 [EEPROM_EIRP_MAX_TX_POWER] = 0x0027,
245 [EEPROM_TXPOWER_DELTA] = 0x0028,
246 [EEPROM_TXPOWER_BG1] = 0x0029,
247 [EEPROM_TXPOWER_BG2] = 0x0030,
248 [EEPROM_TSSI_BOUND_BG1] = 0x0037,
249 [EEPROM_TSSI_BOUND_BG2] = 0x0038,
250 [EEPROM_TSSI_BOUND_BG3] = 0x0039,
251 [EEPROM_TSSI_BOUND_BG4] = 0x003a,
252 [EEPROM_TSSI_BOUND_BG5] = 0x003b,
253 [EEPROM_TXPOWER_A1] = 0x003c,
254 [EEPROM_TXPOWER_A2] = 0x0053,
255 [EEPROM_TSSI_BOUND_A1] = 0x006a,
256 [EEPROM_TSSI_BOUND_A2] = 0x006b,
257 [EEPROM_TSSI_BOUND_A3] = 0x006c,
258 [EEPROM_TSSI_BOUND_A4] = 0x006d,
259 [EEPROM_TSSI_BOUND_A5] = 0x006e,
260 [EEPROM_TXPOWER_BYRATE] = 0x006f,
261 [EEPROM_BBP_START] = 0x0078,
262};
263
fa31d157
GJ		 264static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
265 [EEPROM_CHIP_ID] = 0x0000,
266 [EEPROM_VERSION] = 0x0001,
267 [EEPROM_MAC_ADDR_0] = 0x0002,
268 [EEPROM_MAC_ADDR_1] = 0x0003,
269 [EEPROM_MAC_ADDR_2] = 0x0004,
270 [EEPROM_NIC_CONF0] = 0x001a,
271 [EEPROM_NIC_CONF1] = 0x001b,
272 [EEPROM_NIC_CONF2] = 0x001c,
273 [EEPROM_EIRP_MAX_TX_POWER] = 0x0020,
274 [EEPROM_FREQ] = 0x0022,
275 [EEPROM_LED_AG_CONF] = 0x0023,
276 [EEPROM_LED_ACT_CONF] = 0x0024,
277 [EEPROM_LED_POLARITY] = 0x0025,
278 [EEPROM_LNA] = 0x0026,
279 [EEPROM_EXT_LNA2] = 0x0027,
280 [EEPROM_RSSI_BG] = 0x0028,
281 [EEPROM_TXPOWER_DELTA] = 0x0028, /* Overlaps with RSSI_BG */
282 [EEPROM_RSSI_BG2] = 0x0029,
283 [EEPROM_TXMIXER_GAIN_BG] = 0x0029, /* Overlaps with RSSI_BG2 */
284 [EEPROM_RSSI_A] = 0x002a,
285 [EEPROM_RSSI_A2] = 0x002b,
286 [EEPROM_TXMIXER_GAIN_A] = 0x002b, /* Overlaps with RSSI_A2 */
287 [EEPROM_TXPOWER_BG1] = 0x0030,
288 [EEPROM_TXPOWER_BG2] = 0x0037,
289 [EEPROM_EXT_TXPOWER_BG3] = 0x003e,
290 [EEPROM_TSSI_BOUND_BG1] = 0x0045,
291 [EEPROM_TSSI_BOUND_BG2] = 0x0046,
292 [EEPROM_TSSI_BOUND_BG3] = 0x0047,
293 [EEPROM_TSSI_BOUND_BG4] = 0x0048,
294 [EEPROM_TSSI_BOUND_BG5] = 0x0049,
295 [EEPROM_TXPOWER_A1] = 0x004b,
296 [EEPROM_TXPOWER_A2] = 0x0065,
297 [EEPROM_EXT_TXPOWER_A3] = 0x007f,
298 [EEPROM_TSSI_BOUND_A1] = 0x009a,
299 [EEPROM_TSSI_BOUND_A2] = 0x009b,
300 [EEPROM_TSSI_BOUND_A3] = 0x009c,
301 [EEPROM_TSSI_BOUND_A4] = 0x009d,
302 [EEPROM_TSSI_BOUND_A5] = 0x009e,
303 [EEPROM_TXPOWER_BYRATE] = 0x00a0,
304};
305
379448fe
GJ		 306static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
307 const enum rt2800_eeprom_word word)
308{
309 const unsigned int *map;
310 unsigned int index;
311
312 if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
313 "%s: invalid EEPROM word %d\n",
314 wiphy_name(rt2x00dev->hw->wiphy), word))
315 return 0;
316
fa31d157
GJ		 317 if (rt2x00_rt(rt2x00dev, RT3593))
318 map = rt2800_eeprom_map_ext;
319 else
320 map = rt2800_eeprom_map;
321
379448fe
GJ		 322 index = map[word];
323
324 /* Index 0 is valid only for EEPROM_CHIP_ID.
325 * Otherwise it means that the offset of the
326 * given word is not initialized in the map,
327 * or that the field is not usable on the
328 * actual chipset.
329 */
330 WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
331 "%s: invalid access of EEPROM word %d\n",
332 wiphy_name(rt2x00dev->hw->wiphy), word);
333
334 return index;
335}
336
3e38d3da
GJ		 337static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
338 const enum rt2800_eeprom_word word)
339{
379448fe
GJ		 340 unsigned int index;
341
342 index = rt2800_eeprom_word_index(rt2x00dev, word);
343 return rt2x00_eeprom_addr(rt2x00dev, index);
3e38d3da
GJ		 344}
345
346static void rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
347 const enum rt2800_eeprom_word word, u16 *data)
348{
379448fe
GJ		 349 unsigned int index;
350
351 index = rt2800_eeprom_word_index(rt2x00dev, word);
352 rt2x00_eeprom_read(rt2x00dev, index, data);
3e38d3da
GJ		 353}
354
355static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
356 const enum rt2800_eeprom_word word, u16 data)
357{
379448fe
GJ		 358 unsigned int index;
359
360 index = rt2800_eeprom_word_index(rt2x00dev, word);
361 rt2x00_eeprom_write(rt2x00dev, index, data);
3e38d3da
GJ		 362}
363
022138ca
GJ		 364static void rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
365 const enum rt2800_eeprom_word array,
366 unsigned int offset,
367 u16 *data)
368{
379448fe
GJ		 369 unsigned int index;
370
371 index = rt2800_eeprom_word_index(rt2x00dev, array);
372 rt2x00_eeprom_read(rt2x00dev, index + offset, data);
022138ca
GJ		 373}
374
16ebd608
WH		 375static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
376{
377 u32 reg;
378 int i, count;
379
380 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
381 if (rt2x00_get_field32(reg, WLAN_EN))
382 return 0;
383
384 rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
385 rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
386 rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
387 rt2x00_set_field32(&reg, WLAN_EN, 1);
388 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
389
390 udelay(REGISTER_BUSY_DELAY);
391
392 count = 0;
393 do {
394 /*
395 * Check PLL_LD & XTAL_RDY.
396 */
397 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
398 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
399 if (rt2x00_get_field32(reg, PLL_LD) &&
400 rt2x00_get_field32(reg, XTAL_RDY))
401 break;
402 udelay(REGISTER_BUSY_DELAY);
403 }
404
405 if (i >= REGISTER_BUSY_COUNT) {
406
407 if (count >= 10)
408 return -EIO;
409
410 rt2800_register_write(rt2x00dev, 0x58, 0x018);
411 udelay(REGISTER_BUSY_DELAY);
412 rt2800_register_write(rt2x00dev, 0x58, 0x418);
413 udelay(REGISTER_BUSY_DELAY);
414 rt2800_register_write(rt2x00dev, 0x58, 0x618);
415 udelay(REGISTER_BUSY_DELAY);
416 count++;
417 } else {
418 count = 0;
419 }
420
421 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
422 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
423 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
424 rt2x00_set_field32(&reg, WLAN_RESET, 1);
425 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
426 udelay(10);
427 rt2x00_set_field32(&reg, WLAN_RESET, 0);
428 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
429 udelay(10);
430 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
431 } while (count != 0);
432
433 return 0;
434}
435
89297425
BZ		 436void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
437 const u8 command, const u8 token,
438 const u8 arg0, const u8 arg1)
439{
440 u32 reg;
441
ee303e54 442 /*
cea90e55 443 * SOC devices don't support MCU requests.
ee303e54 444 */
cea90e55 445 if (rt2x00_is_soc(rt2x00dev))
ee303e54 446 return;
89297425
BZ		 447
448 mutex_lock(&rt2x00dev->csr_mutex);
449
450 /*
451 * Wait until the MCU becomes available, afterwards we
452 * can safely write the new data into the register.
453 */
454 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
455 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
456 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
457 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
458 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
459 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
460
461 reg = 0;
462 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
463 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
464 }
465
466 mutex_unlock(&rt2x00dev->csr_mutex);
467}
468EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 469
5ffddc49
ID		 470int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
471{
472 unsigned int i = 0;
473 u32 reg;
474
475 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
476 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
477 if (reg && reg != ~0)
478 return 0;
479 msleep(1);
480 }
481
ec9c4989 482 rt2x00_err(rt2x00dev, "Unstable hardware\n");
5ffddc49
ID		 483 return -EBUSY;
484}
485EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
486
67a4c1e2
GW		 487int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
488{
489 unsigned int i;
490 u32 reg;
491
08e53100
HS		 492 /*
493 * Some devices are really slow to respond here. Wait a whole second
494 * before timing out.
495 */
67a4c1e2
GW		 496 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
497 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
498 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
499 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
500 return 0;
501
08e53100 502 msleep(10);
67a4c1e2
GW		 503 }
504
ec9c4989 505 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
67a4c1e2
GW		 506 return -EACCES;
507}
508EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
509
f7b395e9
JK		 510void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
511{
512 u32 reg;
513
514 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
515 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
516 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
517 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
518 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
519 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
520 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
521}
522EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
523
ae1b1c5d
GJ		 524void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
525 unsigned short *txwi_size,
526 unsigned short *rxwi_size)
527{
528 switch (rt2x00dev->chip.rt) {
529 case RT3593:
530 *txwi_size = TXWI_DESC_SIZE_4WORDS;
531 *rxwi_size = RXWI_DESC_SIZE_5WORDS;
532 break;
533
534 case RT5592:
535 *txwi_size = TXWI_DESC_SIZE_5WORDS;
536 *rxwi_size = RXWI_DESC_SIZE_6WORDS;
537 break;
538
539 default:
540 *txwi_size = TXWI_DESC_SIZE_4WORDS;
541 *rxwi_size = RXWI_DESC_SIZE_4WORDS;
542 break;
543 }
544}
545EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size);
546
f31c9a8c
ID		 547static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
548{
549 u16 fw_crc;
550 u16 crc;
551
552 /*
553 * The last 2 bytes in the firmware array are the crc checksum itself,
554 * this means that we should never pass those 2 bytes to the crc
555 * algorithm.
556 */
557 fw_crc = (data[len - 2] << 8 | data[len - 1]);
558
559 /*
560 * Use the crc ccitt algorithm.
561 * This will return the same value as the legacy driver which
562 * used bit ordering reversion on the both the firmware bytes
563 * before input input as well as on the final output.
564 * Obviously using crc ccitt directly is much more efficient.
565 */
566 crc = crc_ccitt(~0, data, len - 2);
567
568 /*
569 * There is a small difference between the crc-itu-t + bitrev and
570 * the crc-ccitt crc calculation. In the latter method the 2 bytes
571 * will be swapped, use swab16 to convert the crc to the correct
572 * value.
573 */
574 crc = swab16(crc);
575
576 return fw_crc == crc;
577}
578
579int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
580 const u8 *data, const size_t len)
581{
582 size_t offset = 0;
583 size_t fw_len;
584 bool multiple;
585
586 /*
587 * PCI(e) & SOC devices require firmware with a length
588 * of 8kb. USB devices require firmware files with a length
589 * of 4kb. Certain USB chipsets however require different firmware,
590 * which Ralink only provides attached to the original firmware
591 * file. Thus for USB devices, firmware files have a length
a89534ed
WH		 592 * which is a multiple of 4kb. The firmware for rt3290 chip also
593 * have a length which is a multiple of 4kb.
f31c9a8c 594 */
a89534ed 595 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
f31c9a8c 596 fw_len = 4096;
a89534ed 597 else
f31c9a8c 598 fw_len = 8192;
f31c9a8c 599
a89534ed 600 multiple = true;
f31c9a8c
ID		 601 /*
602 * Validate the firmware length
603 */
604 if (len != fw_len && (!multiple || (len % fw_len) != 0))
605 return FW_BAD_LENGTH;
606
607 /*
608 * Check if the chipset requires one of the upper parts
609 * of the firmware.
610 */
611 if (rt2x00_is_usb(rt2x00dev) &&
612 !rt2x00_rt(rt2x00dev, RT2860) &&
613 !rt2x00_rt(rt2x00dev, RT2872) &&
614 !rt2x00_rt(rt2x00dev, RT3070) &&
615 ((len / fw_len) == 1))
616 return FW_BAD_VERSION;
617
618 /*
619 * 8kb firmware files must be checked as if it were
620 * 2 separate firmware files.
621 */
622 while (offset < len) {
623 if (!rt2800_check_firmware_crc(data + offset, fw_len))
624 return FW_BAD_CRC;
625
626 offset += fw_len;
627 }
628
629 return FW_OK;
630}
631EXPORT_SYMBOL_GPL(rt2800_check_firmware);
632
633int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
634 const u8 *data, const size_t len)
635{
636 unsigned int i;
637 u32 reg;
16ebd608
WH		 638 int retval;
639
640 if (rt2x00_rt(rt2x00dev, RT3290)) {
641 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
642 if (retval)
643 return -EBUSY;
644 }
f31c9a8c
ID		 645
646 /*
b9eca242
ID		 647 * If driver doesn't wake up firmware here,
648 * rt2800_load_firmware will hang forever when interface is up again.
f31c9a8c 649 */
b9eca242 650 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
f31c9a8c 651
f31c9a8c
ID		 652 /*
653 * Wait for stable hardware.
654 */
5ffddc49 655 if (rt2800_wait_csr_ready(rt2x00dev))
f31c9a8c 656 return -EBUSY;
f31c9a8c 657
adde5882 658 if (rt2x00_is_pci(rt2x00dev)) {
a89534ed
WH		 659 if (rt2x00_rt(rt2x00dev, RT3290) ||
660 rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884
JL		 661 rt2x00_rt(rt2x00dev, RT5390) ||
662 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 663 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
664 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
665 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
666 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
667 }
f31c9a8c 668 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
adde5882 669 }
f31c9a8c 670
b7e1d225
JK		 671 rt2800_disable_wpdma(rt2x00dev);
672
f31c9a8c
ID		 673 /*
674 * Write firmware to the device.
675 */
676 rt2800_drv_write_firmware(rt2x00dev, data, len);
677
678 /*
679 * Wait for device to stabilize.
680 */
681 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
682 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
683 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
684 break;
685 msleep(1);
686 }
687
688 if (i == REGISTER_BUSY_COUNT) {
ec9c4989 689 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
f31c9a8c
ID		 690 return -EBUSY;
691 }
692
4ed1dd2a
SG		 693 /*
694 * Disable DMA, will be reenabled later when enabling
695 * the radio.
696 */
f7b395e9 697 rt2800_disable_wpdma(rt2x00dev);
4ed1dd2a 698
f31c9a8c
ID		 699 /*
700 * Initialize firmware.
701 */
702 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
703 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
8756130b 704 if (rt2x00_is_usb(rt2x00dev)) {
0c17cf96 705 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
8756130b
SG		 706 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
707 }
f31c9a8c
ID		 708 msleep(1);
709
710 return 0;
711}
712EXPORT_SYMBOL_GPL(rt2800_load_firmware);
713
0c5879bc
ID		 714void rt2800_write_tx_data(struct queue_entry *entry,
715 struct txentry_desc *txdesc)
59679b91 716{
0c5879bc 717 __le32 *txwi = rt2800_drv_get_txwi(entry);
59679b91 718 u32 word;
557985ae 719 int i;
59679b91
GW		 720
721 /*
722 * Initialize TX Info descriptor
723 */
724 rt2x00_desc_read(txwi, 0, &word);
725 rt2x00_set_field32(&word, TXWI_W0_FRAG,
726 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
84804cdc
ID		 727 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
728 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
59679b91
GW		 729 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
730 rt2x00_set_field32(&word, TXWI_W0_TS,
731 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
732 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
733 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
26a1d07f
HS		 734 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
735 txdesc->u.ht.mpdu_density);
736 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
737 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
59679b91
GW		 738 rt2x00_set_field32(&word, TXWI_W0_BW,
739 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
740 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
741 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
26a1d07f 742 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
59679b91
GW		 743 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
744 rt2x00_desc_write(txwi, 0, word);
745
746 rt2x00_desc_read(txwi, 1, &word);
747 rt2x00_set_field32(&word, TXWI_W1_ACK,
748 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
749 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
750 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
26a1d07f 751 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
59679b91
GW		 752 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
753 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
a2b1328a 754 txdesc->key_idx : txdesc->u.ht.wcid);
59679b91
GW		 755 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
756 txdesc->length);
2b23cdaa 757 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
bc8a979e 758 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
59679b91
GW		 759 rt2x00_desc_write(txwi, 1, word);
760
761 /*
557985ae
SG		 762 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
763 * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
59679b91
GW		 764 * When TXD_W3_WIV is set to 1 it will use the IV data
765 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
766 * crypto entry in the registers should be used to encrypt the frame.
557985ae
SG		 767 *
768 * Nulify all remaining words as well, we don't know how to program them.
59679b91 769 */
557985ae
SG		 770 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
771 _rt2x00_desc_write(txwi, i, 0);
59679b91 772}
0c5879bc 773EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
59679b91 774
ff6133be 775static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
2de64dd2 776{
7fc41755
LT		 777 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
778 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
779 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
74861922
ID		 780 u16 eeprom;
781 u8 offset0;
782 u8 offset1;
783 u8 offset2;
784
e5ef5bad 785 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
3e38d3da 786 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
74861922
ID		 787 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
788 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
3e38d3da 789 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
74861922
ID		 790 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
791 } else {
3e38d3da 792 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
74861922
ID		 793 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
794 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
3e38d3da 795 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
74861922
ID		 796 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
797 }
798
799 /*
800 * Convert the value from the descriptor into the RSSI value
801 * If the value in the descriptor is 0, it is considered invalid
802 * and the default (extremely low) rssi value is assumed
803 */
804 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
805 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
806 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
807
808 /*
809 * mac80211 only accepts a single RSSI value. Calculating the
810 * average doesn't deliver a fair answer either since -60:-60 would
811 * be considered equally good as -50:-70 while the second is the one
812 * which gives less energy...
813 */
814 rssi0 = max(rssi0, rssi1);
7fc41755 815 return (int)max(rssi0, rssi2);
74861922
ID		 816}
817
818void rt2800_process_rxwi(struct queue_entry *entry,
819 struct rxdone_entry_desc *rxdesc)
820{
821 __le32 *rxwi = (__le32 *) entry->skb->data;
2de64dd2
GW		 822 u32 word;
823
824 rt2x00_desc_read(rxwi, 0, &word);
825
826 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
827 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
828
829 rt2x00_desc_read(rxwi, 1, &word);
830
831 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
832 rxdesc->flags |= RX_FLAG_SHORT_GI;
833
834 if (rt2x00_get_field32(word, RXWI_W1_BW))
835 rxdesc->flags |= RX_FLAG_40MHZ;
836
837 /*
838 * Detect RX rate, always use MCS as signal type.
839 */
840 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
841 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
842 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
843
844 /*
845 * Mask of 0x8 bit to remove the short preamble flag.
846 */
847 if (rxdesc->rate_mode == RATE_MODE_CCK)
848 rxdesc->signal &= ~0x8;
849
850 rt2x00_desc_read(rxwi, 2, &word);
851
74861922
ID		 852 /*
853 * Convert descriptor AGC value to RSSI value.
854 */
855 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
f0bda571
SG		 856 /*
857 * Remove RXWI descriptor from start of the buffer.
858 */
859 skb_pull(entry->skb, entry->queue->winfo_size);
2de64dd2
GW		 860}
861EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
862
31937c42 863void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
14433331
HS		 864{
865 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b34793ee 866 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
14433331
HS		 867 struct txdone_entry_desc txdesc;
868 u32 word;
869 u16 mcs, real_mcs;
b34793ee 870 int aggr, ampdu;
14433331
HS		 871
872 /*
873 * Obtain the status about this packet.
874 */
875 txdesc.flags = 0;
14433331 876 rt2x00_desc_read(txwi, 0, &word);
b34793ee 877
14433331 878 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
b34793ee
HS		 879 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
880
14433331 881 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
b34793ee
HS		 882 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
883
884 /*
885 * If a frame was meant to be sent as a single non-aggregated MPDU
886 * but ended up in an aggregate the used tx rate doesn't correlate
887 * with the one specified in the TXWI as the whole aggregate is sent
888 * with the same rate.
889 *
890 * For example: two frames are sent to rt2x00, the first one sets
891 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
892 * and requests MCS15. If the hw aggregates both frames into one
893 * AMDPU the tx status for both frames will contain MCS7 although
894 * the frame was sent successfully.
895 *
896 * Hence, replace the requested rate with the real tx rate to not
897 * confuse the rate control algortihm by providing clearly wrong
898 * data.
899 */
5356d963 900 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
b34793ee
HS		 901 skbdesc->tx_rate_idx = real_mcs;
902 mcs = real_mcs;
903 }
14433331 904
f16d2db7
HS		 905 if (aggr == 1 || ampdu == 1)
906 __set_bit(TXDONE_AMPDU, &txdesc.flags);
907
14433331
HS		 908 /*
909 * Ralink has a retry mechanism using a global fallback
910 * table. We setup this fallback table to try the immediate
911 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
912 * always contains the MCS used for the last transmission, be
913 * it successful or not.
914 */
915 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
916 /*
917 * Transmission succeeded. The number of retries is
918 * mcs - real_mcs
919 */
920 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
921 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
922 } else {
923 /*
924 * Transmission failed. The number of retries is
925 * always 7 in this case (for a total number of 8
926 * frames sent).
927 */
928 __set_bit(TXDONE_FAILURE, &txdesc.flags);
929 txdesc.retry = rt2x00dev->long_retry;
930 }
931
932 /*
933 * the frame was retried at least once
934 * -> hw used fallback rates
935 */
936 if (txdesc.retry)
937 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
938
939 rt2x00lib_txdone(entry, &txdesc);
940}
941EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
942
21c6af6b
GJ		 943static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,
944 unsigned int index)
945{
946 return HW_BEACON_BASE(index);
947}
948
634b8059
GJ		 949static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev,
950 unsigned int index)
951{
952 return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index));
953}
954
f0194b2d
GW		 955void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
956{
957 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
958 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
959 unsigned int beacon_base;
739fd940 960 unsigned int padding_len;
d76dfc61 961 u32 orig_reg, reg;
f0bda571 962 const int txwi_desc_size = entry->queue->winfo_size;
f0194b2d
GW		 963
964 /*
965 * Disable beaconing while we are reloading the beacon data,
966 * otherwise we might be sending out invalid data.
967 */
968 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
d76dfc61 969 orig_reg = reg;
f0194b2d
GW		 970 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
971 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
972
973 /*
974 * Add space for the TXWI in front of the skb.
975 */
f0bda571 976 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
f0194b2d
GW		 977
978 /*
979 * Register descriptor details in skb frame descriptor.
980 */
981 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
982 skbdesc->desc = entry->skb->data;
f0bda571 983 skbdesc->desc_len = txwi_desc_size;
f0194b2d
GW		 984
985 /*
986 * Add the TXWI for the beacon to the skb.
987 */
0c5879bc 988 rt2800_write_tx_data(entry, txdesc);
f0194b2d
GW		 989
990 /*
991 * Dump beacon to userspace through debugfs.
992 */
993 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
994
995 /*
739fd940 996 * Write entire beacon with TXWI and padding to register.
f0194b2d 997 */
739fd940 998 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
d76dfc61 999 if (padding_len && skb_pad(entry->skb, padding_len)) {
ec9c4989 1000 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
d76dfc61
SF		 1001 /* skb freed by skb_pad() on failure */
1002 entry->skb = NULL;
1003 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1004 return;
1005 }
1006
21c6af6b
GJ		 1007 beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
1008
739fd940
WK		 1009 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1010 entry->skb->len + padding_len);
f0194b2d
GW		 1011
1012 /*
1013 * Enable beaconing again.
1014 */
f0194b2d
GW		 1015 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
1016 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1017
1018 /*
1019 * Clean up beacon skb.
1020 */
1021 dev_kfree_skb_any(entry->skb);
1022 entry->skb = NULL;
1023}
50e888ea 1024EXPORT_SYMBOL_GPL(rt2800_write_beacon);
f0194b2d 1025
69cf36a4 1026static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
77f7c0f3 1027 unsigned int index)
fdb87251
HS		 1028{
1029 int i;
0879f875 1030 const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
77f7c0f3
GJ		 1031 unsigned int beacon_base;
1032
21c6af6b 1033 beacon_base = rt2800_hw_beacon_base(rt2x00dev, index);
fdb87251
HS		 1034
1035 /*
1036 * For the Beacon base registers we only need to clear
1037 * the whole TXWI which (when set to 0) will invalidate
1038 * the entire beacon.
1039 */
f0bda571 1040 for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
fdb87251
HS		 1041 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1042}
1043
69cf36a4
HS		 1044void rt2800_clear_beacon(struct queue_entry *entry)
1045{
1046 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1047 u32 reg;
1048
1049 /*
1050 * Disable beaconing while we are reloading the beacon data,
1051 * otherwise we might be sending out invalid data.
1052 */
1053 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1054 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1055 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1056
1057 /*
1058 * Clear beacon.
1059 */
77f7c0f3 1060 rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
69cf36a4
HS		 1061
1062 /*
1063 * Enabled beaconing again.
1064 */
1065 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
1066 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1067}
1068EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
1069
f4450616
BZ		 1070#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1071const struct rt2x00debug rt2800_rt2x00debug = {
1072 .owner = THIS_MODULE,
1073 .csr = {
1074 .read = rt2800_register_read,
1075 .write = rt2800_register_write,
1076 .flags = RT2X00DEBUGFS_OFFSET,
1077 .word_base = CSR_REG_BASE,
1078 .word_size = sizeof(u32),
1079 .word_count = CSR_REG_SIZE / sizeof(u32),
1080 },
1081 .eeprom = {
3e38d3da
GJ		 1082 /* NOTE: The local EEPROM access functions can't
1083 * be used here, use the generic versions instead.
1084 */
f4450616
BZ		 1085 .read = rt2x00_eeprom_read,
1086 .write = rt2x00_eeprom_write,
1087 .word_base = EEPROM_BASE,
1088 .word_size = sizeof(u16),
1089 .word_count = EEPROM_SIZE / sizeof(u16),
1090 },
1091 .bbp = {
1092 .read = rt2800_bbp_read,
1093 .write = rt2800_bbp_write,
1094 .word_base = BBP_BASE,
1095 .word_size = sizeof(u8),
1096 .word_count = BBP_SIZE / sizeof(u8),
1097 },
1098 .rf = {
1099 .read = rt2x00_rf_read,
1100 .write = rt2800_rf_write,
1101 .word_base = RF_BASE,
1102 .word_size = sizeof(u32),
1103 .word_count = RF_SIZE / sizeof(u32),
1104 },
f2bd7f16
AA		 1105 .rfcsr = {
1106 .read = rt2800_rfcsr_read,
1107 .write = rt2800_rfcsr_write,
1108 .word_base = RFCSR_BASE,
1109 .word_size = sizeof(u8),
1110 .word_count = RFCSR_SIZE / sizeof(u8),
1111 },
f4450616
BZ		 1112};
1113EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
1114#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1115
1116int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1117{
1118 u32 reg;
1119
a89534ed
WH		 1120 if (rt2x00_rt(rt2x00dev, RT3290)) {
1121 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
1122 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
1123 } else {
99bdf51a
GW		 1124 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1125 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
a89534ed 1126 }
f4450616
BZ		 1127}
1128EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
1129
1130#ifdef CONFIG_RT2X00_LIB_LEDS
1131static void rt2800_brightness_set(struct led_classdev *led_cdev,
1132 enum led_brightness brightness)
1133{
1134 struct rt2x00_led *led =
1135 container_of(led_cdev, struct rt2x00_led, led_dev);
1136 unsigned int enabled = brightness != LED_OFF;
1137 unsigned int bg_mode =
1138 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
1139 unsigned int polarity =
1140 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1141 EEPROM_FREQ_LED_POLARITY);
1142 unsigned int ledmode =
1143 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1144 EEPROM_FREQ_LED_MODE);
44704e5d 1145 u32 reg;
f4450616 1146
44704e5d
LE		 1147 /* Check for SoC (SOC devices don't support MCU requests) */
1148 if (rt2x00_is_soc(led->rt2x00dev)) {
1149 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
1150
1151 /* Set LED Polarity */
1152 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
1153
1154 /* Set LED Mode */
1155 if (led->type == LED_TYPE_RADIO) {
1156 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
1157 enabled ? 3 : 0);
1158 } else if (led->type == LED_TYPE_ASSOC) {
1159 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
1160 enabled ? 3 : 0);
1161 } else if (led->type == LED_TYPE_QUALITY) {
1162 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
1163 enabled ? 3 : 0);
1164 }
1165
1166 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1167
1168 } else {
1169 if (led->type == LED_TYPE_RADIO) {
1170 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1171 enabled ? 0x20 : 0);
1172 } else if (led->type == LED_TYPE_ASSOC) {
1173 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1174 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
1175 } else if (led->type == LED_TYPE_QUALITY) {
1176 /*
1177 * The brightness is divided into 6 levels (0 - 5),
1178 * The specs tell us the following levels:
1179 * 0, 1 ,3, 7, 15, 31
1180 * to determine the level in a simple way we can simply
1181 * work with bitshifting:
1182 * (1 << level) - 1
1183 */
1184 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1185 (1 << brightness / (LED_FULL / 6)) - 1,
1186 polarity);
1187 }
f4450616
BZ		 1188 }
1189}
1190
b3579d6a 1191static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 1192 struct rt2x00_led *led, enum led_type type)
1193{
1194 led->rt2x00dev = rt2x00dev;
1195 led->type = type;
1196 led->led_dev.brightness_set = rt2800_brightness_set;
f4450616
BZ		 1197 led->flags = LED_INITIALIZED;
1198}
f4450616
BZ		 1199#endif /* CONFIG_RT2X00_LIB_LEDS */
1200
1201/*
1202 * Configuration handlers.
1203 */
a2b1328a
HS		 1204static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1205 const u8 *address,
1206 int wcid)
f4450616
BZ		 1207{
1208 struct mac_wcid_entry wcid_entry;
a2b1328a
HS		 1209 u32 offset;
1210
1211 offset = MAC_WCID_ENTRY(wcid);
1212
1213 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1214 if (address)
1215 memcpy(wcid_entry.mac, address, ETH_ALEN);
1216
1217 rt2800_register_multiwrite(rt2x00dev, offset,
1218 &wcid_entry, sizeof(wcid_entry));
1219}
1220
1221static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1222{
1223 u32 offset;
1224 offset = MAC_WCID_ATTR_ENTRY(wcid);
1225 rt2800_register_write(rt2x00dev, offset, 0);
1226}
1227
1228static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1229 int wcid, u32 bssidx)
1230{
1231 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1232 u32 reg;
1233
1234 /*
1235 * The BSS Idx numbers is split in a main value of 3 bits,
1236 * and a extended field for adding one additional bit to the value.
1237 */
1238 rt2800_register_read(rt2x00dev, offset, &reg);
1239 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1240 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1241 (bssidx & 0x8) >> 3);
1242 rt2800_register_write(rt2x00dev, offset, reg);
1243}
1244
1245static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1246 struct rt2x00lib_crypto *crypto,
1247 struct ieee80211_key_conf *key)
1248{
f4450616
BZ		 1249 struct mac_iveiv_entry iveiv_entry;
1250 u32 offset;
1251 u32 reg;
1252
1253 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1254
e4a0ab34
ID		 1255 if (crypto->cmd == SET_KEY) {
1256 rt2800_register_read(rt2x00dev, offset, &reg);
1257 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1258 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1259 /*
1260 * Both the cipher as the BSS Idx numbers are split in a main
1261 * value of 3 bits, and a extended field for adding one additional
1262 * bit to the value.
1263 */
1264 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1265 (crypto->cipher & 0x7));
1266 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1267 (crypto->cipher & 0x8) >> 3);
e4a0ab34
ID		 1268 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1269 rt2800_register_write(rt2x00dev, offset, reg);
1270 } else {
a2b1328a
HS		 1271 /* Delete the cipher without touching the bssidx */
1272 rt2800_register_read(rt2x00dev, offset, &reg);
1273 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1274 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1275 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1276 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1277 rt2800_register_write(rt2x00dev, offset, reg);
e4a0ab34 1278 }
f4450616
BZ		 1279
1280 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1281
1282 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1283 if ((crypto->cipher == CIPHER_TKIP) ||
1284 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1285 (crypto->cipher == CIPHER_AES))
1286 iveiv_entry.iv[3] |= 0x20;
1287 iveiv_entry.iv[3] |= key->keyidx << 6;
1288 rt2800_register_multiwrite(rt2x00dev, offset,
1289 &iveiv_entry, sizeof(iveiv_entry));
f4450616
BZ		 1290}
1291
1292int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1293 struct rt2x00lib_crypto *crypto,
1294 struct ieee80211_key_conf *key)
1295{
1296 struct hw_key_entry key_entry;
1297 struct rt2x00_field32 field;
1298 u32 offset;
1299 u32 reg;
1300
1301 if (crypto->cmd == SET_KEY) {
1302 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1303
1304 memcpy(key_entry.key, crypto->key,
1305 sizeof(key_entry.key));
1306 memcpy(key_entry.tx_mic, crypto->tx_mic,
1307 sizeof(key_entry.tx_mic));
1308 memcpy(key_entry.rx_mic, crypto->rx_mic,
1309 sizeof(key_entry.rx_mic));
1310
1311 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1312 rt2800_register_multiwrite(rt2x00dev, offset,
1313 &key_entry, sizeof(key_entry));
1314 }
1315
1316 /*
1317 * The cipher types are stored over multiple registers
1318 * starting with SHARED_KEY_MODE_BASE each word will have
1319 * 32 bits and contains the cipher types for 2 bssidx each.
1320 * Using the correct defines correctly will cause overhead,
1321 * so just calculate the correct offset.
1322 */
1323 field.bit_offset = 4 * (key->hw_key_idx % 8);
1324 field.bit_mask = 0x7 << field.bit_offset;
1325
1326 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1327
1328 rt2800_register_read(rt2x00dev, offset, &reg);
1329 rt2x00_set_field32(&reg, field,
1330 (crypto->cmd == SET_KEY) * crypto->cipher);
1331 rt2800_register_write(rt2x00dev, offset, reg);
1332
1333 /*
1334 * Update WCID information
1335 */
a2b1328a
HS		 1336 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1337 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1338 crypto->bssidx);
1339 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1340
1341 return 0;
1342}
1343EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1344
a2b1328a 1345static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1ed3811c 1346{
a2b1328a 1347 struct mac_wcid_entry wcid_entry;
1ed3811c 1348 int idx;
a2b1328a 1349 u32 offset;
1ed3811c
HS		 1350
1351 /*
a2b1328a
HS		 1352 * Search for the first free WCID entry and return the corresponding
1353 * index.
1ed3811c
HS		 1354 *
1355 * Make sure the WCID starts _after_ the last possible shared key
1356 * entry (>32).
1357 *
1358 * Since parts of the pairwise key table might be shared with
1359 * the beacon frame buffers 6 & 7 we should only write into the
1360 * first 222 entries.
1361 */
1362 for (idx = 33; idx <= 222; idx++) {
a2b1328a
HS		 1363 offset = MAC_WCID_ENTRY(idx);
1364 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1365 sizeof(wcid_entry));
1366 if (is_broadcast_ether_addr(wcid_entry.mac))
1ed3811c
HS		 1367 return idx;
1368 }
a2b1328a
HS		 1369
1370 /*
1371 * Use -1 to indicate that we don't have any more space in the WCID
1372 * table.
1373 */
1ed3811c
HS		 1374 return -1;
1375}
1376
f4450616
BZ		 1377int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1378 struct rt2x00lib_crypto *crypto,
1379 struct ieee80211_key_conf *key)
1380{
1381 struct hw_key_entry key_entry;
1382 u32 offset;
1383
1384 if (crypto->cmd == SET_KEY) {
a2b1328a
HS		 1385 /*
1386 * Allow key configuration only for STAs that are
1387 * known by the hw.
1388 */
1389 if (crypto->wcid < 0)
f4450616 1390 return -ENOSPC;
a2b1328a 1391 key->hw_key_idx = crypto->wcid;
f4450616
BZ		 1392
1393 memcpy(key_entry.key, crypto->key,
1394 sizeof(key_entry.key));
1395 memcpy(key_entry.tx_mic, crypto->tx_mic,
1396 sizeof(key_entry.tx_mic));
1397 memcpy(key_entry.rx_mic, crypto->rx_mic,
1398 sizeof(key_entry.rx_mic));
1399
1400 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1401 rt2800_register_multiwrite(rt2x00dev, offset,
1402 &key_entry, sizeof(key_entry));
1403 }
1404
1405 /*
1406 * Update WCID information
1407 */
a2b1328a 1408 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1409
1410 return 0;
1411}
1412EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1413
a2b1328a
HS		 1414int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1415 struct ieee80211_sta *sta)
1416{
1417 int wcid;
1418 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1419
1420 /*
1421 * Find next free WCID.
1422 */
1423 wcid = rt2800_find_wcid(rt2x00dev);
1424
1425 /*
1426 * Store selected wcid even if it is invalid so that we can
1427 * later decide if the STA is uploaded into the hw.
1428 */
1429 sta_priv->wcid = wcid;
1430
1431 /*
1432 * No space left in the device, however, we can still communicate
1433 * with the STA -> No error.
1434 */
1435 if (wcid < 0)
1436 return 0;
1437
1438 /*
1439 * Clean up WCID attributes and write STA address to the device.
1440 */
1441 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1442 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1443 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1444 rt2x00lib_get_bssidx(rt2x00dev, vif));
1445 return 0;
1446}
1447EXPORT_SYMBOL_GPL(rt2800_sta_add);
1448
1449int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1450{
1451 /*
1452 * Remove WCID entry, no need to clean the attributes as they will
1453 * get renewed when the WCID is reused.
1454 */
1455 rt2800_config_wcid(rt2x00dev, NULL, wcid);
1456
1457 return 0;
1458}
1459EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1460
f4450616
BZ		 1461void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1462 const unsigned int filter_flags)
1463{
1464 u32 reg;
1465
1466 /*
1467 * Start configuration steps.
1468 * Note that the version error will always be dropped
1469 * and broadcast frames will always be accepted since
1470 * there is no filter for it at this time.
1471 */
1472 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1473 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1474 !(filter_flags & FIF_FCSFAIL));
1475 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1476 !(filter_flags & FIF_PLCPFAIL));
1477 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1478 !(filter_flags & FIF_PROMISC_IN_BSS));
1479 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1480 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1481 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1482 !(filter_flags & FIF_ALLMULTI));
1483 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1484 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1485 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1486 !(filter_flags & FIF_CONTROL));
1487 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1488 !(filter_flags & FIF_CONTROL));
1489 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1490 !(filter_flags & FIF_CONTROL));
1491 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1492 !(filter_flags & FIF_CONTROL));
1493 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1494 !(filter_flags & FIF_CONTROL));
1495 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1496 !(filter_flags & FIF_PSPOLL));
84e9e8eb 1497 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
48839938
HS		 1498 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1499 !(filter_flags & FIF_CONTROL));
f4450616
BZ		 1500 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1501 !(filter_flags & FIF_CONTROL));
1502 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1503}
1504EXPORT_SYMBOL_GPL(rt2800_config_filter);
1505
1506void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1507 struct rt2x00intf_conf *conf, const unsigned int flags)
1508{
f4450616 1509 u32 reg;
fa8b4b22 1510 bool update_bssid = false;
f4450616
BZ		 1511
1512 if (flags & CONFIG_UPDATE_TYPE) {
f4450616
BZ		 1513 /*
1514 * Enable synchronisation.
1515 */
1516 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
f4450616 1517 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
f4450616 1518 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
15a533c4
HS		 1519
1520 if (conf->sync == TSF_SYNC_AP_NONE) {
1521 /*
1522 * Tune beacon queue transmit parameters for AP mode
1523 */
1524 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1525 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1526 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1527 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1528 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1529 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1530 } else {
1531 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1532 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1533 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1534 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1535 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1536 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1537 }
f4450616
BZ		 1538 }
1539
1540 if (flags & CONFIG_UPDATE_MAC) {
fa8b4b22
HS		 1541 if (flags & CONFIG_UPDATE_TYPE &&
1542 conf->sync == TSF_SYNC_AP_NONE) {
1543 /*
1544 * The BSSID register has to be set to our own mac
1545 * address in AP mode.
1546 */
1547 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1548 update_bssid = true;
1549 }
1550
c600c826
ID		 1551 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1552 reg = le32_to_cpu(conf->mac[1]);
1553 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1554 conf->mac[1] = cpu_to_le32(reg);
1555 }
f4450616
BZ		 1556
1557 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1558 conf->mac, sizeof(conf->mac));
1559 }
1560
fa8b4b22 1561 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
c600c826
ID		 1562 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1563 reg = le32_to_cpu(conf->bssid[1]);
1564 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1565 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1566 conf->bssid[1] = cpu_to_le32(reg);
1567 }
f4450616
BZ		 1568
1569 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1570 conf->bssid, sizeof(conf->bssid));
1571 }
1572}
1573EXPORT_SYMBOL_GPL(rt2800_config_intf);
1574
87c1915d
HS		 1575static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1576 struct rt2x00lib_erp *erp)
1577{
1578 bool any_sta_nongf = !!(erp->ht_opmode &
1579 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1580 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1581 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1582 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1583 u32 reg;
1584
1585 /* default protection rate for HT20: OFDM 24M */
1586 mm20_rate = gf20_rate = 0x4004;
1587
1588 /* default protection rate for HT40: duplicate OFDM 24M */
1589 mm40_rate = gf40_rate = 0x4084;
1590
1591 switch (protection) {
1592 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1593 /*
1594 * All STAs in this BSS are HT20/40 but there might be
1595 * STAs not supporting greenfield mode.
1596 * => Disable protection for HT transmissions.
1597 */
1598 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1599
1600 break;
1601 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1602 /*
1603 * All STAs in this BSS are HT20 or HT20/40 but there
1604 * might be STAs not supporting greenfield mode.
1605 * => Protect all HT40 transmissions.
1606 */
1607 mm20_mode = gf20_mode = 0;
1608 mm40_mode = gf40_mode = 2;
1609
1610 break;
1611 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1612 /*
1613 * Nonmember protection:
1614 * According to 802.11n we _should_ protect all
1615 * HT transmissions (but we don't have to).
1616 *
1617 * But if cts_protection is enabled we _shall_ protect
1618 * all HT transmissions using a CCK rate.
1619 *
1620 * And if any station is non GF we _shall_ protect
1621 * GF transmissions.
1622 *
1623 * We decide to protect everything
1624 * -> fall through to mixed mode.
1625 */
1626 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1627 /*
1628 * Legacy STAs are present
1629 * => Protect all HT transmissions.
1630 */
1631 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1632
1633 /*
1634 * If erp protection is needed we have to protect HT
1635 * transmissions with CCK 11M long preamble.
1636 */
1637 if (erp->cts_protection) {
1638 /* don't duplicate RTS/CTS in CCK mode */
1639 mm20_rate = mm40_rate = 0x0003;
1640 gf20_rate = gf40_rate = 0x0003;
1641 }
1642 break;
6403eab1 1643 }
87c1915d
HS		 1644
1645 /* check for STAs not supporting greenfield mode */
1646 if (any_sta_nongf)
1647 gf20_mode = gf40_mode = 2;
1648
1649 /* Update HT protection config */
1650 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1651 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1652 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1653 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1654
1655 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1656 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1657 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1658 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1659
1660 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1661 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1662 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1663 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1664
1665 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1666 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1667 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1668 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1669}
1670
02044643
HS		 1671void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1672 u32 changed)
f4450616
BZ		 1673{
1674 u32 reg;
1675
02044643
HS		 1676 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1677 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1678 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1679 !!erp->short_preamble);
1680 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1681 !!erp->short_preamble);
1682 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1683 }
f4450616 1684
02044643
HS		 1685 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1686 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1687 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1688 erp->cts_protection ? 2 : 0);
1689 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1690 }
f4450616 1691
02044643
HS		 1692 if (changed & BSS_CHANGED_BASIC_RATES) {
1693 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1694 erp->basic_rates);
1695 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1696 }
f4450616 1697
02044643
HS		 1698 if (changed & BSS_CHANGED_ERP_SLOT) {
1699 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1700 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1701 erp->slot_time);
1702 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
f4450616 1703
02044643
HS		 1704 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1705 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1706 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1707 }
f4450616 1708
02044643
HS		 1709 if (changed & BSS_CHANGED_BEACON_INT) {
1710 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1711 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1712 erp->beacon_int * 16);
1713 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1714 }
87c1915d
HS		 1715
1716 if (changed & BSS_CHANGED_HT)
1717 rt2800_config_ht_opmode(rt2x00dev, erp);
f4450616
BZ		 1718}
1719EXPORT_SYMBOL_GPL(rt2800_config_erp);
1720
872834df
GW		 1721static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1722{
1723 u32 reg;
1724 u16 eeprom;
1725 u8 led_ctrl, led_g_mode, led_r_mode;
1726
1727 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1728 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1729 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1730 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1731 } else {
1732 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1733 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1734 }
1735 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1736
1737 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1738 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1739 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1740 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1741 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
3e38d3da 1742 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
872834df
GW		 1743 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1744 if (led_ctrl == 0 || led_ctrl > 0x40) {
1745 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1746 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1747 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1748 } else {
1749 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1750 (led_g_mode << 2) | led_r_mode, 1);
1751 }
1752 }
1753}
1754
d96aa640
RJH		 1755static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1756 enum antenna ant)
1757{
1758 u32 reg;
1759 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1760 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1761
1762 if (rt2x00_is_pci(rt2x00dev)) {
1763 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1764 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1765 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1766 } else if (rt2x00_is_usb(rt2x00dev))
1767 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1768 eesk_pin, 0);
1769
99bdf51a
GW		 1770 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1771 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1772 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1773 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
d96aa640
RJH		 1774}
1775
f4450616
BZ		 1776void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1777{
1778 u8 r1;
1779 u8 r3;
d96aa640 1780 u16 eeprom;
f4450616
BZ		 1781
1782 rt2800_bbp_read(rt2x00dev, 1, &r1);
1783 rt2800_bbp_read(rt2x00dev, 3, &r3);
1784
872834df
GW		 1785 if (rt2x00_rt(rt2x00dev, RT3572) &&
1786 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1787 rt2800_config_3572bt_ant(rt2x00dev);
1788
f4450616
BZ		 1789 /*
1790 * Configure the TX antenna.
1791 */
d96aa640 1792 switch (ant->tx_chain_num) {
f4450616
BZ		 1793 case 1:
1794 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1795 break;
1796 case 2:
872834df
GW		 1797 if (rt2x00_rt(rt2x00dev, RT3572) &&
1798 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1799 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1800 else
1801 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
f4450616
BZ		 1802 break;
1803 case 3:
4788ac1e 1804 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
f4450616
BZ		 1805 break;
1806 }
1807
1808 /*
1809 * Configure the RX antenna.
1810 */
d96aa640 1811 switch (ant->rx_chain_num) {
f4450616 1812 case 1:
d96aa640
RJH		 1813 if (rt2x00_rt(rt2x00dev, RT3070) ||
1814 rt2x00_rt(rt2x00dev, RT3090) ||
03839951 1815 rt2x00_rt(rt2x00dev, RT3352) ||
d96aa640 1816 rt2x00_rt(rt2x00dev, RT3390)) {
3e38d3da 1817 rt2800_eeprom_read(rt2x00dev,
d96aa640
RJH		 1818 EEPROM_NIC_CONF1, &eeprom);
1819 if (rt2x00_get_field16(eeprom,
1820 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1821 rt2800_set_ant_diversity(rt2x00dev,
1822 rt2x00dev->default_ant.rx);
1823 }
f4450616
BZ		 1824 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1825 break;
1826 case 2:
872834df
GW		 1827 if (rt2x00_rt(rt2x00dev, RT3572) &&
1828 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1829 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1830 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1831 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1832 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1833 } else {
1834 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1835 }
f4450616
BZ		 1836 break;
1837 case 3:
1838 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1839 break;
1840 }
1841
1842 rt2800_bbp_write(rt2x00dev, 3, r3);
1843 rt2800_bbp_write(rt2x00dev, 1, r1);
5cddb3c2
GJ		 1844
1845 if (rt2x00_rt(rt2x00dev, RT3593)) {
1846 if (ant->rx_chain_num == 1)
1847 rt2800_bbp_write(rt2x00dev, 86, 0x00);
1848 else
1849 rt2800_bbp_write(rt2x00dev, 86, 0x46);
1850 }
f4450616
BZ		 1851}
1852EXPORT_SYMBOL_GPL(rt2800_config_ant);
1853
1854static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1855 struct rt2x00lib_conf *libconf)
1856{
1857 u16 eeprom;
1858 short lna_gain;
1859
1860 if (libconf->rf.channel <= 14) {
3e38d3da 1861 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
f4450616
BZ		 1862 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1863 } else if (libconf->rf.channel <= 64) {
3e38d3da 1864 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
f4450616
BZ		 1865 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1866 } else if (libconf->rf.channel <= 128) {
f36bb0ca
GJ		 1867 if (rt2x00_rt(rt2x00dev, RT3593)) {
1868 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1869 lna_gain = rt2x00_get_field16(eeprom,
1870 EEPROM_EXT_LNA2_A1);
1871 } else {
1872 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1873 lna_gain = rt2x00_get_field16(eeprom,
1874 EEPROM_RSSI_BG2_LNA_A1);
1875 }
f4450616 1876 } else {
f36bb0ca
GJ		 1877 if (rt2x00_rt(rt2x00dev, RT3593)) {
1878 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1879 lna_gain = rt2x00_get_field16(eeprom,
1880 EEPROM_EXT_LNA2_A2);
1881 } else {
1882 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1883 lna_gain = rt2x00_get_field16(eeprom,
1884 EEPROM_RSSI_A2_LNA_A2);
1885 }
f4450616
BZ		 1886 }
1887
1888 rt2x00dev->lna_gain = lna_gain;
1889}
1890
3f1b8739
GJ		 1891#define FREQ_OFFSET_BOUND 0x5f
1892
1893static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev)
1894{
1895 u8 freq_offset, prev_freq_offset;
1896 u8 rfcsr, prev_rfcsr;
1897
1898 freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
1899 freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND);
1900
1901 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1902 prev_rfcsr = rfcsr;
1903
1904 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset);
1905 if (rfcsr == prev_rfcsr)
1906 return;
1907
1908 if (rt2x00_is_usb(rt2x00dev)) {
1909 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff,
1910 freq_offset, prev_rfcsr);
1911 return;
1912 }
1913
1914 prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE);
1915 while (prev_freq_offset != freq_offset) {
1916 if (prev_freq_offset < freq_offset)
1917 prev_freq_offset++;
1918 else
1919 prev_freq_offset--;
1920
1921 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset);
1922 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1923
1924 usleep_range(1000, 1500);
1925 }
1926}
1927
06855ef4
GW		 1928static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1929 struct ieee80211_conf *conf,
1930 struct rf_channel *rf,
1931 struct channel_info *info)
f4450616
BZ		 1932{
1933 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1934
d96aa640 1935 if (rt2x00dev->default_ant.tx_chain_num == 1)
f4450616
BZ		 1936 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1937
d96aa640 1938 if (rt2x00dev->default_ant.rx_chain_num == 1) {
f4450616
BZ		 1939 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1940 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
d96aa640 1941 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
f4450616
BZ		 1942 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1943
1944 if (rf->channel > 14) {
1945 /*
1946 * When TX power is below 0, we should increase it by 7 to
25985edc 1947 * make it a positive value (Minimum value is -7).
f4450616
BZ		 1948 * However this means that values between 0 and 7 have
1949 * double meaning, and we should set a 7DBm boost flag.
1950 */
1951 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
8d1331b3 1952 (info->default_power1 >= 0));
f4450616 1953
8d1331b3
ID		 1954 if (info->default_power1 < 0)
1955 info->default_power1 += 7;
f4450616 1956
8d1331b3 1957 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
f4450616
BZ		 1958
1959 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
8d1331b3 1960 (info->default_power2 >= 0));
f4450616 1961
8d1331b3
ID		 1962 if (info->default_power2 < 0)
1963 info->default_power2 += 7;
f4450616 1964
8d1331b3 1965 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
f4450616 1966 } else {
8d1331b3
ID		 1967 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1968 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
f4450616
BZ		 1969 }
1970
1971 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1972
1973 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1974 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1975 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1976 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1977
1978 udelay(200);
1979
1980 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1981 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1982 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1983 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1984
1985 udelay(200);
1986
1987 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1988 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1989 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1990 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1991}
1992
06855ef4
GW		 1993static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1994 struct ieee80211_conf *conf,
1995 struct rf_channel *rf,
1996 struct channel_info *info)
f4450616 1997{
3a1c0128 1998 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
f1f12f98 1999 u8 rfcsr, calib_tx, calib_rx;
f4450616
BZ		 2000
2001 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
7f4666ab
SG		 2002
2003 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2004 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
2005 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
f4450616
BZ		 2006
2007 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 2008 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 2009 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2010
2011 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
8d1331b3 2012 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
f4450616
BZ		 2013 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2014
5a673964 2015 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
8d1331b3 2016 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
5a673964 2017 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
e3bab197
SG		 2018
2019 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2020 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
7ad63035
GW		 2021 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2022 rt2x00dev->default_ant.rx_chain_num <= 1);
2023 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
2024 rt2x00dev->default_ant.rx_chain_num <= 2);
e3bab197 2025 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
7ad63035
GW		 2026 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2027 rt2x00dev->default_ant.tx_chain_num <= 1);
2028 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
2029 rt2x00dev->default_ant.tx_chain_num <= 2);
e3bab197 2030 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5a673964 2031
3e0c7643
SG		 2032 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2033 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2034 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2035 msleep(1);
2036 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2037 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2038
f4450616
BZ		 2039 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2040 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2041 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2042
f1f12f98
SG		 2043 if (rt2x00_rt(rt2x00dev, RT3390)) {
2044 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
2045 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
2046 } else {
3a1c0128
GW		 2047 if (conf_is_ht40(conf)) {
2048 calib_tx = drv_data->calibration_bw40;
2049 calib_rx = drv_data->calibration_bw40;
2050 } else {
2051 calib_tx = drv_data->calibration_bw20;
2052 calib_rx = drv_data->calibration_bw20;
2053 }
f1f12f98
SG		 2054 }
2055
2056 rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
2057 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
2058 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
2059
2060 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
2061 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
2062 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
f4450616 2063
71976907 2064 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 2065 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 2066 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
3e0c7643
SG		 2067
2068 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2069 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2070 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2071 msleep(1);
2072 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2073 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
f4450616
BZ		 2074}
2075
872834df
GW		 2076static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
2077 struct ieee80211_conf *conf,
2078 struct rf_channel *rf,
2079 struct channel_info *info)
2080{
3a1c0128 2081 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
872834df
GW		 2082 u8 rfcsr;
2083 u32 reg;
2084
2085 if (rf->channel <= 14) {
5d137dff
GW		 2086 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2087 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
872834df
GW		 2088 } else {
2089 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2090 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2091 }
2092
2093 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2094 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2095
2096 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2097 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2098 if (rf->channel <= 14)
2099 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
2100 else
2101 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
2102 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2103
2104 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
2105 if (rf->channel <= 14)
2106 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
2107 else
2108 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
2109 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2110
2111 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2112 if (rf->channel <= 14) {
2113 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
2114 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
569ffa56 2115 info->default_power1);
872834df
GW		 2116 } else {
2117 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
2118 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2119 (info->default_power1 & 0x3) |
2120 ((info->default_power1 & 0xC) << 1));
2121 }
2122 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2123
2124 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
2125 if (rf->channel <= 14) {
2126 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
2127 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
569ffa56 2128 info->default_power2);
872834df
GW		 2129 } else {
2130 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
2131 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2132 (info->default_power2 & 0x3) |
2133 ((info->default_power2 & 0xC) << 1));
2134 }
2135 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2136
2137 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
872834df
GW		 2138 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2139 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2140 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2141 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
0cd461ef
GW		 2142 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2143 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
872834df
GW		 2144 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
2145 if (rf->channel <= 14) {
2146 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2147 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2148 }
2149 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2150 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2151 } else {
2152 switch (rt2x00dev->default_ant.tx_chain_num) {
2153 case 1:
2154 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2155 case 2:
2156 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2157 break;
2158 }
2159
2160 switch (rt2x00dev->default_ant.rx_chain_num) {
2161 case 1:
2162 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2163 case 2:
2164 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2165 break;
2166 }
2167 }
2168 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2169
2170 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2171 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2172 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2173
3a1c0128
GW		 2174 if (conf_is_ht40(conf)) {
2175 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2176 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2177 } else {
2178 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2179 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2180 }
872834df
GW		 2181
2182 if (rf->channel <= 14) {
2183 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2184 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2185 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2186 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2187 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
77c06c2c
GW		 2188 rfcsr = 0x4c;
2189 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2190 drv_data->txmixer_gain_24g);
2191 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
872834df
GW		 2192 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2193 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2194 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2195 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2196 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2197 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2198 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2199 } else {
58b8ae14
GW		 2200 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2201 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
2202 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
2203 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
2204 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
2205 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
872834df
GW		 2206 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2207 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2208 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2209 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
77c06c2c
GW		 2210 rfcsr = 0x7a;
2211 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2212 drv_data->txmixer_gain_5g);
2213 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
872834df
GW		 2214 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2215 if (rf->channel <= 64) {
2216 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2217 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2218 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2219 } else if (rf->channel <= 128) {
2220 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2221 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2222 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2223 } else {
2224 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2225 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2226 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2227 }
2228 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2229 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2230 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2231 }
2232
99bdf51a
GW		 2233 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
2234 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
872834df 2235 if (rf->channel <= 14)
99bdf51a 2236 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
872834df 2237 else
99bdf51a
GW		 2238 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
2239 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
872834df
GW		 2240
2241 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2242 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2243 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2244}
60687ba7 2245
f42b0465
GJ		 2246static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
2247 struct ieee80211_conf *conf,
2248 struct rf_channel *rf,
2249 struct channel_info *info)
2250{
2251 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2252 u8 txrx_agc_fc;
2253 u8 txrx_h20m;
2254 u8 rfcsr;
2255 u8 bbp;
2256 const bool txbf_enabled = false; /* TODO */
2257
2258 /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */
2259 rt2800_bbp_read(rt2x00dev, 109, &bbp);
2260 rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0);
2261 rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0);
2262 rt2800_bbp_write(rt2x00dev, 109, bbp);
2263
2264 rt2800_bbp_read(rt2x00dev, 110, &bbp);
2265 rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0);
2266 rt2800_bbp_write(rt2x00dev, 110, bbp);
2267
2268 if (rf->channel <= 14) {
2269 /* Restore BBP 25 & 26 for 2.4 GHz */
2270 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2271 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2272 } else {
2273 /* Hard code BBP 25 & 26 for 5GHz */
2274
2275 /* Enable IQ Phase correction */
2276 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2277 /* Setup IQ Phase correction value */
2278 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2279 }
2280
2281 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2282 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
2283
2284 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2285 rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3));
2286 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2287
2288 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2289 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1);
2290 if (rf->channel <= 14)
2291 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1);
2292 else
2293 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2);
2294 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2295
2296 rt2800_rfcsr_read(rt2x00dev, 53, &rfcsr);
2297 if (rf->channel <= 14) {
2298 rfcsr = 0;
2299 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2300 info->default_power1 & 0x1f);
2301 } else {
2302 if (rt2x00_is_usb(rt2x00dev))
2303 rfcsr = 0x40;
2304
2305 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2306 ((info->default_power1 & 0x18) << 1) |
2307 (info->default_power1 & 7));
2308 }
2309 rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
2310
2311 rt2800_rfcsr_read(rt2x00dev, 55, &rfcsr);
2312 if (rf->channel <= 14) {
2313 rfcsr = 0;
2314 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2315 info->default_power2 & 0x1f);
2316 } else {
2317 if (rt2x00_is_usb(rt2x00dev))
2318 rfcsr = 0x40;
2319
2320 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2321 ((info->default_power2 & 0x18) << 1) |
2322 (info->default_power2 & 7));
2323 }
2324 rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
2325
2326 rt2800_rfcsr_read(rt2x00dev, 54, &rfcsr);
2327 if (rf->channel <= 14) {
2328 rfcsr = 0;
2329 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2330 info->default_power3 & 0x1f);
2331 } else {
2332 if (rt2x00_is_usb(rt2x00dev))
2333 rfcsr = 0x40;
2334
2335 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2336 ((info->default_power3 & 0x18) << 1) |
2337 (info->default_power3 & 7));
2338 }
2339 rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
2340
2341 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2342 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2343 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2344 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2345 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2346 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2347 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2348 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2349 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2350
2351 switch (rt2x00dev->default_ant.tx_chain_num) {
2352 case 3:
2353 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2354 /* fallthrough */
2355 case 2:
2356 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2357 /* fallthrough */
2358 case 1:
2359 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2360 break;
2361 }
2362
2363 switch (rt2x00dev->default_ant.rx_chain_num) {
2364 case 3:
2365 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2366 /* fallthrough */
2367 case 2:
2368 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2369 /* fallthrough */
2370 case 1:
2371 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2372 break;
2373 }
2374 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2375
e979a8ab 2376 rt2800_adjust_freq_offset(rt2x00dev);
f42b0465
GJ		 2377
2378 if (conf_is_ht40(conf)) {
2379 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
2380 RFCSR24_TX_AGC_FC);
2381 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40,
2382 RFCSR24_TX_H20M);
2383 } else {
2384 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
2385 RFCSR24_TX_AGC_FC);
2386 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20,
2387 RFCSR24_TX_H20M);
2388 }
2389
2390 /* NOTE: the reference driver does not writes the new value
2391 * back to RFCSR 32
2392 */
2393 rt2800_rfcsr_read(rt2x00dev, 32, &rfcsr);
2394 rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc);
2395
2396 if (rf->channel <= 14)
2397 rfcsr = 0xa0;
2398 else
2399 rfcsr = 0x80;
2400 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2401
2402 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2403 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m);
2404 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m);
2405 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2406
2407 /* Band selection */
2408 rt2800_rfcsr_read(rt2x00dev, 36, &rfcsr);
2409 if (rf->channel <= 14)
2410 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
2411 else
2412 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
2413 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
2414
2415 rt2800_rfcsr_read(rt2x00dev, 34, &rfcsr);
2416 if (rf->channel <= 14)
2417 rfcsr = 0x3c;
2418 else
2419 rfcsr = 0x20;
2420 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
2421
2422 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2423 if (rf->channel <= 14)
2424 rfcsr = 0x1a;
2425 else
2426 rfcsr = 0x12;
2427 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2428
2429 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2430 if (rf->channel >= 1 && rf->channel <= 14)
2431 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2432 else if (rf->channel >= 36 && rf->channel <= 64)
2433 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2434 else if (rf->channel >= 100 && rf->channel <= 128)
2435 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2436 else
2437 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2438 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2439
2440 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2441 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
2442 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2443
2444 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
2445
2446 if (rf->channel <= 14) {
2447 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
2448 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2449 } else {
2450 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
2451 rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
2452 }
2453
2454 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2455 rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1);
2456 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2457
2458 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2459 if (rf->channel <= 14) {
2460 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5);
2461 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3);
2462 } else {
2463 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4);
2464 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2);
2465 }
2466 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2467
2468 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2469 if (rf->channel <= 14)
2470 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3);
2471 else
2472 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2);
2473
2474 if (txbf_enabled)
2475 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1);
2476
2477 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2478
2479 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2480 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0);
2481 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2482
2483 rt2800_rfcsr_read(rt2x00dev, 57, &rfcsr);
2484 if (rf->channel <= 14)
2485 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b);
2486 else
2487 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f);
2488 rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
2489
2490 if (rf->channel <= 14) {
2491 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
2492 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
2493 } else {
2494 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
2495 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
2496 }
2497
2498 /* Initiate VCO calibration */
2499 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2500 if (rf->channel <= 14) {
2501 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2502 } else {
2503 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1);
2504 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1);
2505 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1);
2506 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1);
2507 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1);
2508 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2509 }
2510 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2511
2512 if (rf->channel >= 1 && rf->channel <= 14) {
2513 rfcsr = 0x23;
2514 if (txbf_enabled)
2515 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2516 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2517
2518 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
2519 } else if (rf->channel >= 36 && rf->channel <= 64) {
2520 rfcsr = 0x36;
2521 if (txbf_enabled)
2522 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2523 rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
2524
2525 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
2526 } else if (rf->channel >= 100 && rf->channel <= 128) {
2527 rfcsr = 0x32;
2528 if (txbf_enabled)
2529 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2530 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2531
2532 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
2533 } else {
2534 rfcsr = 0x30;
2535 if (txbf_enabled)
2536 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2537 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2538
2539 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
2540 }
2541}
2542
7573cb5b 2543#define POWER_BOUND 0x27
8f821098 2544#define POWER_BOUND_5G 0x2b
0c9e5fb9 2545
a89534ed
WH		 2546static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2547 struct ieee80211_conf *conf,
2548 struct rf_channel *rf,
2549 struct channel_info *info)
2550{
2551 u8 rfcsr;
2552
2553 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2554 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2555 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2556 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2557 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2558
2559 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
7573cb5b
SG		 2560 if (info->default_power1 > POWER_BOUND)
2561 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
a89534ed
WH		 2562 else
2563 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2564 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2565
0c9e5fb9 2566 rt2800_adjust_freq_offset(rt2x00dev);
a89534ed
WH		 2567
2568 if (rf->channel <= 14) {
2569 if (rf->channel == 6)
2570 rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2571 else
2572 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2573
2574 if (rf->channel >= 1 && rf->channel <= 6)
2575 rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2576 else if (rf->channel >= 7 && rf->channel <= 11)
2577 rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2578 else if (rf->channel >= 12 && rf->channel <= 14)
2579 rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2580 }
2581}
2582
03839951
DG		 2583static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2584 struct ieee80211_conf *conf,
2585 struct rf_channel *rf,
2586 struct channel_info *info)
2587{
2588 u8 rfcsr;
2589
2590 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2591 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2592
2593 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2594 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2595 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2596
2597 if (info->default_power1 > POWER_BOUND)
2598 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2599 else
2600 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2601
2602 if (info->default_power2 > POWER_BOUND)
2603 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2604 else
2605 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2606
0c9e5fb9 2607 rt2800_adjust_freq_offset(rt2x00dev);
03839951
DG		 2608
2609 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2610 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2611 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2612
2613 if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2614 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2615 else
2616 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2617
2618 if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2619 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2620 else
2621 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2622
2623 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2624 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2625
2626 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2627
2628 rt2800_rfcsr_write(rt2x00dev, 31, 80);
2629}
2630
60687ba7 2631static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
adde5882
GJ		 2632 struct ieee80211_conf *conf,
2633 struct rf_channel *rf,
2634 struct channel_info *info)
2635{
2636 u8 rfcsr;
adde5882
GJ		 2637
2638 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2639 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2640 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2641 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2642 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2643
2644 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
7573cb5b
SG		 2645 if (info->default_power1 > POWER_BOUND)
2646 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
adde5882
GJ		 2647 else
2648 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2649 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2650
cff3d1f0
ZL		 2651 if (rt2x00_rt(rt2x00dev, RT5392)) {
2652 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
7573cb5b
SG		 2653 if (info->default_power1 > POWER_BOUND)
2654 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
cff3d1f0
ZL		 2655 else
2656 rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2657 info->default_power2);
2658 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2659 }
2660
adde5882 2661 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
cff3d1f0
ZL		 2662 if (rt2x00_rt(rt2x00dev, RT5392)) {
2663 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2664 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2665 }
adde5882
GJ		 2666 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2667 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2668 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2669 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2670 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2671
0c9e5fb9 2672 rt2800_adjust_freq_offset(rt2x00dev);
adde5882 2673
adde5882
GJ		 2674 if (rf->channel <= 14) {
2675 int idx = rf->channel-1;
2676
fdbc7b0a 2677 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
adde5882
GJ		 2678 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2679 /* r55/r59 value array of channel 1~14 */
2680 static const char r55_bt_rev[] = {0x83, 0x83,
2681 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2682 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2683 static const char r59_bt_rev[] = {0x0e, 0x0e,
2684 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2685 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2686
2687 rt2800_rfcsr_write(rt2x00dev, 55,
2688 r55_bt_rev[idx]);
2689 rt2800_rfcsr_write(rt2x00dev, 59,
2690 r59_bt_rev[idx]);
2691 } else {
2692 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2693 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2694 0x88, 0x88, 0x86, 0x85, 0x84};
2695
2696 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2697 }
2698 } else {
2699 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2700 static const char r55_nonbt_rev[] = {0x23, 0x23,
2701 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2702 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2703 static const char r59_nonbt_rev[] = {0x07, 0x07,
2704 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2705 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2706
2707 rt2800_rfcsr_write(rt2x00dev, 55,
2708 r55_nonbt_rev[idx]);
2709 rt2800_rfcsr_write(rt2x00dev, 59,
2710 r59_nonbt_rev[idx]);
2ed71884 2711 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
e6d227b9 2712 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 2713 static const char r59_non_bt[] = {0x8f, 0x8f,
2714 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2715 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2716
2717 rt2800_rfcsr_write(rt2x00dev, 59,
2718 r59_non_bt[idx]);
2719 }
2720 }
2721 }
60687ba7
RST		 2722}
2723
8f821098
SG		 2724static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2725 struct ieee80211_conf *conf,
2726 struct rf_channel *rf,
2727 struct channel_info *info)
2728{
2729 u8 rfcsr, ep_reg;
d5ae7a6b 2730 u32 reg;
8f821098
SG		 2731 int power_bound;
2732
2733 /* TODO */
2734 const bool is_11b = false;
2735 const bool is_type_ep = false;
2736
d5ae7a6b
SG		 2737 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2738 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
2739 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
2740 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
8f821098
SG		 2741
2742 /* Order of values on rf_channel entry: N, K, mod, R */
2743 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2744
2745 rt2800_rfcsr_read(rt2x00dev, 9, &rfcsr);
2746 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2747 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2748 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2749 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2750
2751 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2752 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2753 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2754 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2755
2756 if (rf->channel <= 14) {
2757 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2758 /* FIXME: RF11 owerwrite ? */
2759 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2760 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2761 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2762 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2763 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2764 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2765 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2766 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2767 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2768 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2769 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2770 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2771 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2772 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2773 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2774 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2775 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2776 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2777 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2778 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2779 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2780 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2781 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2782 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2783 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2784 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2785 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2786 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2787
2788 /* TODO RF27 <- tssi */
2789
2790 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2791 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2792 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2793
2794 if (is_11b) {
2795 /* CCK */
2796 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2797 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2798 if (is_type_ep)
2799 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2800 else
2801 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2802 } else {
2803 /* OFDM */
2804 if (is_type_ep)
2805 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2806 else
2807 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2808 }
2809
2810 power_bound = POWER_BOUND;
2811 ep_reg = 0x2;
2812 } else {
2813 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2814 /* FIMXE: RF11 overwrite */
2815 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2816 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
2817 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2818 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
2819 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
2820 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
2821 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
2822 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
2823 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
2824 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
2825 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
2826 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
2827 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
2828 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
2829
2830 /* TODO RF27 <- tssi */
2831
2832 if (rf->channel >= 36 && rf->channel <= 64) {
2833
2834 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
2835 rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
2836 rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
2837 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
2838 if (rf->channel <= 50)
2839 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
2840 else if (rf->channel >= 52)
2841 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
2842 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
2843 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
2844 rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
2845 rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
2846 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
2847 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
2848 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
2849 if (rf->channel <= 50) {
2850 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
2851 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
2852 } else if (rf->channel >= 52) {
2853 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
2854 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2855 }
2856
2857 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2858 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
2859 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2860
2861 } else if (rf->channel >= 100 && rf->channel <= 165) {
2862
2863 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
2864 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2865 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2866 if (rf->channel <= 153) {
2867 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
2868 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
2869 } else if (rf->channel >= 155) {
2870 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
2871 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
2872 }
2873 if (rf->channel <= 138) {
2874 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
2875 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
2876 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
2877 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
2878 } else if (rf->channel >= 140) {
2879 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
2880 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
2881 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
2882 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
2883 }
2884 if (rf->channel <= 124)
2885 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
2886 else if (rf->channel >= 126)
2887 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
2888 if (rf->channel <= 138)
2889 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2890 else if (rf->channel >= 140)
2891 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2892 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
2893 if (rf->channel <= 138)
2894 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
2895 else if (rf->channel >= 140)
2896 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
2897 if (rf->channel <= 128)
2898 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2899 else if (rf->channel >= 130)
2900 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
2901 if (rf->channel <= 116)
2902 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
2903 else if (rf->channel >= 118)
2904 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2905 if (rf->channel <= 138)
2906 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
2907 else if (rf->channel >= 140)
2908 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
2909 if (rf->channel <= 116)
2910 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
2911 else if (rf->channel >= 118)
2912 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2913 }
2914
2915 power_bound = POWER_BOUND_5G;
2916 ep_reg = 0x3;
2917 }
2918
2919 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2920 if (info->default_power1 > power_bound)
2921 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
2922 else
2923 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2924 if (is_type_ep)
2925 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
2926 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2927
2928 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
0847beb2 2929 if (info->default_power2 > power_bound)
8f821098
SG		 2930 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
2931 else
2932 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
2933 if (is_type_ep)
2934 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
2935 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2936
2937 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2938 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2939 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2940
2941 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
2942 rt2x00dev->default_ant.tx_chain_num >= 1);
2943 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2944 rt2x00dev->default_ant.tx_chain_num == 2);
2945 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2946
2947 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
2948 rt2x00dev->default_ant.rx_chain_num >= 1);
2949 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2950 rt2x00dev->default_ant.rx_chain_num == 2);
2951 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2952
2953 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2954 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
2955
2956 if (conf_is_ht40(conf))
2957 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
2958 else
2959 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
2960
2961 if (!is_11b) {
2962 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2963 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
2964 }
2965
2966 /* TODO proper frequency adjustment */
0c9e5fb9 2967 rt2800_adjust_freq_offset(rt2x00dev);
8f821098
SG		 2968
2969 /* TODO merge with others */
2970 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2971 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2972 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
6803141b
SG		 2973
2974 /* BBP settings */
2975 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2976 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2977 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2978
2979 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
2980 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
2981 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
2982 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
2983
2984 /* GLRT band configuration */
2985 rt2800_bbp_write(rt2x00dev, 195, 128);
2986 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
2987 rt2800_bbp_write(rt2x00dev, 195, 129);
2988 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
2989 rt2800_bbp_write(rt2x00dev, 195, 130);
2990 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
2991 rt2800_bbp_write(rt2x00dev, 195, 131);
2992 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
2993 rt2800_bbp_write(rt2x00dev, 195, 133);
2994 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
2995 rt2800_bbp_write(rt2x00dev, 195, 124);
2996 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
8f821098
SG		 2997}
2998
5bc2dd06
SG		 2999static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
3000 const unsigned int word,
3001 const u8 value)
3002{
3003 u8 chain, reg;
3004
3005 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
3006 rt2800_bbp_read(rt2x00dev, 27, &reg);
3007 rt2x00_set_field8(&reg, BBP27_RX_CHAIN_SEL, chain);
3008 rt2800_bbp_write(rt2x00dev, 27, reg);
3009
3010 rt2800_bbp_write(rt2x00dev, word, value);
3011 }
3012}
3013
8756130b
SG		 3014static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
3015{
3016 u8 cal;
3017
415e3f2f 3018 /* TX0 IQ Gain */
8756130b 3019 rt2800_bbp_write(rt2x00dev, 158, 0x2c);
415e3f2f
SG		 3020 if (channel <= 14)
3021 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
3022 else if (channel >= 36 && channel <= 64)
3023 cal = rt2x00_eeprom_byte(rt2x00dev,
3024 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
3025 else if (channel >= 100 && channel <= 138)
3026 cal = rt2x00_eeprom_byte(rt2x00dev,
3027 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
3028 else if (channel >= 140 && channel <= 165)
3029 cal = rt2x00_eeprom_byte(rt2x00dev,
3030 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
3031 else
3032 cal = 0;
8756130b
SG		 3033 rt2800_bbp_write(rt2x00dev, 159, cal);
3034
415e3f2f 3035 /* TX0 IQ Phase */
8756130b 3036 rt2800_bbp_write(rt2x00dev, 158, 0x2d);
415e3f2f
SG		 3037 if (channel <= 14)
3038 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
3039 else if (channel >= 36 && channel <= 64)
3040 cal = rt2x00_eeprom_byte(rt2x00dev,
3041 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
3042 else if (channel >= 100 && channel <= 138)
3043 cal = rt2x00_eeprom_byte(rt2x00dev,
3044 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
3045 else if (channel >= 140 && channel <= 165)
3046 cal = rt2x00_eeprom_byte(rt2x00dev,
3047 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
3048 else
3049 cal = 0;
8756130b
SG		 3050 rt2800_bbp_write(rt2x00dev, 159, cal);
3051
415e3f2f 3052 /* TX1 IQ Gain */
8756130b 3053 rt2800_bbp_write(rt2x00dev, 158, 0x4a);
415e3f2f
SG		 3054 if (channel <= 14)
3055 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
3056 else if (channel >= 36 && channel <= 64)
3057 cal = rt2x00_eeprom_byte(rt2x00dev,
3058 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
3059 else if (channel >= 100 && channel <= 138)
3060 cal = rt2x00_eeprom_byte(rt2x00dev,
3061 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
3062 else if (channel >= 140 && channel <= 165)
3063 cal = rt2x00_eeprom_byte(rt2x00dev,
3064 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
3065 else
3066 cal = 0;
8756130b
SG		 3067 rt2800_bbp_write(rt2x00dev, 159, cal);
3068
415e3f2f 3069 /* TX1 IQ Phase */
8756130b 3070 rt2800_bbp_write(rt2x00dev, 158, 0x4b);
415e3f2f
SG		 3071 if (channel <= 14)
3072 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
3073 else if (channel >= 36 && channel <= 64)
3074 cal = rt2x00_eeprom_byte(rt2x00dev,
3075 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
3076 else if (channel >= 100 && channel <= 138)
3077 cal = rt2x00_eeprom_byte(rt2x00dev,
3078 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
3079 else if (channel >= 140 && channel <= 165)
3080 cal = rt2x00_eeprom_byte(rt2x00dev,
3081 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
3082 else
3083 cal = 0;
8756130b
SG		 3084 rt2800_bbp_write(rt2x00dev, 159, cal);
3085
415e3f2f
SG		 3086 /* FIXME: possible RX0, RX1 callibration ? */
3087
8756130b
SG		 3088 /* RF IQ compensation control */
3089 rt2800_bbp_write(rt2x00dev, 158, 0x04);
3090 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
3091 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3092
3093 /* RF IQ imbalance compensation control */
3094 rt2800_bbp_write(rt2x00dev, 158, 0x03);
415e3f2f
SG		 3095 cal = rt2x00_eeprom_byte(rt2x00dev,
3096 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
8756130b
SG		 3097 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3098}
3099
97aa03f1
GJ		 3100static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
3101 unsigned int channel,
3102 char txpower)
3103{
fc739cfe
GJ		 3104 if (rt2x00_rt(rt2x00dev, RT3593))
3105 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
3106
97aa03f1
GJ		 3107 if (channel <= 14)
3108 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
fc739cfe
GJ		 3109
3110 if (rt2x00_rt(rt2x00dev, RT3593))
3111 return clamp_t(char, txpower, MIN_A_TXPOWER_3593,
3112 MAX_A_TXPOWER_3593);
97aa03f1
GJ		 3113 else
3114 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
3115}
3116
f4450616
BZ		 3117static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
3118 struct ieee80211_conf *conf,
3119 struct rf_channel *rf,
3120 struct channel_info *info)
3121{
3122 u32 reg;
3123 unsigned int tx_pin;
a89534ed 3124 u8 bbp, rfcsr;
f4450616 3125
97aa03f1
GJ		 3126 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3127 info->default_power1);
3128 info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3129 info->default_power2);
c0a14369
GJ		 3130 if (rt2x00dev->default_ant.tx_chain_num > 2)
3131 info->default_power3 =
3132 rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3133 info->default_power3);
46323e11 3134
5aa57015
GW		 3135 switch (rt2x00dev->chip.rf) {
3136 case RF2020:
3137 case RF3020:
3138 case RF3021:
3139 case RF3022:
3140 case RF3320:
06855ef4 3141 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
5aa57015
GW		 3142 break;
3143 case RF3052:
872834df 3144 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
5aa57015 3145 break;
f42b0465
GJ		 3146 case RF3053:
3147 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
3148 break;
a89534ed
WH		 3149 case RF3290:
3150 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
3151 break;
03839951
DG		 3152 case RF3322:
3153 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
3154 break;
ccf91bd6 3155 case RF5360:
5aa57015 3156 case RF5370:
2ed71884 3157 case RF5372:
5aa57015 3158 case RF5390:
cff3d1f0 3159 case RF5392:
adde5882 3160 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
5aa57015 3161 break;
8f821098
SG		 3162 case RF5592:
3163 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
3164 break;
5aa57015 3165 default:
06855ef4 3166 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
5aa57015 3167 }
f4450616 3168
a89534ed 3169 if (rt2x00_rf(rt2x00dev, RF3290) ||
03839951 3170 rt2x00_rf(rt2x00dev, RF3322) ||
a89534ed
WH		 3171 rt2x00_rf(rt2x00dev, RF5360) ||
3172 rt2x00_rf(rt2x00dev, RF5370) ||
3173 rt2x00_rf(rt2x00dev, RF5372) ||
3174 rt2x00_rf(rt2x00dev, RF5390) ||
3175 rt2x00_rf(rt2x00dev, RF5392)) {
3176 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3177 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
3178 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
3179 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3180
3181 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
d6d82020 3182 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
a89534ed
WH		 3183 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3184 }
3185
f4450616
BZ		 3186 /*
3187 * Change BBP settings
3188 */
03839951
DG		 3189 if (rt2x00_rt(rt2x00dev, RT3352)) {
3190 rt2800_bbp_write(rt2x00dev, 27, 0x0);
cf193f6d 3191 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
03839951 3192 rt2800_bbp_write(rt2x00dev, 27, 0x20);
cf193f6d 3193 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
f42b0465
GJ		 3194 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
3195 if (rf->channel > 14) {
3196 /* Disable CCK Packet detection on 5GHz */
3197 rt2800_bbp_write(rt2x00dev, 70, 0x00);
3198 } else {
3199 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3200 }
3201
3202 if (conf_is_ht40(conf))
3203 rt2800_bbp_write(rt2x00dev, 105, 0x04);
3204 else
3205 rt2800_bbp_write(rt2x00dev, 105, 0x34);
3206
3207 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3208 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3209 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3210 rt2800_bbp_write(rt2x00dev, 77, 0x98);
03839951
DG		 3211 } else {
3212 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3213 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3214 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3215 rt2800_bbp_write(rt2x00dev, 86, 0);
3216 }
f4450616
BZ		 3217
3218 if (rf->channel <= 14) {
2ed71884 3219 if (!rt2x00_rt(rt2x00dev, RT5390) &&
e6d227b9 3220 !rt2x00_rt(rt2x00dev, RT5392)) {
7dab73b3
ID		 3221 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
3222 &rt2x00dev->cap_flags)) {
adde5882
GJ		 3223 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3224 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3225 } else {
f42b0465
GJ		 3226 if (rt2x00_rt(rt2x00dev, RT3593))
3227 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3228 else
3229 rt2800_bbp_write(rt2x00dev, 82, 0x84);
adde5882
GJ		 3230 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3231 }
f42b0465
GJ		 3232 if (rt2x00_rt(rt2x00dev, RT3593))
3233 rt2800_bbp_write(rt2x00dev, 83, 0x8a);
f4450616 3234 }
f42b0465 3235
f4450616 3236 } else {
872834df
GW		 3237 if (rt2x00_rt(rt2x00dev, RT3572))
3238 rt2800_bbp_write(rt2x00dev, 82, 0x94);
f42b0465
GJ		 3239 else if (rt2x00_rt(rt2x00dev, RT3593))
3240 rt2800_bbp_write(rt2x00dev, 82, 0x82);
872834df
GW		 3241 else
3242 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
f4450616 3243
f42b0465
GJ		 3244 if (rt2x00_rt(rt2x00dev, RT3593))
3245 rt2800_bbp_write(rt2x00dev, 83, 0x9a);
3246
7dab73b3 3247 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
f4450616
BZ		 3248 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3249 else
3250 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3251 }
3252
3253 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 3254 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 3255 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
3256 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
3257 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
3258
872834df
GW		 3259 if (rt2x00_rt(rt2x00dev, RT3572))
3260 rt2800_rfcsr_write(rt2x00dev, 8, 0);
3261
f4450616
BZ		 3262 tx_pin = 0;
3263
bb16d488
GJ		 3264 switch (rt2x00dev->default_ant.tx_chain_num) {
3265 case 3:
3266 /* Turn on tertiary PAs */
3267 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
3268 rf->channel > 14);
3269 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
3270 rf->channel <= 14);
3271 /* fall-through */
3272 case 2:
3273 /* Turn on secondary PAs */
65f31b5e
GW		 3274 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
3275 rf->channel > 14);
3276 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
3277 rf->channel <= 14);
bb16d488
GJ		 3278 /* fall-through */
3279 case 1:
3280 /* Turn on primary PAs */
3281 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
3282 rf->channel > 14);
3283 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
3284 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3285 else
3286 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
3287 rf->channel <= 14);
3288 break;
f4450616
BZ		 3289 }
3290
bb16d488
GJ		 3291 switch (rt2x00dev->default_ant.rx_chain_num) {
3292 case 3:
3293 /* Turn on tertiary LNAs */
3294 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1);
3295 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1);
3296 /* fall-through */
3297 case 2:
3298 /* Turn on secondary LNAs */
f4450616
BZ		 3299 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
3300 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
bb16d488
GJ		 3301 /* fall-through */
3302 case 1:
3303 /* Turn on primary LNAs */
3304 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
3305 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
3306 break;
f4450616
BZ		 3307 }
3308
f4450616
BZ		 3309 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
3310 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
f4450616
BZ		 3311
3312 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3313
872834df
GW		 3314 if (rt2x00_rt(rt2x00dev, RT3572))
3315 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
3316
f42b0465
GJ		 3317 if (rt2x00_rt(rt2x00dev, RT3593)) {
3318 if (rt2x00_is_usb(rt2x00dev)) {
3319 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
3320
3321 /* Band selection. GPIO #8 controls all paths */
3322 rt2x00_set_field32(&reg, GPIO_CTRL_DIR8, 0);
3323 if (rf->channel <= 14)
3324 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 1);
3325 else
3326 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 0);
3327
3328 rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3329 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
3330
3331 /* LNA PE control.
3332 * GPIO #4 controls PE0 and PE1,
3333 * GPIO #7 controls PE2
3334 */
3335 rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
3336 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
3337
3338 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
3339 }
3340
3341 /* AGC init */
3342 if (rf->channel <= 14)
3343 reg = 0x1c + 2 * rt2x00dev->lna_gain;
3344 else
3345 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3346
3347 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3348
3349 usleep_range(1000, 1500);
3350 }
3351
6803141b
SG		 3352 if (rt2x00_rt(rt2x00dev, RT5592)) {
3353 rt2800_bbp_write(rt2x00dev, 195, 141);
3354 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
3355
8ba0ebf3
SG		 3356 /* AGC init */
3357 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain;
3358 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3359
8756130b 3360 rt2800_iq_calibrate(rt2x00dev, rf->channel);
6803141b
SG		 3361 }
3362
f4450616
BZ		 3363 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3364 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
3365 rt2800_bbp_write(rt2x00dev, 4, bbp);
3366
3367 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 3368 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 3369 rt2800_bbp_write(rt2x00dev, 3, bbp);
3370
8d0c9b65 3371 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 3372 if (conf_is_ht40(conf)) {
3373 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
3374 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3375 rt2800_bbp_write(rt2x00dev, 73, 0x16);
3376 } else {
3377 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3378 rt2800_bbp_write(rt2x00dev, 70, 0x08);
3379 rt2800_bbp_write(rt2x00dev, 73, 0x11);
3380 }
3381 }
3382
3383 msleep(1);
977206d7
HS		 3384
3385 /*
3386 * Clear channel statistic counters
3387 */
3388 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
3389 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
3390 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
03839951
DG		 3391
3392 /*
3393 * Clear update flag
3394 */
3395 if (rt2x00_rt(rt2x00dev, RT3352)) {
3396 rt2800_bbp_read(rt2x00dev, 49, &bbp);
3397 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
3398 rt2800_bbp_write(rt2x00dev, 49, bbp);
3399 }
f4450616
BZ		 3400}
3401
9e33a355
HS		 3402static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
3403{
3404 u8 tssi_bounds[9];
3405 u8 current_tssi;
3406 u16 eeprom;
3407 u8 step;
3408 int i;
3409
3410 /*
3411 * Read TSSI boundaries for temperature compensation from
3412 * the EEPROM.
3413 *
3414 * Array idx 0 1 2 3 4 5 6 7 8
3415 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
3416 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
3417 */
3418 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
3e38d3da 3419 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
9e33a355
HS		 3420 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3421 EEPROM_TSSI_BOUND_BG1_MINUS4);
3422 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3423 EEPROM_TSSI_BOUND_BG1_MINUS3);
3424
3e38d3da 3425 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
9e33a355
HS		 3426 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3427 EEPROM_TSSI_BOUND_BG2_MINUS2);
3428 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3429 EEPROM_TSSI_BOUND_BG2_MINUS1);
3430
3e38d3da 3431 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
9e33a355
HS		 3432 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3433 EEPROM_TSSI_BOUND_BG3_REF);
3434 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3435 EEPROM_TSSI_BOUND_BG3_PLUS1);
3436
3e38d3da 3437 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
9e33a355
HS		 3438 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3439 EEPROM_TSSI_BOUND_BG4_PLUS2);
3440 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3441 EEPROM_TSSI_BOUND_BG4_PLUS3);
3442
3e38d3da 3443 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
9e33a355
HS		 3444 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3445 EEPROM_TSSI_BOUND_BG5_PLUS4);
3446
3447 step = rt2x00_get_field16(eeprom,
3448 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
3449 } else {
3e38d3da 3450 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
9e33a355
HS		 3451 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3452 EEPROM_TSSI_BOUND_A1_MINUS4);
3453 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3454 EEPROM_TSSI_BOUND_A1_MINUS3);
3455
3e38d3da 3456 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
9e33a355
HS		 3457 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3458 EEPROM_TSSI_BOUND_A2_MINUS2);
3459 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3460 EEPROM_TSSI_BOUND_A2_MINUS1);
3461
3e38d3da 3462 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
9e33a355
HS		 3463 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3464 EEPROM_TSSI_BOUND_A3_REF);
3465 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3466 EEPROM_TSSI_BOUND_A3_PLUS1);
3467
3e38d3da 3468 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
9e33a355
HS		 3469 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3470 EEPROM_TSSI_BOUND_A4_PLUS2);
3471 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3472 EEPROM_TSSI_BOUND_A4_PLUS3);
3473
3e38d3da 3474 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
9e33a355
HS		 3475 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3476 EEPROM_TSSI_BOUND_A5_PLUS4);
3477
3478 step = rt2x00_get_field16(eeprom,
3479 EEPROM_TSSI_BOUND_A5_AGC_STEP);
3480 }
3481
3482 /*
3483 * Check if temperature compensation is supported.
3484 */
bf7e1abe 3485 if (tssi_bounds[4] == 0xff || step == 0xff)
9e33a355
HS		 3486 return 0;
3487
3488 /*
3489 * Read current TSSI (BBP 49).
3490 */
3491 rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
3492
3493 /*
3494 * Compare TSSI value (BBP49) with the compensation boundaries
3495 * from the EEPROM and increase or decrease tx power.
3496 */
3497 for (i = 0; i <= 3; i++) {
3498 if (current_tssi > tssi_bounds[i])
3499 break;
3500 }
3501
3502 if (i == 4) {
3503 for (i = 8; i >= 5; i--) {
3504 if (current_tssi < tssi_bounds[i])
3505 break;
3506 }
3507 }
3508
3509 return (i - 4) * step;
3510}
3511
e90c54b2
RJH		 3512static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
3513 enum ieee80211_band band)
3514{
3515 u16 eeprom;
3516 u8 comp_en;
3517 u8 comp_type;
75faae8b 3518 int comp_value = 0;
e90c54b2 3519
3e38d3da 3520 rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
e90c54b2 3521
75faae8b
HS		 3522 /*
3523 * HT40 compensation not required.
3524 */
3525 if (eeprom == 0xffff ||
3526 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
e90c54b2
RJH		 3527 return 0;
3528
3529 if (band == IEEE80211_BAND_2GHZ) {
3530 comp_en = rt2x00_get_field16(eeprom,
3531 EEPROM_TXPOWER_DELTA_ENABLE_2G);
3532 if (comp_en) {
3533 comp_type = rt2x00_get_field16(eeprom,
3534 EEPROM_TXPOWER_DELTA_TYPE_2G);
3535 comp_value = rt2x00_get_field16(eeprom,
3536 EEPROM_TXPOWER_DELTA_VALUE_2G);
3537 if (!comp_type)
3538 comp_value = -comp_value;
3539 }
3540 } else {
3541 comp_en = rt2x00_get_field16(eeprom,
3542 EEPROM_TXPOWER_DELTA_ENABLE_5G);
3543 if (comp_en) {
3544 comp_type = rt2x00_get_field16(eeprom,
3545 EEPROM_TXPOWER_DELTA_TYPE_5G);
3546 comp_value = rt2x00_get_field16(eeprom,
3547 EEPROM_TXPOWER_DELTA_VALUE_5G);
3548 if (!comp_type)
3549 comp_value = -comp_value;
3550 }
3551 }
3552
3553 return comp_value;
3554}
3555
1e4cf249
SG		 3556static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
3557 int power_level, int max_power)
3558{
3559 int delta;
3560
3561 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags))
3562 return 0;
3563
3564 /*
3565 * XXX: We don't know the maximum transmit power of our hardware since
3566 * the EEPROM doesn't expose it. We only know that we are calibrated
3567 * to 100% tx power.
3568 *
3569 * Hence, we assume the regulatory limit that cfg80211 calulated for
3570 * the current channel is our maximum and if we are requested to lower
3571 * the value we just reduce our tx power accordingly.
3572 */
3573 delta = power_level - max_power;
3574 return min(delta, 0);
3575}
3576
fa71a160
HS		 3577static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
3578 enum ieee80211_band band, int power_level,
3579 u8 txpower, int delta)
e90c54b2 3580{
e90c54b2
RJH		 3581 u16 eeprom;
3582 u8 criterion;
3583 u8 eirp_txpower;
3584 u8 eirp_txpower_criterion;
3585 u8 reg_limit;
e90c54b2 3586
34542ff5
GJ		 3587 if (rt2x00_rt(rt2x00dev, RT3593))
3588 return min_t(u8, txpower, 0xc);
3589
7dab73b3 3590 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
e90c54b2
RJH		 3591 /*
3592 * Check if eirp txpower exceed txpower_limit.
3593 * We use OFDM 6M as criterion and its eirp txpower
3594 * is stored at EEPROM_EIRP_MAX_TX_POWER.
3595 * .11b data rate need add additional 4dbm
3596 * when calculating eirp txpower.
3597 */
022138ca
GJ		 3598 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3599 1, &eeprom);
d9bceaeb
SG		 3600 criterion = rt2x00_get_field16(eeprom,
3601 EEPROM_TXPOWER_BYRATE_RATE0);
e90c54b2 3602
3e38d3da 3603 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
d9bceaeb 3604 &eeprom);
e90c54b2
RJH		 3605
3606 if (band == IEEE80211_BAND_2GHZ)
3607 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3608 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
3609 else
3610 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3611 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
3612
3613 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2af242e1 3614 (is_rate_b ? 4 : 0) + delta;
e90c54b2
RJH		 3615
3616 reg_limit = (eirp_txpower > power_level) ?
3617 (eirp_txpower - power_level) : 0;
3618 } else
3619 reg_limit = 0;
3620
19f3fa24
SG		 3621 txpower = max(0, txpower + delta - reg_limit);
3622 return min_t(u8, txpower, 0xc);
e90c54b2
RJH		 3623}
3624
34542ff5
GJ		 3625
3626enum {
3627 TX_PWR_CFG_0_IDX,
3628 TX_PWR_CFG_1_IDX,
3629 TX_PWR_CFG_2_IDX,
3630 TX_PWR_CFG_3_IDX,
3631 TX_PWR_CFG_4_IDX,
3632 TX_PWR_CFG_5_IDX,
3633 TX_PWR_CFG_6_IDX,
3634 TX_PWR_CFG_7_IDX,
3635 TX_PWR_CFG_8_IDX,
3636 TX_PWR_CFG_9_IDX,
3637 TX_PWR_CFG_0_EXT_IDX,
3638 TX_PWR_CFG_1_EXT_IDX,
3639 TX_PWR_CFG_2_EXT_IDX,
3640 TX_PWR_CFG_3_EXT_IDX,
3641 TX_PWR_CFG_4_EXT_IDX,
3642 TX_PWR_CFG_IDX_COUNT,
3643};
3644
3645static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
3646 struct ieee80211_channel *chan,
3647 int power_level)
3648{
3649 u8 txpower;
3650 u16 eeprom;
3651 u32 regs[TX_PWR_CFG_IDX_COUNT];
3652 unsigned int offset;
3653 enum ieee80211_band band = chan->band;
3654 int delta;
3655 int i;
3656
3657 memset(regs, '\0', sizeof(regs));
3658
3659 /* TODO: adapt TX power reduction from the rt28xx code */
3660
3661 /* calculate temperature compensation delta */
3662 delta = rt2800_get_gain_calibration_delta(rt2x00dev);
3663
3664 if (band == IEEE80211_BAND_5GHZ)
3665 offset = 16;
3666 else
3667 offset = 0;
3668
3669 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3670 offset += 8;
3671
3672 /* read the next four txpower values */
3673 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3674 offset, &eeprom);
3675
3676 /* CCK 1MBS,2MBS */
3677 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3678 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3679 txpower, delta);
3680 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3681 TX_PWR_CFG_0_CCK1_CH0, txpower);
3682 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3683 TX_PWR_CFG_0_CCK1_CH1, txpower);
3684 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3685 TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
3686
3687 /* CCK 5.5MBS,11MBS */
3688 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3689 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3690 txpower, delta);
3691 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3692 TX_PWR_CFG_0_CCK5_CH0, txpower);
3693 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3694 TX_PWR_CFG_0_CCK5_CH1, txpower);
3695 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3696 TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
3697
3698 /* OFDM 6MBS,9MBS */
3699 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3700 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3701 txpower, delta);
3702 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3703 TX_PWR_CFG_0_OFDM6_CH0, txpower);
3704 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3705 TX_PWR_CFG_0_OFDM6_CH1, txpower);
3706 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3707 TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
3708
3709 /* OFDM 12MBS,18MBS */
3710 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3711 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3712 txpower, delta);
3713 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3714 TX_PWR_CFG_0_OFDM12_CH0, txpower);
3715 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3716 TX_PWR_CFG_0_OFDM12_CH1, txpower);
3717 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3718 TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
3719
3720 /* read the next four txpower values */
3721 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3722 offset + 1, &eeprom);
3723
3724 /* OFDM 24MBS,36MBS */
3725 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3726 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3727 txpower, delta);
3728 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3729 TX_PWR_CFG_1_OFDM24_CH0, txpower);
3730 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3731 TX_PWR_CFG_1_OFDM24_CH1, txpower);
3732 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3733 TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
3734
3735 /* OFDM 48MBS */
3736 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3737 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3738 txpower, delta);
3739 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3740 TX_PWR_CFG_1_OFDM48_CH0, txpower);
3741 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3742 TX_PWR_CFG_1_OFDM48_CH1, txpower);
3743 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3744 TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
3745
3746 /* OFDM 54MBS */
3747 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3748 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3749 txpower, delta);
3750 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3751 TX_PWR_CFG_7_OFDM54_CH0, txpower);
3752 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3753 TX_PWR_CFG_7_OFDM54_CH1, txpower);
3754 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3755 TX_PWR_CFG_7_OFDM54_CH2, txpower);
3756
3757 /* read the next four txpower values */
3758 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3759 offset + 2, &eeprom);
3760
3761 /* MCS 0,1 */
3762 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3763 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3764 txpower, delta);
3765 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3766 TX_PWR_CFG_1_MCS0_CH0, txpower);
3767 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3768 TX_PWR_CFG_1_MCS0_CH1, txpower);
3769 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3770 TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
3771
3772 /* MCS 2,3 */
3773 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3774 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3775 txpower, delta);
3776 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3777 TX_PWR_CFG_1_MCS2_CH0, txpower);
3778 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3779 TX_PWR_CFG_1_MCS2_CH1, txpower);
3780 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3781 TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
3782
3783 /* MCS 4,5 */
3784 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3785 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3786 txpower, delta);
3787 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3788 TX_PWR_CFG_2_MCS4_CH0, txpower);
3789 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3790 TX_PWR_CFG_2_MCS4_CH1, txpower);
3791 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3792 TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
3793
3794 /* MCS 6 */
3795 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3796 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3797 txpower, delta);
3798 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3799 TX_PWR_CFG_2_MCS6_CH0, txpower);
3800 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3801 TX_PWR_CFG_2_MCS6_CH1, txpower);
3802 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3803 TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
3804
3805 /* read the next four txpower values */
3806 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3807 offset + 3, &eeprom);
3808
3809 /* MCS 7 */
3810 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3811 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3812 txpower, delta);
3813 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3814 TX_PWR_CFG_7_MCS7_CH0, txpower);
3815 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3816 TX_PWR_CFG_7_MCS7_CH1, txpower);
3817 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3818 TX_PWR_CFG_7_MCS7_CH2, txpower);
3819
3820 /* MCS 8,9 */
3821 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3822 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3823 txpower, delta);
3824 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3825 TX_PWR_CFG_2_MCS8_CH0, txpower);
3826 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3827 TX_PWR_CFG_2_MCS8_CH1, txpower);
3828 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3829 TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
3830
3831 /* MCS 10,11 */
3832 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3833 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3834 txpower, delta);
3835 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3836 TX_PWR_CFG_2_MCS10_CH0, txpower);
3837 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3838 TX_PWR_CFG_2_MCS10_CH1, txpower);
3839 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3840 TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
3841
3842 /* MCS 12,13 */
3843 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3844 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3845 txpower, delta);
3846 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3847 TX_PWR_CFG_3_MCS12_CH0, txpower);
3848 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3849 TX_PWR_CFG_3_MCS12_CH1, txpower);
3850 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3851 TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
3852
3853 /* read the next four txpower values */
3854 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3855 offset + 4, &eeprom);
3856
3857 /* MCS 14 */
3858 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3859 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3860 txpower, delta);
3861 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3862 TX_PWR_CFG_3_MCS14_CH0, txpower);
3863 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3864 TX_PWR_CFG_3_MCS14_CH1, txpower);
3865 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3866 TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
3867
3868 /* MCS 15 */
3869 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3870 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3871 txpower, delta);
3872 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3873 TX_PWR_CFG_8_MCS15_CH0, txpower);
3874 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3875 TX_PWR_CFG_8_MCS15_CH1, txpower);
3876 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3877 TX_PWR_CFG_8_MCS15_CH2, txpower);
3878
3879 /* MCS 16,17 */
3880 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3881 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3882 txpower, delta);
3883 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3884 TX_PWR_CFG_5_MCS16_CH0, txpower);
3885 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3886 TX_PWR_CFG_5_MCS16_CH1, txpower);
3887 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3888 TX_PWR_CFG_5_MCS16_CH2, txpower);
3889
3890 /* MCS 18,19 */
3891 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3892 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3893 txpower, delta);
3894 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3895 TX_PWR_CFG_5_MCS18_CH0, txpower);
3896 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3897 TX_PWR_CFG_5_MCS18_CH1, txpower);
3898 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3899 TX_PWR_CFG_5_MCS18_CH2, txpower);
3900
3901 /* read the next four txpower values */
3902 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3903 offset + 5, &eeprom);
3904
3905 /* MCS 20,21 */
3906 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3907 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3908 txpower, delta);
3909 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3910 TX_PWR_CFG_6_MCS20_CH0, txpower);
3911 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3912 TX_PWR_CFG_6_MCS20_CH1, txpower);
3913 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3914 TX_PWR_CFG_6_MCS20_CH2, txpower);
3915
3916 /* MCS 22 */
3917 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3918 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3919 txpower, delta);
3920 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3921 TX_PWR_CFG_6_MCS22_CH0, txpower);
3922 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3923 TX_PWR_CFG_6_MCS22_CH1, txpower);
3924 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3925 TX_PWR_CFG_6_MCS22_CH2, txpower);
3926
3927 /* MCS 23 */
3928 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3929 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3930 txpower, delta);
3931 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3932 TX_PWR_CFG_8_MCS23_CH0, txpower);
3933 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3934 TX_PWR_CFG_8_MCS23_CH1, txpower);
3935 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3936 TX_PWR_CFG_8_MCS23_CH2, txpower);
3937
3938 /* read the next four txpower values */
3939 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3940 offset + 6, &eeprom);
3941
3942 /* STBC, MCS 0,1 */
3943 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3944 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3945 txpower, delta);
3946 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3947 TX_PWR_CFG_3_STBC0_CH0, txpower);
3948 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3949 TX_PWR_CFG_3_STBC0_CH1, txpower);
3950 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3951 TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
3952
3953 /* STBC, MCS 2,3 */
3954 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3955 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3956 txpower, delta);
3957 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3958 TX_PWR_CFG_3_STBC2_CH0, txpower);
3959 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3960 TX_PWR_CFG_3_STBC2_CH1, txpower);
3961 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3962 TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
3963
3964 /* STBC, MCS 4,5 */
3965 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3966 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3967 txpower, delta);
3968 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
3969 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
3970 rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
3971 txpower);
3972
3973 /* STBC, MCS 6 */
3974 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3975 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3976 txpower, delta);
3977 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
3978 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
3979 rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
3980 txpower);
3981
3982 /* read the next four txpower values */
3983 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3984 offset + 7, &eeprom);
3985
3986 /* STBC, MCS 7 */
3987 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3988 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3989 txpower, delta);
3990 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
3991 TX_PWR_CFG_9_STBC7_CH0, txpower);
3992 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
3993 TX_PWR_CFG_9_STBC7_CH1, txpower);
3994 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
3995 TX_PWR_CFG_9_STBC7_CH2, txpower);
3996
3997 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
3998 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
3999 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
4000 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
4001 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
4002 rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
4003 rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
4004 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
4005 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
4006 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
4007
4008 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
4009 regs[TX_PWR_CFG_0_EXT_IDX]);
4010 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
4011 regs[TX_PWR_CFG_1_EXT_IDX]);
4012 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
4013 regs[TX_PWR_CFG_2_EXT_IDX]);
4014 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
4015 regs[TX_PWR_CFG_3_EXT_IDX]);
4016 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
4017 regs[TX_PWR_CFG_4_EXT_IDX]);
4018
4019 for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
4020 rt2x00_dbg(rt2x00dev,
4021 "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
4022 (band == IEEE80211_BAND_5GHZ) ? '5' : '2',
4023 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
4024 '4' : '2',
4025 (i > TX_PWR_CFG_9_IDX) ?
4026 (i - TX_PWR_CFG_9_IDX - 1) : i,
4027 (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
4028 (unsigned long) regs[i]);
4029}
4030
7a66205a
SG		 4031/*
4032 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
4033 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
4034 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
4035 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
4036 * Reference per rate transmit power values are located in the EEPROM at
4037 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
4038 * current conditions (i.e. band, bandwidth, temperature, user settings).
4039 */
34542ff5
GJ		 4040static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
4041 struct ieee80211_channel *chan,
4042 int power_level)
f4450616 4043{
cee2c731 4044 u8 txpower, r1;
5e846004 4045 u16 eeprom;
cee2c731
SG		 4046 u32 reg, offset;
4047 int i, is_rate_b, delta, power_ctrl;
146c3b0c 4048 enum ieee80211_band band = chan->band;
2af242e1
HS		 4049
4050 /*
7a66205a
SG		 4051 * Calculate HT40 compensation. For 40MHz we need to add or subtract
4052 * value read from EEPROM (different for 2GHz and for 5GHz).
2af242e1
HS		 4053 */
4054 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
f4450616 4055
9e33a355 4056 /*
7a66205a
SG		 4057 * Calculate temperature compensation. Depends on measurement of current
4058 * TSSI (Transmitter Signal Strength Indication) we know TX power (due
4059 * to temperature or maybe other factors) is smaller or bigger than
4060 * expected. We adjust it, based on TSSI reference and boundaries values
4061 * provided in EEPROM.
9e33a355
HS		 4062 */
4063 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
f4450616 4064
1e4cf249 4065 /*
7a66205a
SG		 4066 * Decrease power according to user settings, on devices with unknown
4067 * maximum tx power. For other devices we take user power_level into
4068 * consideration on rt2800_compensate_txpower().
1e4cf249
SG		 4069 */
4070 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
4071 chan->max_power);
4072
5e846004 4073 /*
cee2c731
SG		 4074 * BBP_R1 controls TX power for all rates, it allow to set the following
4075 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
4076 *
4077 * TODO: we do not use +6 dBm option to do not increase power beyond
4078 * regulatory limit, however this could be utilized for devices with
4079 * CAPABILITY_POWER_LIMIT.
8c8d2017
SG		 4080 *
4081 * TODO: add different temperature compensation code for RT3290 & RT5390
4082 * to allow to use BBP_R1 for those chips.
4083 */
4084 if (!rt2x00_rt(rt2x00dev, RT3290) &&
4085 !rt2x00_rt(rt2x00dev, RT5390)) {
4086 rt2800_bbp_read(rt2x00dev, 1, &r1);
4087 if (delta <= -12) {
4088 power_ctrl = 2;
4089 delta += 12;
4090 } else if (delta <= -6) {
4091 power_ctrl = 1;
4092 delta += 6;
4093 } else {
4094 power_ctrl = 0;
4095 }
4096 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
4097 rt2800_bbp_write(rt2x00dev, 1, r1);
cee2c731 4098 }
8c8d2017 4099
5e846004
HS		 4100 offset = TX_PWR_CFG_0;
4101
4102 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
4103 /* just to be safe */
4104 if (offset > TX_PWR_CFG_4)
4105 break;
4106
4107 rt2800_register_read(rt2x00dev, offset, &reg);
4108
4109 /* read the next four txpower values */
022138ca
GJ		 4110 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4111 i, &eeprom);
5e846004 4112
e90c54b2
RJH		 4113 is_rate_b = i ? 0 : 1;
4114 /*
4115 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
5e846004 4116 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
e90c54b2
RJH		 4117 * TX_PWR_CFG_4: unknown
4118 */
5e846004
HS		 4119 txpower = rt2x00_get_field16(eeprom,
4120 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 4121 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4122 power_level, txpower, delta);
e90c54b2 4123 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
5e846004 4124
e90c54b2
RJH		 4125 /*
4126 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
5e846004 4127 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
e90c54b2
RJH		 4128 * TX_PWR_CFG_4: unknown
4129 */
5e846004
HS		 4130 txpower = rt2x00_get_field16(eeprom,
4131 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 4132 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4133 power_level, txpower, delta);
e90c54b2 4134 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
5e846004 4135
e90c54b2
RJH		 4136 /*
4137 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
5e846004 4138 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
e90c54b2
RJH		 4139 * TX_PWR_CFG_4: unknown
4140 */
5e846004
HS		 4141 txpower = rt2x00_get_field16(eeprom,
4142 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 4143 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4144 power_level, txpower, delta);
e90c54b2 4145 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
5e846004 4146
e90c54b2
RJH		 4147 /*
4148 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
5e846004 4149 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
e90c54b2
RJH		 4150 * TX_PWR_CFG_4: unknown
4151 */
5e846004
HS		 4152 txpower = rt2x00_get_field16(eeprom,
4153 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 4154 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4155 power_level, txpower, delta);
e90c54b2 4156 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
5e846004
HS		 4157
4158 /* read the next four txpower values */
022138ca
GJ		 4159 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4160 i + 1, &eeprom);
5e846004 4161
e90c54b2
RJH		 4162 is_rate_b = 0;
4163 /*
4164 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
5e846004 4165 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4166 * TX_PWR_CFG_4: unknown
4167 */
5e846004
HS		 4168 txpower = rt2x00_get_field16(eeprom,
4169 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 4170 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4171 power_level, txpower, delta);
e90c54b2 4172 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
5e846004 4173
e90c54b2
RJH		 4174 /*
4175 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
5e846004 4176 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4177 * TX_PWR_CFG_4: unknown
4178 */
5e846004
HS		 4179 txpower = rt2x00_get_field16(eeprom,
4180 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 4181 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4182 power_level, txpower, delta);
e90c54b2 4183 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
5e846004 4184
e90c54b2
RJH		 4185 /*
4186 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
5e846004 4187 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4188 * TX_PWR_CFG_4: unknown
4189 */
5e846004
HS		 4190 txpower = rt2x00_get_field16(eeprom,
4191 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 4192 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4193 power_level, txpower, delta);
e90c54b2 4194 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
5e846004 4195
e90c54b2
RJH		 4196 /*
4197 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
5e846004 4198 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4199 * TX_PWR_CFG_4: unknown
4200 */
5e846004
HS		 4201 txpower = rt2x00_get_field16(eeprom,
4202 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 4203 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4204 power_level, txpower, delta);
e90c54b2 4205 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
5e846004
HS		 4206
4207 rt2800_register_write(rt2x00dev, offset, reg);
4208
4209 /* next TX_PWR_CFG register */
4210 offset += 4;
4211 }
f4450616
BZ		 4212}
4213
34542ff5
GJ		 4214static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
4215 struct ieee80211_channel *chan,
4216 int power_level)
4217{
4218 if (rt2x00_rt(rt2x00dev, RT3593))
4219 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
4220 else
4221 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
4222}
4223
9e33a355
HS		 4224void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
4225{
675a0b04 4226 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
9e33a355
HS		 4227 rt2x00dev->tx_power);
4228}
4229EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
4230
2e9c43dd
JL		 4231void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
4232{
4233 u32 tx_pin;
4234 u8 rfcsr;
4235
4236 /*
4237 * A voltage-controlled oscillator(VCO) is an electronic oscillator
4238 * designed to be controlled in oscillation frequency by a voltage
4239 * input. Maybe the temperature will affect the frequency of
4240 * oscillation to be shifted. The VCO calibration will be called
4241 * periodically to adjust the frequency to be precision.
4242 */
4243
4244 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4245 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
4246 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4247
4248 switch (rt2x00dev->chip.rf) {
4249 case RF2020:
4250 case RF3020:
4251 case RF3021:
4252 case RF3022:
4253 case RF3320:
4254 case RF3052:
4255 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
4256 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
4257 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
4258 break;
1095df07 4259 case RF3053:
a89534ed 4260 case RF3290:
ccf91bd6 4261 case RF5360:
2e9c43dd
JL		 4262 case RF5370:
4263 case RF5372:
4264 case RF5390:
cff3d1f0 4265 case RF5392:
2e9c43dd 4266 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
d6d82020 4267 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2e9c43dd
JL		 4268 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
4269 break;
4270 default:
4271 return;
4272 }
4273
4274 mdelay(1);
4275
4276 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4277 if (rt2x00dev->rf_channel <= 14) {
4278 switch (rt2x00dev->default_ant.tx_chain_num) {
4279 case 3:
4280 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
4281 /* fall through */
4282 case 2:
4283 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
4284 /* fall through */
4285 case 1:
4286 default:
4287 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
4288 break;
4289 }
4290 } else {
4291 switch (rt2x00dev->default_ant.tx_chain_num) {
4292 case 3:
4293 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
4294 /* fall through */
4295 case 2:
4296 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
4297 /* fall through */
4298 case 1:
4299 default:
4300 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
4301 break;
4302 }
4303 }
4304 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4305
4306}
4307EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
4308
f4450616
BZ		 4309static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
4310 struct rt2x00lib_conf *libconf)
4311{
4312 u32 reg;
4313
4314 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4315 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
4316 libconf->conf->short_frame_max_tx_count);
4317 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
4318 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 4319 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4320}
4321
4322static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
4323 struct rt2x00lib_conf *libconf)
4324{
4325 enum dev_state state =
4326 (libconf->conf->flags & IEEE80211_CONF_PS) ?
4327 STATE_SLEEP : STATE_AWAKE;
4328 u32 reg;
4329
4330 if (state == STATE_SLEEP) {
4331 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
4332
4333 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
4334 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
4335 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
4336 libconf->conf->listen_interval - 1);
4337 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
4338 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
4339
4340 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
4341 } else {
f4450616
BZ		 4342 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
4343 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
4344 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
4345 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
4346 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 4347
4348 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 4349 }
4350}
4351
4352void rt2800_config(struct rt2x00_dev *rt2x00dev,
4353 struct rt2x00lib_conf *libconf,
4354 const unsigned int flags)
4355{
4356 /* Always recalculate LNA gain before changing configuration */
4357 rt2800_config_lna_gain(rt2x00dev, libconf);
4358
e90c54b2 4359 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
f4450616
BZ		 4360 rt2800_config_channel(rt2x00dev, libconf->conf,
4361 &libconf->rf, &libconf->channel);
675a0b04 4362 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
9e33a355 4363 libconf->conf->power_level);
e90c54b2 4364 }
f4450616 4365 if (flags & IEEE80211_CONF_CHANGE_POWER)
675a0b04 4366 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
9e33a355 4367 libconf->conf->power_level);
f4450616
BZ		 4368 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
4369 rt2800_config_retry_limit(rt2x00dev, libconf);
4370 if (flags & IEEE80211_CONF_CHANGE_PS)
4371 rt2800_config_ps(rt2x00dev, libconf);
4372}
4373EXPORT_SYMBOL_GPL(rt2800_config);
4374
4375/*
4376 * Link tuning
4377 */
4378void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
4379{
4380 u32 reg;
4381
4382 /*
4383 * Update FCS error count from register.
4384 */
4385 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
4386 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
4387}
4388EXPORT_SYMBOL_GPL(rt2800_link_stats);
4389
4390static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
4391{
8c6728b0
GW		 4392 u8 vgc;
4393
f4450616 4394 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
d5385bfc 4395 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 4396 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 4397 rt2x00_rt(rt2x00dev, RT3090) ||
a89534ed 4398 rt2x00_rt(rt2x00dev, RT3290) ||
adde5882 4399 rt2x00_rt(rt2x00dev, RT3390) ||
d961e447 4400 rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884 4401 rt2x00_rt(rt2x00dev, RT5390) ||
3d81535e
SG		 4402 rt2x00_rt(rt2x00dev, RT5392) ||
4403 rt2x00_rt(rt2x00dev, RT5592))
8c6728b0
GW		 4404 vgc = 0x1c + (2 * rt2x00dev->lna_gain);
4405 else
4406 vgc = 0x2e + rt2x00dev->lna_gain;
4407 } else { /* 5GHZ band */
d961e447
GW		 4408 if (rt2x00_rt(rt2x00dev, RT3572))
4409 vgc = 0x22 + (rt2x00dev->lna_gain * 5) / 3;
3d81535e
SG		 4410 else if (rt2x00_rt(rt2x00dev, RT5592))
4411 vgc = 0x24 + (2 * rt2x00dev->lna_gain);
d961e447
GW		 4412 else {
4413 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4414 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
4415 else
4416 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
4417 }
f4450616
BZ		 4418 }
4419
8c6728b0 4420 return vgc;
f4450616
BZ		 4421}
4422
4423static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
4424 struct link_qual *qual, u8 vgc_level)
4425{
4426 if (qual->vgc_level != vgc_level) {
3d81535e
SG		 4427 if (rt2x00_rt(rt2x00dev, RT5592)) {
4428 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
4429 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
4430 } else
4431 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
f4450616
BZ		 4432 qual->vgc_level = vgc_level;
4433 qual->vgc_level_reg = vgc_level;
4434 }
4435}
4436
4437void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
4438{
4439 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
4440}
4441EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
4442
4443void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
4444 const u32 count)
4445{
3d81535e
SG		 4446 u8 vgc;
4447
8d0c9b65 4448 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616 4449 return;
f4450616 4450 /*
3d81535e
SG		 4451 * When RSSI is better then -80 increase VGC level with 0x10, except
4452 * for rt5592 chip.
f4450616 4453 */
3d81535e
SG		 4454
4455 vgc = rt2800_get_default_vgc(rt2x00dev);
4456
4457 if (rt2x00_rt(rt2x00dev, RT5592) && qual->rssi > -65)
4458 vgc += 0x20;
4459 else if (qual->rssi > -80)
4460 vgc += 0x10;
4461
4462 rt2800_set_vgc(rt2x00dev, qual, vgc);
f4450616
BZ		 4463}
4464EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 4465
4466/*
4467 * Initialization functions.
4468 */
b9a07ae9 4469static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 4470{
4471 u32 reg;
d5385bfc 4472 u16 eeprom;
fcf51541 4473 unsigned int i;
e3a896b9 4474 int ret;
fcf51541 4475
f7b395e9 4476 rt2800_disable_wpdma(rt2x00dev);
a9dce149 4477
e3a896b9
GW		 4478 ret = rt2800_drv_init_registers(rt2x00dev);
4479 if (ret)
4480 return ret;
fcf51541
BZ		 4481
4482 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
634b8059
GJ		 4483 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0,
4484 rt2800_get_beacon_offset(rt2x00dev, 0));
4485 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1,
4486 rt2800_get_beacon_offset(rt2x00dev, 1));
4487 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2,
4488 rt2800_get_beacon_offset(rt2x00dev, 2));
4489 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3,
4490 rt2800_get_beacon_offset(rt2x00dev, 3));
fcf51541
BZ		 4491 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
4492
4493 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
634b8059
GJ		 4494 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4,
4495 rt2800_get_beacon_offset(rt2x00dev, 4));
4496 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5,
4497 rt2800_get_beacon_offset(rt2x00dev, 5));
4498 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6,
4499 rt2800_get_beacon_offset(rt2x00dev, 6));
4500 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7,
4501 rt2800_get_beacon_offset(rt2x00dev, 7));
fcf51541
BZ		 4502 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
4503
4504 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
4505 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
4506
4507 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
4508
4509 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
8544df32 4510 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
fcf51541
BZ		 4511 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
4512 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
4513 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
4514 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
4515 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
4516 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
4517
a9dce149
GW		 4518 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
4519
4520 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
4521 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
4522 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
4523 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
4524
a89534ed
WH		 4525 if (rt2x00_rt(rt2x00dev, RT3290)) {
4526 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
4527 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
4528 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
4529 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
4530 }
4531
4532 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
4533 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
4534 rt2x00_set_field32(&reg, LDO0_EN, 1);
4535 rt2x00_set_field32(&reg, LDO_BGSEL, 3);
4536 rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
4537 }
4538
4539 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
4540 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
4541 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
4542 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
4543 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
4544
4545 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
4546 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
4547 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
4548
4549 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
4550 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
4551 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
4552 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
4553 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
4554 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
4555
4556 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
4557 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
4558 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
4559 }
4560
64522957 4561 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 4562 rt2x00_rt(rt2x00dev, RT3090) ||
a89534ed 4563 rt2x00_rt(rt2x00dev, RT3290) ||
cc78e904 4564 rt2x00_rt(rt2x00dev, RT3390)) {
a89534ed
WH		 4565
4566 if (rt2x00_rt(rt2x00dev, RT3290))
4567 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4568 0x00000404);
4569 else
4570 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4571 0x00000400);
4572
fcf51541 4573 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 4574 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 4575 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4576 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3e38d3da
GJ		 4577 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4578 &eeprom);
38c8a566 4579 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 4580 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4581 0x0000002c);
4582 else
4583 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4584 0x0000000f);
4585 } else {
4586 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4587 }
d5385bfc 4588 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 4589 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 4590
4591 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4592 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4593 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
4594 } else {
4595 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4596 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4597 }
c295a81d
HS		 4598 } else if (rt2800_is_305x_soc(rt2x00dev)) {
4599 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4600 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
961636ba 4601 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
03839951
DG		 4602 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
4603 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4604 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4605 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
872834df
GW		 4606 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
4607 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4608 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1706d15d
GJ		 4609 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
4610 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4611 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4612 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
4613 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4614 &eeprom);
4615 if (rt2x00_get_field16(eeprom,
4616 EEPROM_NIC_CONF1_DAC_TEST))
4617 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4618 0x0000001f);
4619 else
4620 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4621 0x0000000f);
4622 } else {
4623 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4624 0x00000000);
4625 }
2ed71884 4626 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
7641328d
SG		 4627 rt2x00_rt(rt2x00dev, RT5392) ||
4628 rt2x00_rt(rt2x00dev, RT5592)) {
adde5882
GJ		 4629 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
4630 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4631 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
fcf51541
BZ		 4632 } else {
4633 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
4634 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4635 }
4636
4637 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
4638 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
4639 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
4640 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
4641 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
4642 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
4643 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
4644 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
4645 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
4646 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
4647
4648 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
4649 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 4650 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 4651 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
4652 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
4653
4654 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
4655 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 4656 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 4657 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 4658 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 4659 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
4660 else
4661 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
4662 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
4663 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
4664 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
4665
a9dce149
GW		 4666 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
4667 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
4668 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
4669 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
4670 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
4671 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
4672 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
4673 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
4674 rt2800_register_write(rt2x00dev, LED_CFG, reg);
4675
fcf51541
BZ		 4676 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
4677
a9dce149
GW		 4678 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4679 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
4680 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
4681 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
4682 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
4683 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
4684 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
4685 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4686
fcf51541
BZ		 4687 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
4688 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 4689 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 4690 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
4691 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 4692 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 4693 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
4694 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
4695 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
4696
4697 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 4698 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541 4699 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4700 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4701 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4702 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4703 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 4704 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 4705 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 4706 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4707 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 4708 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4709
4710 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 4711 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541 4712 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4713 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4714 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4715 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4716 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 4717 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 4718 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 4719 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4720 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 4721 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4722
4723 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4724 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
4725 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4726 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4727 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4728 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4729 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4730 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4731 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4732 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 4733 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 4734 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4735
4736 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4737 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
d13a97f0 4738 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4739 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4740 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4741 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4742 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4743 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4744 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4745 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 4746 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 4747 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4748
4749 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4750 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
4751 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4752 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4753 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4754 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4755 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4756 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4757 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4758 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 4759 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 4760 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4761
4762 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4763 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
4764 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4765 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4766 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4767 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4768 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4769 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4770 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4771 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 4772 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 4773 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4774
cea90e55 4775 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 4776 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
4777
4778 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
4779 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
4780 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
4781 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
4782 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
4783 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
4784 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
4785 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
4786 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
4787 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
4788 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
4789 }
4790
961621ab
HS		 4791 /*
4792 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
4793 * although it is reserved.
4794 */
4795 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
4796 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
4797 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
4798 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
4799 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
4800 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
4801 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
4802 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
4803 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
4804 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
4805 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
4806 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
4807
7641328d
SG		 4808 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
4809 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
fcf51541
BZ		 4810
4811 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4812 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
4813 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
4814 IEEE80211_MAX_RTS_THRESHOLD);
4815 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
4816 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4817
4818 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 4819
a21c2ab4
HS		 4820 /*
4821 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
4822 * time should be set to 16. However, the original Ralink driver uses
4823 * 16 for both and indeed using a value of 10 for CCK SIFS results in
4824 * connection problems with 11g + CTS protection. Hence, use the same
4825 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
4826 */
a9dce149 4827 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 4828 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
4829 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 4830 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
4831 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
4832 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
4833 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
4834
fcf51541
BZ		 4835 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
4836
4837 /*
4838 * ASIC will keep garbage value after boot, clear encryption keys.
4839 */
4840 for (i = 0; i < 4; i++)
4841 rt2800_register_write(rt2x00dev,
4842 SHARED_KEY_MODE_ENTRY(i), 0);
4843
4844 for (i = 0; i < 256; i++) {
d7d259d3
HS		 4845 rt2800_config_wcid(rt2x00dev, NULL, i);
4846 rt2800_delete_wcid_attr(rt2x00dev, i);
fcf51541
BZ		 4847 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
4848 }
4849
4850 /*
4851 * Clear all beacons
fcf51541 4852 */
77f7c0f3
GJ		 4853 for (i = 0; i < 8; i++)
4854 rt2800_clear_beacon_register(rt2x00dev, i);
fcf51541 4855
cea90e55 4856 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 4857 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4858 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
4859 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
c6fcc0e5
RJH		 4860 } else if (rt2x00_is_pcie(rt2x00dev)) {
4861 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4862 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
4863 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 4864 }
4865
4866 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
4867 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
4868 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
4869 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
4870 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
4871 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
4872 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
4873 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
4874 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
4875 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
4876
4877 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
4878 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
4879 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
4880 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
4881 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
4882 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
4883 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
4884 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
4885 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
4886 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
4887
4888 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
4889 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
4890 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
4891 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
4892 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
4893 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
4894 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
4895 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
4896 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
4897 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
4898
4899 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
4900 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
4901 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
4902 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
4903 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
4904 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
4905
47ee3eb1
HS		 4906 /*
4907 * Do not force the BA window size, we use the TXWI to set it
4908 */
4909 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
4910 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
4911 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
4912 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
4913
fcf51541
BZ		 4914 /*
4915 * We must clear the error counters.
4916 * These registers are cleared on read,
4917 * so we may pass a useless variable to store the value.
4918 */
4919 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
4920 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
4921 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
4922 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
4923 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
4924 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
4925
9f926fb5
HS		 4926 /*
4927 * Setup leadtime for pre tbtt interrupt to 6ms
4928 */
4929 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
4930 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
4931 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
4932
977206d7
HS		 4933 /*
4934 * Set up channel statistics timer
4935 */
4936 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
4937 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
4938 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
4939 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
4940 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
4941 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
4942 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
4943
fcf51541
BZ		 4944 return 0;
4945}
fcf51541
BZ		 4946
4947static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
4948{
4949 unsigned int i;
4950 u32 reg;
4951
4952 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
4953 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
4954 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
4955 return 0;
4956
4957 udelay(REGISTER_BUSY_DELAY);
4958 }
4959
ec9c4989 4960 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
fcf51541
BZ		 4961 return -EACCES;
4962}
4963
4964static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
4965{
4966 unsigned int i;
4967 u8 value;
4968
4969 /*
4970 * BBP was enabled after firmware was loaded,
4971 * but we need to reactivate it now.
4972 */
4973 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
4974 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
4975 msleep(1);
4976
4977 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
4978 rt2800_bbp_read(rt2x00dev, 0, &value);
4979 if ((value != 0xff) && (value != 0x00))
4980 return 0;
4981 udelay(REGISTER_BUSY_DELAY);
4982 }
4983
ec9c4989 4984 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
fcf51541
BZ		 4985 return -EACCES;
4986}
4987
a7bbbe5c
SG		 4988static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
4989{
4990 u8 value;
4991
4992 rt2800_bbp_read(rt2x00dev, 4, &value);
4993 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
4994 rt2800_bbp_write(rt2x00dev, 4, value);
4995}
4996
c2675487
SG		 4997static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
4998{
4999 rt2800_bbp_write(rt2x00dev, 142, 1);
5000 rt2800_bbp_write(rt2x00dev, 143, 57);
5001}
5002
a7bbbe5c
SG		 5003static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
5004{
5005 const u8 glrt_table[] = {
5006 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
5007 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
5008 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
5009 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
5010 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
5011 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
5012 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
5013 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
5014 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */
5015 };
5016 int i;
5017
5018 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
5019 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
5020 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
5021 }
5022};
5023
624708b8 5024static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
a4969d0d
SG		 5025{
5026 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5027 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5028 rt2800_bbp_write(rt2x00dev, 68, 0x0B);
5029 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5030 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5031 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5032 rt2800_bbp_write(rt2x00dev, 81, 0x37);
5033 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5034 rt2800_bbp_write(rt2x00dev, 83, 0x6A);
5035 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5036 rt2800_bbp_write(rt2x00dev, 86, 0x00);
5037 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5038 rt2800_bbp_write(rt2x00dev, 92, 0x00);
5039 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5040 rt2800_bbp_write(rt2x00dev, 105, 0x05);
5041 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5042}
5043
5df1ff3a
SG		 5044static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
5045{
5046 u16 eeprom;
5047 u8 value;
5048
5049 rt2800_bbp_read(rt2x00dev, 138, &value);
3e38d3da 5050 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5df1ff3a
SG		 5051 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5052 value |= 0x20;
5053 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5054 value &= ~0x02;
5055 rt2800_bbp_write(rt2x00dev, 138, value);
5056}
5057
dae62957
SG		 5058static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
5059{
b2f8e0bd 5060 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 5061
5062 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5063 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5064
5065 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5066 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 5067
5068 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5069
5070 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5071 rt2800_bbp_write(rt2x00dev, 80, 0x08);
fa1e3424
SG		 5072
5073 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5074
5075 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5076
5077 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5078
5079 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5080
5081 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5082
5083 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5084
5085 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
49d61118
SG		 5086
5087 rt2800_bbp_write(rt2x00dev, 105, 0x01);
f867085e
SG		 5088
5089 rt2800_bbp_write(rt2x00dev, 106, 0x35);
dae62957
SG		 5090}
5091
39ab3e8b
SG		 5092static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
5093{
e379de12
SG		 5094 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5095 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5096
5097 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
5098 rt2800_bbp_write(rt2x00dev, 69, 0x16);
5099 rt2800_bbp_write(rt2x00dev, 73, 0x12);
5100 } else {
5101 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5102 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5103 }
8d97be38
SG		 5104
5105 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5106
5107 rt2800_bbp_write(rt2x00dev, 81, 0x37);
fa1e3424
SG		 5108
5109 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5110
5111 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5112
5113 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
5114 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5115 else
5116 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5117
5118 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5119
5120 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5121
5122 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5123
5124 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 5125
5126 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 5127
5128 rt2800_bbp_write(rt2x00dev, 106, 0x35);
39ab3e8b
SG		 5129}
5130
5131static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
5132{
e379de12
SG		 5133 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5134 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5135
5136 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5137 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 5138
5139 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5140
5141 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5142 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5143 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5144
5145 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5146
5147 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5148
5149 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5150
5151 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5152
5153 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5154
5155 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5156
5157 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
5158 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
5159 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
5160 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5161 else
5162 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 5163
5164 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 5165
5166 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 5167
5168 if (rt2x00_rt(rt2x00dev, RT3071) ||
5169 rt2x00_rt(rt2x00dev, RT3090))
5170 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 5171}
5172
5173static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
5174{
6addb24e
SG		 5175 u8 value;
5176
c3223573 5177 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
b2f8e0bd
SG		 5178
5179 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 5180
5181 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5182 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 5183
5184 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142
SG		 5185
5186 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5187 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5188 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5189 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5190
5191 rt2800_bbp_write(rt2x00dev, 77, 0x58);
8d97be38
SG		 5192
5193 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5194
5195 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
5196 rt2800_bbp_write(rt2x00dev, 79, 0x18);
5197 rt2800_bbp_write(rt2x00dev, 80, 0x09);
5198 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5199
5200 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5201
5202 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3c20a122
SG		 5203
5204 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
aef9f38b
SG		 5205
5206 rt2800_bbp_write(rt2x00dev, 86, 0x38);
7af98742
SG		 5207
5208 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5209
5210 rt2800_bbp_write(rt2x00dev, 92, 0x02);
672d1188
SG		 5211
5212 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 5213
5214 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118
SG		 5215
5216 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
f867085e
SG		 5217
5218 rt2800_bbp_write(rt2x00dev, 106, 0x03);
f2b6777c
SG		 5219
5220 rt2800_bbp_write(rt2x00dev, 128, 0x12);
6addb24e
SG		 5221
5222 rt2800_bbp_write(rt2x00dev, 67, 0x24);
5223 rt2800_bbp_write(rt2x00dev, 143, 0x04);
5224 rt2800_bbp_write(rt2x00dev, 142, 0x99);
5225 rt2800_bbp_write(rt2x00dev, 150, 0x30);
5226 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
5227 rt2800_bbp_write(rt2x00dev, 152, 0x20);
5228 rt2800_bbp_write(rt2x00dev, 153, 0x34);
5229 rt2800_bbp_write(rt2x00dev, 154, 0x40);
5230 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
5231 rt2800_bbp_write(rt2x00dev, 253, 0x04);
5232
5233 rt2800_bbp_read(rt2x00dev, 47, &value);
5234 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
5235 rt2800_bbp_write(rt2x00dev, 47, value);
5236
5237 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
5238 rt2800_bbp_read(rt2x00dev, 3, &value);
5239 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
5240 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
5241 rt2800_bbp_write(rt2x00dev, 3, value);
39ab3e8b
SG		 5242}
5243
5244static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
5245{
29f3a58b
SG		 5246 rt2800_bbp_write(rt2x00dev, 3, 0x00);
5247 rt2800_bbp_write(rt2x00dev, 4, 0x50);
b2f8e0bd
SG		 5248
5249 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3420f797
SG		 5250
5251 rt2800_bbp_write(rt2x00dev, 47, 0x48);
e379de12
SG		 5252
5253 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5254 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 5255
5256 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142
SG		 5257
5258 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5259 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5260 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5261 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5262
5263 rt2800_bbp_write(rt2x00dev, 77, 0x59);
8d97be38
SG		 5264
5265 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5266
5267 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5268 rt2800_bbp_write(rt2x00dev, 80, 0x08);
5269 rt2800_bbp_write(rt2x00dev, 81, 0x37);
fa1e3424
SG		 5270
5271 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5272
5273 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5274
5275 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5276
5277 rt2800_bbp_write(rt2x00dev, 86, 0x38);
9400fa87
SG		 5278
5279 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7af98742
SG		 5280
5281 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5282
5283 rt2800_bbp_write(rt2x00dev, 92, 0x02);
672d1188
SG		 5284
5285 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 5286
5287 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118
SG		 5288
5289 rt2800_bbp_write(rt2x00dev, 105, 0x34);
f867085e
SG		 5290
5291 rt2800_bbp_write(rt2x00dev, 106, 0x05);
46b90d32
SG		 5292
5293 rt2800_bbp_write(rt2x00dev, 120, 0x50);
b7feb9ba
SG		 5294
5295 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
c2da5273
SG		 5296
5297 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
5298 /* Set ITxBF timeout to 0x9c40=1000msec */
5299 rt2800_bbp_write(rt2x00dev, 179, 0x02);
5300 rt2800_bbp_write(rt2x00dev, 180, 0x00);
5301 rt2800_bbp_write(rt2x00dev, 182, 0x40);
5302 rt2800_bbp_write(rt2x00dev, 180, 0x01);
5303 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
5304 rt2800_bbp_write(rt2x00dev, 179, 0x00);
5305 /* Reprogram the inband interface to put right values in RXWI */
5306 rt2800_bbp_write(rt2x00dev, 142, 0x04);
5307 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
5308 rt2800_bbp_write(rt2x00dev, 142, 0x06);
5309 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
5310 rt2800_bbp_write(rt2x00dev, 142, 0x07);
5311 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
5312 rt2800_bbp_write(rt2x00dev, 142, 0x08);
5313 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
5314
5315 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
39ab3e8b
SG		 5316}
5317
5318static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
5319{
e379de12
SG		 5320 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5321 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5322
5323 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5324 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 5325
5326 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5327
5328 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5329 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5330 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5331
5332 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5333
5334 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5335
5336 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5337
5338 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5339
5340 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5341
5342 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5343
5344 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
5345 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5346 else
5347 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 5348
5349 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 5350
5351 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 5352
5353 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 5354}
5355
5356static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
5357{
b2f8e0bd 5358 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 5359
5360 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5361 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5362
5363 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5364 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 5365
5366 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5367
5368 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5369 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5370 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5371
5372 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5373
5374 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5375
5376 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5377
5378 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5379
5380 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5381
5382 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5383
5384 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
49d61118
SG		 5385
5386 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 5387
5388 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 5389
5390 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 5391}
5392
b189a181
GJ		 5393static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
5394{
5395 rt2800_init_bbp_early(rt2x00dev);
5396
5397 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5398 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5399 rt2800_bbp_write(rt2x00dev, 81, 0x33);
5400 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
5401
5402 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5403
5404 /* Enable DC filter */
5405 if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
5406 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5407}
5408
39ab3e8b
SG		 5409static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
5410{
32ef8f49
SG		 5411 int ant, div_mode;
5412 u16 eeprom;
5413 u8 value;
5414
c3223573 5415 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
b2f8e0bd
SG		 5416
5417 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 5418
5419 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5420 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 5421
5422 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142
SG		 5423
5424 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5425 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5426 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5427 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5428
5429 rt2800_bbp_write(rt2x00dev, 77, 0x59);
8d97be38
SG		 5430
5431 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5432
5433 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5434 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5435 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5436
5437 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5438
5439 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3c20a122
SG		 5440
5441 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
aef9f38b
SG		 5442
5443 rt2800_bbp_write(rt2x00dev, 86, 0x38);
9400fa87
SG		 5444
5445 if (rt2x00_rt(rt2x00dev, RT5392))
5446 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7af98742
SG		 5447
5448 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5449
5450 rt2800_bbp_write(rt2x00dev, 92, 0x02);
90fed535
SG		 5451
5452 if (rt2x00_rt(rt2x00dev, RT5392)) {
5453 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5454 rt2800_bbp_write(rt2x00dev, 98, 0x12);
5455 }
672d1188
SG		 5456
5457 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 5458
5459 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118
SG		 5460
5461 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
f867085e
SG		 5462
5463 if (rt2x00_rt(rt2x00dev, RT5390))
5464 rt2800_bbp_write(rt2x00dev, 106, 0x03);
5465 else if (rt2x00_rt(rt2x00dev, RT5392))
5466 rt2800_bbp_write(rt2x00dev, 106, 0x12);
5467 else
5468 WARN_ON(1);
f2b6777c
SG		 5469
5470 rt2800_bbp_write(rt2x00dev, 128, 0x12);
72917140
SG		 5471
5472 if (rt2x00_rt(rt2x00dev, RT5392)) {
5473 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
5474 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
5475 }
5df1ff3a
SG		 5476
5477 rt2800_disable_unused_dac_adc(rt2x00dev);
32ef8f49 5478
3e38d3da 5479 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
32ef8f49
SG		 5480 div_mode = rt2x00_get_field16(eeprom,
5481 EEPROM_NIC_CONF1_ANT_DIVERSITY);
5482 ant = (div_mode == 3) ? 1 : 0;
5483
5484 /* check if this is a Bluetooth combo card */
5485 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
5486 u32 reg;
5487
5488 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
5489 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
5490 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
5491 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
5492 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
5493 if (ant == 0)
5494 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
5495 else if (ant == 1)
5496 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
5497 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
5498 }
5499
5500 /* This chip has hardware antenna diversity*/
5501 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
5502 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
5503 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
5504 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
5505 }
5506
5507 rt2800_bbp_read(rt2x00dev, 152, &value);
5508 if (ant == 0)
5509 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5510 else
5511 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5512 rt2800_bbp_write(rt2x00dev, 152, value);
5513
5514 rt2800_init_freq_calibration(rt2x00dev);
39ab3e8b
SG		 5515}
5516
a7bbbe5c
SG		 5517static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
5518{
5519 int ant, div_mode;
5520 u16 eeprom;
5521 u8 value;
5522
624708b8 5523 rt2800_init_bbp_early(rt2x00dev);
a4969d0d 5524
a7bbbe5c
SG		 5525 rt2800_bbp_read(rt2x00dev, 105, &value);
5526 rt2x00_set_field8(&value, BBP105_MLD,
5527 rt2x00dev->default_ant.rx_chain_num == 2);
5528 rt2800_bbp_write(rt2x00dev, 105, value);
5529
5530 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5531
5532 rt2800_bbp_write(rt2x00dev, 20, 0x06);
5533 rt2800_bbp_write(rt2x00dev, 31, 0x08);
5534 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5535 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
5536 rt2800_bbp_write(rt2x00dev, 69, 0x1A);
5537 rt2800_bbp_write(rt2x00dev, 70, 0x05);
5538 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5539 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
5540 rt2800_bbp_write(rt2x00dev, 75, 0x4F);
5541 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5542 rt2800_bbp_write(rt2x00dev, 77, 0x59);
5543 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
5544 rt2800_bbp_write(rt2x00dev, 86, 0x38);
5545 rt2800_bbp_write(rt2x00dev, 88, 0x90);
5546 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5547 rt2800_bbp_write(rt2x00dev, 92, 0x02);
5548 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5549 rt2800_bbp_write(rt2x00dev, 98, 0x12);
5550 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
5551 rt2800_bbp_write(rt2x00dev, 104, 0x92);
5552 /* FIXME BBP105 owerwrite */
5553 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
5554 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5555 rt2800_bbp_write(rt2x00dev, 128, 0x12);
5556 rt2800_bbp_write(rt2x00dev, 134, 0xD0);
5557 rt2800_bbp_write(rt2x00dev, 135, 0xF6);
5558 rt2800_bbp_write(rt2x00dev, 137, 0x0F);
5559
5560 /* Initialize GLRT (Generalized Likehood Radio Test) */
5561 rt2800_init_bbp_5592_glrt(rt2x00dev);
5562
5563 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5564
3e38d3da 5565 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
a7bbbe5c
SG		 5566 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
5567 ant = (div_mode == 3) ? 1 : 0;
5568 rt2800_bbp_read(rt2x00dev, 152, &value);
5569 if (ant == 0) {
5570 /* Main antenna */
5571 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5572 } else {
5573 /* Auxiliary antenna */
5574 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5575 }
5576 rt2800_bbp_write(rt2x00dev, 152, value);
5577
5578 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
5579 rt2800_bbp_read(rt2x00dev, 254, &value);
5580 rt2x00_set_field8(&value, BBP254_BIT7, 1);
5581 rt2800_bbp_write(rt2x00dev, 254, value);
5582 }
5583
c2675487
SG		 5584 rt2800_init_freq_calibration(rt2x00dev);
5585
a7bbbe5c 5586 rt2800_bbp_write(rt2x00dev, 84, 0x19);
6e04f253
SG		 5587 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
5588 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
a7bbbe5c
SG		 5589}
5590
a1ef5039 5591static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 5592{
5593 unsigned int i;
5594 u16 eeprom;
5595 u8 reg_id;
5596 u8 value;
5597
dae62957
SG		 5598 if (rt2800_is_305x_soc(rt2x00dev))
5599 rt2800_init_bbp_305x_soc(rt2x00dev);
5600
39ab3e8b
SG		 5601 switch (rt2x00dev->chip.rt) {
5602 case RT2860:
5603 case RT2872:
5604 case RT2883:
5605 rt2800_init_bbp_28xx(rt2x00dev);
5606 break;
5607 case RT3070:
5608 case RT3071:
5609 case RT3090:
5610 rt2800_init_bbp_30xx(rt2x00dev);
5611 break;
5612 case RT3290:
5613 rt2800_init_bbp_3290(rt2x00dev);
5614 break;
5615 case RT3352:
5616 rt2800_init_bbp_3352(rt2x00dev);
5617 break;
5618 case RT3390:
5619 rt2800_init_bbp_3390(rt2x00dev);
5620 break;
5621 case RT3572:
5622 rt2800_init_bbp_3572(rt2x00dev);
5623 break;
b189a181
GJ		 5624 case RT3593:
5625 rt2800_init_bbp_3593(rt2x00dev);
5626 return;
39ab3e8b
SG		 5627 case RT5390:
5628 case RT5392:
5629 rt2800_init_bbp_53xx(rt2x00dev);
5630 break;
5631 case RT5592:
a7bbbe5c 5632 rt2800_init_bbp_5592(rt2x00dev);
a1ef5039 5633 return;
a7bbbe5c
SG		 5634 }
5635
fcf51541 5636 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
022138ca
GJ		 5637 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_BBP_START, i,
5638 &eeprom);
fcf51541
BZ		 5639
5640 if (eeprom != 0xffff && eeprom != 0x0000) {
5641 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
5642 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
5643 rt2800_bbp_write(rt2x00dev, reg_id, value);
5644 }
5645 }
fcf51541 5646}
fcf51541 5647
d9517f2f
SG		 5648static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
5649{
5650 u32 reg;
5651
5652 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
5653 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
5654 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
5655}
5656
c5b3c350
SG		 5657static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
5658 u8 filter_target)
fcf51541
BZ		 5659{
5660 unsigned int i;
5661 u8 bbp;
5662 u8 rfcsr;
5663 u8 passband;
5664 u8 stopband;
5665 u8 overtuned = 0;
c5b3c350 5666 u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
fcf51541
BZ		 5667
5668 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5669
5670 rt2800_bbp_read(rt2x00dev, 4, &bbp);
5671 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
5672 rt2800_bbp_write(rt2x00dev, 4, bbp);
5673
80d184e6
RJH		 5674 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
5675 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
5676 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
5677
fcf51541
BZ		 5678 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5679 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
5680 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5681
5682 /*
5683 * Set power & frequency of passband test tone
5684 */
5685 rt2800_bbp_write(rt2x00dev, 24, 0);
5686
5687 for (i = 0; i < 100; i++) {
5688 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5689 msleep(1);
5690
5691 rt2800_bbp_read(rt2x00dev, 55, &passband);
5692 if (passband)
5693 break;
5694 }
5695
5696 /*
5697 * Set power & frequency of stopband test tone
5698 */
5699 rt2800_bbp_write(rt2x00dev, 24, 0x06);
5700
5701 for (i = 0; i < 100; i++) {
5702 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5703 msleep(1);
5704
5705 rt2800_bbp_read(rt2x00dev, 55, &stopband);
5706
5707 if ((passband - stopband) <= filter_target) {
5708 rfcsr24++;
5709 overtuned += ((passband - stopband) == filter_target);
5710 } else
5711 break;
5712
5713 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5714 }
5715
5716 rfcsr24 -= !!overtuned;
5717
5718 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5719 return rfcsr24;
5720}
5721
ce94ede9
SG		 5722static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
5723 const unsigned int rf_reg)
5724{
5725 u8 rfcsr;
5726
5727 rt2800_rfcsr_read(rt2x00dev, rf_reg, &rfcsr);
5728 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
5729 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5730 msleep(1);
5731 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
5732 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5733}
5734
c5b3c350
SG		 5735static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
5736{
5737 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5738 u8 filter_tgt_bw20;
5739 u8 filter_tgt_bw40;
5740 u8 rfcsr, bbp;
5741
5742 /*
5743 * TODO: sync filter_tgt values with vendor driver
5744 */
5745 if (rt2x00_rt(rt2x00dev, RT3070)) {
5746 filter_tgt_bw20 = 0x16;
5747 filter_tgt_bw40 = 0x19;
5748 } else {
5749 filter_tgt_bw20 = 0x13;
5750 filter_tgt_bw40 = 0x15;
5751 }
5752
5753 drv_data->calibration_bw20 =
5754 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
5755 drv_data->calibration_bw40 =
5756 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
5757
5758 /*
5759 * Save BBP 25 & 26 values for later use in channel switching (for 3052)
5760 */
5761 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
5762 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
5763
5764 /*
5765 * Set back to initial state
5766 */
5767 rt2800_bbp_write(rt2x00dev, 24, 0);
5768
5769 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5770 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
5771 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5772
5773 /*
5774 * Set BBP back to BW20
5775 */
5776 rt2800_bbp_read(rt2x00dev, 4, &bbp);
5777 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
5778 rt2800_bbp_write(rt2x00dev, 4, bbp);
5779}
5780
da8064c2
SG		 5781static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
5782{
5783 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5784 u8 min_gain, rfcsr, bbp;
5785 u16 eeprom;
5786
5787 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
5788
5789 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
5790 if (rt2x00_rt(rt2x00dev, RT3070) ||
5791 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5792 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5793 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
5794 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags))
5795 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
5796 }
5797
5798 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
5799 if (drv_data->txmixer_gain_24g >= min_gain) {
5800 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
5801 drv_data->txmixer_gain_24g);
5802 }
5803
5804 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
5805
5806 if (rt2x00_rt(rt2x00dev, RT3090)) {
5807 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
5808 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3e38d3da 5809 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
da8064c2
SG		 5810 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5811 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
5812 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5813 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
5814 rt2800_bbp_write(rt2x00dev, 138, bbp);
5815 }
5816
5817 if (rt2x00_rt(rt2x00dev, RT3070)) {
5818 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
5819 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
5820 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
5821 else
5822 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
5823 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
5824 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
5825 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
5826 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
5827 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
5828 rt2x00_rt(rt2x00dev, RT3090) ||
5829 rt2x00_rt(rt2x00dev, RT3390)) {
5830 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5831 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5832 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
5833 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
5834 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
5835 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
5836 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5837
5838 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
5839 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
5840 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
5841
5842 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
5843 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
5844 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
5845
5846 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
5847 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
5848 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
5849 }
5850}
5851
ab7078ac
GJ		 5852static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
5853{
5854 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5855 u8 rfcsr;
5856 u8 tx_gain;
5857
5858 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
5859 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
5860 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
5861
5862 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
5863 tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
5864 RFCSR17_TXMIXER_GAIN);
5865 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
5866 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
5867
5868 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
5869 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
5870 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
5871
5872 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
5873 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
5874 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
5875
5876 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5877 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5878 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
5879 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5880
5881 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
5882 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
5883 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
5884
5885 /* TODO: enable stream mode */
5886}
5887
f7df8fe5
SG		 5888static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
5889{
5890 u8 reg;
5891 u16 eeprom;
5892
5893 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
5894 rt2800_bbp_read(rt2x00dev, 138, &reg);
3e38d3da 5895 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
f7df8fe5
SG		 5896 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5897 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
5898 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5899 rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
5900 rt2800_bbp_write(rt2x00dev, 138, reg);
5901
5902 rt2800_rfcsr_read(rt2x00dev, 38, &reg);
5903 rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
5904 rt2800_rfcsr_write(rt2x00dev, 38, reg);
5905
5906 rt2800_rfcsr_read(rt2x00dev, 39, &reg);
5907 rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
5908 rt2800_rfcsr_write(rt2x00dev, 39, reg);
5909
5910 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5911
5912 rt2800_rfcsr_read(rt2x00dev, 30, &reg);
5913 rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
5914 rt2800_rfcsr_write(rt2x00dev, 30, reg);
5915}
5916
d5374ef1
SG		 5917static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
5918{
ce94ede9
SG		 5919 rt2800_rf_init_calibration(rt2x00dev, 30);
5920
d5374ef1
SG		 5921 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
5922 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
5923 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
5924 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
5925 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
5926 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
5927 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
5928 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
5929 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
5930 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
5931 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
5932 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
5933 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
5934 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
5935 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
5936 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
5937 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
5938 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
5939 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
5940 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
5941 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
5942 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
5943 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
5944 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
5945 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
5946 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
5947 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
5948 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
5949 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
5950 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
5951 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
5952 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
5953}
5954
5955static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
5956{
c9a221b2
SG		 5957 u8 rfcsr;
5958 u16 eeprom;
5959 u32 reg;
5960
ce94ede9
SG		 5961 /* XXX vendor driver do this only for 3070 */
5962 rt2800_rf_init_calibration(rt2x00dev, 30);
5963
d5374ef1
SG		 5964 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
5965 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
5966 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
5967 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
5968 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
5969 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
5970 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
5971 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
5972 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
5973 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
5974 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
5975 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
5976 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
5977 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
5978 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
5979 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
5980 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
5981 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
5982 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
c9a221b2
SG		 5983
5984 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
5985 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
5986 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
5987 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
5988 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
5989 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
5990 rt2x00_rt(rt2x00dev, RT3090)) {
5991 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
5992
5993 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
5994 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
5995 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
5996
5997 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
5998 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
5999 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6000 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
3e38d3da
GJ		 6001 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
6002 &eeprom);
c9a221b2
SG		 6003 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
6004 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6005 else
6006 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6007 }
6008 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6009
6010 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6011 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
6012 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6013 }
c5b3c350
SG		 6014
6015 rt2800_rx_filter_calibration(rt2x00dev);
5de5a1f4
SG		 6016
6017 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
6018 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6019 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
6020 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 6021
6022 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6023 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6024}
6025
6026static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
6027{
f9cdcbb1
SG		 6028 u8 rfcsr;
6029
ce94ede9
SG		 6030 rt2800_rf_init_calibration(rt2x00dev, 2);
6031
d5374ef1
SG		 6032 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
6033 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6034 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6035 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
6036 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
6037 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
6038 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6039 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6040 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6041 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6042 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6043 rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
6044 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6045 rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
6046 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6047 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6048 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6049 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6050 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6051 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6052 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6053 rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
6054 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6055 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6056 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
6057 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6058 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
6059 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6060 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6061 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
6062 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6063 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6064 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6065 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
6066 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6067 rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
6068 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
6069 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6070 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6071 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6072 rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
6073 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6074 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
6075 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
6076 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6077 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
f9cdcbb1
SG		 6078
6079 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
6080 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
6081 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
d9517f2f
SG		 6082
6083 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6084 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6085}
6086
6087static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
6088{
ce94ede9
SG		 6089 rt2800_rf_init_calibration(rt2x00dev, 30);
6090
d5374ef1
SG		 6091 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
6092 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
6093 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
6094 rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
6095 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
6096 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
6097 rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
6098 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6099 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
6100 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6101 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
6102 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
6103 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
6104 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
6105 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
6106 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6107 rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
6108 rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
6109 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6110 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6111 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
6112 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6113 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
6114 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
6115 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6116 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
6117 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6118 rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
6119 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
6120 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6121 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6122 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6123 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6124 rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
6125 rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
6126 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
6127 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
6128 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
6129 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
6130 rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
6131 rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
6132 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
6133 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
6134 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
6135 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
6136 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
6137 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
6138 rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
6139 rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
6140 rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
6141 rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
6142 rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
6143 rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
6144 rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
6145 rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
6146 rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
6147 rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
6148 rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
6149 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
6150 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
6151 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
6152 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6153 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
c5b3c350
SG		 6154
6155 rt2800_rx_filter_calibration(rt2x00dev);
d9517f2f 6156 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6157 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6158}
6159
6160static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
6161{
2971e66f
SG		 6162 u32 reg;
6163
ce94ede9
SG		 6164 rt2800_rf_init_calibration(rt2x00dev, 30);
6165
d5374ef1
SG		 6166 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
6167 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
6168 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
6169 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
6170 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6171 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
6172 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
6173 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
6174 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
6175 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
6176 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
6177 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6178 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
6179 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
6180 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6181 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
6182 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
6183 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
6184 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
6185 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
6186 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
6187 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
6188 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6189 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
6190 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
6191 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
6192 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
6193 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
6194 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
6195 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
6196 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
6197 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
2971e66f
SG		 6198
6199 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6200 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
6201 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
c5b3c350
SG		 6202
6203 rt2800_rx_filter_calibration(rt2x00dev);
5de5a1f4
SG		 6204
6205 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
6206 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 6207
6208 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6209 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6210}
6211
6212static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
6213{
87d91db9
SG		 6214 u8 rfcsr;
6215 u32 reg;
6216
ce94ede9
SG		 6217 rt2800_rf_init_calibration(rt2x00dev, 30);
6218
d5374ef1
SG		 6219 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
6220 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
6221 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
6222 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
6223 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
6224 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
6225 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
6226 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
6227 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
6228 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
6229 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
6230 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
6231 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
6232 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
6233 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
6234 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
6235 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
6236 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
6237 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
6238 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
6239 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
6240 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6241 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
6242 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
6243 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
6244 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
6245 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
6246 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6247 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
6248 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
6249 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
87d91db9
SG		 6250
6251 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
6252 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
6253 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
6254
6255 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6256 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6257 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6258 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6259 msleep(1);
6260 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6261 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6262 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6263 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
c5b3c350
SG		 6264
6265 rt2800_rx_filter_calibration(rt2x00dev);
d9517f2f 6266 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6267 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6268}
6269
d63f7e8c
GJ		 6270static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
6271{
6272 u8 bbp;
6273 bool txbf_enabled = false; /* FIXME */
6274
6275 rt2800_bbp_read(rt2x00dev, 105, &bbp);
6276 if (rt2x00dev->default_ant.rx_chain_num == 1)
6277 rt2x00_set_field8(&bbp, BBP105_MLD, 0);
6278 else
6279 rt2x00_set_field8(&bbp, BBP105_MLD, 1);
6280 rt2800_bbp_write(rt2x00dev, 105, bbp);
6281
6282 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6283
6284 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6285 rt2800_bbp_write(rt2x00dev, 82, 0x82);
6286 rt2800_bbp_write(rt2x00dev, 106, 0x05);
6287 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6288 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6289 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6290 rt2800_bbp_write(rt2x00dev, 47, 0x48);
6291 rt2800_bbp_write(rt2x00dev, 120, 0x50);
6292
6293 if (txbf_enabled)
6294 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
6295 else
6296 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
6297
6298 /* SNR mapping */
6299 rt2800_bbp_write(rt2x00dev, 142, 6);
6300 rt2800_bbp_write(rt2x00dev, 143, 160);
6301 rt2800_bbp_write(rt2x00dev, 142, 7);
6302 rt2800_bbp_write(rt2x00dev, 143, 161);
6303 rt2800_bbp_write(rt2x00dev, 142, 8);
6304 rt2800_bbp_write(rt2x00dev, 143, 162);
6305
6306 /* ADC/DAC control */
6307 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6308
6309 /* RX AGC energy lower bound in log2 */
6310 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6311
6312 /* FIXME: BBP 105 owerwrite? */
6313 rt2800_bbp_write(rt2x00dev, 105, 0x04);
f42b0465 6314
d63f7e8c
GJ		 6315}
6316
ab7078ac
GJ		 6317static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
6318{
6319 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6320 u32 reg;
6321 u8 rfcsr;
6322
6323 /* Disable GPIO #4 and #7 function for LAN PE control */
6324 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6325 rt2x00_set_field32(&reg, GPIO_SWITCH_4, 0);
6326 rt2x00_set_field32(&reg, GPIO_SWITCH_7, 0);
6327 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6328
6329 /* Initialize default register values */
6330 rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
6331 rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
6332 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
6333 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
6334 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
6335 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6336 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
6337 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
6338 rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
6339 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
6340 rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
6341 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6342 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6343 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6344 rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
6345 rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
6346 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
6347 rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
6348 rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
6349 rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
6350 rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
6351 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
6352 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
6353 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
6354 rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
6355 rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
6356 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
6357 rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
6358 rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
6359 rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
6360 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
6361 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
6362
6363 /* Initiate calibration */
6364 /* TODO: use rt2800_rf_init_calibration ? */
6365 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
6366 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
6367 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
6368
6369 rt2800_adjust_freq_offset(rt2x00dev);
6370
6371 rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr);
6372 rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
6373 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
6374
6375 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6376 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6377 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6378 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6379 usleep_range(1000, 1500);
6380 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6381 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6382 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6383
6384 /* Set initial values for RX filter calibration */
6385 drv_data->calibration_bw20 = 0x1f;
6386 drv_data->calibration_bw40 = 0x2f;
6387
6388 /* Save BBP 25 & 26 values for later use in channel switching */
6389 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
6390 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
6391
6392 rt2800_led_open_drain_enable(rt2x00dev);
6393 rt2800_normal_mode_setup_3593(rt2x00dev);
6394
d63f7e8c 6395 rt3593_post_bbp_init(rt2x00dev);
ab7078ac
GJ		 6396
6397 /* TODO: enable stream mode support */
6398}
6399
d5374ef1
SG		 6400static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
6401{
ce94ede9
SG		 6402 rt2800_rf_init_calibration(rt2x00dev, 2);
6403
d5374ef1
SG		 6404 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
6405 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6406 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6407 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6408 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6409 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6410 else
6411 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
6412 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6413 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6414 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6415 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
6416 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6417 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6418 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6419 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6420 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6421 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
6422
6423 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6424 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
6425 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6426 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
6427 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
6428 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6429 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6430 else
6431 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
6432 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
6433 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6434 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6435 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6436
6437 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
6438 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6439 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6440 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6441 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6442 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6443 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6444 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6445 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
6446 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6447
6448 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6449 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
6450 else
6451 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
6452 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6453 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
6454 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
6455 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6456 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6457 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6458 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6459 else
6460 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
6461 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
6462 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6463 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6464
6465 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
6466 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6467 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6468 else
6469 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
6470 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6471 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
6472 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
6473 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6474 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
6475 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
6476
6477 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6478 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6479 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
6480 else
6481 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
6482 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6483 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
f7df8fe5
SG		 6484
6485 rt2800_normal_mode_setup_5xxx(rt2x00dev);
d9517f2f
SG		 6486
6487 rt2800_led_open_drain_enable(rt2x00dev);
d5374ef1
SG		 6488}
6489
6490static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
6491{
ce94ede9
SG		 6492 rt2800_rf_init_calibration(rt2x00dev, 2);
6493
d5374ef1
SG		 6494 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
6495 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6496 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6497 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6498 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6499 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6500 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6501 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6502 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6503 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6504 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6505 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6506 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6507 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6508 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
6509 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6510 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
6511 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6512 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
6513 rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
6514 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6515 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6516 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6517 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6518 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6519 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6520 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6521 rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
6522 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6523 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6524 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6525 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6526 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6527 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
6528 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6529 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
6530 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6531 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6532 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
6533 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6534 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6535 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6536 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
6537 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6538 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6539 rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
6540 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
6541 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
6542 rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
6543 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
6544 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6545 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
6546 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
6547 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
6548 rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
6549 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6550 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
6551 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
6552 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
f7df8fe5
SG		 6553
6554 rt2800_normal_mode_setup_5xxx(rt2x00dev);
d9517f2f
SG		 6555
6556 rt2800_led_open_drain_enable(rt2x00dev);
d5374ef1
SG		 6557}
6558
0c9e5fb9
SG		 6559static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
6560{
ce94ede9
SG		 6561 rt2800_rf_init_calibration(rt2x00dev, 30);
6562
0c9e5fb9
SG		 6563 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
6564 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6565 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6566 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6567 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
6568 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6569 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6570 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6571 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6572 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6573 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
6574 rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
6575 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
6576 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6577 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6578 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6579 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6580 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6581 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6582 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
6583 rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
6584 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
6585
6586 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6587 msleep(1);
6588
6589 rt2800_adjust_freq_offset(rt2x00dev);
c630ccf1 6590
c630ccf1
SG		 6591 /* Enable DC filter */
6592 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
6593 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6594
f7df8fe5 6595 rt2800_normal_mode_setup_5xxx(rt2x00dev);
5de5a1f4
SG		 6596
6597 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
6598 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 6599
6600 rt2800_led_open_drain_enable(rt2x00dev);
0c9e5fb9
SG		 6601}
6602
074f2529 6603static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
fcf51541 6604{
d5374ef1
SG		 6605 if (rt2800_is_305x_soc(rt2x00dev)) {
6606 rt2800_init_rfcsr_305x_soc(rt2x00dev);
074f2529 6607 return;
d5374ef1
SG		 6608 }
6609
6610 switch (rt2x00dev->chip.rt) {
6611 case RT3070:
6612 case RT3071:
6613 case RT3090:
6614 rt2800_init_rfcsr_30xx(rt2x00dev);
6615 break;
6616 case RT3290:
6617 rt2800_init_rfcsr_3290(rt2x00dev);
6618 break;
6619 case RT3352:
6620 rt2800_init_rfcsr_3352(rt2x00dev);
6621 break;
6622 case RT3390:
6623 rt2800_init_rfcsr_3390(rt2x00dev);
6624 break;
6625 case RT3572:
6626 rt2800_init_rfcsr_3572(rt2x00dev);
6627 break;
ab7078ac
GJ		 6628 case RT3593:
6629 rt2800_init_rfcsr_3593(rt2x00dev);
6630 break;
d5374ef1
SG		 6631 case RT5390:
6632 rt2800_init_rfcsr_5390(rt2x00dev);
6633 break;
6634 case RT5392:
6635 rt2800_init_rfcsr_5392(rt2x00dev);
6636 break;
0c9e5fb9
SG		 6637 case RT5592:
6638 rt2800_init_rfcsr_5592(rt2x00dev);
074f2529 6639 break;
8cdd15e0 6640 }
fcf51541 6641}
b9a07ae9
ID		 6642
6643int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
6644{
6645 u32 reg;
6646 u16 word;
6647
6648 /*
6649 * Initialize all registers.
6650 */
6651 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
c630ccf1 6652 rt2800_init_registers(rt2x00dev)))
b9a07ae9
ID		 6653 return -EIO;
6654
6655 /*
6656 * Send signal to firmware during boot time.
6657 */
c630ccf1
SG		 6658 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
6659 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
6660 if (rt2x00_is_usb(rt2x00dev)) {
6661 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
6662 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
6663 }
6664 msleep(1);
6665
a1ef5039
SG		 6666 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
6667 rt2800_wait_bbp_ready(rt2x00dev)))
c630ccf1 6668 return -EIO;
b9a07ae9 6669
a1ef5039 6670 rt2800_init_bbp(rt2x00dev);
074f2529
SG		 6671 rt2800_init_rfcsr(rt2x00dev);
6672
b9a07ae9
ID		 6673 if (rt2x00_is_usb(rt2x00dev) &&
6674 (rt2x00_rt(rt2x00dev, RT3070) ||
6675 rt2x00_rt(rt2x00dev, RT3071) ||
6676 rt2x00_rt(rt2x00dev, RT3572))) {
6677 udelay(200);
6678 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
6679 udelay(10);
6680 }
6681
6682 /*
6683 * Enable RX.
6684 */
6685 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6686 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6687 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6688 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6689
6690 udelay(50);
6691
6692 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
6693 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
6694 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
6695 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
6696 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
6697 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
6698
6699 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6700 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6701 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
6702 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6703
6704 /*
6705 * Initialize LED control
6706 */
3e38d3da 6707 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
38c8a566 6708 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
b9a07ae9
ID		 6709 word & 0xff, (word >> 8) & 0xff);
6710
3e38d3da 6711 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
38c8a566 6712 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
b9a07ae9
ID		 6713 word & 0xff, (word >> 8) & 0xff);
6714
3e38d3da 6715 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
38c8a566 6716 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
b9a07ae9
ID		 6717 word & 0xff, (word >> 8) & 0xff);
6718
6719 return 0;
6720}
6721EXPORT_SYMBOL_GPL(rt2800_enable_radio);
6722
6723void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
6724{
6725 u32 reg;
6726
f7b395e9 6727 rt2800_disable_wpdma(rt2x00dev);
b9a07ae9
ID		 6728
6729 /* Wait for DMA, ignore error */
6730 rt2800_wait_wpdma_ready(rt2x00dev);
6731
6732 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6733 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
6734 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6735 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
b9a07ae9
ID		 6736}
6737EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2ce33995 6738
30e84034
BZ		 6739int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
6740{
6741 u32 reg;
a89534ed 6742 u16 efuse_ctrl_reg;
30e84034 6743
a89534ed
WH		 6744 if (rt2x00_rt(rt2x00dev, RT3290))
6745 efuse_ctrl_reg = EFUSE_CTRL_3290;
6746 else
6747 efuse_ctrl_reg = EFUSE_CTRL;
30e84034 6748
a89534ed 6749 rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
30e84034
BZ		 6750 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
6751}
6752EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
6753
6754static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
6755{
6756 u32 reg;
a89534ed
WH		 6757 u16 efuse_ctrl_reg;
6758 u16 efuse_data0_reg;
6759 u16 efuse_data1_reg;
6760 u16 efuse_data2_reg;
6761 u16 efuse_data3_reg;
6762
6763 if (rt2x00_rt(rt2x00dev, RT3290)) {
6764 efuse_ctrl_reg = EFUSE_CTRL_3290;
6765 efuse_data0_reg = EFUSE_DATA0_3290;
6766 efuse_data1_reg = EFUSE_DATA1_3290;
6767 efuse_data2_reg = EFUSE_DATA2_3290;
6768 efuse_data3_reg = EFUSE_DATA3_3290;
6769 } else {
6770 efuse_ctrl_reg = EFUSE_CTRL;
6771 efuse_data0_reg = EFUSE_DATA0;
6772 efuse_data1_reg = EFUSE_DATA1;
6773 efuse_data2_reg = EFUSE_DATA2;
6774 efuse_data3_reg = EFUSE_DATA3;
6775 }
31a4cf1f
GW		 6776 mutex_lock(&rt2x00dev->csr_mutex);
6777
a89534ed 6778 rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
30e84034
BZ		 6779 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
6780 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
6781 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
a89534ed 6782 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
30e84034
BZ		 6783
6784 /* Wait until the EEPROM has been loaded */
a89534ed 6785 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
30e84034 6786 /* Apparently the data is read from end to start */
a89534ed 6787 rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
daabead1 6788 /* The returned value is in CPU order, but eeprom is le */
68fa64ef 6789 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
a89534ed 6790 rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
daabead1 6791 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
a89534ed 6792 rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
daabead1 6793 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
a89534ed 6794 rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
daabead1 6795 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
31a4cf1f
GW		 6796
6797 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 6798}
6799
a02308e9 6800int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
30e84034
BZ		 6801{
6802 unsigned int i;
6803
6804 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
6805 rt2800_efuse_read(rt2x00dev, i);
a02308e9
GJ		 6806
6807 return 0;
30e84034
BZ		 6808}
6809EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
6810
a3f1625d
GJ		 6811static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
6812{
6813 u16 word;
6814
6316c786
GJ		 6815 if (rt2x00_rt(rt2x00dev, RT3593))
6816 return 0;
6817
a3f1625d
GJ		 6818 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
6819 if ((word & 0x00ff) != 0x00ff)
6820 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
6821
6822 return 0;
6823}
6824
6825static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
6826{
6827 u16 word;
6828
6316c786
GJ		 6829 if (rt2x00_rt(rt2x00dev, RT3593))
6830 return 0;
6831
a3f1625d
GJ		 6832 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
6833 if ((word & 0x00ff) != 0x00ff)
6834 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
6835
6836 return 0;
6837}
6838
ad417a53 6839static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
38bd7b8a 6840{
77c06c2c 6841 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
38bd7b8a
BZ		 6842 u16 word;
6843 u8 *mac;
6844 u8 default_lna_gain;
a02308e9 6845 int retval;
38bd7b8a 6846
ad417a53
GW		 6847 /*
6848 * Read the EEPROM.
6849 */
a02308e9
GJ		 6850 retval = rt2800_read_eeprom(rt2x00dev);
6851 if (retval)
6852 return retval;
ad417a53 6853
38bd7b8a
BZ		 6854 /*
6855 * Start validation of the data that has been read.
6856 */
3e38d3da 6857 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
38bd7b8a 6858 if (!is_valid_ether_addr(mac)) {
f4f7f414 6859 eth_random_addr(mac);
ec9c4989 6860 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
38bd7b8a
BZ		 6861 }
6862
3e38d3da 6863 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
38bd7b8a 6864 if (word == 0xffff) {
38c8a566
RJH		 6865 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
6866 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
6867 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
3e38d3da 6868 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
ec9c4989 6869 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 6870 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 6871 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 6872 /*
6873 * There is a max of 2 RX streams for RT28x0 series
6874 */
38c8a566
RJH		 6875 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
6876 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3e38d3da 6877 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a
BZ		 6878 }
6879
3e38d3da 6880 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
38bd7b8a 6881 if (word == 0xffff) {
38c8a566
RJH		 6882 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
6883 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
6884 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
6885 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
6886 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
6887 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
6888 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
6889 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
6890 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
6891 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
6892 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
6893 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
6894 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
6895 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
6896 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
3e38d3da 6897 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
ec9c4989 6898 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
38bd7b8a
BZ		 6899 }
6900
3e38d3da 6901 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
38bd7b8a
BZ		 6902 if ((word & 0x00ff) == 0x00ff) {
6903 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
3e38d3da 6904 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
ec9c4989 6905 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
ec2d1791
GW		 6906 }
6907 if ((word & 0xff00) == 0xff00) {
38bd7b8a
BZ		 6908 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
6909 LED_MODE_TXRX_ACTIVITY);
6910 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
3e38d3da
GJ		 6911 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
6912 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
6913 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
6914 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
ec9c4989 6915 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
38bd7b8a
BZ		 6916 }
6917
6918 /*
6919 * During the LNA validation we are going to use
6920 * lna0 as correct value. Note that EEPROM_LNA
6921 * is never validated.
6922 */
3e38d3da 6923 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
38bd7b8a
BZ		 6924 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
6925
3e38d3da 6926 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
38bd7b8a
BZ		 6927 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
6928 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
6929 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
6930 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
3e38d3da 6931 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
38bd7b8a 6932
a3f1625d 6933 drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
77c06c2c 6934
3e38d3da 6935 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
38bd7b8a
BZ		 6936 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
6937 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
f36bb0ca
GJ		 6938 if (!rt2x00_rt(rt2x00dev, RT3593)) {
6939 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
6940 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
6941 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
6942 default_lna_gain);
6943 }
3e38d3da 6944 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
38bd7b8a 6945
a3f1625d 6946 drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
77c06c2c 6947
3e38d3da 6948 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
38bd7b8a
BZ		 6949 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
6950 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
6951 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
6952 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
3e38d3da 6953 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
38bd7b8a 6954
3e38d3da 6955 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
38bd7b8a
BZ		 6956 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
6957 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
f36bb0ca
GJ		 6958 if (!rt2x00_rt(rt2x00dev, RT3593)) {
6959 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
6960 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
6961 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
6962 default_lna_gain);
6963 }
3e38d3da 6964 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
38bd7b8a 6965
f36bb0ca
GJ		 6966 if (rt2x00_rt(rt2x00dev, RT3593)) {
6967 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &word);
6968 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
6969 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
6970 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
6971 default_lna_gain);
6972 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 ||
6973 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff)
6974 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
6975 default_lna_gain);
6976 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
6977 }
6978
38bd7b8a
BZ		 6979 return 0;
6980}
38bd7b8a 6981
ad417a53 6982static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
38bd7b8a 6983{
38bd7b8a
BZ		 6984 u16 value;
6985 u16 eeprom;
86868b26 6986 u16 rf;
38bd7b8a 6987
86868b26
GJ		 6988 /*
6989 * Read EEPROM word for configuration.
6990 */
3e38d3da 6991 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
86868b26
GJ		 6992
6993 /*
6994 * Identify RF chipset by EEPROM value
6995 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
6996 * RT53xx: defined in "EEPROM_CHIP_ID" field
6997 */
6998 if (rt2x00_rt(rt2x00dev, RT3290) ||
6999 rt2x00_rt(rt2x00dev, RT5390) ||
7000 rt2x00_rt(rt2x00dev, RT5392))
3e38d3da 7001 rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf);
86868b26
GJ		 7002 else
7003 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
7004
7005 switch (rf) {
d331eb51
LF		 7006 case RF2820:
7007 case RF2850:
7008 case RF2720:
7009 case RF2750:
7010 case RF3020:
7011 case RF2020:
7012 case RF3021:
7013 case RF3022:
7014 case RF3052:
0f5af26a 7015 case RF3053:
a89534ed 7016 case RF3290:
d331eb51 7017 case RF3320:
03839951 7018 case RF3322:
ccf91bd6 7019 case RF5360:
d331eb51 7020 case RF5370:
2ed71884 7021 case RF5372:
d331eb51 7022 case RF5390:
cff3d1f0 7023 case RF5392:
b8863f8b 7024 case RF5592:
d331eb51
LF		 7025 break;
7026 default:
ec9c4989
JP		 7027 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
7028 rf);
38bd7b8a
BZ		 7029 return -ENODEV;
7030 }
7031
86868b26
GJ		 7032 rt2x00_set_rf(rt2x00dev, rf);
7033
38bd7b8a
BZ		 7034 /*
7035 * Identify default antenna configuration.
7036 */
d96aa640 7037 rt2x00dev->default_ant.tx_chain_num =
38c8a566 7038 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
d96aa640 7039 rt2x00dev->default_ant.rx_chain_num =
38c8a566 7040 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
38bd7b8a 7041
3e38d3da 7042 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
d96aa640
RJH		 7043
7044 if (rt2x00_rt(rt2x00dev, RT3070) ||
7045 rt2x00_rt(rt2x00dev, RT3090) ||
03839951 7046 rt2x00_rt(rt2x00dev, RT3352) ||
d96aa640
RJH		 7047 rt2x00_rt(rt2x00dev, RT3390)) {
7048 value = rt2x00_get_field16(eeprom,
7049 EEPROM_NIC_CONF1_ANT_DIVERSITY);
7050 switch (value) {
7051 case 0:
7052 case 1:
7053 case 2:
7054 rt2x00dev->default_ant.tx = ANTENNA_A;
7055 rt2x00dev->default_ant.rx = ANTENNA_A;
7056 break;
7057 case 3:
7058 rt2x00dev->default_ant.tx = ANTENNA_A;
7059 rt2x00dev->default_ant.rx = ANTENNA_B;
7060 break;
7061 }
7062 } else {
7063 rt2x00dev->default_ant.tx = ANTENNA_A;
7064 rt2x00dev->default_ant.rx = ANTENNA_A;
7065 }
7066
0586a11b
AA		 7067 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
7068 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
7069 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
7070 }
7071
38bd7b8a 7072 /*
9328fdac 7073 * Determine external LNA informations.
38bd7b8a 7074 */
38c8a566 7075 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
7dab73b3 7076 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
38c8a566 7077 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
7dab73b3 7078 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
38bd7b8a
BZ		 7079
7080 /*
7081 * Detect if this device has an hardware controlled radio.
7082 */
38c8a566 7083 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
7dab73b3 7084 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
38bd7b8a 7085
fdbc7b0a
GW		 7086 /*
7087 * Detect if this device has Bluetooth co-existence.
7088 */
7089 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
7090 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
7091
9328fdac
GW		 7092 /*
7093 * Read frequency offset and RF programming sequence.
7094 */
3e38d3da 7095 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
9328fdac
GW		 7096 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
7097
38bd7b8a
BZ		 7098 /*
7099 * Store led settings, for correct led behaviour.
7100 */
7101#ifdef CONFIG_RT2X00_LIB_LEDS
7102 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
7103 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
7104 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
7105
9328fdac 7106 rt2x00dev->led_mcu_reg = eeprom;
38bd7b8a
BZ		 7107#endif /* CONFIG_RT2X00_LIB_LEDS */
7108
e90c54b2
RJH		 7109 /*
7110 * Check if support EIRP tx power limit feature.
7111 */
3e38d3da 7112 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
e90c54b2
RJH		 7113
7114 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
7115 EIRP_MAX_TX_POWER_LIMIT)
7dab73b3 7116 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
e90c54b2 7117
38bd7b8a
BZ		 7118 return 0;
7119}
38bd7b8a 7120
4da2933f 7121/*
55f9321a 7122 * RF value list for rt28xx
4da2933f
BZ		 7123 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
7124 */
7125static const struct rf_channel rf_vals[] = {
7126 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
7127 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
7128 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
7129 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
7130 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
7131 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
7132 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
7133 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
7134 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
7135 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
7136 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
7137 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
7138 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
7139 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
7140
7141 /* 802.11 UNI / HyperLan 2 */
7142 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
7143 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
7144 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
7145 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
7146 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
7147 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
7148 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
7149 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
7150 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
7151 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
7152 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
7153 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
7154
7155 /* 802.11 HyperLan 2 */
7156 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
7157 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
7158 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
7159 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
7160 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
7161 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
7162 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
7163 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
7164 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
7165 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
7166 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
7167 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
7168 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
7169 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
7170 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
7171 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
7172
7173 /* 802.11 UNII */
7174 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
7175 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
7176 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
7177 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
7178 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
7179 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
7180 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
7181 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
7182 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
7183 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
7184 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
7185
7186 /* 802.11 Japan */
7187 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
7188 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
7189 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
7190 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
7191 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
7192 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
7193 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
7194};
7195
7196/*
55f9321a
ID		 7197 * RF value list for rt3xxx
7198 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4da2933f 7199 */
55f9321a 7200static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 7201 {1, 241, 2, 2 },
7202 {2, 241, 2, 7 },
7203 {3, 242, 2, 2 },
7204 {4, 242, 2, 7 },
7205 {5, 243, 2, 2 },
7206 {6, 243, 2, 7 },
7207 {7, 244, 2, 2 },
7208 {8, 244, 2, 7 },
7209 {9, 245, 2, 2 },
7210 {10, 245, 2, 7 },
7211 {11, 246, 2, 2 },
7212 {12, 246, 2, 7 },
7213 {13, 247, 2, 2 },
7214 {14, 248, 2, 4 },
55f9321a
ID		 7215
7216 /* 802.11 UNI / HyperLan 2 */
7217 {36, 0x56, 0, 4},
7218 {38, 0x56, 0, 6},
7219 {40, 0x56, 0, 8},
7220 {44, 0x57, 0, 0},
7221 {46, 0x57, 0, 2},
7222 {48, 0x57, 0, 4},
7223 {52, 0x57, 0, 8},
7224 {54, 0x57, 0, 10},
7225 {56, 0x58, 0, 0},
7226 {60, 0x58, 0, 4},
7227 {62, 0x58, 0, 6},
7228 {64, 0x58, 0, 8},
7229
7230 /* 802.11 HyperLan 2 */
7231 {100, 0x5b, 0, 8},
7232 {102, 0x5b, 0, 10},
7233 {104, 0x5c, 0, 0},
7234 {108, 0x5c, 0, 4},
7235 {110, 0x5c, 0, 6},
7236 {112, 0x5c, 0, 8},
7237 {116, 0x5d, 0, 0},
7238 {118, 0x5d, 0, 2},
7239 {120, 0x5d, 0, 4},
7240 {124, 0x5d, 0, 8},
7241 {126, 0x5d, 0, 10},
7242 {128, 0x5e, 0, 0},
7243 {132, 0x5e, 0, 4},
7244 {134, 0x5e, 0, 6},
7245 {136, 0x5e, 0, 8},
7246 {140, 0x5f, 0, 0},
7247
7248 /* 802.11 UNII */
7249 {149, 0x5f, 0, 9},
7250 {151, 0x5f, 0, 11},
7251 {153, 0x60, 0, 1},
7252 {157, 0x60, 0, 5},
7253 {159, 0x60, 0, 7},
7254 {161, 0x60, 0, 9},
7255 {165, 0x61, 0, 1},
7256 {167, 0x61, 0, 3},
7257 {169, 0x61, 0, 5},
7258 {171, 0x61, 0, 7},
7259 {173, 0x61, 0, 9},
4da2933f
BZ		 7260};
7261
7848b231
SG		 7262static const struct rf_channel rf_vals_5592_xtal20[] = {
7263 /* Channel, N, K, mod, R */
7264 {1, 482, 4, 10, 3},
7265 {2, 483, 4, 10, 3},
7266 {3, 484, 4, 10, 3},
7267 {4, 485, 4, 10, 3},
7268 {5, 486, 4, 10, 3},
7269 {6, 487, 4, 10, 3},
7270 {7, 488, 4, 10, 3},
7271 {8, 489, 4, 10, 3},
7272 {9, 490, 4, 10, 3},
7273 {10, 491, 4, 10, 3},
7274 {11, 492, 4, 10, 3},
7275 {12, 493, 4, 10, 3},
7276 {13, 494, 4, 10, 3},
7277 {14, 496, 8, 10, 3},
7278 {36, 172, 8, 12, 1},
7279 {38, 173, 0, 12, 1},
7280 {40, 173, 4, 12, 1},
7281 {42, 173, 8, 12, 1},
7282 {44, 174, 0, 12, 1},
7283 {46, 174, 4, 12, 1},
7284 {48, 174, 8, 12, 1},
7285 {50, 175, 0, 12, 1},
7286 {52, 175, 4, 12, 1},
7287 {54, 175, 8, 12, 1},
7288 {56, 176, 0, 12, 1},
7289 {58, 176, 4, 12, 1},
7290 {60, 176, 8, 12, 1},
7291 {62, 177, 0, 12, 1},
7292 {64, 177, 4, 12, 1},
7293 {100, 183, 4, 12, 1},
7294 {102, 183, 8, 12, 1},
7295 {104, 184, 0, 12, 1},
7296 {106, 184, 4, 12, 1},
7297 {108, 184, 8, 12, 1},
7298 {110, 185, 0, 12, 1},
7299 {112, 185, 4, 12, 1},
7300 {114, 185, 8, 12, 1},
7301 {116, 186, 0, 12, 1},
7302 {118, 186, 4, 12, 1},
7303 {120, 186, 8, 12, 1},
7304 {122, 187, 0, 12, 1},
7305 {124, 187, 4, 12, 1},
7306 {126, 187, 8, 12, 1},
7307 {128, 188, 0, 12, 1},
7308 {130, 188, 4, 12, 1},
7309 {132, 188, 8, 12, 1},
7310 {134, 189, 0, 12, 1},
7311 {136, 189, 4, 12, 1},
7312 {138, 189, 8, 12, 1},
7313 {140, 190, 0, 12, 1},
7314 {149, 191, 6, 12, 1},
7315 {151, 191, 10, 12, 1},
7316 {153, 192, 2, 12, 1},
7317 {155, 192, 6, 12, 1},
7318 {157, 192, 10, 12, 1},
7319 {159, 193, 2, 12, 1},
7320 {161, 193, 6, 12, 1},
7321 {165, 194, 2, 12, 1},
7322 {184, 164, 0, 12, 1},
7323 {188, 164, 4, 12, 1},
7324 {192, 165, 8, 12, 1},
7325 {196, 166, 0, 12, 1},
7326};
7327
7328static const struct rf_channel rf_vals_5592_xtal40[] = {
7329 /* Channel, N, K, mod, R */
7330 {1, 241, 2, 10, 3},
7331 {2, 241, 7, 10, 3},
7332 {3, 242, 2, 10, 3},
7333 {4, 242, 7, 10, 3},
7334 {5, 243, 2, 10, 3},
7335 {6, 243, 7, 10, 3},
7336 {7, 244, 2, 10, 3},
7337 {8, 244, 7, 10, 3},
7338 {9, 245, 2, 10, 3},
7339 {10, 245, 7, 10, 3},
7340 {11, 246, 2, 10, 3},
7341 {12, 246, 7, 10, 3},
7342 {13, 247, 2, 10, 3},
7343 {14, 248, 4, 10, 3},
7344 {36, 86, 4, 12, 1},
7345 {38, 86, 6, 12, 1},
7346 {40, 86, 8, 12, 1},
7347 {42, 86, 10, 12, 1},
7348 {44, 87, 0, 12, 1},
7349 {46, 87, 2, 12, 1},
7350 {48, 87, 4, 12, 1},
7351 {50, 87, 6, 12, 1},
7352 {52, 87, 8, 12, 1},
7353 {54, 87, 10, 12, 1},
7354 {56, 88, 0, 12, 1},
7355 {58, 88, 2, 12, 1},
7356 {60, 88, 4, 12, 1},
7357 {62, 88, 6, 12, 1},
7358 {64, 88, 8, 12, 1},
7359 {100, 91, 8, 12, 1},
7360 {102, 91, 10, 12, 1},
7361 {104, 92, 0, 12, 1},
7362 {106, 92, 2, 12, 1},
7363 {108, 92, 4, 12, 1},
7364 {110, 92, 6, 12, 1},
7365 {112, 92, 8, 12, 1},
7366 {114, 92, 10, 12, 1},
7367 {116, 93, 0, 12, 1},
7368 {118, 93, 2, 12, 1},
7369 {120, 93, 4, 12, 1},
7370 {122, 93, 6, 12, 1},
7371 {124, 93, 8, 12, 1},
7372 {126, 93, 10, 12, 1},
7373 {128, 94, 0, 12, 1},
7374 {130, 94, 2, 12, 1},
7375 {132, 94, 4, 12, 1},
7376 {134, 94, 6, 12, 1},
7377 {136, 94, 8, 12, 1},
7378 {138, 94, 10, 12, 1},
7379 {140, 95, 0, 12, 1},
7380 {149, 95, 9, 12, 1},
7381 {151, 95, 11, 12, 1},
7382 {153, 96, 1, 12, 1},
7383 {155, 96, 3, 12, 1},
7384 {157, 96, 5, 12, 1},
7385 {159, 96, 7, 12, 1},
7386 {161, 96, 9, 12, 1},
7387 {165, 97, 1, 12, 1},
7388 {184, 82, 0, 12, 1},
7389 {188, 82, 4, 12, 1},
7390 {192, 82, 8, 12, 1},
7391 {196, 83, 0, 12, 1},
7392};
7393
c8b9d3dc
GJ		 7394static const struct rf_channel rf_vals_3053[] = {
7395 /* Channel, N, R, K */
7396 {1, 241, 2, 2},
7397 {2, 241, 2, 7},
7398 {3, 242, 2, 2},
7399 {4, 242, 2, 7},
7400 {5, 243, 2, 2},
7401 {6, 243, 2, 7},
7402 {7, 244, 2, 2},
7403 {8, 244, 2, 7},
7404 {9, 245, 2, 2},
7405 {10, 245, 2, 7},
7406 {11, 246, 2, 2},
7407 {12, 246, 2, 7},
7408 {13, 247, 2, 2},
7409 {14, 248, 2, 4},
7410
7411 {36, 0x56, 0, 4},
7412 {38, 0x56, 0, 6},
7413 {40, 0x56, 0, 8},
7414 {44, 0x57, 0, 0},
7415 {46, 0x57, 0, 2},
7416 {48, 0x57, 0, 4},
7417 {52, 0x57, 0, 8},
7418 {54, 0x57, 0, 10},
7419 {56, 0x58, 0, 0},
7420 {60, 0x58, 0, 4},
7421 {62, 0x58, 0, 6},
7422 {64, 0x58, 0, 8},
7423
7424 {100, 0x5B, 0, 8},
7425 {102, 0x5B, 0, 10},
7426 {104, 0x5C, 0, 0},
7427 {108, 0x5C, 0, 4},
7428 {110, 0x5C, 0, 6},
7429 {112, 0x5C, 0, 8},
7430
7431 /* NOTE: Channel 114 has been removed intentionally.
7432 * The EEPROM contains no TX power values for that,
7433 * and it is disabled in the vendor driver as well.
7434 */
7435
7436 {116, 0x5D, 0, 0},
7437 {118, 0x5D, 0, 2},
7438 {120, 0x5D, 0, 4},
7439 {124, 0x5D, 0, 8},
7440 {126, 0x5D, 0, 10},
7441 {128, 0x5E, 0, 0},
7442 {132, 0x5E, 0, 4},
7443 {134, 0x5E, 0, 6},
7444 {136, 0x5E, 0, 8},
7445 {140, 0x5F, 0, 0},
7446
7447 {149, 0x5F, 0, 9},
7448 {151, 0x5F, 0, 11},
7449 {153, 0x60, 0, 1},
7450 {157, 0x60, 0, 5},
7451 {159, 0x60, 0, 7},
7452 {161, 0x60, 0, 9},
7453 {165, 0x61, 0, 1},
7454 {167, 0x61, 0, 3},
7455 {169, 0x61, 0, 5},
7456 {171, 0x61, 0, 7},
7457 {173, 0x61, 0, 9},
7458};
7459
ad417a53 7460static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4da2933f 7461{
4da2933f
BZ		 7462 struct hw_mode_spec *spec = &rt2x00dev->spec;
7463 struct channel_info *info;
8d1331b3
ID		 7464 char *default_power1;
7465 char *default_power2;
c0a14369 7466 char *default_power3;
4da2933f
BZ		 7467 unsigned int i;
7468 u16 eeprom;
7848b231 7469 u32 reg;
4da2933f 7470
93b6bd26
GW		 7471 /*
7472 * Disable powersaving as default on PCI devices.
7473 */
cea90e55 7474 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
93b6bd26
GW		 7475 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
7476
4da2933f
BZ		 7477 /*
7478 * Initialize all hw fields.
7479 */
7480 rt2x00dev->hw->flags =
4da2933f
BZ		 7481 IEEE80211_HW_SIGNAL_DBM |
7482 IEEE80211_HW_SUPPORTS_PS |
1df90809 7483 IEEE80211_HW_PS_NULLFUNC_STACK |
9d4f09b8 7484 IEEE80211_HW_AMPDU_AGGREGATION |
84e9e8eb 7485 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
9d4f09b8 7486
5a5b6ed6
HS		 7487 /*
7488 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
7489 * unless we are capable of sending the buffered frames out after the
7490 * DTIM transmission using rt2x00lib_beacondone. This will send out
7491 * multicast and broadcast traffic immediately instead of buffering it
7492 * infinitly and thus dropping it after some time.
7493 */
7494 if (!rt2x00_is_usb(rt2x00dev))
7495 rt2x00dev->hw->flags |=
7496 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
4da2933f 7497
4da2933f
BZ		 7498 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
7499 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3e38d3da 7500 rt2800_eeprom_addr(rt2x00dev,
4da2933f
BZ		 7501 EEPROM_MAC_ADDR_0));
7502
3f2bee24
HS		 7503 /*
7504 * As rt2800 has a global fallback table we cannot specify
7505 * more then one tx rate per frame but since the hw will
7506 * try several rates (based on the fallback table) we should
ba3b9e5e 7507 * initialize max_report_rates to the maximum number of rates
3f2bee24
HS		 7508 * we are going to try. Otherwise mac80211 will truncate our
7509 * reported tx rates and the rc algortihm will end up with
7510 * incorrect data.
7511 */
ba3b9e5e
HS		 7512 rt2x00dev->hw->max_rates = 1;
7513 rt2x00dev->hw->max_report_rates = 7;
3f2bee24
HS		 7514 rt2x00dev->hw->max_rate_tries = 1;
7515
3e38d3da 7516 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4da2933f
BZ		 7517
7518 /*
7519 * Initialize hw_mode information.
7520 */
7521 spec->supported_bands = SUPPORT_BAND_2GHZ;
7522 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
7523
5122d898 7524 if (rt2x00_rf(rt2x00dev, RF2820) ||
55f9321a 7525 rt2x00_rf(rt2x00dev, RF2720)) {
4da2933f
BZ		 7526 spec->num_channels = 14;
7527 spec->channels = rf_vals;
55f9321a
ID		 7528 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
7529 rt2x00_rf(rt2x00dev, RF2750)) {
4da2933f
BZ		 7530 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7531 spec->num_channels = ARRAY_SIZE(rf_vals);
7532 spec->channels = rf_vals;
5122d898
GW		 7533 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
7534 rt2x00_rf(rt2x00dev, RF2020) ||
7535 rt2x00_rf(rt2x00dev, RF3021) ||
f93bc9b3 7536 rt2x00_rf(rt2x00dev, RF3022) ||
a89534ed 7537 rt2x00_rf(rt2x00dev, RF3290) ||
adde5882 7538 rt2x00_rf(rt2x00dev, RF3320) ||
03839951 7539 rt2x00_rf(rt2x00dev, RF3322) ||
ccf91bd6 7540 rt2x00_rf(rt2x00dev, RF5360) ||
aca355b9 7541 rt2x00_rf(rt2x00dev, RF5370) ||
2ed71884 7542 rt2x00_rf(rt2x00dev, RF5372) ||
cff3d1f0
ZL		 7543 rt2x00_rf(rt2x00dev, RF5390) ||
7544 rt2x00_rf(rt2x00dev, RF5392)) {
55f9321a
ID		 7545 spec->num_channels = 14;
7546 spec->channels = rf_vals_3x;
7547 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
7548 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7549 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
7550 spec->channels = rf_vals_3x;
c8b9d3dc
GJ		 7551 } else if (rt2x00_rf(rt2x00dev, RF3053)) {
7552 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7553 spec->num_channels = ARRAY_SIZE(rf_vals_3053);
7554 spec->channels = rf_vals_3053;
7848b231
SG		 7555 } else if (rt2x00_rf(rt2x00dev, RF5592)) {
7556 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7557
7558 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, &reg);
7559 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
7560 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
7561 spec->channels = rf_vals_5592_xtal40;
7562 } else {
7563 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
7564 spec->channels = rf_vals_5592_xtal20;
7565 }
4da2933f
BZ		 7566 }
7567
53216d6a
SG		 7568 if (WARN_ON_ONCE(!spec->channels))
7569 return -ENODEV;
7570
4da2933f
BZ		 7571 /*
7572 * Initialize HT information.
7573 */
5122d898 7574 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 7575 spec->ht.ht_supported = true;
7576 else
7577 spec->ht.ht_supported = false;
7578
4da2933f 7579 spec->ht.cap =
06443e46 7580 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 7581 IEEE80211_HT_CAP_GRN_FLD |
7582 IEEE80211_HT_CAP_SGI_20 |
aa674631 7583 IEEE80211_HT_CAP_SGI_40;
22cabaa6 7584
38c8a566 7585 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
22cabaa6
HS		 7586 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
7587
aa674631 7588 spec->ht.cap |=
38c8a566 7589 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
aa674631
ID		 7590 IEEE80211_HT_CAP_RX_STBC_SHIFT;
7591
4da2933f
BZ		 7592 spec->ht.ampdu_factor = 3;
7593 spec->ht.ampdu_density = 4;
7594 spec->ht.mcs.tx_params =
7595 IEEE80211_HT_MCS_TX_DEFINED |
7596 IEEE80211_HT_MCS_TX_RX_DIFF |
38c8a566 7597 ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
4da2933f
BZ		 7598 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
7599
38c8a566 7600 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
4da2933f
BZ		 7601 case 3:
7602 spec->ht.mcs.rx_mask[2] = 0xff;
7603 case 2:
7604 spec->ht.mcs.rx_mask[1] = 0xff;
7605 case 1:
7606 spec->ht.mcs.rx_mask[0] = 0xff;
7607 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
7608 break;
7609 }
7610
7611 /*
7612 * Create channel information array
7613 */
baeb2ffa 7614 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4da2933f
BZ		 7615 if (!info)
7616 return -ENOMEM;
7617
7618 spec->channels_info = info;
7619
3e38d3da
GJ		 7620 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
7621 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4da2933f 7622
c0a14369
GJ		 7623 if (rt2x00dev->default_ant.tx_chain_num > 2)
7624 default_power3 = rt2800_eeprom_addr(rt2x00dev,
7625 EEPROM_EXT_TXPOWER_BG3);
7626 else
7627 default_power3 = NULL;
7628
4da2933f 7629 for (i = 0; i < 14; i++) {
e90c54b2
RJH		 7630 info[i].default_power1 = default_power1[i];
7631 info[i].default_power2 = default_power2[i];
c0a14369
GJ		 7632 if (default_power3)
7633 info[i].default_power3 = default_power3[i];
4da2933f
BZ		 7634 }
7635
7636 if (spec->num_channels > 14) {
3e38d3da
GJ		 7637 default_power1 = rt2800_eeprom_addr(rt2x00dev,
7638 EEPROM_TXPOWER_A1);
7639 default_power2 = rt2800_eeprom_addr(rt2x00dev,
7640 EEPROM_TXPOWER_A2);
4da2933f 7641
c0a14369
GJ		 7642 if (rt2x00dev->default_ant.tx_chain_num > 2)
7643 default_power3 =
7644 rt2800_eeprom_addr(rt2x00dev,
7645 EEPROM_EXT_TXPOWER_A3);
7646 else
7647 default_power3 = NULL;
7648
4da2933f 7649 for (i = 14; i < spec->num_channels; i++) {
0a6f3a8e
GJ		 7650 info[i].default_power1 = default_power1[i - 14];
7651 info[i].default_power2 = default_power2[i - 14];
c0a14369
GJ		 7652 if (default_power3)
7653 info[i].default_power3 = default_power3[i - 14];
4da2933f
BZ		 7654 }
7655 }
7656
2e9c43dd
JL		 7657 switch (rt2x00dev->chip.rf) {
7658 case RF2020:
7659 case RF3020:
7660 case RF3021:
7661 case RF3022:
7662 case RF3320:
7663 case RF3052:
1095df07 7664 case RF3053:
a89534ed 7665 case RF3290:
ccf91bd6 7666 case RF5360:
2e9c43dd
JL		 7667 case RF5370:
7668 case RF5372:
7669 case RF5390:
cff3d1f0 7670 case RF5392:
2e9c43dd
JL		 7671 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
7672 break;
7673 }
7674
4da2933f
BZ		 7675 return 0;
7676}
ad417a53 7677
cbafb601
GJ		 7678static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
7679{
7680 u32 reg;
7681 u32 rt;
7682 u32 rev;
7683
7684 if (rt2x00_rt(rt2x00dev, RT3290))
7685 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
7686 else
7687 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
7688
7689 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
7690 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
7691
7692 switch (rt) {
7693 case RT2860:
7694 case RT2872:
7695 case RT2883:
7696 case RT3070:
7697 case RT3071:
7698 case RT3090:
7699 case RT3290:
7700 case RT3352:
7701 case RT3390:
7702 case RT3572:
2dc2bd2f 7703 case RT3593:
cbafb601
GJ		 7704 case RT5390:
7705 case RT5392:
7706 case RT5592:
7707 break;
7708 default:
ec9c4989
JP		 7709 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
7710 rt, rev);
cbafb601
GJ		 7711 return -ENODEV;
7712 }
7713
7714 rt2x00_set_rt(rt2x00dev, rt, rev);
7715
7716 return 0;
7717}
7718
ad417a53
GW		 7719int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
7720{
7721 int retval;
7722 u32 reg;
7723
cbafb601
GJ		 7724 retval = rt2800_probe_rt(rt2x00dev);
7725 if (retval)
7726 return retval;
7727
ad417a53
GW		 7728 /*
7729 * Allocate eeprom data.
7730 */
7731 retval = rt2800_validate_eeprom(rt2x00dev);
7732 if (retval)
7733 return retval;
7734
7735 retval = rt2800_init_eeprom(rt2x00dev);
7736 if (retval)
7737 return retval;
7738
7739 /*
7740 * Enable rfkill polling by setting GPIO direction of the
7741 * rfkill switch GPIO pin correctly.
7742 */
7743 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
7744 rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
7745 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
7746
7747 /*
7748 * Initialize hw specifications.
7749 */
7750 retval = rt2800_probe_hw_mode(rt2x00dev);
7751 if (retval)
7752 return retval;
7753
7754 /*
7755 * Set device capabilities.
7756 */
7757 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
7758 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
7759 if (!rt2x00_is_usb(rt2x00dev))
7760 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
7761
7762 /*
7763 * Set device requirements.
7764 */
7765 if (!rt2x00_is_soc(rt2x00dev))
7766 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
7767 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
7768 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
7769 if (!rt2800_hwcrypt_disabled(rt2x00dev))
7770 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
7771 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
7772 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
7773 if (rt2x00_is_usb(rt2x00dev))
7774 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
7775 else {
7776 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
7777 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
7778 }
7779
7780 /*
7781 * Set the rssi offset.
7782 */
7783 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
7784
7785 return 0;
7786}
7787EXPORT_SYMBOL_GPL(rt2800_probe_hw);
4da2933f 7788
2ce33995
BZ		 7789/*
7790 * IEEE80211 stack callback functions.
7791 */
e783619e
HS		 7792void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
7793 u16 *iv16)
2ce33995
BZ		 7794{
7795 struct rt2x00_dev *rt2x00dev = hw->priv;
7796 struct mac_iveiv_entry iveiv_entry;
7797 u32 offset;
7798
7799 offset = MAC_IVEIV_ENTRY(hw_key_idx);
7800 rt2800_register_multiread(rt2x00dev, offset,
7801 &iveiv_entry, sizeof(iveiv_entry));
7802
855da5e0
JL		 7803 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
7804 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995 7805}
e783619e 7806EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
2ce33995 7807
e783619e 7808int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2ce33995
BZ		 7809{
7810 struct rt2x00_dev *rt2x00dev = hw->priv;
7811 u32 reg;
7812 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
7813
7814 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
7815 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
7816 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
7817
7818 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
7819 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
7820 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
7821
7822 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
7823 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
7824 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
7825
7826 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
7827 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
7828 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
7829
7830 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
7831 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
7832 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
7833
7834 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
7835 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
7836 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
7837
7838 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
7839 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
7840 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
7841
7842 return 0;
7843}
e783619e 7844EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2ce33995 7845
8a3a3c85
EP		 7846int rt2800_conf_tx(struct ieee80211_hw *hw,
7847 struct ieee80211_vif *vif, u16 queue_idx,
e783619e 7848 const struct ieee80211_tx_queue_params *params)
2ce33995
BZ		 7849{
7850 struct rt2x00_dev *rt2x00dev = hw->priv;
7851 struct data_queue *queue;
7852 struct rt2x00_field32 field;
7853 int retval;
7854 u32 reg;
7855 u32 offset;
7856
7857 /*
7858 * First pass the configuration through rt2x00lib, that will
7859 * update the queue settings and validate the input. After that
7860 * we are free to update the registers based on the value
7861 * in the queue parameter.
7862 */
8a3a3c85 7863 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
2ce33995
BZ		 7864 if (retval)
7865 return retval;
7866
7867 /*
7868 * We only need to perform additional register initialization
7869 * for WMM queues/
7870 */
7871 if (queue_idx >= 4)
7872 return 0;
7873
11f818e0 7874 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2ce33995
BZ		 7875
7876 /* Update WMM TXOP register */
7877 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
7878 field.bit_offset = (queue_idx & 1) * 16;
7879 field.bit_mask = 0xffff << field.bit_offset;
7880
7881 rt2800_register_read(rt2x00dev, offset, &reg);
7882 rt2x00_set_field32(&reg, field, queue->txop);
7883 rt2800_register_write(rt2x00dev, offset, reg);
7884
7885 /* Update WMM registers */
7886 field.bit_offset = queue_idx * 4;
7887 field.bit_mask = 0xf << field.bit_offset;
7888
7889 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
7890 rt2x00_set_field32(&reg, field, queue->aifs);
7891 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
7892
7893 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
7894 rt2x00_set_field32(&reg, field, queue->cw_min);
7895 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
7896
7897 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
7898 rt2x00_set_field32(&reg, field, queue->cw_max);
7899 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
7900
7901 /* Update EDCA registers */
7902 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
7903
7904 rt2800_register_read(rt2x00dev, offset, &reg);
7905 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
7906 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
7907 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
7908 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
7909 rt2800_register_write(rt2x00dev, offset, reg);
7910
7911 return 0;
7912}
e783619e 7913EXPORT_SYMBOL_GPL(rt2800_conf_tx);
2ce33995 7914
37a41b4a 7915u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2ce33995
BZ		 7916{
7917 struct rt2x00_dev *rt2x00dev = hw->priv;
7918 u64 tsf;
7919 u32 reg;
7920
7921 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
7922 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
7923 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
7924 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
7925
7926 return tsf;
7927}
e783619e 7928EXPORT_SYMBOL_GPL(rt2800_get_tsf);
2ce33995 7929
e783619e
HS		 7930int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
7931 enum ieee80211_ampdu_mlme_action action,
0b01f030
JB		 7932 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
7933 u8 buf_size)
1df90809 7934{
af35323d 7935 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
1df90809
HS		 7936 int ret = 0;
7937
af35323d
HS		 7938 /*
7939 * Don't allow aggregation for stations the hardware isn't aware
7940 * of because tx status reports for frames to an unknown station
7941 * always contain wcid=255 and thus we can't distinguish between
7942 * multiple stations which leads to unwanted situations when the
7943 * hw reorders frames due to aggregation.
7944 */
7945 if (sta_priv->wcid < 0)
7946 return 1;
7947
1df90809
HS		 7948 switch (action) {
7949 case IEEE80211_AMPDU_RX_START:
7950 case IEEE80211_AMPDU_RX_STOP:
58ed826e
HS		 7951 /*
7952 * The hw itself takes care of setting up BlockAck mechanisms.
7953 * So, we only have to allow mac80211 to nagotiate a BlockAck
7954 * agreement. Once that is done, the hw will BlockAck incoming
7955 * AMPDUs without further setup.
7956 */
1df90809
HS		 7957 break;
7958 case IEEE80211_AMPDU_TX_START:
7959 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7960 break;
18b559d5
JB		 7961 case IEEE80211_AMPDU_TX_STOP_CONT:
7962 case IEEE80211_AMPDU_TX_STOP_FLUSH:
7963 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
1df90809
HS		 7964 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7965 break;
7966 case IEEE80211_AMPDU_TX_OPERATIONAL:
7967 break;
7968 default:
ec9c4989
JP		 7969 rt2x00_warn((struct rt2x00_dev *)hw->priv,
7970 "Unknown AMPDU action\n");
1df90809
HS		 7971 }
7972
7973 return ret;
7974}
e783619e 7975EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
a5ea2f02 7976
977206d7
HS		 7977int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
7978 struct survey_info *survey)
7979{
7980 struct rt2x00_dev *rt2x00dev = hw->priv;
7981 struct ieee80211_conf *conf = &hw->conf;
7982 u32 idle, busy, busy_ext;
7983
7984 if (idx != 0)
7985 return -ENOENT;
7986
675a0b04 7987 survey->channel = conf->chandef.chan;
977206d7
HS		 7988
7989 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
7990 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
7991 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
7992
7993 if (idle || busy) {
7994 survey->filled = SURVEY_INFO_CHANNEL_TIME |
7995 SURVEY_INFO_CHANNEL_TIME_BUSY |
7996 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
7997
7998 survey->channel_time = (idle + busy) / 1000;
7999 survey->channel_time_busy = busy / 1000;
8000 survey->channel_time_ext_busy = busy_ext / 1000;
8001 }
8002
9931df26
HS		 8003 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
8004 survey->filled |= SURVEY_INFO_IN_USE;
8005
977206d7
HS		 8006 return 0;
8007
8008}
8009EXPORT_SYMBOL_GPL(rt2800_get_survey);
8010
a5ea2f02
ID		 8011MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
8012MODULE_VERSION(DRV_VERSION);
8013MODULE_DESCRIPTION("Ralink RT2800 library");
8014MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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