Commit | Line | Data |
---|---|---|
89297425 | 1 | /* |
96481b20 | 2 | Copyright (C) 2010 Willow Garage <http://www.willowgarage.com> |
a5ea2f02 | 3 | Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com> |
9c9a0d14 | 4 | Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> |
cce5fc45 | 5 | Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com> |
89297425 | 6 | |
9c9a0d14 | 7 | Based on the original rt2800pci.c and rt2800usb.c. |
9c9a0d14 GW |
8 | Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> |
9 | Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> | |
10 | Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> | |
11 | Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de> | |
12 | Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com> | |
13 | Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com> | |
89297425 BZ |
14 | <http://rt2x00.serialmonkey.com> |
15 | ||
16 | This program is free software; you can redistribute it and/or modify | |
17 | it under the terms of the GNU General Public License as published by | |
18 | the Free Software Foundation; either version 2 of the License, or | |
19 | (at your option) any later version. | |
20 | ||
21 | This program is distributed in the hope that it will be useful, | |
22 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
23 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
24 | GNU General Public License for more details. | |
25 | ||
26 | You should have received a copy of the GNU General Public License | |
27 | along with this program; if not, write to the | |
28 | Free Software Foundation, Inc., | |
29 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
30 | */ | |
31 | ||
32 | /* | |
33 | Module: rt2800lib | |
34 | Abstract: rt2800 generic device routines. | |
35 | */ | |
36 | ||
f31c9a8c | 37 | #include <linux/crc-ccitt.h> |
89297425 BZ |
38 | #include <linux/kernel.h> |
39 | #include <linux/module.h> | |
5a0e3ad6 | 40 | #include <linux/slab.h> |
89297425 BZ |
41 | |
42 | #include "rt2x00.h" | |
43 | #include "rt2800lib.h" | |
44 | #include "rt2800.h" | |
45 | ||
89297425 BZ |
46 | /* |
47 | * Register access. | |
48 | * All access to the CSR registers will go through the methods | |
49 | * rt2800_register_read and rt2800_register_write. | |
50 | * BBP and RF register require indirect register access, | |
51 | * and use the CSR registers BBPCSR and RFCSR to achieve this. | |
52 | * These indirect registers work with busy bits, | |
53 | * and we will try maximal REGISTER_BUSY_COUNT times to access | |
54 | * the register while taking a REGISTER_BUSY_DELAY us delay | |
55 | * between each attampt. When the busy bit is still set at that time, | |
56 | * the access attempt is considered to have failed, | |
57 | * and we will print an error. | |
58 | * The _lock versions must be used if you already hold the csr_mutex | |
59 | */ | |
60 | #define WAIT_FOR_BBP(__dev, __reg) \ | |
61 | rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg)) | |
62 | #define WAIT_FOR_RFCSR(__dev, __reg) \ | |
63 | rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg)) | |
64 | #define WAIT_FOR_RF(__dev, __reg) \ | |
65 | rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg)) | |
66 | #define WAIT_FOR_MCU(__dev, __reg) \ | |
67 | rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \ | |
68 | H2M_MAILBOX_CSR_OWNER, (__reg)) | |
69 | ||
baff8006 HS |
70 | static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev) |
71 | { | |
72 | /* check for rt2872 on SoC */ | |
73 | if (!rt2x00_is_soc(rt2x00dev) || | |
74 | !rt2x00_rt(rt2x00dev, RT2872)) | |
75 | return false; | |
76 | ||
77 | /* we know for sure that these rf chipsets are used on rt305x boards */ | |
78 | if (rt2x00_rf(rt2x00dev, RF3020) || | |
79 | rt2x00_rf(rt2x00dev, RF3021) || | |
80 | rt2x00_rf(rt2x00dev, RF3022)) | |
81 | return true; | |
82 | ||
83 | NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n"); | |
84 | return false; | |
85 | } | |
86 | ||
fcf51541 BZ |
87 | static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev, |
88 | const unsigned int word, const u8 value) | |
89297425 BZ |
89 | { |
90 | u32 reg; | |
91 | ||
92 | mutex_lock(&rt2x00dev->csr_mutex); | |
93 | ||
94 | /* | |
95 | * Wait until the BBP becomes available, afterwards we | |
96 | * can safely write the new data into the register. | |
97 | */ | |
98 | if (WAIT_FOR_BBP(rt2x00dev, ®)) { | |
99 | reg = 0; | |
100 | rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value); | |
101 | rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); | |
102 | rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); | |
103 | rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0); | |
efc7d36f | 104 | rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); |
89297425 BZ |
105 | |
106 | rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); | |
107 | } | |
108 | ||
109 | mutex_unlock(&rt2x00dev->csr_mutex); | |
110 | } | |
89297425 | 111 | |
fcf51541 BZ |
112 | static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, |
113 | const unsigned int word, u8 *value) | |
89297425 BZ |
114 | { |
115 | u32 reg; | |
116 | ||
117 | mutex_lock(&rt2x00dev->csr_mutex); | |
118 | ||
119 | /* | |
120 | * Wait until the BBP becomes available, afterwards we | |
121 | * can safely write the read request into the register. | |
122 | * After the data has been written, we wait until hardware | |
123 | * returns the correct value, if at any time the register | |
124 | * doesn't become available in time, reg will be 0xffffffff | |
125 | * which means we return 0xff to the caller. | |
126 | */ | |
127 | if (WAIT_FOR_BBP(rt2x00dev, ®)) { | |
128 | reg = 0; | |
129 | rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); | |
130 | rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); | |
131 | rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1); | |
efc7d36f | 132 | rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); |
89297425 BZ |
133 | |
134 | rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); | |
135 | ||
136 | WAIT_FOR_BBP(rt2x00dev, ®); | |
137 | } | |
138 | ||
139 | *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE); | |
140 | ||
141 | mutex_unlock(&rt2x00dev->csr_mutex); | |
142 | } | |
89297425 | 143 | |
fcf51541 BZ |
144 | static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev, |
145 | const unsigned int word, const u8 value) | |
89297425 BZ |
146 | { |
147 | u32 reg; | |
148 | ||
149 | mutex_lock(&rt2x00dev->csr_mutex); | |
150 | ||
151 | /* | |
152 | * Wait until the RFCSR becomes available, afterwards we | |
153 | * can safely write the new data into the register. | |
154 | */ | |
155 | if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { | |
156 | reg = 0; | |
157 | rt2x00_set_field32(®, RF_CSR_CFG_DATA, value); | |
158 | rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); | |
159 | rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1); | |
160 | rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); | |
161 | ||
162 | rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); | |
163 | } | |
164 | ||
165 | mutex_unlock(&rt2x00dev->csr_mutex); | |
166 | } | |
89297425 | 167 | |
fcf51541 BZ |
168 | static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev, |
169 | const unsigned int word, u8 *value) | |
89297425 BZ |
170 | { |
171 | u32 reg; | |
172 | ||
173 | mutex_lock(&rt2x00dev->csr_mutex); | |
174 | ||
175 | /* | |
176 | * Wait until the RFCSR becomes available, afterwards we | |
177 | * can safely write the read request into the register. | |
178 | * After the data has been written, we wait until hardware | |
179 | * returns the correct value, if at any time the register | |
180 | * doesn't become available in time, reg will be 0xffffffff | |
181 | * which means we return 0xff to the caller. | |
182 | */ | |
183 | if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { | |
184 | reg = 0; | |
185 | rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); | |
186 | rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0); | |
187 | rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); | |
188 | ||
189 | rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); | |
190 | ||
191 | WAIT_FOR_RFCSR(rt2x00dev, ®); | |
192 | } | |
193 | ||
194 | *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA); | |
195 | ||
196 | mutex_unlock(&rt2x00dev->csr_mutex); | |
197 | } | |
89297425 | 198 | |
fcf51541 BZ |
199 | static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev, |
200 | const unsigned int word, const u32 value) | |
89297425 BZ |
201 | { |
202 | u32 reg; | |
203 | ||
204 | mutex_lock(&rt2x00dev->csr_mutex); | |
205 | ||
206 | /* | |
207 | * Wait until the RF becomes available, afterwards we | |
208 | * can safely write the new data into the register. | |
209 | */ | |
210 | if (WAIT_FOR_RF(rt2x00dev, ®)) { | |
211 | reg = 0; | |
212 | rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value); | |
213 | rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0); | |
214 | rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0); | |
215 | rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1); | |
216 | ||
217 | rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg); | |
218 | rt2x00_rf_write(rt2x00dev, word, value); | |
219 | } | |
220 | ||
221 | mutex_unlock(&rt2x00dev->csr_mutex); | |
222 | } | |
89297425 BZ |
223 | |
224 | void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev, | |
225 | const u8 command, const u8 token, | |
226 | const u8 arg0, const u8 arg1) | |
227 | { | |
228 | u32 reg; | |
229 | ||
ee303e54 | 230 | /* |
cea90e55 | 231 | * SOC devices don't support MCU requests. |
ee303e54 | 232 | */ |
cea90e55 | 233 | if (rt2x00_is_soc(rt2x00dev)) |
ee303e54 | 234 | return; |
89297425 BZ |
235 | |
236 | mutex_lock(&rt2x00dev->csr_mutex); | |
237 | ||
238 | /* | |
239 | * Wait until the MCU becomes available, afterwards we | |
240 | * can safely write the new data into the register. | |
241 | */ | |
242 | if (WAIT_FOR_MCU(rt2x00dev, ®)) { | |
243 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); | |
244 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); | |
245 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); | |
246 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); | |
247 | rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg); | |
248 | ||
249 | reg = 0; | |
250 | rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); | |
251 | rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg); | |
252 | } | |
253 | ||
254 | mutex_unlock(&rt2x00dev->csr_mutex); | |
255 | } | |
256 | EXPORT_SYMBOL_GPL(rt2800_mcu_request); | |
f4450616 | 257 | |
5ffddc49 ID |
258 | int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev) |
259 | { | |
260 | unsigned int i = 0; | |
261 | u32 reg; | |
262 | ||
263 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
264 | rt2800_register_read(rt2x00dev, MAC_CSR0, ®); | |
265 | if (reg && reg != ~0) | |
266 | return 0; | |
267 | msleep(1); | |
268 | } | |
269 | ||
270 | ERROR(rt2x00dev, "Unstable hardware.\n"); | |
271 | return -EBUSY; | |
272 | } | |
273 | EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready); | |
274 | ||
67a4c1e2 GW |
275 | int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev) |
276 | { | |
277 | unsigned int i; | |
278 | u32 reg; | |
279 | ||
08e53100 HS |
280 | /* |
281 | * Some devices are really slow to respond here. Wait a whole second | |
282 | * before timing out. | |
283 | */ | |
67a4c1e2 GW |
284 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { |
285 | rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); | |
286 | if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) && | |
287 | !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY)) | |
288 | return 0; | |
289 | ||
08e53100 | 290 | msleep(10); |
67a4c1e2 GW |
291 | } |
292 | ||
293 | ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n"); | |
294 | return -EACCES; | |
295 | } | |
296 | EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready); | |
297 | ||
f31c9a8c ID |
298 | static bool rt2800_check_firmware_crc(const u8 *data, const size_t len) |
299 | { | |
300 | u16 fw_crc; | |
301 | u16 crc; | |
302 | ||
303 | /* | |
304 | * The last 2 bytes in the firmware array are the crc checksum itself, | |
305 | * this means that we should never pass those 2 bytes to the crc | |
306 | * algorithm. | |
307 | */ | |
308 | fw_crc = (data[len - 2] << 8 | data[len - 1]); | |
309 | ||
310 | /* | |
311 | * Use the crc ccitt algorithm. | |
312 | * This will return the same value as the legacy driver which | |
313 | * used bit ordering reversion on the both the firmware bytes | |
314 | * before input input as well as on the final output. | |
315 | * Obviously using crc ccitt directly is much more efficient. | |
316 | */ | |
317 | crc = crc_ccitt(~0, data, len - 2); | |
318 | ||
319 | /* | |
320 | * There is a small difference between the crc-itu-t + bitrev and | |
321 | * the crc-ccitt crc calculation. In the latter method the 2 bytes | |
322 | * will be swapped, use swab16 to convert the crc to the correct | |
323 | * value. | |
324 | */ | |
325 | crc = swab16(crc); | |
326 | ||
327 | return fw_crc == crc; | |
328 | } | |
329 | ||
330 | int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev, | |
331 | const u8 *data, const size_t len) | |
332 | { | |
333 | size_t offset = 0; | |
334 | size_t fw_len; | |
335 | bool multiple; | |
336 | ||
337 | /* | |
338 | * PCI(e) & SOC devices require firmware with a length | |
339 | * of 8kb. USB devices require firmware files with a length | |
340 | * of 4kb. Certain USB chipsets however require different firmware, | |
341 | * which Ralink only provides attached to the original firmware | |
342 | * file. Thus for USB devices, firmware files have a length | |
343 | * which is a multiple of 4kb. | |
344 | */ | |
345 | if (rt2x00_is_usb(rt2x00dev)) { | |
346 | fw_len = 4096; | |
347 | multiple = true; | |
348 | } else { | |
349 | fw_len = 8192; | |
350 | multiple = true; | |
351 | } | |
352 | ||
353 | /* | |
354 | * Validate the firmware length | |
355 | */ | |
356 | if (len != fw_len && (!multiple || (len % fw_len) != 0)) | |
357 | return FW_BAD_LENGTH; | |
358 | ||
359 | /* | |
360 | * Check if the chipset requires one of the upper parts | |
361 | * of the firmware. | |
362 | */ | |
363 | if (rt2x00_is_usb(rt2x00dev) && | |
364 | !rt2x00_rt(rt2x00dev, RT2860) && | |
365 | !rt2x00_rt(rt2x00dev, RT2872) && | |
366 | !rt2x00_rt(rt2x00dev, RT3070) && | |
367 | ((len / fw_len) == 1)) | |
368 | return FW_BAD_VERSION; | |
369 | ||
370 | /* | |
371 | * 8kb firmware files must be checked as if it were | |
372 | * 2 separate firmware files. | |
373 | */ | |
374 | while (offset < len) { | |
375 | if (!rt2800_check_firmware_crc(data + offset, fw_len)) | |
376 | return FW_BAD_CRC; | |
377 | ||
378 | offset += fw_len; | |
379 | } | |
380 | ||
381 | return FW_OK; | |
382 | } | |
383 | EXPORT_SYMBOL_GPL(rt2800_check_firmware); | |
384 | ||
385 | int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev, | |
386 | const u8 *data, const size_t len) | |
387 | { | |
388 | unsigned int i; | |
389 | u32 reg; | |
390 | ||
391 | /* | |
b9eca242 ID |
392 | * If driver doesn't wake up firmware here, |
393 | * rt2800_load_firmware will hang forever when interface is up again. | |
f31c9a8c | 394 | */ |
b9eca242 | 395 | rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000); |
f31c9a8c | 396 | |
f31c9a8c ID |
397 | /* |
398 | * Wait for stable hardware. | |
399 | */ | |
5ffddc49 | 400 | if (rt2800_wait_csr_ready(rt2x00dev)) |
f31c9a8c | 401 | return -EBUSY; |
f31c9a8c | 402 | |
adde5882 GJ |
403 | if (rt2x00_is_pci(rt2x00dev)) { |
404 | if (rt2x00_rt(rt2x00dev, RT5390)) { | |
405 | rt2800_register_read(rt2x00dev, AUX_CTRL, ®); | |
406 | rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); | |
407 | rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); | |
408 | rt2800_register_write(rt2x00dev, AUX_CTRL, reg); | |
409 | } | |
f31c9a8c | 410 | rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002); |
adde5882 | 411 | } |
f31c9a8c ID |
412 | |
413 | /* | |
414 | * Disable DMA, will be reenabled later when enabling | |
415 | * the radio. | |
416 | */ | |
417 | rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); | |
418 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); | |
419 | rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); | |
420 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); | |
421 | rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); | |
422 | rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); | |
423 | rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); | |
424 | ||
425 | /* | |
426 | * Write firmware to the device. | |
427 | */ | |
428 | rt2800_drv_write_firmware(rt2x00dev, data, len); | |
429 | ||
430 | /* | |
431 | * Wait for device to stabilize. | |
432 | */ | |
433 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
434 | rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, ®); | |
435 | if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY)) | |
436 | break; | |
437 | msleep(1); | |
438 | } | |
439 | ||
440 | if (i == REGISTER_BUSY_COUNT) { | |
441 | ERROR(rt2x00dev, "PBF system register not ready.\n"); | |
442 | return -EBUSY; | |
443 | } | |
444 | ||
445 | /* | |
446 | * Initialize firmware. | |
447 | */ | |
448 | rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); | |
449 | rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); | |
450 | msleep(1); | |
451 | ||
452 | return 0; | |
453 | } | |
454 | EXPORT_SYMBOL_GPL(rt2800_load_firmware); | |
455 | ||
0c5879bc ID |
456 | void rt2800_write_tx_data(struct queue_entry *entry, |
457 | struct txentry_desc *txdesc) | |
59679b91 | 458 | { |
0c5879bc | 459 | __le32 *txwi = rt2800_drv_get_txwi(entry); |
59679b91 GW |
460 | u32 word; |
461 | ||
462 | /* | |
463 | * Initialize TX Info descriptor | |
464 | */ | |
465 | rt2x00_desc_read(txwi, 0, &word); | |
466 | rt2x00_set_field32(&word, TXWI_W0_FRAG, | |
467 | test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); | |
84804cdc ID |
468 | rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, |
469 | test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags)); | |
59679b91 GW |
470 | rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0); |
471 | rt2x00_set_field32(&word, TXWI_W0_TS, | |
472 | test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); | |
473 | rt2x00_set_field32(&word, TXWI_W0_AMPDU, | |
474 | test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags)); | |
26a1d07f HS |
475 | rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, |
476 | txdesc->u.ht.mpdu_density); | |
477 | rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop); | |
478 | rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs); | |
59679b91 GW |
479 | rt2x00_set_field32(&word, TXWI_W0_BW, |
480 | test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags)); | |
481 | rt2x00_set_field32(&word, TXWI_W0_SHORT_GI, | |
482 | test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags)); | |
26a1d07f | 483 | rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc); |
59679b91 GW |
484 | rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode); |
485 | rt2x00_desc_write(txwi, 0, word); | |
486 | ||
487 | rt2x00_desc_read(txwi, 1, &word); | |
488 | rt2x00_set_field32(&word, TXWI_W1_ACK, | |
489 | test_bit(ENTRY_TXD_ACK, &txdesc->flags)); | |
490 | rt2x00_set_field32(&word, TXWI_W1_NSEQ, | |
491 | test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); | |
26a1d07f | 492 | rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size); |
59679b91 GW |
493 | rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, |
494 | test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ? | |
495 | txdesc->key_idx : 0xff); | |
496 | rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, | |
497 | txdesc->length); | |
2b23cdaa | 498 | rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid); |
bc8a979e | 499 | rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1); |
59679b91 GW |
500 | rt2x00_desc_write(txwi, 1, word); |
501 | ||
502 | /* | |
503 | * Always write 0 to IV/EIV fields, hardware will insert the IV | |
504 | * from the IVEIV register when TXD_W3_WIV is set to 0. | |
505 | * When TXD_W3_WIV is set to 1 it will use the IV data | |
506 | * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which | |
507 | * crypto entry in the registers should be used to encrypt the frame. | |
508 | */ | |
509 | _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */); | |
510 | _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */); | |
511 | } | |
0c5879bc | 512 | EXPORT_SYMBOL_GPL(rt2800_write_tx_data); |
59679b91 | 513 | |
ff6133be | 514 | static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2) |
2de64dd2 | 515 | { |
74861922 ID |
516 | int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0); |
517 | int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1); | |
518 | int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2); | |
519 | u16 eeprom; | |
520 | u8 offset0; | |
521 | u8 offset1; | |
522 | u8 offset2; | |
523 | ||
e5ef5bad | 524 | if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) { |
74861922 ID |
525 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom); |
526 | offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0); | |
527 | offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1); | |
528 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom); | |
529 | offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2); | |
530 | } else { | |
531 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom); | |
532 | offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0); | |
533 | offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1); | |
534 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom); | |
535 | offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2); | |
536 | } | |
537 | ||
538 | /* | |
539 | * Convert the value from the descriptor into the RSSI value | |
540 | * If the value in the descriptor is 0, it is considered invalid | |
541 | * and the default (extremely low) rssi value is assumed | |
542 | */ | |
543 | rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128; | |
544 | rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128; | |
545 | rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128; | |
546 | ||
547 | /* | |
548 | * mac80211 only accepts a single RSSI value. Calculating the | |
549 | * average doesn't deliver a fair answer either since -60:-60 would | |
550 | * be considered equally good as -50:-70 while the second is the one | |
551 | * which gives less energy... | |
552 | */ | |
553 | rssi0 = max(rssi0, rssi1); | |
554 | return max(rssi0, rssi2); | |
555 | } | |
556 | ||
557 | void rt2800_process_rxwi(struct queue_entry *entry, | |
558 | struct rxdone_entry_desc *rxdesc) | |
559 | { | |
560 | __le32 *rxwi = (__le32 *) entry->skb->data; | |
2de64dd2 GW |
561 | u32 word; |
562 | ||
563 | rt2x00_desc_read(rxwi, 0, &word); | |
564 | ||
565 | rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF); | |
566 | rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT); | |
567 | ||
568 | rt2x00_desc_read(rxwi, 1, &word); | |
569 | ||
570 | if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI)) | |
571 | rxdesc->flags |= RX_FLAG_SHORT_GI; | |
572 | ||
573 | if (rt2x00_get_field32(word, RXWI_W1_BW)) | |
574 | rxdesc->flags |= RX_FLAG_40MHZ; | |
575 | ||
576 | /* | |
577 | * Detect RX rate, always use MCS as signal type. | |
578 | */ | |
579 | rxdesc->dev_flags |= RXDONE_SIGNAL_MCS; | |
580 | rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS); | |
581 | rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE); | |
582 | ||
583 | /* | |
584 | * Mask of 0x8 bit to remove the short preamble flag. | |
585 | */ | |
586 | if (rxdesc->rate_mode == RATE_MODE_CCK) | |
587 | rxdesc->signal &= ~0x8; | |
588 | ||
589 | rt2x00_desc_read(rxwi, 2, &word); | |
590 | ||
74861922 ID |
591 | /* |
592 | * Convert descriptor AGC value to RSSI value. | |
593 | */ | |
594 | rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word); | |
2de64dd2 GW |
595 | |
596 | /* | |
597 | * Remove RXWI descriptor from start of buffer. | |
598 | */ | |
74861922 | 599 | skb_pull(entry->skb, RXWI_DESC_SIZE); |
2de64dd2 GW |
600 | } |
601 | EXPORT_SYMBOL_GPL(rt2800_process_rxwi); | |
602 | ||
3613884d ID |
603 | static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg) |
604 | { | |
605 | __le32 *txwi; | |
606 | u32 word; | |
607 | int wcid, ack, pid; | |
608 | int tx_wcid, tx_ack, tx_pid; | |
609 | ||
610 | wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID); | |
611 | ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED); | |
612 | pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE); | |
613 | ||
614 | /* | |
615 | * This frames has returned with an IO error, | |
616 | * so the status report is not intended for this | |
617 | * frame. | |
618 | */ | |
619 | if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) { | |
620 | rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE); | |
621 | return false; | |
622 | } | |
623 | ||
624 | /* | |
625 | * Validate if this TX status report is intended for | |
626 | * this entry by comparing the WCID/ACK/PID fields. | |
627 | */ | |
628 | txwi = rt2800_drv_get_txwi(entry); | |
629 | ||
630 | rt2x00_desc_read(txwi, 1, &word); | |
631 | tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID); | |
632 | tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK); | |
633 | tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID); | |
634 | ||
635 | if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid)) { | |
636 | WARNING(entry->queue->rt2x00dev, | |
637 | "TX status report missed for queue %d entry %d\n", | |
638 | entry->queue->qid, entry->entry_idx); | |
639 | rt2x00lib_txdone_noinfo(entry, TXDONE_UNKNOWN); | |
640 | return false; | |
641 | } | |
642 | ||
643 | return true; | |
644 | } | |
645 | ||
14433331 HS |
646 | void rt2800_txdone_entry(struct queue_entry *entry, u32 status) |
647 | { | |
648 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; | |
b34793ee | 649 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); |
14433331 HS |
650 | struct txdone_entry_desc txdesc; |
651 | u32 word; | |
652 | u16 mcs, real_mcs; | |
b34793ee | 653 | int aggr, ampdu; |
14433331 HS |
654 | __le32 *txwi; |
655 | ||
656 | /* | |
657 | * Obtain the status about this packet. | |
658 | */ | |
659 | txdesc.flags = 0; | |
660 | txwi = rt2800_drv_get_txwi(entry); | |
661 | rt2x00_desc_read(txwi, 0, &word); | |
b34793ee | 662 | |
14433331 | 663 | mcs = rt2x00_get_field32(word, TXWI_W0_MCS); |
b34793ee HS |
664 | ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU); |
665 | ||
14433331 | 666 | real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS); |
b34793ee HS |
667 | aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE); |
668 | ||
669 | /* | |
670 | * If a frame was meant to be sent as a single non-aggregated MPDU | |
671 | * but ended up in an aggregate the used tx rate doesn't correlate | |
672 | * with the one specified in the TXWI as the whole aggregate is sent | |
673 | * with the same rate. | |
674 | * | |
675 | * For example: two frames are sent to rt2x00, the first one sets | |
676 | * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0 | |
677 | * and requests MCS15. If the hw aggregates both frames into one | |
678 | * AMDPU the tx status for both frames will contain MCS7 although | |
679 | * the frame was sent successfully. | |
680 | * | |
681 | * Hence, replace the requested rate with the real tx rate to not | |
682 | * confuse the rate control algortihm by providing clearly wrong | |
683 | * data. | |
684 | */ | |
5356d963 | 685 | if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) { |
b34793ee HS |
686 | skbdesc->tx_rate_idx = real_mcs; |
687 | mcs = real_mcs; | |
688 | } | |
14433331 | 689 | |
f16d2db7 HS |
690 | if (aggr == 1 || ampdu == 1) |
691 | __set_bit(TXDONE_AMPDU, &txdesc.flags); | |
692 | ||
14433331 HS |
693 | /* |
694 | * Ralink has a retry mechanism using a global fallback | |
695 | * table. We setup this fallback table to try the immediate | |
696 | * lower rate for all rates. In the TX_STA_FIFO, the MCS field | |
697 | * always contains the MCS used for the last transmission, be | |
698 | * it successful or not. | |
699 | */ | |
700 | if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) { | |
701 | /* | |
702 | * Transmission succeeded. The number of retries is | |
703 | * mcs - real_mcs | |
704 | */ | |
705 | __set_bit(TXDONE_SUCCESS, &txdesc.flags); | |
706 | txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0); | |
707 | } else { | |
708 | /* | |
709 | * Transmission failed. The number of retries is | |
710 | * always 7 in this case (for a total number of 8 | |
711 | * frames sent). | |
712 | */ | |
713 | __set_bit(TXDONE_FAILURE, &txdesc.flags); | |
714 | txdesc.retry = rt2x00dev->long_retry; | |
715 | } | |
716 | ||
717 | /* | |
718 | * the frame was retried at least once | |
719 | * -> hw used fallback rates | |
720 | */ | |
721 | if (txdesc.retry) | |
722 | __set_bit(TXDONE_FALLBACK, &txdesc.flags); | |
723 | ||
724 | rt2x00lib_txdone(entry, &txdesc); | |
725 | } | |
726 | EXPORT_SYMBOL_GPL(rt2800_txdone_entry); | |
727 | ||
96481b20 ID |
728 | void rt2800_txdone(struct rt2x00_dev *rt2x00dev) |
729 | { | |
730 | struct data_queue *queue; | |
731 | struct queue_entry *entry; | |
96481b20 | 732 | u32 reg; |
0e0d39e5 | 733 | u8 qid; |
96481b20 | 734 | |
0e0d39e5 | 735 | while (kfifo_get(&rt2x00dev->txstatus_fifo, ®)) { |
96481b20 | 736 | |
0e0d39e5 JS |
737 | /* TX_STA_FIFO_PID_QUEUE is a 2-bit field, thus |
738 | * qid is guaranteed to be one of the TX QIDs | |
96481b20 | 739 | */ |
0e0d39e5 JS |
740 | qid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE); |
741 | queue = rt2x00queue_get_tx_queue(rt2x00dev, qid); | |
742 | if (unlikely(!queue)) { | |
743 | WARNING(rt2x00dev, "Got TX status for an unavailable " | |
744 | "queue %u, dropping\n", qid); | |
96481b20 | 745 | continue; |
0e0d39e5 | 746 | } |
96481b20 ID |
747 | |
748 | /* | |
749 | * Inside each queue, we process each entry in a chronological | |
750 | * order. We first check that the queue is not empty. | |
751 | */ | |
752 | entry = NULL; | |
753 | while (!rt2x00queue_empty(queue)) { | |
754 | entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); | |
3613884d | 755 | if (rt2800_txdone_entry_check(entry, reg)) |
96481b20 | 756 | break; |
96481b20 ID |
757 | } |
758 | ||
759 | if (!entry || rt2x00queue_empty(queue)) | |
760 | break; | |
761 | ||
14433331 | 762 | rt2800_txdone_entry(entry, reg); |
96481b20 ID |
763 | } |
764 | } | |
765 | EXPORT_SYMBOL_GPL(rt2800_txdone); | |
766 | ||
f0194b2d GW |
767 | void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc) |
768 | { | |
769 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; | |
770 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); | |
771 | unsigned int beacon_base; | |
739fd940 | 772 | unsigned int padding_len; |
d76dfc61 | 773 | u32 orig_reg, reg; |
f0194b2d GW |
774 | |
775 | /* | |
776 | * Disable beaconing while we are reloading the beacon data, | |
777 | * otherwise we might be sending out invalid data. | |
778 | */ | |
779 | rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); | |
d76dfc61 | 780 | orig_reg = reg; |
f0194b2d GW |
781 | rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); |
782 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); | |
783 | ||
784 | /* | |
785 | * Add space for the TXWI in front of the skb. | |
786 | */ | |
787 | skb_push(entry->skb, TXWI_DESC_SIZE); | |
788 | memset(entry->skb, 0, TXWI_DESC_SIZE); | |
789 | ||
790 | /* | |
791 | * Register descriptor details in skb frame descriptor. | |
792 | */ | |
793 | skbdesc->flags |= SKBDESC_DESC_IN_SKB; | |
794 | skbdesc->desc = entry->skb->data; | |
795 | skbdesc->desc_len = TXWI_DESC_SIZE; | |
796 | ||
797 | /* | |
798 | * Add the TXWI for the beacon to the skb. | |
799 | */ | |
0c5879bc | 800 | rt2800_write_tx_data(entry, txdesc); |
f0194b2d GW |
801 | |
802 | /* | |
803 | * Dump beacon to userspace through debugfs. | |
804 | */ | |
805 | rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb); | |
806 | ||
807 | /* | |
739fd940 | 808 | * Write entire beacon with TXWI and padding to register. |
f0194b2d | 809 | */ |
739fd940 | 810 | padding_len = roundup(entry->skb->len, 4) - entry->skb->len; |
d76dfc61 SF |
811 | if (padding_len && skb_pad(entry->skb, padding_len)) { |
812 | ERROR(rt2x00dev, "Failure padding beacon, aborting\n"); | |
813 | /* skb freed by skb_pad() on failure */ | |
814 | entry->skb = NULL; | |
815 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); | |
816 | return; | |
817 | } | |
818 | ||
f0194b2d | 819 | beacon_base = HW_BEACON_OFFSET(entry->entry_idx); |
739fd940 WK |
820 | rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data, |
821 | entry->skb->len + padding_len); | |
f0194b2d GW |
822 | |
823 | /* | |
824 | * Enable beaconing again. | |
825 | */ | |
f0194b2d GW |
826 | rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 1); |
827 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); | |
828 | ||
829 | /* | |
830 | * Clean up beacon skb. | |
831 | */ | |
832 | dev_kfree_skb_any(entry->skb); | |
833 | entry->skb = NULL; | |
834 | } | |
50e888ea | 835 | EXPORT_SYMBOL_GPL(rt2800_write_beacon); |
f0194b2d | 836 | |
69cf36a4 HS |
837 | static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev, |
838 | unsigned int beacon_base) | |
fdb87251 HS |
839 | { |
840 | int i; | |
841 | ||
842 | /* | |
843 | * For the Beacon base registers we only need to clear | |
844 | * the whole TXWI which (when set to 0) will invalidate | |
845 | * the entire beacon. | |
846 | */ | |
847 | for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32)) | |
848 | rt2800_register_write(rt2x00dev, beacon_base + i, 0); | |
849 | } | |
850 | ||
69cf36a4 HS |
851 | void rt2800_clear_beacon(struct queue_entry *entry) |
852 | { | |
853 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; | |
854 | u32 reg; | |
855 | ||
856 | /* | |
857 | * Disable beaconing while we are reloading the beacon data, | |
858 | * otherwise we might be sending out invalid data. | |
859 | */ | |
860 | rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); | |
861 | rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); | |
862 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); | |
863 | ||
864 | /* | |
865 | * Clear beacon. | |
866 | */ | |
867 | rt2800_clear_beacon_register(rt2x00dev, | |
868 | HW_BEACON_OFFSET(entry->entry_idx)); | |
869 | ||
870 | /* | |
871 | * Enabled beaconing again. | |
872 | */ | |
873 | rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 1); | |
874 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); | |
875 | } | |
876 | EXPORT_SYMBOL_GPL(rt2800_clear_beacon); | |
877 | ||
f4450616 BZ |
878 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS |
879 | const struct rt2x00debug rt2800_rt2x00debug = { | |
880 | .owner = THIS_MODULE, | |
881 | .csr = { | |
882 | .read = rt2800_register_read, | |
883 | .write = rt2800_register_write, | |
884 | .flags = RT2X00DEBUGFS_OFFSET, | |
885 | .word_base = CSR_REG_BASE, | |
886 | .word_size = sizeof(u32), | |
887 | .word_count = CSR_REG_SIZE / sizeof(u32), | |
888 | }, | |
889 | .eeprom = { | |
890 | .read = rt2x00_eeprom_read, | |
891 | .write = rt2x00_eeprom_write, | |
892 | .word_base = EEPROM_BASE, | |
893 | .word_size = sizeof(u16), | |
894 | .word_count = EEPROM_SIZE / sizeof(u16), | |
895 | }, | |
896 | .bbp = { | |
897 | .read = rt2800_bbp_read, | |
898 | .write = rt2800_bbp_write, | |
899 | .word_base = BBP_BASE, | |
900 | .word_size = sizeof(u8), | |
901 | .word_count = BBP_SIZE / sizeof(u8), | |
902 | }, | |
903 | .rf = { | |
904 | .read = rt2x00_rf_read, | |
905 | .write = rt2800_rf_write, | |
906 | .word_base = RF_BASE, | |
907 | .word_size = sizeof(u32), | |
908 | .word_count = RF_SIZE / sizeof(u32), | |
909 | }, | |
910 | }; | |
911 | EXPORT_SYMBOL_GPL(rt2800_rt2x00debug); | |
912 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ | |
913 | ||
914 | int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev) | |
915 | { | |
916 | u32 reg; | |
917 | ||
918 | rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, ®); | |
919 | return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2); | |
920 | } | |
921 | EXPORT_SYMBOL_GPL(rt2800_rfkill_poll); | |
922 | ||
923 | #ifdef CONFIG_RT2X00_LIB_LEDS | |
924 | static void rt2800_brightness_set(struct led_classdev *led_cdev, | |
925 | enum led_brightness brightness) | |
926 | { | |
927 | struct rt2x00_led *led = | |
928 | container_of(led_cdev, struct rt2x00_led, led_dev); | |
929 | unsigned int enabled = brightness != LED_OFF; | |
930 | unsigned int bg_mode = | |
931 | (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ); | |
932 | unsigned int polarity = | |
933 | rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, | |
934 | EEPROM_FREQ_LED_POLARITY); | |
935 | unsigned int ledmode = | |
936 | rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, | |
937 | EEPROM_FREQ_LED_MODE); | |
44704e5d | 938 | u32 reg; |
f4450616 | 939 | |
44704e5d LE |
940 | /* Check for SoC (SOC devices don't support MCU requests) */ |
941 | if (rt2x00_is_soc(led->rt2x00dev)) { | |
942 | rt2800_register_read(led->rt2x00dev, LED_CFG, ®); | |
943 | ||
944 | /* Set LED Polarity */ | |
945 | rt2x00_set_field32(®, LED_CFG_LED_POLAR, polarity); | |
946 | ||
947 | /* Set LED Mode */ | |
948 | if (led->type == LED_TYPE_RADIO) { | |
949 | rt2x00_set_field32(®, LED_CFG_G_LED_MODE, | |
950 | enabled ? 3 : 0); | |
951 | } else if (led->type == LED_TYPE_ASSOC) { | |
952 | rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, | |
953 | enabled ? 3 : 0); | |
954 | } else if (led->type == LED_TYPE_QUALITY) { | |
955 | rt2x00_set_field32(®, LED_CFG_R_LED_MODE, | |
956 | enabled ? 3 : 0); | |
957 | } | |
958 | ||
959 | rt2800_register_write(led->rt2x00dev, LED_CFG, reg); | |
960 | ||
961 | } else { | |
962 | if (led->type == LED_TYPE_RADIO) { | |
963 | rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, | |
964 | enabled ? 0x20 : 0); | |
965 | } else if (led->type == LED_TYPE_ASSOC) { | |
966 | rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, | |
967 | enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20); | |
968 | } else if (led->type == LED_TYPE_QUALITY) { | |
969 | /* | |
970 | * The brightness is divided into 6 levels (0 - 5), | |
971 | * The specs tell us the following levels: | |
972 | * 0, 1 ,3, 7, 15, 31 | |
973 | * to determine the level in a simple way we can simply | |
974 | * work with bitshifting: | |
975 | * (1 << level) - 1 | |
976 | */ | |
977 | rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff, | |
978 | (1 << brightness / (LED_FULL / 6)) - 1, | |
979 | polarity); | |
980 | } | |
f4450616 BZ |
981 | } |
982 | } | |
983 | ||
984 | static int rt2800_blink_set(struct led_classdev *led_cdev, | |
985 | unsigned long *delay_on, unsigned long *delay_off) | |
986 | { | |
987 | struct rt2x00_led *led = | |
988 | container_of(led_cdev, struct rt2x00_led, led_dev); | |
989 | u32 reg; | |
990 | ||
991 | rt2800_register_read(led->rt2x00dev, LED_CFG, ®); | |
992 | rt2x00_set_field32(®, LED_CFG_ON_PERIOD, *delay_on); | |
993 | rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, *delay_off); | |
f4450616 BZ |
994 | rt2800_register_write(led->rt2x00dev, LED_CFG, reg); |
995 | ||
996 | return 0; | |
997 | } | |
998 | ||
b3579d6a | 999 | static void rt2800_init_led(struct rt2x00_dev *rt2x00dev, |
f4450616 BZ |
1000 | struct rt2x00_led *led, enum led_type type) |
1001 | { | |
1002 | led->rt2x00dev = rt2x00dev; | |
1003 | led->type = type; | |
1004 | led->led_dev.brightness_set = rt2800_brightness_set; | |
1005 | led->led_dev.blink_set = rt2800_blink_set; | |
1006 | led->flags = LED_INITIALIZED; | |
1007 | } | |
f4450616 BZ |
1008 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
1009 | ||
1010 | /* | |
1011 | * Configuration handlers. | |
1012 | */ | |
1013 | static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev, | |
1014 | struct rt2x00lib_crypto *crypto, | |
1015 | struct ieee80211_key_conf *key) | |
1016 | { | |
1017 | struct mac_wcid_entry wcid_entry; | |
1018 | struct mac_iveiv_entry iveiv_entry; | |
1019 | u32 offset; | |
1020 | u32 reg; | |
1021 | ||
1022 | offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx); | |
1023 | ||
e4a0ab34 ID |
1024 | if (crypto->cmd == SET_KEY) { |
1025 | rt2800_register_read(rt2x00dev, offset, ®); | |
1026 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, | |
1027 | !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); | |
1028 | /* | |
1029 | * Both the cipher as the BSS Idx numbers are split in a main | |
1030 | * value of 3 bits, and a extended field for adding one additional | |
1031 | * bit to the value. | |
1032 | */ | |
1033 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, | |
1034 | (crypto->cipher & 0x7)); | |
1035 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, | |
1036 | (crypto->cipher & 0x8) >> 3); | |
1037 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, | |
1038 | (crypto->bssidx & 0x7)); | |
1039 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT, | |
1040 | (crypto->bssidx & 0x8) >> 3); | |
1041 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher); | |
1042 | rt2800_register_write(rt2x00dev, offset, reg); | |
1043 | } else { | |
1044 | rt2800_register_write(rt2x00dev, offset, 0); | |
1045 | } | |
f4450616 BZ |
1046 | |
1047 | offset = MAC_IVEIV_ENTRY(key->hw_key_idx); | |
1048 | ||
1049 | memset(&iveiv_entry, 0, sizeof(iveiv_entry)); | |
1050 | if ((crypto->cipher == CIPHER_TKIP) || | |
1051 | (crypto->cipher == CIPHER_TKIP_NO_MIC) || | |
1052 | (crypto->cipher == CIPHER_AES)) | |
1053 | iveiv_entry.iv[3] |= 0x20; | |
1054 | iveiv_entry.iv[3] |= key->keyidx << 6; | |
1055 | rt2800_register_multiwrite(rt2x00dev, offset, | |
1056 | &iveiv_entry, sizeof(iveiv_entry)); | |
1057 | ||
1058 | offset = MAC_WCID_ENTRY(key->hw_key_idx); | |
1059 | ||
1060 | memset(&wcid_entry, 0, sizeof(wcid_entry)); | |
1061 | if (crypto->cmd == SET_KEY) | |
10026f77 | 1062 | memcpy(wcid_entry.mac, crypto->address, ETH_ALEN); |
f4450616 BZ |
1063 | rt2800_register_multiwrite(rt2x00dev, offset, |
1064 | &wcid_entry, sizeof(wcid_entry)); | |
1065 | } | |
1066 | ||
1067 | int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev, | |
1068 | struct rt2x00lib_crypto *crypto, | |
1069 | struct ieee80211_key_conf *key) | |
1070 | { | |
1071 | struct hw_key_entry key_entry; | |
1072 | struct rt2x00_field32 field; | |
1073 | u32 offset; | |
1074 | u32 reg; | |
1075 | ||
1076 | if (crypto->cmd == SET_KEY) { | |
1077 | key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx; | |
1078 | ||
1079 | memcpy(key_entry.key, crypto->key, | |
1080 | sizeof(key_entry.key)); | |
1081 | memcpy(key_entry.tx_mic, crypto->tx_mic, | |
1082 | sizeof(key_entry.tx_mic)); | |
1083 | memcpy(key_entry.rx_mic, crypto->rx_mic, | |
1084 | sizeof(key_entry.rx_mic)); | |
1085 | ||
1086 | offset = SHARED_KEY_ENTRY(key->hw_key_idx); | |
1087 | rt2800_register_multiwrite(rt2x00dev, offset, | |
1088 | &key_entry, sizeof(key_entry)); | |
1089 | } | |
1090 | ||
1091 | /* | |
1092 | * The cipher types are stored over multiple registers | |
1093 | * starting with SHARED_KEY_MODE_BASE each word will have | |
1094 | * 32 bits and contains the cipher types for 2 bssidx each. | |
1095 | * Using the correct defines correctly will cause overhead, | |
1096 | * so just calculate the correct offset. | |
1097 | */ | |
1098 | field.bit_offset = 4 * (key->hw_key_idx % 8); | |
1099 | field.bit_mask = 0x7 << field.bit_offset; | |
1100 | ||
1101 | offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8); | |
1102 | ||
1103 | rt2800_register_read(rt2x00dev, offset, ®); | |
1104 | rt2x00_set_field32(®, field, | |
1105 | (crypto->cmd == SET_KEY) * crypto->cipher); | |
1106 | rt2800_register_write(rt2x00dev, offset, reg); | |
1107 | ||
1108 | /* | |
1109 | * Update WCID information | |
1110 | */ | |
1111 | rt2800_config_wcid_attr(rt2x00dev, crypto, key); | |
1112 | ||
1113 | return 0; | |
1114 | } | |
1115 | EXPORT_SYMBOL_GPL(rt2800_config_shared_key); | |
1116 | ||
1ed3811c HS |
1117 | static inline int rt2800_find_pairwise_keyslot(struct rt2x00_dev *rt2x00dev) |
1118 | { | |
1119 | int idx; | |
1120 | u32 offset, reg; | |
1121 | ||
1122 | /* | |
1123 | * Search for the first free pairwise key entry and return the | |
1124 | * corresponding index. | |
1125 | * | |
1126 | * Make sure the WCID starts _after_ the last possible shared key | |
1127 | * entry (>32). | |
1128 | * | |
1129 | * Since parts of the pairwise key table might be shared with | |
1130 | * the beacon frame buffers 6 & 7 we should only write into the | |
1131 | * first 222 entries. | |
1132 | */ | |
1133 | for (idx = 33; idx <= 222; idx++) { | |
1134 | offset = MAC_WCID_ATTR_ENTRY(idx); | |
1135 | rt2800_register_read(rt2x00dev, offset, ®); | |
1136 | if (!reg) | |
1137 | return idx; | |
1138 | } | |
1139 | return -1; | |
1140 | } | |
1141 | ||
f4450616 BZ |
1142 | int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev, |
1143 | struct rt2x00lib_crypto *crypto, | |
1144 | struct ieee80211_key_conf *key) | |
1145 | { | |
1146 | struct hw_key_entry key_entry; | |
1147 | u32 offset; | |
1ed3811c | 1148 | int idx; |
f4450616 BZ |
1149 | |
1150 | if (crypto->cmd == SET_KEY) { | |
1ed3811c HS |
1151 | idx = rt2800_find_pairwise_keyslot(rt2x00dev); |
1152 | if (idx < 0) | |
f4450616 | 1153 | return -ENOSPC; |
1ed3811c | 1154 | key->hw_key_idx = idx; |
f4450616 BZ |
1155 | |
1156 | memcpy(key_entry.key, crypto->key, | |
1157 | sizeof(key_entry.key)); | |
1158 | memcpy(key_entry.tx_mic, crypto->tx_mic, | |
1159 | sizeof(key_entry.tx_mic)); | |
1160 | memcpy(key_entry.rx_mic, crypto->rx_mic, | |
1161 | sizeof(key_entry.rx_mic)); | |
1162 | ||
1163 | offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx); | |
1164 | rt2800_register_multiwrite(rt2x00dev, offset, | |
1165 | &key_entry, sizeof(key_entry)); | |
1166 | } | |
1167 | ||
1168 | /* | |
1169 | * Update WCID information | |
1170 | */ | |
1171 | rt2800_config_wcid_attr(rt2x00dev, crypto, key); | |
1172 | ||
1173 | return 0; | |
1174 | } | |
1175 | EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key); | |
1176 | ||
1177 | void rt2800_config_filter(struct rt2x00_dev *rt2x00dev, | |
1178 | const unsigned int filter_flags) | |
1179 | { | |
1180 | u32 reg; | |
1181 | ||
1182 | /* | |
1183 | * Start configuration steps. | |
1184 | * Note that the version error will always be dropped | |
1185 | * and broadcast frames will always be accepted since | |
1186 | * there is no filter for it at this time. | |
1187 | */ | |
1188 | rt2800_register_read(rt2x00dev, RX_FILTER_CFG, ®); | |
1189 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR, | |
1190 | !(filter_flags & FIF_FCSFAIL)); | |
1191 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR, | |
1192 | !(filter_flags & FIF_PLCPFAIL)); | |
1193 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME, | |
1194 | !(filter_flags & FIF_PROMISC_IN_BSS)); | |
1195 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0); | |
1196 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1); | |
1197 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST, | |
1198 | !(filter_flags & FIF_ALLMULTI)); | |
1199 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0); | |
1200 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1); | |
1201 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK, | |
1202 | !(filter_flags & FIF_CONTROL)); | |
1203 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END, | |
1204 | !(filter_flags & FIF_CONTROL)); | |
1205 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK, | |
1206 | !(filter_flags & FIF_CONTROL)); | |
1207 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS, | |
1208 | !(filter_flags & FIF_CONTROL)); | |
1209 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS, | |
1210 | !(filter_flags & FIF_CONTROL)); | |
1211 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL, | |
1212 | !(filter_flags & FIF_PSPOLL)); | |
1213 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA, 1); | |
1214 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR, 0); | |
1215 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL, | |
1216 | !(filter_flags & FIF_CONTROL)); | |
1217 | rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg); | |
1218 | } | |
1219 | EXPORT_SYMBOL_GPL(rt2800_config_filter); | |
1220 | ||
1221 | void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf, | |
1222 | struct rt2x00intf_conf *conf, const unsigned int flags) | |
1223 | { | |
f4450616 | 1224 | u32 reg; |
fa8b4b22 | 1225 | bool update_bssid = false; |
f4450616 BZ |
1226 | |
1227 | if (flags & CONFIG_UPDATE_TYPE) { | |
f4450616 BZ |
1228 | /* |
1229 | * Enable synchronisation. | |
1230 | */ | |
1231 | rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); | |
f4450616 | 1232 | rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync); |
f4450616 | 1233 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); |
15a533c4 HS |
1234 | |
1235 | if (conf->sync == TSF_SYNC_AP_NONE) { | |
1236 | /* | |
1237 | * Tune beacon queue transmit parameters for AP mode | |
1238 | */ | |
1239 | rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, ®); | |
1240 | rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 0); | |
1241 | rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 1); | |
1242 | rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); | |
1243 | rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 0); | |
1244 | rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); | |
1245 | } else { | |
1246 | rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, ®); | |
1247 | rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 4); | |
1248 | rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 2); | |
1249 | rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); | |
1250 | rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 16); | |
1251 | rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); | |
1252 | } | |
f4450616 BZ |
1253 | } |
1254 | ||
1255 | if (flags & CONFIG_UPDATE_MAC) { | |
fa8b4b22 HS |
1256 | if (flags & CONFIG_UPDATE_TYPE && |
1257 | conf->sync == TSF_SYNC_AP_NONE) { | |
1258 | /* | |
1259 | * The BSSID register has to be set to our own mac | |
1260 | * address in AP mode. | |
1261 | */ | |
1262 | memcpy(conf->bssid, conf->mac, sizeof(conf->mac)); | |
1263 | update_bssid = true; | |
1264 | } | |
1265 | ||
c600c826 ID |
1266 | if (!is_zero_ether_addr((const u8 *)conf->mac)) { |
1267 | reg = le32_to_cpu(conf->mac[1]); | |
1268 | rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff); | |
1269 | conf->mac[1] = cpu_to_le32(reg); | |
1270 | } | |
f4450616 BZ |
1271 | |
1272 | rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0, | |
1273 | conf->mac, sizeof(conf->mac)); | |
1274 | } | |
1275 | ||
fa8b4b22 | 1276 | if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) { |
c600c826 ID |
1277 | if (!is_zero_ether_addr((const u8 *)conf->bssid)) { |
1278 | reg = le32_to_cpu(conf->bssid[1]); | |
1279 | rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 3); | |
1280 | rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 7); | |
1281 | conf->bssid[1] = cpu_to_le32(reg); | |
1282 | } | |
f4450616 BZ |
1283 | |
1284 | rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0, | |
1285 | conf->bssid, sizeof(conf->bssid)); | |
1286 | } | |
1287 | } | |
1288 | EXPORT_SYMBOL_GPL(rt2800_config_intf); | |
1289 | ||
87c1915d HS |
1290 | static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev, |
1291 | struct rt2x00lib_erp *erp) | |
1292 | { | |
1293 | bool any_sta_nongf = !!(erp->ht_opmode & | |
1294 | IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT); | |
1295 | u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION; | |
1296 | u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode; | |
1297 | u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate; | |
1298 | u32 reg; | |
1299 | ||
1300 | /* default protection rate for HT20: OFDM 24M */ | |
1301 | mm20_rate = gf20_rate = 0x4004; | |
1302 | ||
1303 | /* default protection rate for HT40: duplicate OFDM 24M */ | |
1304 | mm40_rate = gf40_rate = 0x4084; | |
1305 | ||
1306 | switch (protection) { | |
1307 | case IEEE80211_HT_OP_MODE_PROTECTION_NONE: | |
1308 | /* | |
1309 | * All STAs in this BSS are HT20/40 but there might be | |
1310 | * STAs not supporting greenfield mode. | |
1311 | * => Disable protection for HT transmissions. | |
1312 | */ | |
1313 | mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0; | |
1314 | ||
1315 | break; | |
1316 | case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ: | |
1317 | /* | |
1318 | * All STAs in this BSS are HT20 or HT20/40 but there | |
1319 | * might be STAs not supporting greenfield mode. | |
1320 | * => Protect all HT40 transmissions. | |
1321 | */ | |
1322 | mm20_mode = gf20_mode = 0; | |
1323 | mm40_mode = gf40_mode = 2; | |
1324 | ||
1325 | break; | |
1326 | case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER: | |
1327 | /* | |
1328 | * Nonmember protection: | |
1329 | * According to 802.11n we _should_ protect all | |
1330 | * HT transmissions (but we don't have to). | |
1331 | * | |
1332 | * But if cts_protection is enabled we _shall_ protect | |
1333 | * all HT transmissions using a CCK rate. | |
1334 | * | |
1335 | * And if any station is non GF we _shall_ protect | |
1336 | * GF transmissions. | |
1337 | * | |
1338 | * We decide to protect everything | |
1339 | * -> fall through to mixed mode. | |
1340 | */ | |
1341 | case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED: | |
1342 | /* | |
1343 | * Legacy STAs are present | |
1344 | * => Protect all HT transmissions. | |
1345 | */ | |
1346 | mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2; | |
1347 | ||
1348 | /* | |
1349 | * If erp protection is needed we have to protect HT | |
1350 | * transmissions with CCK 11M long preamble. | |
1351 | */ | |
1352 | if (erp->cts_protection) { | |
1353 | /* don't duplicate RTS/CTS in CCK mode */ | |
1354 | mm20_rate = mm40_rate = 0x0003; | |
1355 | gf20_rate = gf40_rate = 0x0003; | |
1356 | } | |
1357 | break; | |
1358 | }; | |
1359 | ||
1360 | /* check for STAs not supporting greenfield mode */ | |
1361 | if (any_sta_nongf) | |
1362 | gf20_mode = gf40_mode = 2; | |
1363 | ||
1364 | /* Update HT protection config */ | |
1365 | rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); | |
1366 | rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, mm20_rate); | |
1367 | rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode); | |
1368 | rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); | |
1369 | ||
1370 | rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); | |
1371 | rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, mm40_rate); | |
1372 | rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode); | |
1373 | rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); | |
1374 | ||
1375 | rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); | |
1376 | rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, gf20_rate); | |
1377 | rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode); | |
1378 | rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); | |
1379 | ||
1380 | rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); | |
1381 | rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, gf40_rate); | |
1382 | rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode); | |
1383 | rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); | |
1384 | } | |
1385 | ||
02044643 HS |
1386 | void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp, |
1387 | u32 changed) | |
f4450616 BZ |
1388 | { |
1389 | u32 reg; | |
1390 | ||
02044643 HS |
1391 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
1392 | rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®); | |
1393 | rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, | |
1394 | !!erp->short_preamble); | |
1395 | rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, | |
1396 | !!erp->short_preamble); | |
1397 | rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); | |
1398 | } | |
f4450616 | 1399 | |
02044643 HS |
1400 | if (changed & BSS_CHANGED_ERP_CTS_PROT) { |
1401 | rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); | |
1402 | rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, | |
1403 | erp->cts_protection ? 2 : 0); | |
1404 | rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); | |
1405 | } | |
f4450616 | 1406 | |
02044643 HS |
1407 | if (changed & BSS_CHANGED_BASIC_RATES) { |
1408 | rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, | |
1409 | erp->basic_rates); | |
1410 | rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); | |
1411 | } | |
f4450616 | 1412 | |
02044643 HS |
1413 | if (changed & BSS_CHANGED_ERP_SLOT) { |
1414 | rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®); | |
1415 | rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, | |
1416 | erp->slot_time); | |
1417 | rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); | |
f4450616 | 1418 | |
02044643 HS |
1419 | rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, ®); |
1420 | rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs); | |
1421 | rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); | |
1422 | } | |
f4450616 | 1423 | |
02044643 HS |
1424 | if (changed & BSS_CHANGED_BEACON_INT) { |
1425 | rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); | |
1426 | rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, | |
1427 | erp->beacon_int * 16); | |
1428 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); | |
1429 | } | |
87c1915d HS |
1430 | |
1431 | if (changed & BSS_CHANGED_HT) | |
1432 | rt2800_config_ht_opmode(rt2x00dev, erp); | |
f4450616 BZ |
1433 | } |
1434 | EXPORT_SYMBOL_GPL(rt2800_config_erp); | |
1435 | ||
d96aa640 RJH |
1436 | static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev, |
1437 | enum antenna ant) | |
1438 | { | |
1439 | u32 reg; | |
1440 | u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0; | |
1441 | u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1; | |
1442 | ||
1443 | if (rt2x00_is_pci(rt2x00dev)) { | |
1444 | rt2800_register_read(rt2x00dev, E2PROM_CSR, ®); | |
1445 | rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, eesk_pin); | |
1446 | rt2800_register_write(rt2x00dev, E2PROM_CSR, reg); | |
1447 | } else if (rt2x00_is_usb(rt2x00dev)) | |
1448 | rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff, | |
1449 | eesk_pin, 0); | |
1450 | ||
1451 | rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, ®); | |
fe59147c | 1452 | rt2x00_set_field32(®, GPIO_CTRL_CFG_GPIOD_BIT3, 0); |
d96aa640 RJH |
1453 | rt2x00_set_field32(®, GPIO_CTRL_CFG_BIT3, gpio_bit3); |
1454 | rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg); | |
1455 | } | |
1456 | ||
f4450616 BZ |
1457 | void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) |
1458 | { | |
1459 | u8 r1; | |
1460 | u8 r3; | |
d96aa640 | 1461 | u16 eeprom; |
f4450616 BZ |
1462 | |
1463 | rt2800_bbp_read(rt2x00dev, 1, &r1); | |
1464 | rt2800_bbp_read(rt2x00dev, 3, &r3); | |
1465 | ||
1466 | /* | |
1467 | * Configure the TX antenna. | |
1468 | */ | |
d96aa640 | 1469 | switch (ant->tx_chain_num) { |
f4450616 BZ |
1470 | case 1: |
1471 | rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0); | |
f4450616 BZ |
1472 | break; |
1473 | case 2: | |
1474 | rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); | |
1475 | break; | |
1476 | case 3: | |
e22557f2 | 1477 | rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0); |
f4450616 BZ |
1478 | break; |
1479 | } | |
1480 | ||
1481 | /* | |
1482 | * Configure the RX antenna. | |
1483 | */ | |
d96aa640 | 1484 | switch (ant->rx_chain_num) { |
f4450616 | 1485 | case 1: |
d96aa640 RJH |
1486 | if (rt2x00_rt(rt2x00dev, RT3070) || |
1487 | rt2x00_rt(rt2x00dev, RT3090) || | |
1488 | rt2x00_rt(rt2x00dev, RT3390)) { | |
1489 | rt2x00_eeprom_read(rt2x00dev, | |
1490 | EEPROM_NIC_CONF1, &eeprom); | |
1491 | if (rt2x00_get_field16(eeprom, | |
1492 | EEPROM_NIC_CONF1_ANT_DIVERSITY)) | |
1493 | rt2800_set_ant_diversity(rt2x00dev, | |
1494 | rt2x00dev->default_ant.rx); | |
1495 | } | |
f4450616 BZ |
1496 | rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0); |
1497 | break; | |
1498 | case 2: | |
1499 | rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1); | |
1500 | break; | |
1501 | case 3: | |
1502 | rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2); | |
1503 | break; | |
1504 | } | |
1505 | ||
1506 | rt2800_bbp_write(rt2x00dev, 3, r3); | |
1507 | rt2800_bbp_write(rt2x00dev, 1, r1); | |
1508 | } | |
1509 | EXPORT_SYMBOL_GPL(rt2800_config_ant); | |
1510 | ||
1511 | static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev, | |
1512 | struct rt2x00lib_conf *libconf) | |
1513 | { | |
1514 | u16 eeprom; | |
1515 | short lna_gain; | |
1516 | ||
1517 | if (libconf->rf.channel <= 14) { | |
1518 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom); | |
1519 | lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG); | |
1520 | } else if (libconf->rf.channel <= 64) { | |
1521 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom); | |
1522 | lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0); | |
1523 | } else if (libconf->rf.channel <= 128) { | |
1524 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom); | |
1525 | lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1); | |
1526 | } else { | |
1527 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom); | |
1528 | lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2); | |
1529 | } | |
1530 | ||
1531 | rt2x00dev->lna_gain = lna_gain; | |
1532 | } | |
1533 | ||
06855ef4 GW |
1534 | static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev, |
1535 | struct ieee80211_conf *conf, | |
1536 | struct rf_channel *rf, | |
1537 | struct channel_info *info) | |
f4450616 BZ |
1538 | { |
1539 | rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); | |
1540 | ||
d96aa640 | 1541 | if (rt2x00dev->default_ant.tx_chain_num == 1) |
f4450616 BZ |
1542 | rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1); |
1543 | ||
d96aa640 | 1544 | if (rt2x00dev->default_ant.rx_chain_num == 1) { |
f4450616 BZ |
1545 | rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1); |
1546 | rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); | |
d96aa640 | 1547 | } else if (rt2x00dev->default_ant.rx_chain_num == 2) |
f4450616 BZ |
1548 | rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); |
1549 | ||
1550 | if (rf->channel > 14) { | |
1551 | /* | |
1552 | * When TX power is below 0, we should increase it by 7 to | |
1553 | * make it a positive value (Minumum value is -7). | |
1554 | * However this means that values between 0 and 7 have | |
1555 | * double meaning, and we should set a 7DBm boost flag. | |
1556 | */ | |
1557 | rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST, | |
8d1331b3 | 1558 | (info->default_power1 >= 0)); |
f4450616 | 1559 | |
8d1331b3 ID |
1560 | if (info->default_power1 < 0) |
1561 | info->default_power1 += 7; | |
f4450616 | 1562 | |
8d1331b3 | 1563 | rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1); |
f4450616 BZ |
1564 | |
1565 | rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST, | |
8d1331b3 | 1566 | (info->default_power2 >= 0)); |
f4450616 | 1567 | |
8d1331b3 ID |
1568 | if (info->default_power2 < 0) |
1569 | info->default_power2 += 7; | |
f4450616 | 1570 | |
8d1331b3 | 1571 | rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2); |
f4450616 | 1572 | } else { |
8d1331b3 ID |
1573 | rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1); |
1574 | rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2); | |
f4450616 BZ |
1575 | } |
1576 | ||
1577 | rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf)); | |
1578 | ||
1579 | rt2800_rf_write(rt2x00dev, 1, rf->rf1); | |
1580 | rt2800_rf_write(rt2x00dev, 2, rf->rf2); | |
1581 | rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); | |
1582 | rt2800_rf_write(rt2x00dev, 4, rf->rf4); | |
1583 | ||
1584 | udelay(200); | |
1585 | ||
1586 | rt2800_rf_write(rt2x00dev, 1, rf->rf1); | |
1587 | rt2800_rf_write(rt2x00dev, 2, rf->rf2); | |
1588 | rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); | |
1589 | rt2800_rf_write(rt2x00dev, 4, rf->rf4); | |
1590 | ||
1591 | udelay(200); | |
1592 | ||
1593 | rt2800_rf_write(rt2x00dev, 1, rf->rf1); | |
1594 | rt2800_rf_write(rt2x00dev, 2, rf->rf2); | |
1595 | rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); | |
1596 | rt2800_rf_write(rt2x00dev, 4, rf->rf4); | |
1597 | } | |
1598 | ||
06855ef4 GW |
1599 | static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev, |
1600 | struct ieee80211_conf *conf, | |
1601 | struct rf_channel *rf, | |
1602 | struct channel_info *info) | |
f4450616 BZ |
1603 | { |
1604 | u8 rfcsr; | |
1605 | ||
1606 | rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); | |
41a26170 | 1607 | rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3); |
f4450616 BZ |
1608 | |
1609 | rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); | |
fab799c3 | 1610 | rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); |
f4450616 BZ |
1611 | rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); |
1612 | ||
1613 | rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr); | |
8d1331b3 | 1614 | rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1); |
f4450616 BZ |
1615 | rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); |
1616 | ||
5a673964 | 1617 | rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr); |
8d1331b3 | 1618 | rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2); |
5a673964 HS |
1619 | rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); |
1620 | ||
f4450616 BZ |
1621 | rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr); |
1622 | rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); | |
1623 | rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); | |
1624 | ||
1625 | rt2800_rfcsr_write(rt2x00dev, 24, | |
1626 | rt2x00dev->calibration[conf_is_ht40(conf)]); | |
1627 | ||
71976907 | 1628 | rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr); |
f4450616 | 1629 | rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); |
71976907 | 1630 | rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); |
f4450616 BZ |
1631 | } |
1632 | ||
60687ba7 RST |
1633 | |
1634 | #define RT5390_POWER_BOUND 0x27 | |
1635 | #define RT5390_FREQ_OFFSET_BOUND 0x5f | |
1636 | ||
1637 | static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, | |
adde5882 GJ |
1638 | struct ieee80211_conf *conf, |
1639 | struct rf_channel *rf, | |
1640 | struct channel_info *info) | |
1641 | { | |
1642 | u8 rfcsr; | |
adde5882 GJ |
1643 | |
1644 | rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); | |
1645 | rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); | |
1646 | rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr); | |
1647 | rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); | |
1648 | rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); | |
1649 | ||
1650 | rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr); | |
1651 | if (info->default_power1 > RT5390_POWER_BOUND) | |
1652 | rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT5390_POWER_BOUND); | |
1653 | else | |
1654 | rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); | |
1655 | rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); | |
1656 | ||
1657 | rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); | |
1658 | rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); | |
1659 | rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); | |
1660 | rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); | |
1661 | rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); | |
1662 | rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); | |
1663 | ||
1664 | rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr); | |
1665 | if (rt2x00dev->freq_offset > RT5390_FREQ_OFFSET_BOUND) | |
1666 | rt2x00_set_field8(&rfcsr, RFCSR17_CODE, | |
1667 | RT5390_FREQ_OFFSET_BOUND); | |
1668 | else | |
1669 | rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset); | |
1670 | rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); | |
1671 | ||
adde5882 GJ |
1672 | if (rf->channel <= 14) { |
1673 | int idx = rf->channel-1; | |
1674 | ||
fdbc7b0a | 1675 | if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) { |
adde5882 GJ |
1676 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { |
1677 | /* r55/r59 value array of channel 1~14 */ | |
1678 | static const char r55_bt_rev[] = {0x83, 0x83, | |
1679 | 0x83, 0x73, 0x73, 0x63, 0x53, 0x53, | |
1680 | 0x53, 0x43, 0x43, 0x43, 0x43, 0x43}; | |
1681 | static const char r59_bt_rev[] = {0x0e, 0x0e, | |
1682 | 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09, | |
1683 | 0x07, 0x07, 0x07, 0x07, 0x07, 0x07}; | |
1684 | ||
1685 | rt2800_rfcsr_write(rt2x00dev, 55, | |
1686 | r55_bt_rev[idx]); | |
1687 | rt2800_rfcsr_write(rt2x00dev, 59, | |
1688 | r59_bt_rev[idx]); | |
1689 | } else { | |
1690 | static const char r59_bt[] = {0x8b, 0x8b, 0x8b, | |
1691 | 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89, | |
1692 | 0x88, 0x88, 0x86, 0x85, 0x84}; | |
1693 | ||
1694 | rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]); | |
1695 | } | |
1696 | } else { | |
1697 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { | |
1698 | static const char r55_nonbt_rev[] = {0x23, 0x23, | |
1699 | 0x23, 0x23, 0x13, 0x13, 0x03, 0x03, | |
1700 | 0x03, 0x03, 0x03, 0x03, 0x03, 0x03}; | |
1701 | static const char r59_nonbt_rev[] = {0x07, 0x07, | |
1702 | 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, | |
1703 | 0x07, 0x07, 0x06, 0x05, 0x04, 0x04}; | |
1704 | ||
1705 | rt2800_rfcsr_write(rt2x00dev, 55, | |
1706 | r55_nonbt_rev[idx]); | |
1707 | rt2800_rfcsr_write(rt2x00dev, 59, | |
1708 | r59_nonbt_rev[idx]); | |
1709 | } else if (rt2x00_rt(rt2x00dev, RT5390)) { | |
1710 | static const char r59_non_bt[] = {0x8f, 0x8f, | |
1711 | 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d, | |
1712 | 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86}; | |
1713 | ||
1714 | rt2800_rfcsr_write(rt2x00dev, 59, | |
1715 | r59_non_bt[idx]); | |
1716 | } | |
1717 | } | |
1718 | } | |
1719 | ||
1720 | rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); | |
1721 | rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0); | |
1722 | rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0); | |
1723 | rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); | |
1724 | ||
1725 | rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr); | |
1726 | rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1); | |
1727 | rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); | |
60687ba7 RST |
1728 | } |
1729 | ||
f4450616 BZ |
1730 | static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, |
1731 | struct ieee80211_conf *conf, | |
1732 | struct rf_channel *rf, | |
1733 | struct channel_info *info) | |
1734 | { | |
1735 | u32 reg; | |
1736 | unsigned int tx_pin; | |
1737 | u8 bbp; | |
1738 | ||
46323e11 | 1739 | if (rf->channel <= 14) { |
8d1331b3 ID |
1740 | info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1); |
1741 | info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2); | |
46323e11 | 1742 | } else { |
8d1331b3 ID |
1743 | info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1); |
1744 | info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2); | |
46323e11 ID |
1745 | } |
1746 | ||
06855ef4 GW |
1747 | if (rt2x00_rf(rt2x00dev, RF2020) || |
1748 | rt2x00_rf(rt2x00dev, RF3020) || | |
1749 | rt2x00_rf(rt2x00dev, RF3021) || | |
46323e11 | 1750 | rt2x00_rf(rt2x00dev, RF3022) || |
f93bc9b3 GW |
1751 | rt2x00_rf(rt2x00dev, RF3052) || |
1752 | rt2x00_rf(rt2x00dev, RF3320)) | |
06855ef4 | 1753 | rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info); |
aca355b9 GW |
1754 | else if (rt2x00_rf(rt2x00dev, RF5370) || |
1755 | rt2x00_rf(rt2x00dev, RF5390)) | |
adde5882 | 1756 | rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info); |
fa6f632f | 1757 | else |
06855ef4 | 1758 | rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info); |
f4450616 BZ |
1759 | |
1760 | /* | |
1761 | * Change BBP settings | |
1762 | */ | |
1763 | rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); | |
1764 | rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); | |
1765 | rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); | |
1766 | rt2800_bbp_write(rt2x00dev, 86, 0); | |
1767 | ||
1768 | if (rf->channel <= 14) { | |
adde5882 | 1769 | if (!rt2x00_rt(rt2x00dev, RT5390)) { |
7dab73b3 ID |
1770 | if (test_bit(CAPABILITY_EXTERNAL_LNA_BG, |
1771 | &rt2x00dev->cap_flags)) { | |
adde5882 GJ |
1772 | rt2800_bbp_write(rt2x00dev, 82, 0x62); |
1773 | rt2800_bbp_write(rt2x00dev, 75, 0x46); | |
1774 | } else { | |
1775 | rt2800_bbp_write(rt2x00dev, 82, 0x84); | |
1776 | rt2800_bbp_write(rt2x00dev, 75, 0x50); | |
1777 | } | |
f4450616 BZ |
1778 | } |
1779 | } else { | |
1780 | rt2800_bbp_write(rt2x00dev, 82, 0xf2); | |
1781 | ||
7dab73b3 | 1782 | if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags)) |
f4450616 BZ |
1783 | rt2800_bbp_write(rt2x00dev, 75, 0x46); |
1784 | else | |
1785 | rt2800_bbp_write(rt2x00dev, 75, 0x50); | |
1786 | } | |
1787 | ||
1788 | rt2800_register_read(rt2x00dev, TX_BAND_CFG, ®); | |
a21ee724 | 1789 | rt2x00_set_field32(®, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf)); |
f4450616 BZ |
1790 | rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14); |
1791 | rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14); | |
1792 | rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg); | |
1793 | ||
1794 | tx_pin = 0; | |
1795 | ||
1796 | /* Turn on unused PA or LNA when not using 1T or 1R */ | |
d96aa640 | 1797 | if (rt2x00dev->default_ant.tx_chain_num == 2) { |
f4450616 BZ |
1798 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1); |
1799 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1); | |
1800 | } | |
1801 | ||
1802 | /* Turn on unused PA or LNA when not using 1T or 1R */ | |
d96aa640 | 1803 | if (rt2x00dev->default_ant.rx_chain_num == 2) { |
f4450616 BZ |
1804 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1); |
1805 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1); | |
1806 | } | |
1807 | ||
1808 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1); | |
1809 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1); | |
1810 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1); | |
1811 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1); | |
1812 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14); | |
1813 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14); | |
1814 | ||
1815 | rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); | |
1816 | ||
1817 | rt2800_bbp_read(rt2x00dev, 4, &bbp); | |
1818 | rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf)); | |
1819 | rt2800_bbp_write(rt2x00dev, 4, bbp); | |
1820 | ||
1821 | rt2800_bbp_read(rt2x00dev, 3, &bbp); | |
a21ee724 | 1822 | rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf)); |
f4450616 BZ |
1823 | rt2800_bbp_write(rt2x00dev, 3, bbp); |
1824 | ||
8d0c9b65 | 1825 | if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { |
f4450616 BZ |
1826 | if (conf_is_ht40(conf)) { |
1827 | rt2800_bbp_write(rt2x00dev, 69, 0x1a); | |
1828 | rt2800_bbp_write(rt2x00dev, 70, 0x0a); | |
1829 | rt2800_bbp_write(rt2x00dev, 73, 0x16); | |
1830 | } else { | |
1831 | rt2800_bbp_write(rt2x00dev, 69, 0x16); | |
1832 | rt2800_bbp_write(rt2x00dev, 70, 0x08); | |
1833 | rt2800_bbp_write(rt2x00dev, 73, 0x11); | |
1834 | } | |
1835 | } | |
1836 | ||
1837 | msleep(1); | |
977206d7 HS |
1838 | |
1839 | /* | |
1840 | * Clear channel statistic counters | |
1841 | */ | |
1842 | rt2800_register_read(rt2x00dev, CH_IDLE_STA, ®); | |
1843 | rt2800_register_read(rt2x00dev, CH_BUSY_STA, ®); | |
1844 | rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, ®); | |
f4450616 BZ |
1845 | } |
1846 | ||
9e33a355 HS |
1847 | static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev) |
1848 | { | |
1849 | u8 tssi_bounds[9]; | |
1850 | u8 current_tssi; | |
1851 | u16 eeprom; | |
1852 | u8 step; | |
1853 | int i; | |
1854 | ||
1855 | /* | |
1856 | * Read TSSI boundaries for temperature compensation from | |
1857 | * the EEPROM. | |
1858 | * | |
1859 | * Array idx 0 1 2 3 4 5 6 7 8 | |
1860 | * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4 | |
1861 | * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00 | |
1862 | */ | |
1863 | if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) { | |
1864 | rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom); | |
1865 | tssi_bounds[0] = rt2x00_get_field16(eeprom, | |
1866 | EEPROM_TSSI_BOUND_BG1_MINUS4); | |
1867 | tssi_bounds[1] = rt2x00_get_field16(eeprom, | |
1868 | EEPROM_TSSI_BOUND_BG1_MINUS3); | |
1869 | ||
1870 | rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom); | |
1871 | tssi_bounds[2] = rt2x00_get_field16(eeprom, | |
1872 | EEPROM_TSSI_BOUND_BG2_MINUS2); | |
1873 | tssi_bounds[3] = rt2x00_get_field16(eeprom, | |
1874 | EEPROM_TSSI_BOUND_BG2_MINUS1); | |
1875 | ||
1876 | rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom); | |
1877 | tssi_bounds[4] = rt2x00_get_field16(eeprom, | |
1878 | EEPROM_TSSI_BOUND_BG3_REF); | |
1879 | tssi_bounds[5] = rt2x00_get_field16(eeprom, | |
1880 | EEPROM_TSSI_BOUND_BG3_PLUS1); | |
1881 | ||
1882 | rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom); | |
1883 | tssi_bounds[6] = rt2x00_get_field16(eeprom, | |
1884 | EEPROM_TSSI_BOUND_BG4_PLUS2); | |
1885 | tssi_bounds[7] = rt2x00_get_field16(eeprom, | |
1886 | EEPROM_TSSI_BOUND_BG4_PLUS3); | |
1887 | ||
1888 | rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom); | |
1889 | tssi_bounds[8] = rt2x00_get_field16(eeprom, | |
1890 | EEPROM_TSSI_BOUND_BG5_PLUS4); | |
1891 | ||
1892 | step = rt2x00_get_field16(eeprom, | |
1893 | EEPROM_TSSI_BOUND_BG5_AGC_STEP); | |
1894 | } else { | |
1895 | rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom); | |
1896 | tssi_bounds[0] = rt2x00_get_field16(eeprom, | |
1897 | EEPROM_TSSI_BOUND_A1_MINUS4); | |
1898 | tssi_bounds[1] = rt2x00_get_field16(eeprom, | |
1899 | EEPROM_TSSI_BOUND_A1_MINUS3); | |
1900 | ||
1901 | rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom); | |
1902 | tssi_bounds[2] = rt2x00_get_field16(eeprom, | |
1903 | EEPROM_TSSI_BOUND_A2_MINUS2); | |
1904 | tssi_bounds[3] = rt2x00_get_field16(eeprom, | |
1905 | EEPROM_TSSI_BOUND_A2_MINUS1); | |
1906 | ||
1907 | rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom); | |
1908 | tssi_bounds[4] = rt2x00_get_field16(eeprom, | |
1909 | EEPROM_TSSI_BOUND_A3_REF); | |
1910 | tssi_bounds[5] = rt2x00_get_field16(eeprom, | |
1911 | EEPROM_TSSI_BOUND_A3_PLUS1); | |
1912 | ||
1913 | rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom); | |
1914 | tssi_bounds[6] = rt2x00_get_field16(eeprom, | |
1915 | EEPROM_TSSI_BOUND_A4_PLUS2); | |
1916 | tssi_bounds[7] = rt2x00_get_field16(eeprom, | |
1917 | EEPROM_TSSI_BOUND_A4_PLUS3); | |
1918 | ||
1919 | rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom); | |
1920 | tssi_bounds[8] = rt2x00_get_field16(eeprom, | |
1921 | EEPROM_TSSI_BOUND_A5_PLUS4); | |
1922 | ||
1923 | step = rt2x00_get_field16(eeprom, | |
1924 | EEPROM_TSSI_BOUND_A5_AGC_STEP); | |
1925 | } | |
1926 | ||
1927 | /* | |
1928 | * Check if temperature compensation is supported. | |
1929 | */ | |
1930 | if (tssi_bounds[4] == 0xff) | |
1931 | return 0; | |
1932 | ||
1933 | /* | |
1934 | * Read current TSSI (BBP 49). | |
1935 | */ | |
1936 | rt2800_bbp_read(rt2x00dev, 49, ¤t_tssi); | |
1937 | ||
1938 | /* | |
1939 | * Compare TSSI value (BBP49) with the compensation boundaries | |
1940 | * from the EEPROM and increase or decrease tx power. | |
1941 | */ | |
1942 | for (i = 0; i <= 3; i++) { | |
1943 | if (current_tssi > tssi_bounds[i]) | |
1944 | break; | |
1945 | } | |
1946 | ||
1947 | if (i == 4) { | |
1948 | for (i = 8; i >= 5; i--) { | |
1949 | if (current_tssi < tssi_bounds[i]) | |
1950 | break; | |
1951 | } | |
1952 | } | |
1953 | ||
1954 | return (i - 4) * step; | |
1955 | } | |
1956 | ||
e90c54b2 RJH |
1957 | static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev, |
1958 | enum ieee80211_band band) | |
1959 | { | |
1960 | u16 eeprom; | |
1961 | u8 comp_en; | |
1962 | u8 comp_type; | |
75faae8b | 1963 | int comp_value = 0; |
e90c54b2 RJH |
1964 | |
1965 | rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom); | |
1966 | ||
75faae8b HS |
1967 | /* |
1968 | * HT40 compensation not required. | |
1969 | */ | |
1970 | if (eeprom == 0xffff || | |
1971 | !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) | |
e90c54b2 RJH |
1972 | return 0; |
1973 | ||
1974 | if (band == IEEE80211_BAND_2GHZ) { | |
1975 | comp_en = rt2x00_get_field16(eeprom, | |
1976 | EEPROM_TXPOWER_DELTA_ENABLE_2G); | |
1977 | if (comp_en) { | |
1978 | comp_type = rt2x00_get_field16(eeprom, | |
1979 | EEPROM_TXPOWER_DELTA_TYPE_2G); | |
1980 | comp_value = rt2x00_get_field16(eeprom, | |
1981 | EEPROM_TXPOWER_DELTA_VALUE_2G); | |
1982 | if (!comp_type) | |
1983 | comp_value = -comp_value; | |
1984 | } | |
1985 | } else { | |
1986 | comp_en = rt2x00_get_field16(eeprom, | |
1987 | EEPROM_TXPOWER_DELTA_ENABLE_5G); | |
1988 | if (comp_en) { | |
1989 | comp_type = rt2x00_get_field16(eeprom, | |
1990 | EEPROM_TXPOWER_DELTA_TYPE_5G); | |
1991 | comp_value = rt2x00_get_field16(eeprom, | |
1992 | EEPROM_TXPOWER_DELTA_VALUE_5G); | |
1993 | if (!comp_type) | |
1994 | comp_value = -comp_value; | |
1995 | } | |
1996 | } | |
1997 | ||
1998 | return comp_value; | |
1999 | } | |
2000 | ||
fa71a160 HS |
2001 | static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b, |
2002 | enum ieee80211_band band, int power_level, | |
2003 | u8 txpower, int delta) | |
e90c54b2 RJH |
2004 | { |
2005 | u32 reg; | |
2006 | u16 eeprom; | |
2007 | u8 criterion; | |
2008 | u8 eirp_txpower; | |
2009 | u8 eirp_txpower_criterion; | |
2010 | u8 reg_limit; | |
e90c54b2 RJH |
2011 | |
2012 | if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b)) | |
2013 | return txpower; | |
2014 | ||
7dab73b3 | 2015 | if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) { |
e90c54b2 RJH |
2016 | /* |
2017 | * Check if eirp txpower exceed txpower_limit. | |
2018 | * We use OFDM 6M as criterion and its eirp txpower | |
2019 | * is stored at EEPROM_EIRP_MAX_TX_POWER. | |
2020 | * .11b data rate need add additional 4dbm | |
2021 | * when calculating eirp txpower. | |
2022 | */ | |
2023 | rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, ®); | |
2024 | criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS); | |
2025 | ||
2026 | rt2x00_eeprom_read(rt2x00dev, | |
2027 | EEPROM_EIRP_MAX_TX_POWER, &eeprom); | |
2028 | ||
2029 | if (band == IEEE80211_BAND_2GHZ) | |
2030 | eirp_txpower_criterion = rt2x00_get_field16(eeprom, | |
2031 | EEPROM_EIRP_MAX_TX_POWER_2GHZ); | |
2032 | else | |
2033 | eirp_txpower_criterion = rt2x00_get_field16(eeprom, | |
2034 | EEPROM_EIRP_MAX_TX_POWER_5GHZ); | |
2035 | ||
2036 | eirp_txpower = eirp_txpower_criterion + (txpower - criterion) + | |
2af242e1 | 2037 | (is_rate_b ? 4 : 0) + delta; |
e90c54b2 RJH |
2038 | |
2039 | reg_limit = (eirp_txpower > power_level) ? | |
2040 | (eirp_txpower - power_level) : 0; | |
2041 | } else | |
2042 | reg_limit = 0; | |
2043 | ||
2af242e1 | 2044 | return txpower + delta - reg_limit; |
e90c54b2 RJH |
2045 | } |
2046 | ||
f4450616 | 2047 | static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev, |
9e33a355 HS |
2048 | enum ieee80211_band band, |
2049 | int power_level) | |
f4450616 | 2050 | { |
5e846004 | 2051 | u8 txpower; |
5e846004 | 2052 | u16 eeprom; |
e90c54b2 | 2053 | int i, is_rate_b; |
f4450616 | 2054 | u32 reg; |
f4450616 | 2055 | u8 r1; |
5e846004 | 2056 | u32 offset; |
2af242e1 HS |
2057 | int delta; |
2058 | ||
2059 | /* | |
2060 | * Calculate HT40 compensation delta | |
2061 | */ | |
2062 | delta = rt2800_get_txpower_bw_comp(rt2x00dev, band); | |
f4450616 | 2063 | |
9e33a355 HS |
2064 | /* |
2065 | * calculate temperature compensation delta | |
2066 | */ | |
2067 | delta += rt2800_get_gain_calibration_delta(rt2x00dev); | |
2068 | ||
5e846004 | 2069 | /* |
e90c54b2 | 2070 | * set to normal bbp tx power control mode: +/- 0dBm |
5e846004 | 2071 | */ |
f4450616 | 2072 | rt2800_bbp_read(rt2x00dev, 1, &r1); |
e90c54b2 | 2073 | rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0); |
f4450616 | 2074 | rt2800_bbp_write(rt2x00dev, 1, r1); |
5e846004 HS |
2075 | offset = TX_PWR_CFG_0; |
2076 | ||
2077 | for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) { | |
2078 | /* just to be safe */ | |
2079 | if (offset > TX_PWR_CFG_4) | |
2080 | break; | |
2081 | ||
2082 | rt2800_register_read(rt2x00dev, offset, ®); | |
2083 | ||
2084 | /* read the next four txpower values */ | |
2085 | rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i, | |
2086 | &eeprom); | |
2087 | ||
e90c54b2 RJH |
2088 | is_rate_b = i ? 0 : 1; |
2089 | /* | |
2090 | * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS, | |
5e846004 | 2091 | * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12, |
e90c54b2 RJH |
2092 | * TX_PWR_CFG_4: unknown |
2093 | */ | |
5e846004 HS |
2094 | txpower = rt2x00_get_field16(eeprom, |
2095 | EEPROM_TXPOWER_BYRATE_RATE0); | |
fa71a160 | 2096 | txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, |
2af242e1 | 2097 | power_level, txpower, delta); |
e90c54b2 | 2098 | rt2x00_set_field32(®, TX_PWR_CFG_RATE0, txpower); |
5e846004 | 2099 | |
e90c54b2 RJH |
2100 | /* |
2101 | * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS, | |
5e846004 | 2102 | * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13, |
e90c54b2 RJH |
2103 | * TX_PWR_CFG_4: unknown |
2104 | */ | |
5e846004 HS |
2105 | txpower = rt2x00_get_field16(eeprom, |
2106 | EEPROM_TXPOWER_BYRATE_RATE1); | |
fa71a160 | 2107 | txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, |
2af242e1 | 2108 | power_level, txpower, delta); |
e90c54b2 | 2109 | rt2x00_set_field32(®, TX_PWR_CFG_RATE1, txpower); |
5e846004 | 2110 | |
e90c54b2 RJH |
2111 | /* |
2112 | * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS, | |
5e846004 | 2113 | * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14, |
e90c54b2 RJH |
2114 | * TX_PWR_CFG_4: unknown |
2115 | */ | |
5e846004 HS |
2116 | txpower = rt2x00_get_field16(eeprom, |
2117 | EEPROM_TXPOWER_BYRATE_RATE2); | |
fa71a160 | 2118 | txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, |
2af242e1 | 2119 | power_level, txpower, delta); |
e90c54b2 | 2120 | rt2x00_set_field32(®, TX_PWR_CFG_RATE2, txpower); |
5e846004 | 2121 | |
e90c54b2 RJH |
2122 | /* |
2123 | * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS, | |
5e846004 | 2124 | * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15, |
e90c54b2 RJH |
2125 | * TX_PWR_CFG_4: unknown |
2126 | */ | |
5e846004 HS |
2127 | txpower = rt2x00_get_field16(eeprom, |
2128 | EEPROM_TXPOWER_BYRATE_RATE3); | |
fa71a160 | 2129 | txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, |
2af242e1 | 2130 | power_level, txpower, delta); |
e90c54b2 | 2131 | rt2x00_set_field32(®, TX_PWR_CFG_RATE3, txpower); |
5e846004 HS |
2132 | |
2133 | /* read the next four txpower values */ | |
2134 | rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1, | |
2135 | &eeprom); | |
2136 | ||
e90c54b2 RJH |
2137 | is_rate_b = 0; |
2138 | /* | |
2139 | * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0, | |
5e846004 | 2140 | * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown, |
e90c54b2 RJH |
2141 | * TX_PWR_CFG_4: unknown |
2142 | */ | |
5e846004 HS |
2143 | txpower = rt2x00_get_field16(eeprom, |
2144 | EEPROM_TXPOWER_BYRATE_RATE0); | |
fa71a160 | 2145 | txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, |
2af242e1 | 2146 | power_level, txpower, delta); |
e90c54b2 | 2147 | rt2x00_set_field32(®, TX_PWR_CFG_RATE4, txpower); |
5e846004 | 2148 | |
e90c54b2 RJH |
2149 | /* |
2150 | * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1, | |
5e846004 | 2151 | * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown, |
e90c54b2 RJH |
2152 | * TX_PWR_CFG_4: unknown |
2153 | */ | |
5e846004 HS |
2154 | txpower = rt2x00_get_field16(eeprom, |
2155 | EEPROM_TXPOWER_BYRATE_RATE1); | |
fa71a160 | 2156 | txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, |
2af242e1 | 2157 | power_level, txpower, delta); |
e90c54b2 | 2158 | rt2x00_set_field32(®, TX_PWR_CFG_RATE5, txpower); |
5e846004 | 2159 | |
e90c54b2 RJH |
2160 | /* |
2161 | * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2, | |
5e846004 | 2162 | * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown, |
e90c54b2 RJH |
2163 | * TX_PWR_CFG_4: unknown |
2164 | */ | |
5e846004 HS |
2165 | txpower = rt2x00_get_field16(eeprom, |
2166 | EEPROM_TXPOWER_BYRATE_RATE2); | |
fa71a160 | 2167 | txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, |
2af242e1 | 2168 | power_level, txpower, delta); |
e90c54b2 | 2169 | rt2x00_set_field32(®, TX_PWR_CFG_RATE6, txpower); |
5e846004 | 2170 | |
e90c54b2 RJH |
2171 | /* |
2172 | * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3, | |
5e846004 | 2173 | * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown, |
e90c54b2 RJH |
2174 | * TX_PWR_CFG_4: unknown |
2175 | */ | |
5e846004 HS |
2176 | txpower = rt2x00_get_field16(eeprom, |
2177 | EEPROM_TXPOWER_BYRATE_RATE3); | |
fa71a160 | 2178 | txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, |
2af242e1 | 2179 | power_level, txpower, delta); |
e90c54b2 | 2180 | rt2x00_set_field32(®, TX_PWR_CFG_RATE7, txpower); |
5e846004 HS |
2181 | |
2182 | rt2800_register_write(rt2x00dev, offset, reg); | |
2183 | ||
2184 | /* next TX_PWR_CFG register */ | |
2185 | offset += 4; | |
2186 | } | |
f4450616 BZ |
2187 | } |
2188 | ||
9e33a355 HS |
2189 | void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev) |
2190 | { | |
2191 | rt2800_config_txpower(rt2x00dev, rt2x00dev->curr_band, | |
2192 | rt2x00dev->tx_power); | |
2193 | } | |
2194 | EXPORT_SYMBOL_GPL(rt2800_gain_calibration); | |
2195 | ||
f4450616 BZ |
2196 | static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev, |
2197 | struct rt2x00lib_conf *libconf) | |
2198 | { | |
2199 | u32 reg; | |
2200 | ||
2201 | rt2800_register_read(rt2x00dev, TX_RTY_CFG, ®); | |
2202 | rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, | |
2203 | libconf->conf->short_frame_max_tx_count); | |
2204 | rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, | |
2205 | libconf->conf->long_frame_max_tx_count); | |
f4450616 BZ |
2206 | rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); |
2207 | } | |
2208 | ||
2209 | static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev, | |
2210 | struct rt2x00lib_conf *libconf) | |
2211 | { | |
2212 | enum dev_state state = | |
2213 | (libconf->conf->flags & IEEE80211_CONF_PS) ? | |
2214 | STATE_SLEEP : STATE_AWAKE; | |
2215 | u32 reg; | |
2216 | ||
2217 | if (state == STATE_SLEEP) { | |
2218 | rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0); | |
2219 | ||
2220 | rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®); | |
2221 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5); | |
2222 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, | |
2223 | libconf->conf->listen_interval - 1); | |
2224 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1); | |
2225 | rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); | |
2226 | ||
2227 | rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); | |
2228 | } else { | |
f4450616 BZ |
2229 | rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®); |
2230 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); | |
2231 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); | |
2232 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0); | |
2233 | rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); | |
5731858d GW |
2234 | |
2235 | rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); | |
f4450616 BZ |
2236 | } |
2237 | } | |
2238 | ||
2239 | void rt2800_config(struct rt2x00_dev *rt2x00dev, | |
2240 | struct rt2x00lib_conf *libconf, | |
2241 | const unsigned int flags) | |
2242 | { | |
2243 | /* Always recalculate LNA gain before changing configuration */ | |
2244 | rt2800_config_lna_gain(rt2x00dev, libconf); | |
2245 | ||
e90c54b2 | 2246 | if (flags & IEEE80211_CONF_CHANGE_CHANNEL) { |
f4450616 BZ |
2247 | rt2800_config_channel(rt2x00dev, libconf->conf, |
2248 | &libconf->rf, &libconf->channel); | |
9e33a355 HS |
2249 | rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band, |
2250 | libconf->conf->power_level); | |
e90c54b2 | 2251 | } |
f4450616 | 2252 | if (flags & IEEE80211_CONF_CHANGE_POWER) |
9e33a355 HS |
2253 | rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band, |
2254 | libconf->conf->power_level); | |
f4450616 BZ |
2255 | if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) |
2256 | rt2800_config_retry_limit(rt2x00dev, libconf); | |
2257 | if (flags & IEEE80211_CONF_CHANGE_PS) | |
2258 | rt2800_config_ps(rt2x00dev, libconf); | |
2259 | } | |
2260 | EXPORT_SYMBOL_GPL(rt2800_config); | |
2261 | ||
2262 | /* | |
2263 | * Link tuning | |
2264 | */ | |
2265 | void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) | |
2266 | { | |
2267 | u32 reg; | |
2268 | ||
2269 | /* | |
2270 | * Update FCS error count from register. | |
2271 | */ | |
2272 | rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®); | |
2273 | qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR); | |
2274 | } | |
2275 | EXPORT_SYMBOL_GPL(rt2800_link_stats); | |
2276 | ||
2277 | static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev) | |
2278 | { | |
2279 | if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) { | |
d5385bfc | 2280 | if (rt2x00_rt(rt2x00dev, RT3070) || |
64522957 | 2281 | rt2x00_rt(rt2x00dev, RT3071) || |
cc78e904 | 2282 | rt2x00_rt(rt2x00dev, RT3090) || |
adde5882 GJ |
2283 | rt2x00_rt(rt2x00dev, RT3390) || |
2284 | rt2x00_rt(rt2x00dev, RT5390)) | |
f4450616 BZ |
2285 | return 0x1c + (2 * rt2x00dev->lna_gain); |
2286 | else | |
2287 | return 0x2e + rt2x00dev->lna_gain; | |
2288 | } | |
2289 | ||
2290 | if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) | |
2291 | return 0x32 + (rt2x00dev->lna_gain * 5) / 3; | |
2292 | else | |
2293 | return 0x3a + (rt2x00dev->lna_gain * 5) / 3; | |
2294 | } | |
2295 | ||
2296 | static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev, | |
2297 | struct link_qual *qual, u8 vgc_level) | |
2298 | { | |
2299 | if (qual->vgc_level != vgc_level) { | |
2300 | rt2800_bbp_write(rt2x00dev, 66, vgc_level); | |
2301 | qual->vgc_level = vgc_level; | |
2302 | qual->vgc_level_reg = vgc_level; | |
2303 | } | |
2304 | } | |
2305 | ||
2306 | void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) | |
2307 | { | |
2308 | rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev)); | |
2309 | } | |
2310 | EXPORT_SYMBOL_GPL(rt2800_reset_tuner); | |
2311 | ||
2312 | void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual, | |
2313 | const u32 count) | |
2314 | { | |
8d0c9b65 | 2315 | if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) |
f4450616 BZ |
2316 | return; |
2317 | ||
2318 | /* | |
2319 | * When RSSI is better then -80 increase VGC level with 0x10 | |
2320 | */ | |
2321 | rt2800_set_vgc(rt2x00dev, qual, | |
2322 | rt2800_get_default_vgc(rt2x00dev) + | |
2323 | ((qual->rssi > -80) * 0x10)); | |
2324 | } | |
2325 | EXPORT_SYMBOL_GPL(rt2800_link_tuner); | |
fcf51541 BZ |
2326 | |
2327 | /* | |
2328 | * Initialization functions. | |
2329 | */ | |
b9a07ae9 | 2330 | static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) |
fcf51541 BZ |
2331 | { |
2332 | u32 reg; | |
d5385bfc | 2333 | u16 eeprom; |
fcf51541 | 2334 | unsigned int i; |
e3a896b9 | 2335 | int ret; |
fcf51541 | 2336 | |
a9dce149 GW |
2337 | rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); |
2338 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); | |
2339 | rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); | |
2340 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); | |
2341 | rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); | |
2342 | rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); | |
2343 | rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); | |
2344 | ||
e3a896b9 GW |
2345 | ret = rt2800_drv_init_registers(rt2x00dev); |
2346 | if (ret) | |
2347 | return ret; | |
fcf51541 BZ |
2348 | |
2349 | rt2800_register_read(rt2x00dev, BCN_OFFSET0, ®); | |
2350 | rt2x00_set_field32(®, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */ | |
2351 | rt2x00_set_field32(®, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */ | |
2352 | rt2x00_set_field32(®, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */ | |
2353 | rt2x00_set_field32(®, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */ | |
2354 | rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg); | |
2355 | ||
2356 | rt2800_register_read(rt2x00dev, BCN_OFFSET1, ®); | |
2357 | rt2x00_set_field32(®, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */ | |
2358 | rt2x00_set_field32(®, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */ | |
2359 | rt2x00_set_field32(®, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */ | |
2360 | rt2x00_set_field32(®, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */ | |
2361 | rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg); | |
2362 | ||
2363 | rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f); | |
2364 | rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); | |
2365 | ||
2366 | rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); | |
2367 | ||
2368 | rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); | |
8544df32 | 2369 | rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1600); |
fcf51541 BZ |
2370 | rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0); |
2371 | rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0); | |
2372 | rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0); | |
2373 | rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); | |
2374 | rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0); | |
2375 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); | |
2376 | ||
a9dce149 GW |
2377 | rt2800_config_filter(rt2x00dev, FIF_ALLMULTI); |
2378 | ||
2379 | rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®); | |
2380 | rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 9); | |
2381 | rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); | |
2382 | rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); | |
2383 | ||
64522957 | 2384 | if (rt2x00_rt(rt2x00dev, RT3071) || |
cc78e904 GW |
2385 | rt2x00_rt(rt2x00dev, RT3090) || |
2386 | rt2x00_rt(rt2x00dev, RT3390)) { | |
fcf51541 BZ |
2387 | rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); |
2388 | rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); | |
64522957 | 2389 | if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || |
cc78e904 GW |
2390 | rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || |
2391 | rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { | |
38c8a566 RJH |
2392 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom); |
2393 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) | |
d5385bfc GW |
2394 | rt2800_register_write(rt2x00dev, TX_SW_CFG2, |
2395 | 0x0000002c); | |
2396 | else | |
2397 | rt2800_register_write(rt2x00dev, TX_SW_CFG2, | |
2398 | 0x0000000f); | |
2399 | } else { | |
2400 | rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); | |
2401 | } | |
d5385bfc | 2402 | } else if (rt2x00_rt(rt2x00dev, RT3070)) { |
fcf51541 | 2403 | rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); |
8cdd15e0 GW |
2404 | |
2405 | if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { | |
2406 | rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); | |
2407 | rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c); | |
2408 | } else { | |
2409 | rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); | |
2410 | rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); | |
2411 | } | |
c295a81d HS |
2412 | } else if (rt2800_is_305x_soc(rt2x00dev)) { |
2413 | rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); | |
2414 | rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); | |
961636ba | 2415 | rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030); |
adde5882 GJ |
2416 | } else if (rt2x00_rt(rt2x00dev, RT5390)) { |
2417 | rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); | |
2418 | rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); | |
2419 | rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); | |
fcf51541 BZ |
2420 | } else { |
2421 | rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000); | |
2422 | rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); | |
2423 | } | |
2424 | ||
2425 | rt2800_register_read(rt2x00dev, TX_LINK_CFG, ®); | |
2426 | rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32); | |
2427 | rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0); | |
2428 | rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0); | |
2429 | rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0); | |
2430 | rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0); | |
2431 | rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1); | |
2432 | rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0); | |
2433 | rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0); | |
2434 | rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg); | |
2435 | ||
2436 | rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, ®); | |
2437 | rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); | |
a9dce149 | 2438 | rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32); |
fcf51541 BZ |
2439 | rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); |
2440 | rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); | |
2441 | ||
2442 | rt2800_register_read(rt2x00dev, MAX_LEN_CFG, ®); | |
2443 | rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); | |
8d0c9b65 | 2444 | if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) || |
49e721ec | 2445 | rt2x00_rt(rt2x00dev, RT2883) || |
8d0c9b65 | 2446 | rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) |
fcf51541 BZ |
2447 | rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 2); |
2448 | else | |
2449 | rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 1); | |
2450 | rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 0); | |
2451 | rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 0); | |
2452 | rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); | |
2453 | ||
a9dce149 GW |
2454 | rt2800_register_read(rt2x00dev, LED_CFG, ®); |
2455 | rt2x00_set_field32(®, LED_CFG_ON_PERIOD, 70); | |
2456 | rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, 30); | |
2457 | rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3); | |
2458 | rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3); | |
2459 | rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 3); | |
2460 | rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3); | |
2461 | rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1); | |
2462 | rt2800_register_write(rt2x00dev, LED_CFG, reg); | |
2463 | ||
fcf51541 BZ |
2464 | rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f); |
2465 | ||
a9dce149 GW |
2466 | rt2800_register_read(rt2x00dev, TX_RTY_CFG, ®); |
2467 | rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 15); | |
2468 | rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 31); | |
2469 | rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000); | |
2470 | rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0); | |
2471 | rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0); | |
2472 | rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1); | |
2473 | rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); | |
2474 | ||
fcf51541 BZ |
2475 | rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®); |
2476 | rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1); | |
a9dce149 | 2477 | rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1); |
fcf51541 BZ |
2478 | rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 0); |
2479 | rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0); | |
a9dce149 | 2480 | rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 1); |
fcf51541 BZ |
2481 | rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0); |
2482 | rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); | |
2483 | rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); | |
2484 | ||
2485 | rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®); | |
a9dce149 | 2486 | rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 3); |
fcf51541 | 2487 | rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0); |
6f492b6d | 2488 | rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1); |
fcf51541 BZ |
2489 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); |
2490 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); | |
2491 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); | |
a9dce149 | 2492 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0); |
fcf51541 | 2493 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1); |
a9dce149 GW |
2494 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0); |
2495 | rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, 1); | |
fcf51541 BZ |
2496 | rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); |
2497 | ||
2498 | rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); | |
a9dce149 | 2499 | rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 3); |
fcf51541 | 2500 | rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0); |
6f492b6d | 2501 | rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1); |
fcf51541 BZ |
2502 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); |
2503 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); | |
2504 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); | |
a9dce149 | 2505 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0); |
fcf51541 | 2506 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1); |
a9dce149 GW |
2507 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0); |
2508 | rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, 1); | |
fcf51541 BZ |
2509 | rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); |
2510 | ||
2511 | rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); | |
2512 | rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004); | |
2513 | rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 0); | |
6f492b6d | 2514 | rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1); |
fcf51541 BZ |
2515 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1); |
2516 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); | |
2517 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1); | |
2518 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0); | |
2519 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1); | |
2520 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0); | |
a9dce149 | 2521 | rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, 0); |
fcf51541 BZ |
2522 | rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); |
2523 | ||
2524 | rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); | |
2525 | rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084); | |
d13a97f0 | 2526 | rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 0); |
6f492b6d | 2527 | rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1); |
fcf51541 BZ |
2528 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1); |
2529 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); | |
2530 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1); | |
2531 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1); | |
2532 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1); | |
2533 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1); | |
a9dce149 | 2534 | rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, 0); |
fcf51541 BZ |
2535 | rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); |
2536 | ||
2537 | rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); | |
2538 | rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004); | |
2539 | rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 0); | |
6f492b6d | 2540 | rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1); |
fcf51541 BZ |
2541 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1); |
2542 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); | |
2543 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1); | |
2544 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0); | |
2545 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1); | |
2546 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0); | |
a9dce149 | 2547 | rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, 0); |
fcf51541 BZ |
2548 | rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); |
2549 | ||
2550 | rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); | |
2551 | rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084); | |
2552 | rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 0); | |
6f492b6d | 2553 | rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1); |
fcf51541 BZ |
2554 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1); |
2555 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); | |
2556 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1); | |
2557 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1); | |
2558 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1); | |
2559 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); | |
a9dce149 | 2560 | rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, 0); |
fcf51541 BZ |
2561 | rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); |
2562 | ||
cea90e55 | 2563 | if (rt2x00_is_usb(rt2x00dev)) { |
fcf51541 BZ |
2564 | rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006); |
2565 | ||
2566 | rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); | |
2567 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); | |
2568 | rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); | |
2569 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); | |
2570 | rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); | |
2571 | rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3); | |
2572 | rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0); | |
2573 | rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0); | |
2574 | rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0); | |
2575 | rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0); | |
2576 | rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); | |
2577 | } | |
2578 | ||
961621ab HS |
2579 | /* |
2580 | * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1 | |
2581 | * although it is reserved. | |
2582 | */ | |
2583 | rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, ®); | |
2584 | rt2x00_set_field32(®, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1); | |
2585 | rt2x00_set_field32(®, TXOP_CTRL_CFG_AC_TRUN_EN, 1); | |
2586 | rt2x00_set_field32(®, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1); | |
2587 | rt2x00_set_field32(®, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1); | |
2588 | rt2x00_set_field32(®, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1); | |
2589 | rt2x00_set_field32(®, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1); | |
2590 | rt2x00_set_field32(®, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0); | |
2591 | rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_EN, 0); | |
2592 | rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_DLY, 88); | |
2593 | rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CWMIN, 0); | |
2594 | rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg); | |
2595 | ||
fcf51541 BZ |
2596 | rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002); |
2597 | ||
2598 | rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®); | |
2599 | rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32); | |
2600 | rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, | |
2601 | IEEE80211_MAX_RTS_THRESHOLD); | |
2602 | rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 0); | |
2603 | rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); | |
2604 | ||
2605 | rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca); | |
a9dce149 | 2606 | |
a21c2ab4 HS |
2607 | /* |
2608 | * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS | |
2609 | * time should be set to 16. However, the original Ralink driver uses | |
2610 | * 16 for both and indeed using a value of 10 for CCK SIFS results in | |
2611 | * connection problems with 11g + CTS protection. Hence, use the same | |
2612 | * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS. | |
2613 | */ | |
a9dce149 | 2614 | rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, ®); |
a21c2ab4 HS |
2615 | rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16); |
2616 | rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16); | |
a9dce149 GW |
2617 | rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4); |
2618 | rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, 314); | |
2619 | rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1); | |
2620 | rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); | |
2621 | ||
fcf51541 BZ |
2622 | rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); |
2623 | ||
2624 | /* | |
2625 | * ASIC will keep garbage value after boot, clear encryption keys. | |
2626 | */ | |
2627 | for (i = 0; i < 4; i++) | |
2628 | rt2800_register_write(rt2x00dev, | |
2629 | SHARED_KEY_MODE_ENTRY(i), 0); | |
2630 | ||
2631 | for (i = 0; i < 256; i++) { | |
f4e16e41 | 2632 | static const u32 wcid[2] = { 0xffffffff, 0x00ffffff }; |
fcf51541 BZ |
2633 | rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i), |
2634 | wcid, sizeof(wcid)); | |
2635 | ||
1ed3811c | 2636 | rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 0); |
fcf51541 BZ |
2637 | rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0); |
2638 | } | |
2639 | ||
2640 | /* | |
2641 | * Clear all beacons | |
fcf51541 | 2642 | */ |
69cf36a4 HS |
2643 | rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0); |
2644 | rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1); | |
2645 | rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2); | |
2646 | rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3); | |
2647 | rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4); | |
2648 | rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5); | |
2649 | rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6); | |
2650 | rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7); | |
fcf51541 | 2651 | |
cea90e55 | 2652 | if (rt2x00_is_usb(rt2x00dev)) { |
785c3c06 GW |
2653 | rt2800_register_read(rt2x00dev, US_CYC_CNT, ®); |
2654 | rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 30); | |
2655 | rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); | |
c6fcc0e5 RJH |
2656 | } else if (rt2x00_is_pcie(rt2x00dev)) { |
2657 | rt2800_register_read(rt2x00dev, US_CYC_CNT, ®); | |
2658 | rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 125); | |
2659 | rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); | |
fcf51541 BZ |
2660 | } |
2661 | ||
2662 | rt2800_register_read(rt2x00dev, HT_FBK_CFG0, ®); | |
2663 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0); | |
2664 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0); | |
2665 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1); | |
2666 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2); | |
2667 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3); | |
2668 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4); | |
2669 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5); | |
2670 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6); | |
2671 | rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg); | |
2672 | ||
2673 | rt2800_register_read(rt2x00dev, HT_FBK_CFG1, ®); | |
2674 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8); | |
2675 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8); | |
2676 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9); | |
2677 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10); | |
2678 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11); | |
2679 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12); | |
2680 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13); | |
2681 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14); | |
2682 | rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg); | |
2683 | ||
2684 | rt2800_register_read(rt2x00dev, LG_FBK_CFG0, ®); | |
2685 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8); | |
2686 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8); | |
2687 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9); | |
2688 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10); | |
2689 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11); | |
2690 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12); | |
2691 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13); | |
2692 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14); | |
2693 | rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg); | |
2694 | ||
2695 | rt2800_register_read(rt2x00dev, LG_FBK_CFG1, ®); | |
2696 | rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0); | |
2697 | rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0); | |
2698 | rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1); | |
2699 | rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2); | |
2700 | rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg); | |
2701 | ||
47ee3eb1 HS |
2702 | /* |
2703 | * Do not force the BA window size, we use the TXWI to set it | |
2704 | */ | |
2705 | rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, ®); | |
2706 | rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0); | |
2707 | rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0); | |
2708 | rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg); | |
2709 | ||
fcf51541 BZ |
2710 | /* |
2711 | * We must clear the error counters. | |
2712 | * These registers are cleared on read, | |
2713 | * so we may pass a useless variable to store the value. | |
2714 | */ | |
2715 | rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®); | |
2716 | rt2800_register_read(rt2x00dev, RX_STA_CNT1, ®); | |
2717 | rt2800_register_read(rt2x00dev, RX_STA_CNT2, ®); | |
2718 | rt2800_register_read(rt2x00dev, TX_STA_CNT0, ®); | |
2719 | rt2800_register_read(rt2x00dev, TX_STA_CNT1, ®); | |
2720 | rt2800_register_read(rt2x00dev, TX_STA_CNT2, ®); | |
2721 | ||
9f926fb5 HS |
2722 | /* |
2723 | * Setup leadtime for pre tbtt interrupt to 6ms | |
2724 | */ | |
2725 | rt2800_register_read(rt2x00dev, INT_TIMER_CFG, ®); | |
2726 | rt2x00_set_field32(®, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4); | |
2727 | rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg); | |
2728 | ||
977206d7 HS |
2729 | /* |
2730 | * Set up channel statistics timer | |
2731 | */ | |
2732 | rt2800_register_read(rt2x00dev, CH_TIME_CFG, ®); | |
2733 | rt2x00_set_field32(®, CH_TIME_CFG_EIFS_BUSY, 1); | |
2734 | rt2x00_set_field32(®, CH_TIME_CFG_NAV_BUSY, 1); | |
2735 | rt2x00_set_field32(®, CH_TIME_CFG_RX_BUSY, 1); | |
2736 | rt2x00_set_field32(®, CH_TIME_CFG_TX_BUSY, 1); | |
2737 | rt2x00_set_field32(®, CH_TIME_CFG_TMR_EN, 1); | |
2738 | rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg); | |
2739 | ||
fcf51541 BZ |
2740 | return 0; |
2741 | } | |
fcf51541 BZ |
2742 | |
2743 | static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev) | |
2744 | { | |
2745 | unsigned int i; | |
2746 | u32 reg; | |
2747 | ||
2748 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
2749 | rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, ®); | |
2750 | if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY)) | |
2751 | return 0; | |
2752 | ||
2753 | udelay(REGISTER_BUSY_DELAY); | |
2754 | } | |
2755 | ||
2756 | ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n"); | |
2757 | return -EACCES; | |
2758 | } | |
2759 | ||
2760 | static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) | |
2761 | { | |
2762 | unsigned int i; | |
2763 | u8 value; | |
2764 | ||
2765 | /* | |
2766 | * BBP was enabled after firmware was loaded, | |
2767 | * but we need to reactivate it now. | |
2768 | */ | |
2769 | rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); | |
2770 | rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); | |
2771 | msleep(1); | |
2772 | ||
2773 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
2774 | rt2800_bbp_read(rt2x00dev, 0, &value); | |
2775 | if ((value != 0xff) && (value != 0x00)) | |
2776 | return 0; | |
2777 | udelay(REGISTER_BUSY_DELAY); | |
2778 | } | |
2779 | ||
2780 | ERROR(rt2x00dev, "BBP register access failed, aborting.\n"); | |
2781 | return -EACCES; | |
2782 | } | |
2783 | ||
b9a07ae9 | 2784 | static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev) |
fcf51541 BZ |
2785 | { |
2786 | unsigned int i; | |
2787 | u16 eeprom; | |
2788 | u8 reg_id; | |
2789 | u8 value; | |
2790 | ||
2791 | if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) || | |
2792 | rt2800_wait_bbp_ready(rt2x00dev))) | |
2793 | return -EACCES; | |
2794 | ||
adde5882 GJ |
2795 | if (rt2x00_rt(rt2x00dev, RT5390)) { |
2796 | rt2800_bbp_read(rt2x00dev, 4, &value); | |
2797 | rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1); | |
2798 | rt2800_bbp_write(rt2x00dev, 4, value); | |
2799 | } | |
60687ba7 | 2800 | |
adde5882 GJ |
2801 | if (rt2800_is_305x_soc(rt2x00dev) || |
2802 | rt2x00_rt(rt2x00dev, RT5390)) | |
baff8006 HS |
2803 | rt2800_bbp_write(rt2x00dev, 31, 0x08); |
2804 | ||
fcf51541 BZ |
2805 | rt2800_bbp_write(rt2x00dev, 65, 0x2c); |
2806 | rt2800_bbp_write(rt2x00dev, 66, 0x38); | |
a9dce149 | 2807 | |
adde5882 GJ |
2808 | if (rt2x00_rt(rt2x00dev, RT5390)) |
2809 | rt2800_bbp_write(rt2x00dev, 68, 0x0b); | |
60687ba7 | 2810 | |
a9dce149 GW |
2811 | if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { |
2812 | rt2800_bbp_write(rt2x00dev, 69, 0x16); | |
2813 | rt2800_bbp_write(rt2x00dev, 73, 0x12); | |
adde5882 GJ |
2814 | } else if (rt2x00_rt(rt2x00dev, RT5390)) { |
2815 | rt2800_bbp_write(rt2x00dev, 69, 0x12); | |
2816 | rt2800_bbp_write(rt2x00dev, 73, 0x13); | |
2817 | rt2800_bbp_write(rt2x00dev, 75, 0x46); | |
2818 | rt2800_bbp_write(rt2x00dev, 76, 0x28); | |
2819 | rt2800_bbp_write(rt2x00dev, 77, 0x59); | |
a9dce149 GW |
2820 | } else { |
2821 | rt2800_bbp_write(rt2x00dev, 69, 0x12); | |
2822 | rt2800_bbp_write(rt2x00dev, 73, 0x10); | |
2823 | } | |
2824 | ||
fcf51541 | 2825 | rt2800_bbp_write(rt2x00dev, 70, 0x0a); |
8cdd15e0 | 2826 | |
d5385bfc | 2827 | if (rt2x00_rt(rt2x00dev, RT3070) || |
64522957 | 2828 | rt2x00_rt(rt2x00dev, RT3071) || |
cc78e904 | 2829 | rt2x00_rt(rt2x00dev, RT3090) || |
adde5882 GJ |
2830 | rt2x00_rt(rt2x00dev, RT3390) || |
2831 | rt2x00_rt(rt2x00dev, RT5390)) { | |
8cdd15e0 GW |
2832 | rt2800_bbp_write(rt2x00dev, 79, 0x13); |
2833 | rt2800_bbp_write(rt2x00dev, 80, 0x05); | |
2834 | rt2800_bbp_write(rt2x00dev, 81, 0x33); | |
baff8006 HS |
2835 | } else if (rt2800_is_305x_soc(rt2x00dev)) { |
2836 | rt2800_bbp_write(rt2x00dev, 78, 0x0e); | |
2837 | rt2800_bbp_write(rt2x00dev, 80, 0x08); | |
8cdd15e0 GW |
2838 | } else { |
2839 | rt2800_bbp_write(rt2x00dev, 81, 0x37); | |
2840 | } | |
2841 | ||
fcf51541 | 2842 | rt2800_bbp_write(rt2x00dev, 82, 0x62); |
adde5882 GJ |
2843 | if (rt2x00_rt(rt2x00dev, RT5390)) |
2844 | rt2800_bbp_write(rt2x00dev, 83, 0x7a); | |
2845 | else | |
2846 | rt2800_bbp_write(rt2x00dev, 83, 0x6a); | |
a9dce149 | 2847 | |
5ed8f458 | 2848 | if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D)) |
a9dce149 | 2849 | rt2800_bbp_write(rt2x00dev, 84, 0x19); |
adde5882 GJ |
2850 | else if (rt2x00_rt(rt2x00dev, RT5390)) |
2851 | rt2800_bbp_write(rt2x00dev, 84, 0x9a); | |
a9dce149 GW |
2852 | else |
2853 | rt2800_bbp_write(rt2x00dev, 84, 0x99); | |
2854 | ||
adde5882 GJ |
2855 | if (rt2x00_rt(rt2x00dev, RT5390)) |
2856 | rt2800_bbp_write(rt2x00dev, 86, 0x38); | |
2857 | else | |
2858 | rt2800_bbp_write(rt2x00dev, 86, 0x00); | |
60687ba7 | 2859 | |
fcf51541 | 2860 | rt2800_bbp_write(rt2x00dev, 91, 0x04); |
60687ba7 | 2861 | |
adde5882 GJ |
2862 | if (rt2x00_rt(rt2x00dev, RT5390)) |
2863 | rt2800_bbp_write(rt2x00dev, 92, 0x02); | |
2864 | else | |
2865 | rt2800_bbp_write(rt2x00dev, 92, 0x00); | |
8cdd15e0 | 2866 | |
d5385bfc | 2867 | if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) || |
64522957 | 2868 | rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) || |
cc78e904 | 2869 | rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) || |
baff8006 | 2870 | rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) || |
adde5882 | 2871 | rt2x00_rt(rt2x00dev, RT5390) || |
baff8006 | 2872 | rt2800_is_305x_soc(rt2x00dev)) |
8cdd15e0 GW |
2873 | rt2800_bbp_write(rt2x00dev, 103, 0xc0); |
2874 | else | |
2875 | rt2800_bbp_write(rt2x00dev, 103, 0x00); | |
2876 | ||
adde5882 GJ |
2877 | if (rt2x00_rt(rt2x00dev, RT5390)) |
2878 | rt2800_bbp_write(rt2x00dev, 104, 0x92); | |
60687ba7 | 2879 | |
baff8006 HS |
2880 | if (rt2800_is_305x_soc(rt2x00dev)) |
2881 | rt2800_bbp_write(rt2x00dev, 105, 0x01); | |
adde5882 GJ |
2882 | else if (rt2x00_rt(rt2x00dev, RT5390)) |
2883 | rt2800_bbp_write(rt2x00dev, 105, 0x3c); | |
baff8006 HS |
2884 | else |
2885 | rt2800_bbp_write(rt2x00dev, 105, 0x05); | |
60687ba7 | 2886 | |
adde5882 GJ |
2887 | if (rt2x00_rt(rt2x00dev, RT5390)) |
2888 | rt2800_bbp_write(rt2x00dev, 106, 0x03); | |
2889 | else | |
2890 | rt2800_bbp_write(rt2x00dev, 106, 0x35); | |
60687ba7 | 2891 | |
adde5882 GJ |
2892 | if (rt2x00_rt(rt2x00dev, RT5390)) |
2893 | rt2800_bbp_write(rt2x00dev, 128, 0x12); | |
fcf51541 | 2894 | |
64522957 | 2895 | if (rt2x00_rt(rt2x00dev, RT3071) || |
cc78e904 | 2896 | rt2x00_rt(rt2x00dev, RT3090) || |
adde5882 GJ |
2897 | rt2x00_rt(rt2x00dev, RT3390) || |
2898 | rt2x00_rt(rt2x00dev, RT5390)) { | |
d5385bfc | 2899 | rt2800_bbp_read(rt2x00dev, 138, &value); |
fcf51541 | 2900 | |
38c8a566 RJH |
2901 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); |
2902 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) | |
d5385bfc | 2903 | value |= 0x20; |
38c8a566 | 2904 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) |
d5385bfc | 2905 | value &= ~0x02; |
fcf51541 | 2906 | |
d5385bfc | 2907 | rt2800_bbp_write(rt2x00dev, 138, value); |
fcf51541 BZ |
2908 | } |
2909 | ||
adde5882 GJ |
2910 | if (rt2x00_rt(rt2x00dev, RT5390)) { |
2911 | int ant, div_mode; | |
2912 | ||
2913 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom); | |
2914 | div_mode = rt2x00_get_field16(eeprom, | |
2915 | EEPROM_NIC_CONF1_ANT_DIVERSITY); | |
2916 | ant = (div_mode == 3) ? 1 : 0; | |
2917 | ||
2918 | /* check if this is a Bluetooth combo card */ | |
fdbc7b0a | 2919 | if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) { |
adde5882 GJ |
2920 | u32 reg; |
2921 | ||
2922 | rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, ®); | |
2923 | rt2x00_set_field32(®, GPIO_CTRL_CFG_GPIOD_BIT3, 0); | |
2924 | rt2x00_set_field32(®, GPIO_CTRL_CFG_GPIOD_BIT6, 0); | |
2925 | rt2x00_set_field32(®, GPIO_CTRL_CFG_BIT3, 0); | |
2926 | rt2x00_set_field32(®, GPIO_CTRL_CFG_BIT6, 0); | |
2927 | if (ant == 0) | |
2928 | rt2x00_set_field32(®, GPIO_CTRL_CFG_BIT3, 1); | |
2929 | else if (ant == 1) | |
2930 | rt2x00_set_field32(®, GPIO_CTRL_CFG_BIT6, 1); | |
2931 | rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg); | |
2932 | } | |
2933 | ||
2934 | rt2800_bbp_read(rt2x00dev, 152, &value); | |
2935 | if (ant == 0) | |
2936 | rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); | |
2937 | else | |
2938 | rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0); | |
2939 | rt2800_bbp_write(rt2x00dev, 152, value); | |
2940 | ||
2941 | /* Init frequency calibration */ | |
2942 | rt2800_bbp_write(rt2x00dev, 142, 1); | |
2943 | rt2800_bbp_write(rt2x00dev, 143, 57); | |
2944 | } | |
fcf51541 BZ |
2945 | |
2946 | for (i = 0; i < EEPROM_BBP_SIZE; i++) { | |
2947 | rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); | |
2948 | ||
2949 | if (eeprom != 0xffff && eeprom != 0x0000) { | |
2950 | reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); | |
2951 | value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); | |
2952 | rt2800_bbp_write(rt2x00dev, reg_id, value); | |
2953 | } | |
2954 | } | |
2955 | ||
2956 | return 0; | |
2957 | } | |
fcf51541 BZ |
2958 | |
2959 | static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, | |
2960 | bool bw40, u8 rfcsr24, u8 filter_target) | |
2961 | { | |
2962 | unsigned int i; | |
2963 | u8 bbp; | |
2964 | u8 rfcsr; | |
2965 | u8 passband; | |
2966 | u8 stopband; | |
2967 | u8 overtuned = 0; | |
2968 | ||
2969 | rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); | |
2970 | ||
2971 | rt2800_bbp_read(rt2x00dev, 4, &bbp); | |
2972 | rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40); | |
2973 | rt2800_bbp_write(rt2x00dev, 4, bbp); | |
2974 | ||
80d184e6 RJH |
2975 | rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr); |
2976 | rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40); | |
2977 | rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); | |
2978 | ||
fcf51541 BZ |
2979 | rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr); |
2980 | rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1); | |
2981 | rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); | |
2982 | ||
2983 | /* | |
2984 | * Set power & frequency of passband test tone | |
2985 | */ | |
2986 | rt2800_bbp_write(rt2x00dev, 24, 0); | |
2987 | ||
2988 | for (i = 0; i < 100; i++) { | |
2989 | rt2800_bbp_write(rt2x00dev, 25, 0x90); | |
2990 | msleep(1); | |
2991 | ||
2992 | rt2800_bbp_read(rt2x00dev, 55, &passband); | |
2993 | if (passband) | |
2994 | break; | |
2995 | } | |
2996 | ||
2997 | /* | |
2998 | * Set power & frequency of stopband test tone | |
2999 | */ | |
3000 | rt2800_bbp_write(rt2x00dev, 24, 0x06); | |
3001 | ||
3002 | for (i = 0; i < 100; i++) { | |
3003 | rt2800_bbp_write(rt2x00dev, 25, 0x90); | |
3004 | msleep(1); | |
3005 | ||
3006 | rt2800_bbp_read(rt2x00dev, 55, &stopband); | |
3007 | ||
3008 | if ((passband - stopband) <= filter_target) { | |
3009 | rfcsr24++; | |
3010 | overtuned += ((passband - stopband) == filter_target); | |
3011 | } else | |
3012 | break; | |
3013 | ||
3014 | rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); | |
3015 | } | |
3016 | ||
3017 | rfcsr24 -= !!overtuned; | |
3018 | ||
3019 | rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); | |
3020 | return rfcsr24; | |
3021 | } | |
3022 | ||
b9a07ae9 | 3023 | static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) |
fcf51541 BZ |
3024 | { |
3025 | u8 rfcsr; | |
3026 | u8 bbp; | |
8cdd15e0 GW |
3027 | u32 reg; |
3028 | u16 eeprom; | |
fcf51541 | 3029 | |
d5385bfc | 3030 | if (!rt2x00_rt(rt2x00dev, RT3070) && |
64522957 | 3031 | !rt2x00_rt(rt2x00dev, RT3071) && |
cc78e904 | 3032 | !rt2x00_rt(rt2x00dev, RT3090) && |
23812383 | 3033 | !rt2x00_rt(rt2x00dev, RT3390) && |
adde5882 | 3034 | !rt2x00_rt(rt2x00dev, RT5390) && |
baff8006 | 3035 | !rt2800_is_305x_soc(rt2x00dev)) |
fcf51541 BZ |
3036 | return 0; |
3037 | ||
fcf51541 BZ |
3038 | /* |
3039 | * Init RF calibration. | |
3040 | */ | |
adde5882 GJ |
3041 | if (rt2x00_rt(rt2x00dev, RT5390)) { |
3042 | rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr); | |
3043 | rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1); | |
3044 | rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); | |
3045 | msleep(1); | |
3046 | rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0); | |
3047 | rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); | |
3048 | } else { | |
3049 | rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); | |
3050 | rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1); | |
3051 | rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); | |
3052 | msleep(1); | |
3053 | rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); | |
3054 | rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); | |
3055 | } | |
fcf51541 | 3056 | |
d5385bfc | 3057 | if (rt2x00_rt(rt2x00dev, RT3070) || |
64522957 GW |
3058 | rt2x00_rt(rt2x00dev, RT3071) || |
3059 | rt2x00_rt(rt2x00dev, RT3090)) { | |
fcf51541 BZ |
3060 | rt2800_rfcsr_write(rt2x00dev, 4, 0x40); |
3061 | rt2800_rfcsr_write(rt2x00dev, 5, 0x03); | |
3062 | rt2800_rfcsr_write(rt2x00dev, 6, 0x02); | |
80d184e6 | 3063 | rt2800_rfcsr_write(rt2x00dev, 7, 0x60); |
fcf51541 | 3064 | rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); |
8cdd15e0 | 3065 | rt2800_rfcsr_write(rt2x00dev, 10, 0x41); |
fcf51541 BZ |
3066 | rt2800_rfcsr_write(rt2x00dev, 11, 0x21); |
3067 | rt2800_rfcsr_write(rt2x00dev, 12, 0x7b); | |
3068 | rt2800_rfcsr_write(rt2x00dev, 14, 0x90); | |
3069 | rt2800_rfcsr_write(rt2x00dev, 15, 0x58); | |
3070 | rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); | |
3071 | rt2800_rfcsr_write(rt2x00dev, 17, 0x92); | |
3072 | rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); | |
3073 | rt2800_rfcsr_write(rt2x00dev, 19, 0x02); | |
3074 | rt2800_rfcsr_write(rt2x00dev, 20, 0xba); | |
3075 | rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); | |
3076 | rt2800_rfcsr_write(rt2x00dev, 24, 0x16); | |
3077 | rt2800_rfcsr_write(rt2x00dev, 25, 0x01); | |
fcf51541 | 3078 | rt2800_rfcsr_write(rt2x00dev, 29, 0x1f); |
cc78e904 GW |
3079 | } else if (rt2x00_rt(rt2x00dev, RT3390)) { |
3080 | rt2800_rfcsr_write(rt2x00dev, 0, 0xa0); | |
3081 | rt2800_rfcsr_write(rt2x00dev, 1, 0xe1); | |
3082 | rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); | |
3083 | rt2800_rfcsr_write(rt2x00dev, 3, 0x62); | |
fcf51541 | 3084 | rt2800_rfcsr_write(rt2x00dev, 4, 0x40); |
cc78e904 GW |
3085 | rt2800_rfcsr_write(rt2x00dev, 5, 0x8b); |
3086 | rt2800_rfcsr_write(rt2x00dev, 6, 0x42); | |
3087 | rt2800_rfcsr_write(rt2x00dev, 7, 0x34); | |
3088 | rt2800_rfcsr_write(rt2x00dev, 8, 0x00); | |
3089 | rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); | |
3090 | rt2800_rfcsr_write(rt2x00dev, 10, 0x61); | |
fcf51541 | 3091 | rt2800_rfcsr_write(rt2x00dev, 11, 0x21); |
cc78e904 GW |
3092 | rt2800_rfcsr_write(rt2x00dev, 12, 0x3b); |
3093 | rt2800_rfcsr_write(rt2x00dev, 13, 0xe0); | |
fcf51541 | 3094 | rt2800_rfcsr_write(rt2x00dev, 14, 0x90); |
cc78e904 GW |
3095 | rt2800_rfcsr_write(rt2x00dev, 15, 0x53); |
3096 | rt2800_rfcsr_write(rt2x00dev, 16, 0xe0); | |
3097 | rt2800_rfcsr_write(rt2x00dev, 17, 0x94); | |
3098 | rt2800_rfcsr_write(rt2x00dev, 18, 0x5c); | |
3099 | rt2800_rfcsr_write(rt2x00dev, 19, 0x4a); | |
3100 | rt2800_rfcsr_write(rt2x00dev, 20, 0xb2); | |
3101 | rt2800_rfcsr_write(rt2x00dev, 21, 0xf6); | |
fcf51541 | 3102 | rt2800_rfcsr_write(rt2x00dev, 22, 0x00); |
cc78e904 | 3103 | rt2800_rfcsr_write(rt2x00dev, 23, 0x14); |
fcf51541 | 3104 | rt2800_rfcsr_write(rt2x00dev, 24, 0x08); |
cc78e904 GW |
3105 | rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); |
3106 | rt2800_rfcsr_write(rt2x00dev, 26, 0x85); | |
3107 | rt2800_rfcsr_write(rt2x00dev, 27, 0x00); | |
3108 | rt2800_rfcsr_write(rt2x00dev, 28, 0x41); | |
3109 | rt2800_rfcsr_write(rt2x00dev, 29, 0x8f); | |
3110 | rt2800_rfcsr_write(rt2x00dev, 30, 0x20); | |
3111 | rt2800_rfcsr_write(rt2x00dev, 31, 0x0f); | |
baff8006 | 3112 | } else if (rt2800_is_305x_soc(rt2x00dev)) { |
23812383 HS |
3113 | rt2800_rfcsr_write(rt2x00dev, 0, 0x50); |
3114 | rt2800_rfcsr_write(rt2x00dev, 1, 0x01); | |
3115 | rt2800_rfcsr_write(rt2x00dev, 2, 0xf7); | |
3116 | rt2800_rfcsr_write(rt2x00dev, 3, 0x75); | |
3117 | rt2800_rfcsr_write(rt2x00dev, 4, 0x40); | |
3118 | rt2800_rfcsr_write(rt2x00dev, 5, 0x03); | |
3119 | rt2800_rfcsr_write(rt2x00dev, 6, 0x02); | |
3120 | rt2800_rfcsr_write(rt2x00dev, 7, 0x50); | |
3121 | rt2800_rfcsr_write(rt2x00dev, 8, 0x39); | |
3122 | rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); | |
3123 | rt2800_rfcsr_write(rt2x00dev, 10, 0x60); | |
3124 | rt2800_rfcsr_write(rt2x00dev, 11, 0x21); | |
3125 | rt2800_rfcsr_write(rt2x00dev, 12, 0x75); | |
3126 | rt2800_rfcsr_write(rt2x00dev, 13, 0x75); | |
3127 | rt2800_rfcsr_write(rt2x00dev, 14, 0x90); | |
3128 | rt2800_rfcsr_write(rt2x00dev, 15, 0x58); | |
3129 | rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); | |
3130 | rt2800_rfcsr_write(rt2x00dev, 17, 0x92); | |
3131 | rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); | |
3132 | rt2800_rfcsr_write(rt2x00dev, 19, 0x02); | |
3133 | rt2800_rfcsr_write(rt2x00dev, 20, 0xba); | |
3134 | rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); | |
3135 | rt2800_rfcsr_write(rt2x00dev, 22, 0x00); | |
3136 | rt2800_rfcsr_write(rt2x00dev, 23, 0x31); | |
3137 | rt2800_rfcsr_write(rt2x00dev, 24, 0x08); | |
3138 | rt2800_rfcsr_write(rt2x00dev, 25, 0x01); | |
3139 | rt2800_rfcsr_write(rt2x00dev, 26, 0x25); | |
3140 | rt2800_rfcsr_write(rt2x00dev, 27, 0x23); | |
3141 | rt2800_rfcsr_write(rt2x00dev, 28, 0x13); | |
3142 | rt2800_rfcsr_write(rt2x00dev, 29, 0x83); | |
baff8006 HS |
3143 | rt2800_rfcsr_write(rt2x00dev, 30, 0x00); |
3144 | rt2800_rfcsr_write(rt2x00dev, 31, 0x00); | |
3145 | return 0; | |
adde5882 GJ |
3146 | } else if (rt2x00_rt(rt2x00dev, RT5390)) { |
3147 | rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); | |
3148 | rt2800_rfcsr_write(rt2x00dev, 2, 0x80); | |
3149 | rt2800_rfcsr_write(rt2x00dev, 3, 0x88); | |
3150 | rt2800_rfcsr_write(rt2x00dev, 5, 0x10); | |
3151 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) | |
3152 | rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); | |
3153 | else | |
3154 | rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); | |
3155 | rt2800_rfcsr_write(rt2x00dev, 7, 0x00); | |
3156 | rt2800_rfcsr_write(rt2x00dev, 10, 0x53); | |
3157 | rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); | |
3158 | rt2800_rfcsr_write(rt2x00dev, 12, 0xc6); | |
3159 | rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); | |
3160 | rt2800_rfcsr_write(rt2x00dev, 14, 0x00); | |
3161 | rt2800_rfcsr_write(rt2x00dev, 15, 0x00); | |
3162 | rt2800_rfcsr_write(rt2x00dev, 16, 0x00); | |
3163 | rt2800_rfcsr_write(rt2x00dev, 18, 0x03); | |
3164 | rt2800_rfcsr_write(rt2x00dev, 19, 0x00); | |
3165 | ||
3166 | rt2800_rfcsr_write(rt2x00dev, 20, 0x00); | |
3167 | rt2800_rfcsr_write(rt2x00dev, 21, 0x00); | |
3168 | rt2800_rfcsr_write(rt2x00dev, 22, 0x20); | |
3169 | rt2800_rfcsr_write(rt2x00dev, 23, 0x00); | |
3170 | rt2800_rfcsr_write(rt2x00dev, 24, 0x00); | |
3171 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) | |
3172 | rt2800_rfcsr_write(rt2x00dev, 25, 0x80); | |
3173 | else | |
3174 | rt2800_rfcsr_write(rt2x00dev, 25, 0xc0); | |
3175 | rt2800_rfcsr_write(rt2x00dev, 26, 0x00); | |
3176 | rt2800_rfcsr_write(rt2x00dev, 27, 0x09); | |
3177 | rt2800_rfcsr_write(rt2x00dev, 28, 0x00); | |
3178 | rt2800_rfcsr_write(rt2x00dev, 29, 0x10); | |
3179 | ||
3180 | rt2800_rfcsr_write(rt2x00dev, 30, 0x00); | |
3181 | rt2800_rfcsr_write(rt2x00dev, 31, 0x80); | |
3182 | rt2800_rfcsr_write(rt2x00dev, 32, 0x80); | |
3183 | rt2800_rfcsr_write(rt2x00dev, 33, 0x00); | |
3184 | rt2800_rfcsr_write(rt2x00dev, 34, 0x07); | |
3185 | rt2800_rfcsr_write(rt2x00dev, 35, 0x12); | |
3186 | rt2800_rfcsr_write(rt2x00dev, 36, 0x00); | |
3187 | rt2800_rfcsr_write(rt2x00dev, 37, 0x08); | |
3188 | rt2800_rfcsr_write(rt2x00dev, 38, 0x85); | |
3189 | rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); | |
3190 | ||
3191 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) | |
3192 | rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); | |
3193 | else | |
3194 | rt2800_rfcsr_write(rt2x00dev, 40, 0x4b); | |
3195 | rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); | |
3196 | rt2800_rfcsr_write(rt2x00dev, 42, 0xd2); | |
3197 | rt2800_rfcsr_write(rt2x00dev, 43, 0x9a); | |
3198 | rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); | |
3199 | rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); | |
3200 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) | |
3201 | rt2800_rfcsr_write(rt2x00dev, 46, 0x73); | |
3202 | else | |
3203 | rt2800_rfcsr_write(rt2x00dev, 46, 0x7b); | |
3204 | rt2800_rfcsr_write(rt2x00dev, 47, 0x00); | |
3205 | rt2800_rfcsr_write(rt2x00dev, 48, 0x10); | |
3206 | rt2800_rfcsr_write(rt2x00dev, 49, 0x94); | |
3207 | ||
3208 | rt2800_rfcsr_write(rt2x00dev, 52, 0x38); | |
3209 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) | |
3210 | rt2800_rfcsr_write(rt2x00dev, 53, 0x00); | |
3211 | else | |
3212 | rt2800_rfcsr_write(rt2x00dev, 53, 0x84); | |
3213 | rt2800_rfcsr_write(rt2x00dev, 54, 0x78); | |
3214 | rt2800_rfcsr_write(rt2x00dev, 55, 0x44); | |
3215 | rt2800_rfcsr_write(rt2x00dev, 56, 0x22); | |
3216 | rt2800_rfcsr_write(rt2x00dev, 57, 0x80); | |
3217 | rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); | |
3218 | rt2800_rfcsr_write(rt2x00dev, 59, 0x63); | |
3219 | ||
3220 | rt2800_rfcsr_write(rt2x00dev, 60, 0x45); | |
3221 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) | |
3222 | rt2800_rfcsr_write(rt2x00dev, 61, 0xd1); | |
3223 | else | |
3224 | rt2800_rfcsr_write(rt2x00dev, 61, 0xdd); | |
3225 | rt2800_rfcsr_write(rt2x00dev, 62, 0x00); | |
3226 | rt2800_rfcsr_write(rt2x00dev, 63, 0x00); | |
8cdd15e0 GW |
3227 | } |
3228 | ||
3229 | if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { | |
3230 | rt2800_register_read(rt2x00dev, LDO_CFG0, ®); | |
3231 | rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); | |
3232 | rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); | |
3233 | rt2800_register_write(rt2x00dev, LDO_CFG0, reg); | |
64522957 GW |
3234 | } else if (rt2x00_rt(rt2x00dev, RT3071) || |
3235 | rt2x00_rt(rt2x00dev, RT3090)) { | |
80d184e6 RJH |
3236 | rt2800_rfcsr_write(rt2x00dev, 31, 0x14); |
3237 | ||
d5385bfc GW |
3238 | rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); |
3239 | rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); | |
3240 | rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); | |
3241 | ||
d5385bfc GW |
3242 | rt2800_register_read(rt2x00dev, LDO_CFG0, ®); |
3243 | rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); | |
64522957 GW |
3244 | if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || |
3245 | rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) { | |
38c8a566 RJH |
3246 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom); |
3247 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) | |
d5385bfc GW |
3248 | rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); |
3249 | else | |
3250 | rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); | |
3251 | } | |
3252 | rt2800_register_write(rt2x00dev, LDO_CFG0, reg); | |
80d184e6 RJH |
3253 | |
3254 | rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); | |
3255 | rt2x00_set_field32(®, GPIO_SWITCH_5, 0); | |
3256 | rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); | |
cc78e904 GW |
3257 | } else if (rt2x00_rt(rt2x00dev, RT3390)) { |
3258 | rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); | |
3259 | rt2x00_set_field32(®, GPIO_SWITCH_5, 0); | |
3260 | rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); | |
fcf51541 BZ |
3261 | } |
3262 | ||
3263 | /* | |
3264 | * Set RX Filter calibration for 20MHz and 40MHz | |
3265 | */ | |
8cdd15e0 GW |
3266 | if (rt2x00_rt(rt2x00dev, RT3070)) { |
3267 | rt2x00dev->calibration[0] = | |
3268 | rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16); | |
3269 | rt2x00dev->calibration[1] = | |
3270 | rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19); | |
64522957 | 3271 | } else if (rt2x00_rt(rt2x00dev, RT3071) || |
cc78e904 GW |
3272 | rt2x00_rt(rt2x00dev, RT3090) || |
3273 | rt2x00_rt(rt2x00dev, RT3390)) { | |
d5385bfc GW |
3274 | rt2x00dev->calibration[0] = |
3275 | rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13); | |
3276 | rt2x00dev->calibration[1] = | |
3277 | rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15); | |
8cdd15e0 | 3278 | } |
fcf51541 | 3279 | |
adde5882 GJ |
3280 | if (!rt2x00_rt(rt2x00dev, RT5390)) { |
3281 | /* | |
3282 | * Set back to initial state | |
3283 | */ | |
3284 | rt2800_bbp_write(rt2x00dev, 24, 0); | |
fcf51541 | 3285 | |
adde5882 GJ |
3286 | rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr); |
3287 | rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0); | |
3288 | rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); | |
fcf51541 | 3289 | |
adde5882 GJ |
3290 | /* |
3291 | * Set BBP back to BW20 | |
3292 | */ | |
3293 | rt2800_bbp_read(rt2x00dev, 4, &bbp); | |
3294 | rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0); | |
3295 | rt2800_bbp_write(rt2x00dev, 4, bbp); | |
3296 | } | |
fcf51541 | 3297 | |
d5385bfc | 3298 | if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) || |
64522957 | 3299 | rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || |
cc78e904 GW |
3300 | rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || |
3301 | rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) | |
8cdd15e0 GW |
3302 | rt2800_rfcsr_write(rt2x00dev, 27, 0x03); |
3303 | ||
3304 | rt2800_register_read(rt2x00dev, OPT_14_CSR, ®); | |
3305 | rt2x00_set_field32(®, OPT_14_CSR_BIT0, 1); | |
3306 | rt2800_register_write(rt2x00dev, OPT_14_CSR, reg); | |
3307 | ||
adde5882 GJ |
3308 | if (!rt2x00_rt(rt2x00dev, RT5390)) { |
3309 | rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr); | |
3310 | rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0); | |
3311 | if (rt2x00_rt(rt2x00dev, RT3070) || | |
3312 | rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || | |
3313 | rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || | |
3314 | rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { | |
7dab73b3 ID |
3315 | if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG, |
3316 | &rt2x00dev->cap_flags)) | |
adde5882 GJ |
3317 | rt2x00_set_field8(&rfcsr, RFCSR17_R, 1); |
3318 | } | |
3319 | rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom); | |
3320 | if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1) | |
3321 | rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN, | |
3322 | rt2x00_get_field16(eeprom, | |
3323 | EEPROM_TXMIXER_GAIN_BG_VAL)); | |
3324 | rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); | |
3325 | } | |
8cdd15e0 | 3326 | |
64522957 GW |
3327 | if (rt2x00_rt(rt2x00dev, RT3090)) { |
3328 | rt2800_bbp_read(rt2x00dev, 138, &bbp); | |
3329 | ||
80d184e6 | 3330 | /* Turn off unused DAC1 and ADC1 to reduce power consumption */ |
38c8a566 RJH |
3331 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); |
3332 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) | |
64522957 | 3333 | rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0); |
38c8a566 | 3334 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) |
64522957 GW |
3335 | rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1); |
3336 | ||
3337 | rt2800_bbp_write(rt2x00dev, 138, bbp); | |
3338 | } | |
3339 | ||
3340 | if (rt2x00_rt(rt2x00dev, RT3071) || | |
cc78e904 GW |
3341 | rt2x00_rt(rt2x00dev, RT3090) || |
3342 | rt2x00_rt(rt2x00dev, RT3390)) { | |
d5385bfc GW |
3343 | rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); |
3344 | rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); | |
3345 | rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); | |
3346 | rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); | |
3347 | rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); | |
3348 | rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); | |
3349 | rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); | |
3350 | ||
3351 | rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr); | |
3352 | rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0); | |
3353 | rt2800_rfcsr_write(rt2x00dev, 15, rfcsr); | |
3354 | ||
3355 | rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr); | |
3356 | rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0); | |
3357 | rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); | |
3358 | ||
3359 | rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr); | |
3360 | rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0); | |
3361 | rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); | |
3362 | } | |
3363 | ||
80d184e6 | 3364 | if (rt2x00_rt(rt2x00dev, RT3070)) { |
8cdd15e0 | 3365 | rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr); |
80d184e6 | 3366 | if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) |
8cdd15e0 GW |
3367 | rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3); |
3368 | else | |
3369 | rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0); | |
3370 | rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0); | |
3371 | rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0); | |
3372 | rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0); | |
3373 | rt2800_rfcsr_write(rt2x00dev, 27, rfcsr); | |
3374 | } | |
3375 | ||
adde5882 GJ |
3376 | if (rt2x00_rt(rt2x00dev, RT5390)) { |
3377 | rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr); | |
3378 | rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0); | |
3379 | rt2800_rfcsr_write(rt2x00dev, 38, rfcsr); | |
60687ba7 | 3380 | |
adde5882 GJ |
3381 | rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr); |
3382 | rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0); | |
3383 | rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); | |
60687ba7 | 3384 | |
adde5882 GJ |
3385 | rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); |
3386 | rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); | |
3387 | rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); | |
3388 | } | |
60687ba7 | 3389 | |
fcf51541 BZ |
3390 | return 0; |
3391 | } | |
b9a07ae9 ID |
3392 | |
3393 | int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev) | |
3394 | { | |
3395 | u32 reg; | |
3396 | u16 word; | |
3397 | ||
3398 | /* | |
3399 | * Initialize all registers. | |
3400 | */ | |
3401 | if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) || | |
3402 | rt2800_init_registers(rt2x00dev) || | |
3403 | rt2800_init_bbp(rt2x00dev) || | |
3404 | rt2800_init_rfcsr(rt2x00dev))) | |
3405 | return -EIO; | |
3406 | ||
3407 | /* | |
3408 | * Send signal to firmware during boot time. | |
3409 | */ | |
3410 | rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); | |
3411 | ||
3412 | if (rt2x00_is_usb(rt2x00dev) && | |
3413 | (rt2x00_rt(rt2x00dev, RT3070) || | |
3414 | rt2x00_rt(rt2x00dev, RT3071) || | |
3415 | rt2x00_rt(rt2x00dev, RT3572))) { | |
3416 | udelay(200); | |
3417 | rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0); | |
3418 | udelay(10); | |
3419 | } | |
3420 | ||
3421 | /* | |
3422 | * Enable RX. | |
3423 | */ | |
3424 | rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); | |
3425 | rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); | |
3426 | rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); | |
3427 | rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); | |
3428 | ||
3429 | udelay(50); | |
3430 | ||
3431 | rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); | |
3432 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); | |
3433 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); | |
3434 | rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2); | |
3435 | rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); | |
3436 | rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); | |
3437 | ||
3438 | rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); | |
3439 | rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); | |
3440 | rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1); | |
3441 | rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); | |
3442 | ||
3443 | /* | |
3444 | * Initialize LED control | |
3445 | */ | |
38c8a566 RJH |
3446 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word); |
3447 | rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff, | |
b9a07ae9 ID |
3448 | word & 0xff, (word >> 8) & 0xff); |
3449 | ||
38c8a566 RJH |
3450 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word); |
3451 | rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff, | |
b9a07ae9 ID |
3452 | word & 0xff, (word >> 8) & 0xff); |
3453 | ||
38c8a566 RJH |
3454 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word); |
3455 | rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff, | |
b9a07ae9 ID |
3456 | word & 0xff, (word >> 8) & 0xff); |
3457 | ||
3458 | return 0; | |
3459 | } | |
3460 | EXPORT_SYMBOL_GPL(rt2800_enable_radio); | |
3461 | ||
3462 | void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev) | |
3463 | { | |
3464 | u32 reg; | |
3465 | ||
3466 | rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); | |
3467 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); | |
b9a07ae9 | 3468 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); |
b9a07ae9 ID |
3469 | rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); |
3470 | ||
3471 | /* Wait for DMA, ignore error */ | |
3472 | rt2800_wait_wpdma_ready(rt2x00dev); | |
3473 | ||
3474 | rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); | |
3475 | rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 0); | |
3476 | rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); | |
3477 | rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); | |
b9a07ae9 ID |
3478 | } |
3479 | EXPORT_SYMBOL_GPL(rt2800_disable_radio); | |
2ce33995 | 3480 | |
30e84034 BZ |
3481 | int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev) |
3482 | { | |
3483 | u32 reg; | |
3484 | ||
3485 | rt2800_register_read(rt2x00dev, EFUSE_CTRL, ®); | |
3486 | ||
3487 | return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT); | |
3488 | } | |
3489 | EXPORT_SYMBOL_GPL(rt2800_efuse_detect); | |
3490 | ||
3491 | static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i) | |
3492 | { | |
3493 | u32 reg; | |
3494 | ||
31a4cf1f GW |
3495 | mutex_lock(&rt2x00dev->csr_mutex); |
3496 | ||
3497 | rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, ®); | |
30e84034 BZ |
3498 | rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i); |
3499 | rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0); | |
3500 | rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1); | |
31a4cf1f | 3501 | rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg); |
30e84034 BZ |
3502 | |
3503 | /* Wait until the EEPROM has been loaded */ | |
3504 | rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, ®); | |
3505 | ||
3506 | /* Apparently the data is read from end to start */ | |
31a4cf1f GW |
3507 | rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3, |
3508 | (u32 *)&rt2x00dev->eeprom[i]); | |
3509 | rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2, | |
3510 | (u32 *)&rt2x00dev->eeprom[i + 2]); | |
3511 | rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1, | |
3512 | (u32 *)&rt2x00dev->eeprom[i + 4]); | |
3513 | rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0, | |
3514 | (u32 *)&rt2x00dev->eeprom[i + 6]); | |
3515 | ||
3516 | mutex_unlock(&rt2x00dev->csr_mutex); | |
30e84034 BZ |
3517 | } |
3518 | ||
3519 | void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev) | |
3520 | { | |
3521 | unsigned int i; | |
3522 | ||
3523 | for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8) | |
3524 | rt2800_efuse_read(rt2x00dev, i); | |
3525 | } | |
3526 | EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse); | |
3527 | ||
38bd7b8a BZ |
3528 | int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev) |
3529 | { | |
3530 | u16 word; | |
3531 | u8 *mac; | |
3532 | u8 default_lna_gain; | |
3533 | ||
3534 | /* | |
3535 | * Start validation of the data that has been read. | |
3536 | */ | |
3537 | mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); | |
3538 | if (!is_valid_ether_addr(mac)) { | |
3539 | random_ether_addr(mac); | |
3540 | EEPROM(rt2x00dev, "MAC: %pM\n", mac); | |
3541 | } | |
3542 | ||
38c8a566 | 3543 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word); |
38bd7b8a | 3544 | if (word == 0xffff) { |
38c8a566 RJH |
3545 | rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); |
3546 | rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1); | |
3547 | rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820); | |
3548 | rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); | |
38bd7b8a | 3549 | EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word); |
49e721ec | 3550 | } else if (rt2x00_rt(rt2x00dev, RT2860) || |
e148b4c8 | 3551 | rt2x00_rt(rt2x00dev, RT2872)) { |
38bd7b8a BZ |
3552 | /* |
3553 | * There is a max of 2 RX streams for RT28x0 series | |
3554 | */ | |
38c8a566 RJH |
3555 | if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2) |
3556 | rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); | |
3557 | rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); | |
38bd7b8a BZ |
3558 | } |
3559 | ||
38c8a566 | 3560 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word); |
38bd7b8a | 3561 | if (word == 0xffff) { |
38c8a566 RJH |
3562 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0); |
3563 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0); | |
3564 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0); | |
3565 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0); | |
3566 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0); | |
3567 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0); | |
3568 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0); | |
3569 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0); | |
3570 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0); | |
3571 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0); | |
3572 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0); | |
3573 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0); | |
3574 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0); | |
3575 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0); | |
3576 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0); | |
3577 | rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word); | |
38bd7b8a BZ |
3578 | EEPROM(rt2x00dev, "NIC: 0x%04x\n", word); |
3579 | } | |
3580 | ||
3581 | rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word); | |
3582 | if ((word & 0x00ff) == 0x00ff) { | |
3583 | rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); | |
ec2d1791 GW |
3584 | rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word); |
3585 | EEPROM(rt2x00dev, "Freq: 0x%04x\n", word); | |
3586 | } | |
3587 | if ((word & 0xff00) == 0xff00) { | |
38bd7b8a BZ |
3588 | rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE, |
3589 | LED_MODE_TXRX_ACTIVITY); | |
3590 | rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0); | |
3591 | rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word); | |
38c8a566 RJH |
3592 | rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555); |
3593 | rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221); | |
3594 | rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8); | |
ec2d1791 | 3595 | EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word); |
38bd7b8a BZ |
3596 | } |
3597 | ||
3598 | /* | |
3599 | * During the LNA validation we are going to use | |
3600 | * lna0 as correct value. Note that EEPROM_LNA | |
3601 | * is never validated. | |
3602 | */ | |
3603 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word); | |
3604 | default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0); | |
3605 | ||
3606 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word); | |
3607 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10) | |
3608 | rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0); | |
3609 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10) | |
3610 | rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0); | |
3611 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word); | |
3612 | ||
3613 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word); | |
3614 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10) | |
3615 | rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0); | |
3616 | if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 || | |
3617 | rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff) | |
3618 | rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1, | |
3619 | default_lna_gain); | |
3620 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word); | |
3621 | ||
3622 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word); | |
3623 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10) | |
3624 | rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0); | |
3625 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10) | |
3626 | rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0); | |
3627 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word); | |
3628 | ||
3629 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word); | |
3630 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10) | |
3631 | rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0); | |
3632 | if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 || | |
3633 | rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff) | |
3634 | rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2, | |
3635 | default_lna_gain); | |
3636 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word); | |
3637 | ||
3638 | return 0; | |
3639 | } | |
3640 | EXPORT_SYMBOL_GPL(rt2800_validate_eeprom); | |
3641 | ||
3642 | int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) | |
3643 | { | |
3644 | u32 reg; | |
3645 | u16 value; | |
3646 | u16 eeprom; | |
3647 | ||
3648 | /* | |
3649 | * Read EEPROM word for configuration. | |
3650 | */ | |
38c8a566 | 3651 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); |
38bd7b8a BZ |
3652 | |
3653 | /* | |
adde5882 GJ |
3654 | * Identify RF chipset by EEPROM value |
3655 | * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field | |
3656 | * RT53xx: defined in "EEPROM_CHIP_ID" field | |
38bd7b8a | 3657 | */ |
38bd7b8a | 3658 | rt2800_register_read(rt2x00dev, MAC_CSR0, ®); |
adde5882 GJ |
3659 | if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390) |
3660 | rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value); | |
3661 | else | |
3662 | value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE); | |
38bd7b8a | 3663 | |
49e721ec GW |
3664 | rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET), |
3665 | value, rt2x00_get_field32(reg, MAC_CSR0_REVISION)); | |
3666 | ||
3667 | if (!rt2x00_rt(rt2x00dev, RT2860) && | |
49e721ec | 3668 | !rt2x00_rt(rt2x00dev, RT2872) && |
49e721ec | 3669 | !rt2x00_rt(rt2x00dev, RT2883) && |
49e721ec GW |
3670 | !rt2x00_rt(rt2x00dev, RT3070) && |
3671 | !rt2x00_rt(rt2x00dev, RT3071) && | |
3672 | !rt2x00_rt(rt2x00dev, RT3090) && | |
3673 | !rt2x00_rt(rt2x00dev, RT3390) && | |
adde5882 GJ |
3674 | !rt2x00_rt(rt2x00dev, RT3572) && |
3675 | !rt2x00_rt(rt2x00dev, RT5390)) { | |
49e721ec GW |
3676 | ERROR(rt2x00dev, "Invalid RT chipset detected.\n"); |
3677 | return -ENODEV; | |
f273fe55 | 3678 | } |
714fa663 | 3679 | |
5122d898 GW |
3680 | if (!rt2x00_rf(rt2x00dev, RF2820) && |
3681 | !rt2x00_rf(rt2x00dev, RF2850) && | |
3682 | !rt2x00_rf(rt2x00dev, RF2720) && | |
3683 | !rt2x00_rf(rt2x00dev, RF2750) && | |
3684 | !rt2x00_rf(rt2x00dev, RF3020) && | |
3685 | !rt2x00_rf(rt2x00dev, RF2020) && | |
3686 | !rt2x00_rf(rt2x00dev, RF3021) && | |
6c0fe265 | 3687 | !rt2x00_rf(rt2x00dev, RF3022) && |
f93bc9b3 | 3688 | !rt2x00_rf(rt2x00dev, RF3052) && |
adde5882 | 3689 | !rt2x00_rf(rt2x00dev, RF3320) && |
aca355b9 | 3690 | !rt2x00_rf(rt2x00dev, RF5370) && |
adde5882 | 3691 | !rt2x00_rf(rt2x00dev, RF5390)) { |
38bd7b8a BZ |
3692 | ERROR(rt2x00dev, "Invalid RF chipset detected.\n"); |
3693 | return -ENODEV; | |
3694 | } | |
3695 | ||
3696 | /* | |
3697 | * Identify default antenna configuration. | |
3698 | */ | |
d96aa640 | 3699 | rt2x00dev->default_ant.tx_chain_num = |
38c8a566 | 3700 | rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH); |
d96aa640 | 3701 | rt2x00dev->default_ant.rx_chain_num = |
38c8a566 | 3702 | rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH); |
38bd7b8a | 3703 | |
d96aa640 RJH |
3704 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom); |
3705 | ||
3706 | if (rt2x00_rt(rt2x00dev, RT3070) || | |
3707 | rt2x00_rt(rt2x00dev, RT3090) || | |
3708 | rt2x00_rt(rt2x00dev, RT3390)) { | |
3709 | value = rt2x00_get_field16(eeprom, | |
3710 | EEPROM_NIC_CONF1_ANT_DIVERSITY); | |
3711 | switch (value) { | |
3712 | case 0: | |
3713 | case 1: | |
3714 | case 2: | |
3715 | rt2x00dev->default_ant.tx = ANTENNA_A; | |
3716 | rt2x00dev->default_ant.rx = ANTENNA_A; | |
3717 | break; | |
3718 | case 3: | |
3719 | rt2x00dev->default_ant.tx = ANTENNA_A; | |
3720 | rt2x00dev->default_ant.rx = ANTENNA_B; | |
3721 | break; | |
3722 | } | |
3723 | } else { | |
3724 | rt2x00dev->default_ant.tx = ANTENNA_A; | |
3725 | rt2x00dev->default_ant.rx = ANTENNA_A; | |
3726 | } | |
3727 | ||
38bd7b8a | 3728 | /* |
9328fdac | 3729 | * Determine external LNA informations. |
38bd7b8a | 3730 | */ |
38c8a566 | 3731 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G)) |
7dab73b3 | 3732 | __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags); |
38c8a566 | 3733 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G)) |
7dab73b3 | 3734 | __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags); |
38bd7b8a BZ |
3735 | |
3736 | /* | |
3737 | * Detect if this device has an hardware controlled radio. | |
3738 | */ | |
38c8a566 | 3739 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO)) |
7dab73b3 | 3740 | __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags); |
38bd7b8a | 3741 | |
fdbc7b0a GW |
3742 | /* |
3743 | * Detect if this device has Bluetooth co-existence. | |
3744 | */ | |
3745 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) | |
3746 | __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags); | |
3747 | ||
9328fdac GW |
3748 | /* |
3749 | * Read frequency offset and RF programming sequence. | |
3750 | */ | |
3751 | rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); | |
3752 | rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); | |
3753 | ||
38bd7b8a BZ |
3754 | /* |
3755 | * Store led settings, for correct led behaviour. | |
3756 | */ | |
3757 | #ifdef CONFIG_RT2X00_LIB_LEDS | |
3758 | rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); | |
3759 | rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); | |
3760 | rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY); | |
3761 | ||
9328fdac | 3762 | rt2x00dev->led_mcu_reg = eeprom; |
38bd7b8a BZ |
3763 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
3764 | ||
e90c54b2 RJH |
3765 | /* |
3766 | * Check if support EIRP tx power limit feature. | |
3767 | */ | |
3768 | rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom); | |
3769 | ||
3770 | if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) < | |
3771 | EIRP_MAX_TX_POWER_LIMIT) | |
7dab73b3 | 3772 | __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags); |
e90c54b2 | 3773 | |
38bd7b8a BZ |
3774 | return 0; |
3775 | } | |
3776 | EXPORT_SYMBOL_GPL(rt2800_init_eeprom); | |
3777 | ||
4da2933f | 3778 | /* |
55f9321a | 3779 | * RF value list for rt28xx |
4da2933f BZ |
3780 | * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750) |
3781 | */ | |
3782 | static const struct rf_channel rf_vals[] = { | |
3783 | { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b }, | |
3784 | { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f }, | |
3785 | { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b }, | |
3786 | { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f }, | |
3787 | { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b }, | |
3788 | { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f }, | |
3789 | { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b }, | |
3790 | { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f }, | |
3791 | { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b }, | |
3792 | { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f }, | |
3793 | { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b }, | |
3794 | { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f }, | |
3795 | { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b }, | |
3796 | { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 }, | |
3797 | ||
3798 | /* 802.11 UNI / HyperLan 2 */ | |
3799 | { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 }, | |
3800 | { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 }, | |
3801 | { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 }, | |
3802 | { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 }, | |
3803 | { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b }, | |
3804 | { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b }, | |
3805 | { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 }, | |
3806 | { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 }, | |
3807 | { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b }, | |
3808 | { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 }, | |
3809 | { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 }, | |
3810 | { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 }, | |
3811 | ||
3812 | /* 802.11 HyperLan 2 */ | |
3813 | { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 }, | |
3814 | { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 }, | |
3815 | { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 }, | |
3816 | { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 }, | |
3817 | { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 }, | |
3818 | { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b }, | |
3819 | { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 }, | |
3820 | { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 }, | |
3821 | { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 }, | |
3822 | { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 }, | |
3823 | { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b }, | |
3824 | { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 }, | |
3825 | { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b }, | |
3826 | { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 }, | |
3827 | { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b }, | |
3828 | { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 }, | |
3829 | ||
3830 | /* 802.11 UNII */ | |
3831 | { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 }, | |
3832 | { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 }, | |
3833 | { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f }, | |
3834 | { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f }, | |
3835 | { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 }, | |
3836 | { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 }, | |
3837 | { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 }, | |
3838 | { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f }, | |
3839 | { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 }, | |
3840 | { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 }, | |
3841 | { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f }, | |
3842 | ||
3843 | /* 802.11 Japan */ | |
3844 | { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b }, | |
3845 | { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 }, | |
3846 | { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b }, | |
3847 | { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 }, | |
3848 | { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 }, | |
3849 | { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b }, | |
3850 | { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 }, | |
3851 | }; | |
3852 | ||
3853 | /* | |
55f9321a ID |
3854 | * RF value list for rt3xxx |
3855 | * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052) | |
4da2933f | 3856 | */ |
55f9321a | 3857 | static const struct rf_channel rf_vals_3x[] = { |
4da2933f BZ |
3858 | {1, 241, 2, 2 }, |
3859 | {2, 241, 2, 7 }, | |
3860 | {3, 242, 2, 2 }, | |
3861 | {4, 242, 2, 7 }, | |
3862 | {5, 243, 2, 2 }, | |
3863 | {6, 243, 2, 7 }, | |
3864 | {7, 244, 2, 2 }, | |
3865 | {8, 244, 2, 7 }, | |
3866 | {9, 245, 2, 2 }, | |
3867 | {10, 245, 2, 7 }, | |
3868 | {11, 246, 2, 2 }, | |
3869 | {12, 246, 2, 7 }, | |
3870 | {13, 247, 2, 2 }, | |
3871 | {14, 248, 2, 4 }, | |
55f9321a ID |
3872 | |
3873 | /* 802.11 UNI / HyperLan 2 */ | |
3874 | {36, 0x56, 0, 4}, | |
3875 | {38, 0x56, 0, 6}, | |
3876 | {40, 0x56, 0, 8}, | |
3877 | {44, 0x57, 0, 0}, | |
3878 | {46, 0x57, 0, 2}, | |
3879 | {48, 0x57, 0, 4}, | |
3880 | {52, 0x57, 0, 8}, | |
3881 | {54, 0x57, 0, 10}, | |
3882 | {56, 0x58, 0, 0}, | |
3883 | {60, 0x58, 0, 4}, | |
3884 | {62, 0x58, 0, 6}, | |
3885 | {64, 0x58, 0, 8}, | |
3886 | ||
3887 | /* 802.11 HyperLan 2 */ | |
3888 | {100, 0x5b, 0, 8}, | |
3889 | {102, 0x5b, 0, 10}, | |
3890 | {104, 0x5c, 0, 0}, | |
3891 | {108, 0x5c, 0, 4}, | |
3892 | {110, 0x5c, 0, 6}, | |
3893 | {112, 0x5c, 0, 8}, | |
3894 | {116, 0x5d, 0, 0}, | |
3895 | {118, 0x5d, 0, 2}, | |
3896 | {120, 0x5d, 0, 4}, | |
3897 | {124, 0x5d, 0, 8}, | |
3898 | {126, 0x5d, 0, 10}, | |
3899 | {128, 0x5e, 0, 0}, | |
3900 | {132, 0x5e, 0, 4}, | |
3901 | {134, 0x5e, 0, 6}, | |
3902 | {136, 0x5e, 0, 8}, | |
3903 | {140, 0x5f, 0, 0}, | |
3904 | ||
3905 | /* 802.11 UNII */ | |
3906 | {149, 0x5f, 0, 9}, | |
3907 | {151, 0x5f, 0, 11}, | |
3908 | {153, 0x60, 0, 1}, | |
3909 | {157, 0x60, 0, 5}, | |
3910 | {159, 0x60, 0, 7}, | |
3911 | {161, 0x60, 0, 9}, | |
3912 | {165, 0x61, 0, 1}, | |
3913 | {167, 0x61, 0, 3}, | |
3914 | {169, 0x61, 0, 5}, | |
3915 | {171, 0x61, 0, 7}, | |
3916 | {173, 0x61, 0, 9}, | |
4da2933f BZ |
3917 | }; |
3918 | ||
3919 | int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) | |
3920 | { | |
4da2933f BZ |
3921 | struct hw_mode_spec *spec = &rt2x00dev->spec; |
3922 | struct channel_info *info; | |
8d1331b3 ID |
3923 | char *default_power1; |
3924 | char *default_power2; | |
4da2933f BZ |
3925 | unsigned int i; |
3926 | u16 eeprom; | |
3927 | ||
93b6bd26 GW |
3928 | /* |
3929 | * Disable powersaving as default on PCI devices. | |
3930 | */ | |
cea90e55 | 3931 | if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) |
93b6bd26 GW |
3932 | rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; |
3933 | ||
4da2933f BZ |
3934 | /* |
3935 | * Initialize all hw fields. | |
3936 | */ | |
3937 | rt2x00dev->hw->flags = | |
4da2933f BZ |
3938 | IEEE80211_HW_SIGNAL_DBM | |
3939 | IEEE80211_HW_SUPPORTS_PS | | |
1df90809 HS |
3940 | IEEE80211_HW_PS_NULLFUNC_STACK | |
3941 | IEEE80211_HW_AMPDU_AGGREGATION; | |
5a5b6ed6 HS |
3942 | /* |
3943 | * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices | |
3944 | * unless we are capable of sending the buffered frames out after the | |
3945 | * DTIM transmission using rt2x00lib_beacondone. This will send out | |
3946 | * multicast and broadcast traffic immediately instead of buffering it | |
3947 | * infinitly and thus dropping it after some time. | |
3948 | */ | |
3949 | if (!rt2x00_is_usb(rt2x00dev)) | |
3950 | rt2x00dev->hw->flags |= | |
3951 | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING; | |
4da2933f | 3952 | |
4da2933f BZ |
3953 | SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); |
3954 | SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, | |
3955 | rt2x00_eeprom_addr(rt2x00dev, | |
3956 | EEPROM_MAC_ADDR_0)); | |
3957 | ||
3f2bee24 HS |
3958 | /* |
3959 | * As rt2800 has a global fallback table we cannot specify | |
3960 | * more then one tx rate per frame but since the hw will | |
3961 | * try several rates (based on the fallback table) we should | |
ba3b9e5e | 3962 | * initialize max_report_rates to the maximum number of rates |
3f2bee24 HS |
3963 | * we are going to try. Otherwise mac80211 will truncate our |
3964 | * reported tx rates and the rc algortihm will end up with | |
3965 | * incorrect data. | |
3966 | */ | |
ba3b9e5e HS |
3967 | rt2x00dev->hw->max_rates = 1; |
3968 | rt2x00dev->hw->max_report_rates = 7; | |
3f2bee24 HS |
3969 | rt2x00dev->hw->max_rate_tries = 1; |
3970 | ||
38c8a566 | 3971 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); |
4da2933f BZ |
3972 | |
3973 | /* | |
3974 | * Initialize hw_mode information. | |
3975 | */ | |
3976 | spec->supported_bands = SUPPORT_BAND_2GHZ; | |
3977 | spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; | |
3978 | ||
5122d898 | 3979 | if (rt2x00_rf(rt2x00dev, RF2820) || |
55f9321a | 3980 | rt2x00_rf(rt2x00dev, RF2720)) { |
4da2933f BZ |
3981 | spec->num_channels = 14; |
3982 | spec->channels = rf_vals; | |
55f9321a ID |
3983 | } else if (rt2x00_rf(rt2x00dev, RF2850) || |
3984 | rt2x00_rf(rt2x00dev, RF2750)) { | |
4da2933f BZ |
3985 | spec->supported_bands |= SUPPORT_BAND_5GHZ; |
3986 | spec->num_channels = ARRAY_SIZE(rf_vals); | |
3987 | spec->channels = rf_vals; | |
5122d898 GW |
3988 | } else if (rt2x00_rf(rt2x00dev, RF3020) || |
3989 | rt2x00_rf(rt2x00dev, RF2020) || | |
3990 | rt2x00_rf(rt2x00dev, RF3021) || | |
f93bc9b3 | 3991 | rt2x00_rf(rt2x00dev, RF3022) || |
adde5882 | 3992 | rt2x00_rf(rt2x00dev, RF3320) || |
aca355b9 | 3993 | rt2x00_rf(rt2x00dev, RF5370) || |
adde5882 | 3994 | rt2x00_rf(rt2x00dev, RF5390)) { |
55f9321a ID |
3995 | spec->num_channels = 14; |
3996 | spec->channels = rf_vals_3x; | |
3997 | } else if (rt2x00_rf(rt2x00dev, RF3052)) { | |
3998 | spec->supported_bands |= SUPPORT_BAND_5GHZ; | |
3999 | spec->num_channels = ARRAY_SIZE(rf_vals_3x); | |
4000 | spec->channels = rf_vals_3x; | |
4da2933f BZ |
4001 | } |
4002 | ||
4003 | /* | |
4004 | * Initialize HT information. | |
4005 | */ | |
5122d898 | 4006 | if (!rt2x00_rf(rt2x00dev, RF2020)) |
38a522e6 GW |
4007 | spec->ht.ht_supported = true; |
4008 | else | |
4009 | spec->ht.ht_supported = false; | |
4010 | ||
4da2933f | 4011 | spec->ht.cap = |
06443e46 | 4012 | IEEE80211_HT_CAP_SUP_WIDTH_20_40 | |
4da2933f BZ |
4013 | IEEE80211_HT_CAP_GRN_FLD | |
4014 | IEEE80211_HT_CAP_SGI_20 | | |
aa674631 | 4015 | IEEE80211_HT_CAP_SGI_40; |
22cabaa6 | 4016 | |
38c8a566 | 4017 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2) |
22cabaa6 HS |
4018 | spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC; |
4019 | ||
aa674631 | 4020 | spec->ht.cap |= |
38c8a566 | 4021 | rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) << |
aa674631 ID |
4022 | IEEE80211_HT_CAP_RX_STBC_SHIFT; |
4023 | ||
4da2933f BZ |
4024 | spec->ht.ampdu_factor = 3; |
4025 | spec->ht.ampdu_density = 4; | |
4026 | spec->ht.mcs.tx_params = | |
4027 | IEEE80211_HT_MCS_TX_DEFINED | | |
4028 | IEEE80211_HT_MCS_TX_RX_DIFF | | |
38c8a566 | 4029 | ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) << |
4da2933f BZ |
4030 | IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); |
4031 | ||
38c8a566 | 4032 | switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) { |
4da2933f BZ |
4033 | case 3: |
4034 | spec->ht.mcs.rx_mask[2] = 0xff; | |
4035 | case 2: | |
4036 | spec->ht.mcs.rx_mask[1] = 0xff; | |
4037 | case 1: | |
4038 | spec->ht.mcs.rx_mask[0] = 0xff; | |
4039 | spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */ | |
4040 | break; | |
4041 | } | |
4042 | ||
4043 | /* | |
4044 | * Create channel information array | |
4045 | */ | |
baeb2ffa | 4046 | info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL); |
4da2933f BZ |
4047 | if (!info) |
4048 | return -ENOMEM; | |
4049 | ||
4050 | spec->channels_info = info; | |
4051 | ||
8d1331b3 ID |
4052 | default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1); |
4053 | default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2); | |
4da2933f BZ |
4054 | |
4055 | for (i = 0; i < 14; i++) { | |
e90c54b2 RJH |
4056 | info[i].default_power1 = default_power1[i]; |
4057 | info[i].default_power2 = default_power2[i]; | |
4da2933f BZ |
4058 | } |
4059 | ||
4060 | if (spec->num_channels > 14) { | |
8d1331b3 ID |
4061 | default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1); |
4062 | default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2); | |
4da2933f BZ |
4063 | |
4064 | for (i = 14; i < spec->num_channels; i++) { | |
e90c54b2 RJH |
4065 | info[i].default_power1 = default_power1[i]; |
4066 | info[i].default_power2 = default_power2[i]; | |
4da2933f BZ |
4067 | } |
4068 | } | |
4069 | ||
4070 | return 0; | |
4071 | } | |
4072 | EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode); | |
4073 | ||
2ce33995 BZ |
4074 | /* |
4075 | * IEEE80211 stack callback functions. | |
4076 | */ | |
e783619e HS |
4077 | void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32, |
4078 | u16 *iv16) | |
2ce33995 BZ |
4079 | { |
4080 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
4081 | struct mac_iveiv_entry iveiv_entry; | |
4082 | u32 offset; | |
4083 | ||
4084 | offset = MAC_IVEIV_ENTRY(hw_key_idx); | |
4085 | rt2800_register_multiread(rt2x00dev, offset, | |
4086 | &iveiv_entry, sizeof(iveiv_entry)); | |
4087 | ||
855da5e0 JL |
4088 | memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16)); |
4089 | memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32)); | |
2ce33995 | 4090 | } |
e783619e | 4091 | EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq); |
2ce33995 | 4092 | |
e783619e | 4093 | int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value) |
2ce33995 BZ |
4094 | { |
4095 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
4096 | u32 reg; | |
4097 | bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD); | |
4098 | ||
4099 | rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®); | |
4100 | rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value); | |
4101 | rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); | |
4102 | ||
4103 | rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®); | |
4104 | rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled); | |
4105 | rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); | |
4106 | ||
4107 | rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); | |
4108 | rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled); | |
4109 | rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); | |
4110 | ||
4111 | rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); | |
4112 | rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled); | |
4113 | rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); | |
4114 | ||
4115 | rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); | |
4116 | rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled); | |
4117 | rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); | |
4118 | ||
4119 | rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); | |
4120 | rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled); | |
4121 | rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); | |
4122 | ||
4123 | rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); | |
4124 | rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled); | |
4125 | rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); | |
4126 | ||
4127 | return 0; | |
4128 | } | |
e783619e | 4129 | EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold); |
2ce33995 | 4130 | |
e783619e HS |
4131 | int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx, |
4132 | const struct ieee80211_tx_queue_params *params) | |
2ce33995 BZ |
4133 | { |
4134 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
4135 | struct data_queue *queue; | |
4136 | struct rt2x00_field32 field; | |
4137 | int retval; | |
4138 | u32 reg; | |
4139 | u32 offset; | |
4140 | ||
4141 | /* | |
4142 | * First pass the configuration through rt2x00lib, that will | |
4143 | * update the queue settings and validate the input. After that | |
4144 | * we are free to update the registers based on the value | |
4145 | * in the queue parameter. | |
4146 | */ | |
4147 | retval = rt2x00mac_conf_tx(hw, queue_idx, params); | |
4148 | if (retval) | |
4149 | return retval; | |
4150 | ||
4151 | /* | |
4152 | * We only need to perform additional register initialization | |
4153 | * for WMM queues/ | |
4154 | */ | |
4155 | if (queue_idx >= 4) | |
4156 | return 0; | |
4157 | ||
11f818e0 | 4158 | queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); |
2ce33995 BZ |
4159 | |
4160 | /* Update WMM TXOP register */ | |
4161 | offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2))); | |
4162 | field.bit_offset = (queue_idx & 1) * 16; | |
4163 | field.bit_mask = 0xffff << field.bit_offset; | |
4164 | ||
4165 | rt2800_register_read(rt2x00dev, offset, ®); | |
4166 | rt2x00_set_field32(®, field, queue->txop); | |
4167 | rt2800_register_write(rt2x00dev, offset, reg); | |
4168 | ||
4169 | /* Update WMM registers */ | |
4170 | field.bit_offset = queue_idx * 4; | |
4171 | field.bit_mask = 0xf << field.bit_offset; | |
4172 | ||
4173 | rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, ®); | |
4174 | rt2x00_set_field32(®, field, queue->aifs); | |
4175 | rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg); | |
4176 | ||
4177 | rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, ®); | |
4178 | rt2x00_set_field32(®, field, queue->cw_min); | |
4179 | rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg); | |
4180 | ||
4181 | rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, ®); | |
4182 | rt2x00_set_field32(®, field, queue->cw_max); | |
4183 | rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg); | |
4184 | ||
4185 | /* Update EDCA registers */ | |
4186 | offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx); | |
4187 | ||
4188 | rt2800_register_read(rt2x00dev, offset, ®); | |
4189 | rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop); | |
4190 | rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs); | |
4191 | rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min); | |
4192 | rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max); | |
4193 | rt2800_register_write(rt2x00dev, offset, reg); | |
4194 | ||
4195 | return 0; | |
4196 | } | |
e783619e | 4197 | EXPORT_SYMBOL_GPL(rt2800_conf_tx); |
2ce33995 | 4198 | |
e783619e | 4199 | u64 rt2800_get_tsf(struct ieee80211_hw *hw) |
2ce33995 BZ |
4200 | { |
4201 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
4202 | u64 tsf; | |
4203 | u32 reg; | |
4204 | ||
4205 | rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, ®); | |
4206 | tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32; | |
4207 | rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, ®); | |
4208 | tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD); | |
4209 | ||
4210 | return tsf; | |
4211 | } | |
e783619e | 4212 | EXPORT_SYMBOL_GPL(rt2800_get_tsf); |
2ce33995 | 4213 | |
e783619e HS |
4214 | int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
4215 | enum ieee80211_ampdu_mlme_action action, | |
0b01f030 JB |
4216 | struct ieee80211_sta *sta, u16 tid, u16 *ssn, |
4217 | u8 buf_size) | |
1df90809 | 4218 | { |
1df90809 HS |
4219 | int ret = 0; |
4220 | ||
4221 | switch (action) { | |
4222 | case IEEE80211_AMPDU_RX_START: | |
4223 | case IEEE80211_AMPDU_RX_STOP: | |
58ed826e HS |
4224 | /* |
4225 | * The hw itself takes care of setting up BlockAck mechanisms. | |
4226 | * So, we only have to allow mac80211 to nagotiate a BlockAck | |
4227 | * agreement. Once that is done, the hw will BlockAck incoming | |
4228 | * AMPDUs without further setup. | |
4229 | */ | |
1df90809 HS |
4230 | break; |
4231 | case IEEE80211_AMPDU_TX_START: | |
4232 | ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); | |
4233 | break; | |
4234 | case IEEE80211_AMPDU_TX_STOP: | |
4235 | ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); | |
4236 | break; | |
4237 | case IEEE80211_AMPDU_TX_OPERATIONAL: | |
4238 | break; | |
4239 | default: | |
4e9e58c6 | 4240 | WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n"); |
1df90809 HS |
4241 | } |
4242 | ||
4243 | return ret; | |
4244 | } | |
e783619e | 4245 | EXPORT_SYMBOL_GPL(rt2800_ampdu_action); |
a5ea2f02 | 4246 | |
977206d7 HS |
4247 | int rt2800_get_survey(struct ieee80211_hw *hw, int idx, |
4248 | struct survey_info *survey) | |
4249 | { | |
4250 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
4251 | struct ieee80211_conf *conf = &hw->conf; | |
4252 | u32 idle, busy, busy_ext; | |
4253 | ||
4254 | if (idx != 0) | |
4255 | return -ENOENT; | |
4256 | ||
4257 | survey->channel = conf->channel; | |
4258 | ||
4259 | rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle); | |
4260 | rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy); | |
4261 | rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext); | |
4262 | ||
4263 | if (idle || busy) { | |
4264 | survey->filled = SURVEY_INFO_CHANNEL_TIME | | |
4265 | SURVEY_INFO_CHANNEL_TIME_BUSY | | |
4266 | SURVEY_INFO_CHANNEL_TIME_EXT_BUSY; | |
4267 | ||
4268 | survey->channel_time = (idle + busy) / 1000; | |
4269 | survey->channel_time_busy = busy / 1000; | |
4270 | survey->channel_time_ext_busy = busy_ext / 1000; | |
4271 | } | |
4272 | ||
4273 | return 0; | |
4274 | ||
4275 | } | |
4276 | EXPORT_SYMBOL_GPL(rt2800_get_survey); | |
4277 | ||
a5ea2f02 ID |
4278 | MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz"); |
4279 | MODULE_VERSION(DRV_VERSION); | |
4280 | MODULE_DESCRIPTION("Ralink RT2800 library"); | |
4281 | MODULE_LICENSE("GPL"); |