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b43: N-PHY: rev3+: implement gain ctl workarounds
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
CommitLineData
89297425 1/*
96481b20 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
a5ea2f02 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 6
9c9a0d14 7 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32/*
33 Module: rt2800lib
34 Abstract: rt2800 generic device routines.
35 */
36
f31c9a8c 37#include <linux/crc-ccitt.h>
89297425
BZ		 38#include <linux/kernel.h>
39#include <linux/module.h>
5a0e3ad6 40#include <linux/slab.h>
89297425
BZ		 41
42#include "rt2x00.h"
43#include "rt2800lib.h"
44#include "rt2800.h"
45
89297425
BZ		 46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60#define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64#define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66#define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
baff8006
HS		 70static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71{
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
75 return false;
76
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
81 return true;
82
83 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
84 return false;
85}
86
fcf51541
BZ		 87static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
89297425
BZ		 89{
90 u32 reg;
91
92 mutex_lock(&rt2x00dev->csr_mutex);
93
94 /*
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
97 */
98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
efc7d36f 104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 105
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107 }
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110}
89297425 111
fcf51541
BZ		 112static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
89297425
BZ		 114{
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
126 */
127 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 reg = 0;
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
efc7d36f 132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142}
89297425 143
fcf51541
BZ		 144static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
89297425
BZ		 146{
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166}
89297425 167
fcf51541
BZ		 168static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
89297425
BZ		 170{
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197}
89297425 198
fcf51541
BZ		 199static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
89297425
BZ		 201{
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222}
89297425
BZ		 223
224void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
225 const u8 command, const u8 token,
226 const u8 arg0, const u8 arg1)
227{
228 u32 reg;
229
ee303e54 230 /*
cea90e55 231 * SOC devices don't support MCU requests.
ee303e54 232 */
cea90e55 233 if (rt2x00_is_soc(rt2x00dev))
ee303e54 234 return;
89297425
BZ		 235
236 mutex_lock(&rt2x00dev->csr_mutex);
237
238 /*
239 * Wait until the MCU becomes available, afterwards we
240 * can safely write the new data into the register.
241 */
242 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
243 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
244 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
245 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
246 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
247 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
248
249 reg = 0;
250 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
251 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
252 }
253
254 mutex_unlock(&rt2x00dev->csr_mutex);
255}
256EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 257
5ffddc49
ID		 258int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
259{
260 unsigned int i = 0;
261 u32 reg;
262
263 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
264 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
265 if (reg && reg != ~0)
266 return 0;
267 msleep(1);
268 }
269
270 ERROR(rt2x00dev, "Unstable hardware.\n");
271 return -EBUSY;
272}
273EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
274
67a4c1e2
GW		 275int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
276{
277 unsigned int i;
278 u32 reg;
279
08e53100
HS		 280 /*
281 * Some devices are really slow to respond here. Wait a whole second
282 * before timing out.
283 */
67a4c1e2
GW		 284 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
285 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
286 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
287 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
288 return 0;
289
08e53100 290 msleep(10);
67a4c1e2
GW		 291 }
292
293 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
294 return -EACCES;
295}
296EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
297
f31c9a8c
ID		 298static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
299{
300 u16 fw_crc;
301 u16 crc;
302
303 /*
304 * The last 2 bytes in the firmware array are the crc checksum itself,
305 * this means that we should never pass those 2 bytes to the crc
306 * algorithm.
307 */
308 fw_crc = (data[len - 2] << 8 | data[len - 1]);
309
310 /*
311 * Use the crc ccitt algorithm.
312 * This will return the same value as the legacy driver which
313 * used bit ordering reversion on the both the firmware bytes
314 * before input input as well as on the final output.
315 * Obviously using crc ccitt directly is much more efficient.
316 */
317 crc = crc_ccitt(~0, data, len - 2);
318
319 /*
320 * There is a small difference between the crc-itu-t + bitrev and
321 * the crc-ccitt crc calculation. In the latter method the 2 bytes
322 * will be swapped, use swab16 to convert the crc to the correct
323 * value.
324 */
325 crc = swab16(crc);
326
327 return fw_crc == crc;
328}
329
330int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
331 const u8 *data, const size_t len)
332{
333 size_t offset = 0;
334 size_t fw_len;
335 bool multiple;
336
337 /*
338 * PCI(e) & SOC devices require firmware with a length
339 * of 8kb. USB devices require firmware files with a length
340 * of 4kb. Certain USB chipsets however require different firmware,
341 * which Ralink only provides attached to the original firmware
342 * file. Thus for USB devices, firmware files have a length
343 * which is a multiple of 4kb.
344 */
345 if (rt2x00_is_usb(rt2x00dev)) {
346 fw_len = 4096;
347 multiple = true;
348 } else {
349 fw_len = 8192;
350 multiple = true;
351 }
352
353 /*
354 * Validate the firmware length
355 */
356 if (len != fw_len && (!multiple || (len % fw_len) != 0))
357 return FW_BAD_LENGTH;
358
359 /*
360 * Check if the chipset requires one of the upper parts
361 * of the firmware.
362 */
363 if (rt2x00_is_usb(rt2x00dev) &&
364 !rt2x00_rt(rt2x00dev, RT2860) &&
365 !rt2x00_rt(rt2x00dev, RT2872) &&
366 !rt2x00_rt(rt2x00dev, RT3070) &&
367 ((len / fw_len) == 1))
368 return FW_BAD_VERSION;
369
370 /*
371 * 8kb firmware files must be checked as if it were
372 * 2 separate firmware files.
373 */
374 while (offset < len) {
375 if (!rt2800_check_firmware_crc(data + offset, fw_len))
376 return FW_BAD_CRC;
377
378 offset += fw_len;
379 }
380
381 return FW_OK;
382}
383EXPORT_SYMBOL_GPL(rt2800_check_firmware);
384
385int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
386 const u8 *data, const size_t len)
387{
388 unsigned int i;
389 u32 reg;
390
391 /*
b9eca242
ID		 392 * If driver doesn't wake up firmware here,
393 * rt2800_load_firmware will hang forever when interface is up again.
f31c9a8c 394 */
b9eca242 395 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
f31c9a8c 396
f31c9a8c
ID		 397 /*
398 * Wait for stable hardware.
399 */
5ffddc49 400 if (rt2800_wait_csr_ready(rt2x00dev))
f31c9a8c 401 return -EBUSY;
f31c9a8c 402
60687ba7
RST		 403 if (rt2x00_is_pci(rt2x00dev)) {
404 if (rt2x00_rt(rt2x00dev, RT5390)) {
405 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
406 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
407 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
408 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
409 }
f31c9a8c 410 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
60687ba7 411 }
f31c9a8c
ID		 412
413 /*
414 * Disable DMA, will be reenabled later when enabling
415 * the radio.
416 */
417 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
418 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
419 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
420 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
421 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
422 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
423 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
424
425 /*
426 * Write firmware to the device.
427 */
428 rt2800_drv_write_firmware(rt2x00dev, data, len);
429
430 /*
431 * Wait for device to stabilize.
432 */
433 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
434 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
435 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
436 break;
437 msleep(1);
438 }
439
440 if (i == REGISTER_BUSY_COUNT) {
441 ERROR(rt2x00dev, "PBF system register not ready.\n");
442 return -EBUSY;
443 }
444
445 /*
446 * Initialize firmware.
447 */
448 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
449 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
450 msleep(1);
451
452 return 0;
453}
454EXPORT_SYMBOL_GPL(rt2800_load_firmware);
455
0c5879bc
ID		 456void rt2800_write_tx_data(struct queue_entry *entry,
457 struct txentry_desc *txdesc)
59679b91 458{
0c5879bc 459 __le32 *txwi = rt2800_drv_get_txwi(entry);
59679b91
GW		 460 u32 word;
461
462 /*
463 * Initialize TX Info descriptor
464 */
465 rt2x00_desc_read(txwi, 0, &word);
466 rt2x00_set_field32(&word, TXWI_W0_FRAG,
467 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
84804cdc
ID		 468 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
469 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
59679b91
GW		 470 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
471 rt2x00_set_field32(&word, TXWI_W0_TS,
472 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
473 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
474 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
475 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
476 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop);
477 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
478 rt2x00_set_field32(&word, TXWI_W0_BW,
479 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
480 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
481 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
482 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
483 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
484 rt2x00_desc_write(txwi, 0, word);
485
486 rt2x00_desc_read(txwi, 1, &word);
487 rt2x00_set_field32(&word, TXWI_W1_ACK,
488 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
489 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
490 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
491 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
492 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
493 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
494 txdesc->key_idx : 0xff);
495 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
496 txdesc->length);
2b23cdaa 497 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
bc8a979e 498 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
59679b91
GW		 499 rt2x00_desc_write(txwi, 1, word);
500
501 /*
502 * Always write 0 to IV/EIV fields, hardware will insert the IV
503 * from the IVEIV register when TXD_W3_WIV is set to 0.
504 * When TXD_W3_WIV is set to 1 it will use the IV data
505 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
506 * crypto entry in the registers should be used to encrypt the frame.
507 */
508 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
509 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
510}
0c5879bc 511EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
59679b91 512
ff6133be 513static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
2de64dd2 514{
74861922
ID		 515 int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
516 int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
517 int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
518 u16 eeprom;
519 u8 offset0;
520 u8 offset1;
521 u8 offset2;
522
e5ef5bad 523 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
74861922
ID		 524 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
525 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
526 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
527 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
528 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
529 } else {
530 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
531 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
532 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
533 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
534 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
535 }
536
537 /*
538 * Convert the value from the descriptor into the RSSI value
539 * If the value in the descriptor is 0, it is considered invalid
540 * and the default (extremely low) rssi value is assumed
541 */
542 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
543 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
544 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
545
546 /*
547 * mac80211 only accepts a single RSSI value. Calculating the
548 * average doesn't deliver a fair answer either since -60:-60 would
549 * be considered equally good as -50:-70 while the second is the one
550 * which gives less energy...
551 */
552 rssi0 = max(rssi0, rssi1);
553 return max(rssi0, rssi2);
554}
555
556void rt2800_process_rxwi(struct queue_entry *entry,
557 struct rxdone_entry_desc *rxdesc)
558{
559 __le32 *rxwi = (__le32 *) entry->skb->data;
2de64dd2
GW		 560 u32 word;
561
562 rt2x00_desc_read(rxwi, 0, &word);
563
564 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
565 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
566
567 rt2x00_desc_read(rxwi, 1, &word);
568
569 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
570 rxdesc->flags |= RX_FLAG_SHORT_GI;
571
572 if (rt2x00_get_field32(word, RXWI_W1_BW))
573 rxdesc->flags |= RX_FLAG_40MHZ;
574
575 /*
576 * Detect RX rate, always use MCS as signal type.
577 */
578 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
579 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
580 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
581
582 /*
583 * Mask of 0x8 bit to remove the short preamble flag.
584 */
585 if (rxdesc->rate_mode == RATE_MODE_CCK)
586 rxdesc->signal &= ~0x8;
587
588 rt2x00_desc_read(rxwi, 2, &word);
589
74861922
ID		 590 /*
591 * Convert descriptor AGC value to RSSI value.
592 */
593 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
2de64dd2
GW		 594
595 /*
596 * Remove RXWI descriptor from start of buffer.
597 */
74861922 598 skb_pull(entry->skb, RXWI_DESC_SIZE);
2de64dd2
GW		 599}
600EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
601
3613884d
ID		 602static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)
603{
604 __le32 *txwi;
605 u32 word;
606 int wcid, ack, pid;
607 int tx_wcid, tx_ack, tx_pid;
608
609 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
610 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
611 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
612
613 /*
614 * This frames has returned with an IO error,
615 * so the status report is not intended for this
616 * frame.
617 */
618 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) {
619 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
620 return false;
621 }
622
623 /*
624 * Validate if this TX status report is intended for
625 * this entry by comparing the WCID/ACK/PID fields.
626 */
627 txwi = rt2800_drv_get_txwi(entry);
628
629 rt2x00_desc_read(txwi, 1, &word);
630 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
631 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK);
632 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID);
633
634 if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid)) {
635 WARNING(entry->queue->rt2x00dev,
636 "TX status report missed for queue %d entry %d\n",
637 entry->queue->qid, entry->entry_idx);
638 rt2x00lib_txdone_noinfo(entry, TXDONE_UNKNOWN);
639 return false;
640 }
641
642 return true;
643}
644
14433331
HS		 645void rt2800_txdone_entry(struct queue_entry *entry, u32 status)
646{
647 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b34793ee 648 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
14433331
HS		 649 struct txdone_entry_desc txdesc;
650 u32 word;
651 u16 mcs, real_mcs;
b34793ee 652 int aggr, ampdu;
14433331
HS		 653 __le32 *txwi;
654
655 /*
656 * Obtain the status about this packet.
657 */
658 txdesc.flags = 0;
659 txwi = rt2800_drv_get_txwi(entry);
660 rt2x00_desc_read(txwi, 0, &word);
b34793ee 661
14433331 662 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
b34793ee
HS		 663 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
664
14433331 665 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
b34793ee
HS		 666 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
667
668 /*
669 * If a frame was meant to be sent as a single non-aggregated MPDU
670 * but ended up in an aggregate the used tx rate doesn't correlate
671 * with the one specified in the TXWI as the whole aggregate is sent
672 * with the same rate.
673 *
674 * For example: two frames are sent to rt2x00, the first one sets
675 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
676 * and requests MCS15. If the hw aggregates both frames into one
677 * AMDPU the tx status for both frames will contain MCS7 although
678 * the frame was sent successfully.
679 *
680 * Hence, replace the requested rate with the real tx rate to not
681 * confuse the rate control algortihm by providing clearly wrong
682 * data.
683 */
684 if (aggr == 1 && ampdu == 0 && real_mcs != mcs) {
685 skbdesc->tx_rate_idx = real_mcs;
686 mcs = real_mcs;
687 }
14433331
HS		 688
689 /*
690 * Ralink has a retry mechanism using a global fallback
691 * table. We setup this fallback table to try the immediate
692 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
693 * always contains the MCS used for the last transmission, be
694 * it successful or not.
695 */
696 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
697 /*
698 * Transmission succeeded. The number of retries is
699 * mcs - real_mcs
700 */
701 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
702 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
703 } else {
704 /*
705 * Transmission failed. The number of retries is
706 * always 7 in this case (for a total number of 8
707 * frames sent).
708 */
709 __set_bit(TXDONE_FAILURE, &txdesc.flags);
710 txdesc.retry = rt2x00dev->long_retry;
711 }
712
713 /*
714 * the frame was retried at least once
715 * -> hw used fallback rates
716 */
717 if (txdesc.retry)
718 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
719
720 rt2x00lib_txdone(entry, &txdesc);
721}
722EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
723
96481b20
ID		 724void rt2800_txdone(struct rt2x00_dev *rt2x00dev)
725{
726 struct data_queue *queue;
727 struct queue_entry *entry;
96481b20 728 u32 reg;
3613884d 729 u8 pid;
96481b20
ID		 730 int i;
731
732 /*
733 * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
734 * at most X times and also stop processing once the TX_STA_FIFO_VALID
735 * flag is not set anymore.
736 *
737 * The legacy drivers use X=TX_RING_SIZE but state in a comment
738 * that the TX_STA_FIFO stack has a size of 16. We stick to our
739 * tx ring size for now.
740 */
efd2f271 741 for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
96481b20
ID		 742 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
743 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
744 break;
745
96481b20
ID		 746 /*
747 * Skip this entry when it contains an invalid
748 * queue identication number.
749 */
bc8a979e 750 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE);
3613884d 751 if (pid >= QID_RX)
96481b20
ID		 752 continue;
753
3613884d 754 queue = rt2x00queue_get_queue(rt2x00dev, pid);
96481b20
ID		 755 if (unlikely(!queue))
756 continue;
757
758 /*
759 * Inside each queue, we process each entry in a chronological
760 * order. We first check that the queue is not empty.
761 */
762 entry = NULL;
763 while (!rt2x00queue_empty(queue)) {
764 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
3613884d 765 if (rt2800_txdone_entry_check(entry, reg))
96481b20 766 break;
96481b20
ID		 767 }
768
769 if (!entry || rt2x00queue_empty(queue))
770 break;
771
14433331 772 rt2800_txdone_entry(entry, reg);
96481b20
ID		 773 }
774}
775EXPORT_SYMBOL_GPL(rt2800_txdone);
776
f0194b2d
GW		 777void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
778{
779 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
780 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
781 unsigned int beacon_base;
739fd940 782 unsigned int padding_len;
d76dfc61 783 u32 orig_reg, reg;
f0194b2d
GW		 784
785 /*
786 * Disable beaconing while we are reloading the beacon data,
787 * otherwise we might be sending out invalid data.
788 */
789 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
d76dfc61 790 orig_reg = reg;
f0194b2d
GW		 791 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
792 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
793
794 /*
795 * Add space for the TXWI in front of the skb.
796 */
797 skb_push(entry->skb, TXWI_DESC_SIZE);
798 memset(entry->skb, 0, TXWI_DESC_SIZE);
799
800 /*
801 * Register descriptor details in skb frame descriptor.
802 */
803 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
804 skbdesc->desc = entry->skb->data;
805 skbdesc->desc_len = TXWI_DESC_SIZE;
806
807 /*
808 * Add the TXWI for the beacon to the skb.
809 */
0c5879bc 810 rt2800_write_tx_data(entry, txdesc);
f0194b2d
GW		 811
812 /*
813 * Dump beacon to userspace through debugfs.
814 */
815 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
816
817 /*
739fd940 818 * Write entire beacon with TXWI and padding to register.
f0194b2d 819 */
739fd940 820 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
d76dfc61
SF		 821 if (padding_len && skb_pad(entry->skb, padding_len)) {
822 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
823 /* skb freed by skb_pad() on failure */
824 entry->skb = NULL;
825 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
826 return;
827 }
828
f0194b2d 829 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
739fd940
WK		 830 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
831 entry->skb->len + padding_len);
f0194b2d
GW		 832
833 /*
834 * Enable beaconing again.
835 */
f0194b2d
GW		 836 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
837 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
838
839 /*
840 * Clean up beacon skb.
841 */
842 dev_kfree_skb_any(entry->skb);
843 entry->skb = NULL;
844}
50e888ea 845EXPORT_SYMBOL_GPL(rt2800_write_beacon);
f0194b2d 846
69cf36a4
HS		 847static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
848 unsigned int beacon_base)
fdb87251
HS		 849{
850 int i;
851
852 /*
853 * For the Beacon base registers we only need to clear
854 * the whole TXWI which (when set to 0) will invalidate
855 * the entire beacon.
856 */
857 for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
858 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
859}
860
69cf36a4
HS		 861void rt2800_clear_beacon(struct queue_entry *entry)
862{
863 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
864 u32 reg;
865
866 /*
867 * Disable beaconing while we are reloading the beacon data,
868 * otherwise we might be sending out invalid data.
869 */
870 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
871 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
872 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
873
874 /*
875 * Clear beacon.
876 */
877 rt2800_clear_beacon_register(rt2x00dev,
878 HW_BEACON_OFFSET(entry->entry_idx));
879
880 /*
881 * Enabled beaconing again.
882 */
883 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
884 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
885}
886EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
887
f4450616
BZ		 888#ifdef CONFIG_RT2X00_LIB_DEBUGFS
889const struct rt2x00debug rt2800_rt2x00debug = {
890 .owner = THIS_MODULE,
891 .csr = {
892 .read = rt2800_register_read,
893 .write = rt2800_register_write,
894 .flags = RT2X00DEBUGFS_OFFSET,
895 .word_base = CSR_REG_BASE,
896 .word_size = sizeof(u32),
897 .word_count = CSR_REG_SIZE / sizeof(u32),
898 },
899 .eeprom = {
900 .read = rt2x00_eeprom_read,
901 .write = rt2x00_eeprom_write,
902 .word_base = EEPROM_BASE,
903 .word_size = sizeof(u16),
904 .word_count = EEPROM_SIZE / sizeof(u16),
905 },
906 .bbp = {
907 .read = rt2800_bbp_read,
908 .write = rt2800_bbp_write,
909 .word_base = BBP_BASE,
910 .word_size = sizeof(u8),
911 .word_count = BBP_SIZE / sizeof(u8),
912 },
913 .rf = {
914 .read = rt2x00_rf_read,
915 .write = rt2800_rf_write,
916 .word_base = RF_BASE,
917 .word_size = sizeof(u32),
918 .word_count = RF_SIZE / sizeof(u32),
919 },
920};
921EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
922#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
923
924int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
925{
926 u32 reg;
927
928 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
929 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
930}
931EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
932
933#ifdef CONFIG_RT2X00_LIB_LEDS
934static void rt2800_brightness_set(struct led_classdev *led_cdev,
935 enum led_brightness brightness)
936{
937 struct rt2x00_led *led =
938 container_of(led_cdev, struct rt2x00_led, led_dev);
939 unsigned int enabled = brightness != LED_OFF;
940 unsigned int bg_mode =
941 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
942 unsigned int polarity =
943 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
944 EEPROM_FREQ_LED_POLARITY);
945 unsigned int ledmode =
946 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
947 EEPROM_FREQ_LED_MODE);
948
949 if (led->type == LED_TYPE_RADIO) {
950 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
951 enabled ? 0x20 : 0);
952 } else if (led->type == LED_TYPE_ASSOC) {
953 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
954 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
955 } else if (led->type == LED_TYPE_QUALITY) {
956 /*
957 * The brightness is divided into 6 levels (0 - 5),
958 * The specs tell us the following levels:
959 * 0, 1 ,3, 7, 15, 31
960 * to determine the level in a simple way we can simply
961 * work with bitshifting:
962 * (1 << level) - 1
963 */
964 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
965 (1 << brightness / (LED_FULL / 6)) - 1,
966 polarity);
967 }
968}
969
970static int rt2800_blink_set(struct led_classdev *led_cdev,
971 unsigned long *delay_on, unsigned long *delay_off)
972{
973 struct rt2x00_led *led =
974 container_of(led_cdev, struct rt2x00_led, led_dev);
975 u32 reg;
976
977 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
978 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
979 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
f4450616
BZ		 980 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
981
982 return 0;
983}
984
b3579d6a 985static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 986 struct rt2x00_led *led, enum led_type type)
987{
988 led->rt2x00dev = rt2x00dev;
989 led->type = type;
990 led->led_dev.brightness_set = rt2800_brightness_set;
991 led->led_dev.blink_set = rt2800_blink_set;
992 led->flags = LED_INITIALIZED;
993}
f4450616
BZ		 994#endif /* CONFIG_RT2X00_LIB_LEDS */
995
996/*
997 * Configuration handlers.
998 */
999static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
1000 struct rt2x00lib_crypto *crypto,
1001 struct ieee80211_key_conf *key)
1002{
1003 struct mac_wcid_entry wcid_entry;
1004 struct mac_iveiv_entry iveiv_entry;
1005 u32 offset;
1006 u32 reg;
1007
1008 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1009
e4a0ab34
ID		 1010 if (crypto->cmd == SET_KEY) {
1011 rt2800_register_read(rt2x00dev, offset, &reg);
1012 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1013 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1014 /*
1015 * Both the cipher as the BSS Idx numbers are split in a main
1016 * value of 3 bits, and a extended field for adding one additional
1017 * bit to the value.
1018 */
1019 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1020 (crypto->cipher & 0x7));
1021 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1022 (crypto->cipher & 0x8) >> 3);
1023 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
1024 (crypto->bssidx & 0x7));
1025 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1026 (crypto->bssidx & 0x8) >> 3);
1027 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1028 rt2800_register_write(rt2x00dev, offset, reg);
1029 } else {
1030 rt2800_register_write(rt2x00dev, offset, 0);
1031 }
f4450616
BZ		 1032
1033 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1034
1035 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1036 if ((crypto->cipher == CIPHER_TKIP) ||
1037 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1038 (crypto->cipher == CIPHER_AES))
1039 iveiv_entry.iv[3] |= 0x20;
1040 iveiv_entry.iv[3] |= key->keyidx << 6;
1041 rt2800_register_multiwrite(rt2x00dev, offset,
1042 &iveiv_entry, sizeof(iveiv_entry));
1043
1044 offset = MAC_WCID_ENTRY(key->hw_key_idx);
1045
1046 memset(&wcid_entry, 0, sizeof(wcid_entry));
1047 if (crypto->cmd == SET_KEY)
10026f77 1048 memcpy(wcid_entry.mac, crypto->address, ETH_ALEN);
f4450616
BZ		 1049 rt2800_register_multiwrite(rt2x00dev, offset,
1050 &wcid_entry, sizeof(wcid_entry));
1051}
1052
1053int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1054 struct rt2x00lib_crypto *crypto,
1055 struct ieee80211_key_conf *key)
1056{
1057 struct hw_key_entry key_entry;
1058 struct rt2x00_field32 field;
1059 u32 offset;
1060 u32 reg;
1061
1062 if (crypto->cmd == SET_KEY) {
1063 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1064
1065 memcpy(key_entry.key, crypto->key,
1066 sizeof(key_entry.key));
1067 memcpy(key_entry.tx_mic, crypto->tx_mic,
1068 sizeof(key_entry.tx_mic));
1069 memcpy(key_entry.rx_mic, crypto->rx_mic,
1070 sizeof(key_entry.rx_mic));
1071
1072 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1073 rt2800_register_multiwrite(rt2x00dev, offset,
1074 &key_entry, sizeof(key_entry));
1075 }
1076
1077 /*
1078 * The cipher types are stored over multiple registers
1079 * starting with SHARED_KEY_MODE_BASE each word will have
1080 * 32 bits and contains the cipher types for 2 bssidx each.
1081 * Using the correct defines correctly will cause overhead,
1082 * so just calculate the correct offset.
1083 */
1084 field.bit_offset = 4 * (key->hw_key_idx % 8);
1085 field.bit_mask = 0x7 << field.bit_offset;
1086
1087 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1088
1089 rt2800_register_read(rt2x00dev, offset, &reg);
1090 rt2x00_set_field32(&reg, field,
1091 (crypto->cmd == SET_KEY) * crypto->cipher);
1092 rt2800_register_write(rt2x00dev, offset, reg);
1093
1094 /*
1095 * Update WCID information
1096 */
1097 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1098
1099 return 0;
1100}
1101EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1102
1103int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1104 struct rt2x00lib_crypto *crypto,
1105 struct ieee80211_key_conf *key)
1106{
1107 struct hw_key_entry key_entry;
1108 u32 offset;
1109
1110 if (crypto->cmd == SET_KEY) {
1111 /*
1112 * 1 pairwise key is possible per AID, this means that the AID
1113 * equals our hw_key_idx. Make sure the WCID starts _after_ the
1114 * last possible shared key entry.
2a0cfeb8
HS		 1115 *
1116 * Since parts of the pairwise key table might be shared with
1117 * the beacon frame buffers 6 & 7 we should only write into the
1118 * first 222 entries.
f4450616 1119 */
2a0cfeb8 1120 if (crypto->aid > (222 - 32))
f4450616
BZ		 1121 return -ENOSPC;
1122
1123 key->hw_key_idx = 32 + crypto->aid;
1124
1125 memcpy(key_entry.key, crypto->key,
1126 sizeof(key_entry.key));
1127 memcpy(key_entry.tx_mic, crypto->tx_mic,
1128 sizeof(key_entry.tx_mic));
1129 memcpy(key_entry.rx_mic, crypto->rx_mic,
1130 sizeof(key_entry.rx_mic));
1131
1132 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1133 rt2800_register_multiwrite(rt2x00dev, offset,
1134 &key_entry, sizeof(key_entry));
1135 }
1136
1137 /*
1138 * Update WCID information
1139 */
1140 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1141
1142 return 0;
1143}
1144EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1145
1146void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1147 const unsigned int filter_flags)
1148{
1149 u32 reg;
1150
1151 /*
1152 * Start configuration steps.
1153 * Note that the version error will always be dropped
1154 * and broadcast frames will always be accepted since
1155 * there is no filter for it at this time.
1156 */
1157 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1158 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1159 !(filter_flags & FIF_FCSFAIL));
1160 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1161 !(filter_flags & FIF_PLCPFAIL));
1162 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1163 !(filter_flags & FIF_PROMISC_IN_BSS));
1164 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1165 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1166 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1167 !(filter_flags & FIF_ALLMULTI));
1168 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1169 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1170 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1171 !(filter_flags & FIF_CONTROL));
1172 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1173 !(filter_flags & FIF_CONTROL));
1174 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1175 !(filter_flags & FIF_CONTROL));
1176 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1177 !(filter_flags & FIF_CONTROL));
1178 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1179 !(filter_flags & FIF_CONTROL));
1180 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1181 !(filter_flags & FIF_PSPOLL));
1182 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
1183 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
1184 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1185 !(filter_flags & FIF_CONTROL));
1186 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1187}
1188EXPORT_SYMBOL_GPL(rt2800_config_filter);
1189
1190void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1191 struct rt2x00intf_conf *conf, const unsigned int flags)
1192{
f4450616 1193 u32 reg;
fa8b4b22 1194 bool update_bssid = false;
f4450616
BZ		 1195
1196 if (flags & CONFIG_UPDATE_TYPE) {
f4450616
BZ		 1197 /*
1198 * Enable synchronisation.
1199 */
1200 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
f4450616 1201 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
f4450616
BZ		 1202 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1203 }
1204
1205 if (flags & CONFIG_UPDATE_MAC) {
fa8b4b22
HS		 1206 if (flags & CONFIG_UPDATE_TYPE &&
1207 conf->sync == TSF_SYNC_AP_NONE) {
1208 /*
1209 * The BSSID register has to be set to our own mac
1210 * address in AP mode.
1211 */
1212 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1213 update_bssid = true;
1214 }
1215
c600c826
ID		 1216 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1217 reg = le32_to_cpu(conf->mac[1]);
1218 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1219 conf->mac[1] = cpu_to_le32(reg);
1220 }
f4450616
BZ		 1221
1222 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1223 conf->mac, sizeof(conf->mac));
1224 }
1225
fa8b4b22 1226 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
c600c826
ID		 1227 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1228 reg = le32_to_cpu(conf->bssid[1]);
1229 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1230 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1231 conf->bssid[1] = cpu_to_le32(reg);
1232 }
f4450616
BZ		 1233
1234 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1235 conf->bssid, sizeof(conf->bssid));
1236 }
1237}
1238EXPORT_SYMBOL_GPL(rt2800_config_intf);
1239
87c1915d
HS		 1240static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1241 struct rt2x00lib_erp *erp)
1242{
1243 bool any_sta_nongf = !!(erp->ht_opmode &
1244 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1245 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1246 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1247 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1248 u32 reg;
1249
1250 /* default protection rate for HT20: OFDM 24M */
1251 mm20_rate = gf20_rate = 0x4004;
1252
1253 /* default protection rate for HT40: duplicate OFDM 24M */
1254 mm40_rate = gf40_rate = 0x4084;
1255
1256 switch (protection) {
1257 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1258 /*
1259 * All STAs in this BSS are HT20/40 but there might be
1260 * STAs not supporting greenfield mode.
1261 * => Disable protection for HT transmissions.
1262 */
1263 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1264
1265 break;
1266 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1267 /*
1268 * All STAs in this BSS are HT20 or HT20/40 but there
1269 * might be STAs not supporting greenfield mode.
1270 * => Protect all HT40 transmissions.
1271 */
1272 mm20_mode = gf20_mode = 0;
1273 mm40_mode = gf40_mode = 2;
1274
1275 break;
1276 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1277 /*
1278 * Nonmember protection:
1279 * According to 802.11n we _should_ protect all
1280 * HT transmissions (but we don't have to).
1281 *
1282 * But if cts_protection is enabled we _shall_ protect
1283 * all HT transmissions using a CCK rate.
1284 *
1285 * And if any station is non GF we _shall_ protect
1286 * GF transmissions.
1287 *
1288 * We decide to protect everything
1289 * -> fall through to mixed mode.
1290 */
1291 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1292 /*
1293 * Legacy STAs are present
1294 * => Protect all HT transmissions.
1295 */
1296 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1297
1298 /*
1299 * If erp protection is needed we have to protect HT
1300 * transmissions with CCK 11M long preamble.
1301 */
1302 if (erp->cts_protection) {
1303 /* don't duplicate RTS/CTS in CCK mode */
1304 mm20_rate = mm40_rate = 0x0003;
1305 gf20_rate = gf40_rate = 0x0003;
1306 }
1307 break;
1308 };
1309
1310 /* check for STAs not supporting greenfield mode */
1311 if (any_sta_nongf)
1312 gf20_mode = gf40_mode = 2;
1313
1314 /* Update HT protection config */
1315 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1316 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1317 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1318 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1319
1320 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1321 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1322 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1323 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1324
1325 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1326 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1327 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1328 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1329
1330 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1331 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1332 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1333 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1334}
1335
02044643
HS		 1336void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1337 u32 changed)
f4450616
BZ		 1338{
1339 u32 reg;
1340
02044643
HS		 1341 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1342 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1343 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1344 !!erp->short_preamble);
1345 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1346 !!erp->short_preamble);
1347 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1348 }
f4450616 1349
02044643
HS		 1350 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1351 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1352 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1353 erp->cts_protection ? 2 : 0);
1354 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1355 }
f4450616 1356
02044643
HS		 1357 if (changed & BSS_CHANGED_BASIC_RATES) {
1358 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1359 erp->basic_rates);
1360 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1361 }
f4450616 1362
02044643
HS		 1363 if (changed & BSS_CHANGED_ERP_SLOT) {
1364 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1365 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1366 erp->slot_time);
1367 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
f4450616 1368
02044643
HS		 1369 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1370 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1371 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1372 }
f4450616 1373
02044643
HS		 1374 if (changed & BSS_CHANGED_BEACON_INT) {
1375 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1376 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1377 erp->beacon_int * 16);
1378 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1379 }
87c1915d
HS		 1380
1381 if (changed & BSS_CHANGED_HT)
1382 rt2800_config_ht_opmode(rt2x00dev, erp);
f4450616
BZ		 1383}
1384EXPORT_SYMBOL_GPL(rt2800_config_erp);
1385
d96aa640
RJH		 1386static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1387 enum antenna ant)
1388{
1389 u32 reg;
1390 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1391 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1392
1393 if (rt2x00_is_pci(rt2x00dev)) {
1394 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1395 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1396 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1397 } else if (rt2x00_is_usb(rt2x00dev))
1398 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1399 eesk_pin, 0);
1400
1401 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
fe59147c 1402 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
d96aa640
RJH		 1403 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, gpio_bit3);
1404 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1405}
1406
f4450616
BZ		 1407void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1408{
1409 u8 r1;
1410 u8 r3;
d96aa640 1411 u16 eeprom;
f4450616
BZ		 1412
1413 rt2800_bbp_read(rt2x00dev, 1, &r1);
1414 rt2800_bbp_read(rt2x00dev, 3, &r3);
1415
1416 /*
1417 * Configure the TX antenna.
1418 */
d96aa640 1419 switch (ant->tx_chain_num) {
f4450616
BZ		 1420 case 1:
1421 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1422 break;
1423 case 2:
1424 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1425 break;
1426 case 3:
e22557f2 1427 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1428 break;
1429 }
1430
1431 /*
1432 * Configure the RX antenna.
1433 */
d96aa640 1434 switch (ant->rx_chain_num) {
f4450616 1435 case 1:
d96aa640
RJH		 1436 if (rt2x00_rt(rt2x00dev, RT3070) ||
1437 rt2x00_rt(rt2x00dev, RT3090) ||
1438 rt2x00_rt(rt2x00dev, RT3390)) {
1439 rt2x00_eeprom_read(rt2x00dev,
1440 EEPROM_NIC_CONF1, &eeprom);
1441 if (rt2x00_get_field16(eeprom,
1442 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1443 rt2800_set_ant_diversity(rt2x00dev,
1444 rt2x00dev->default_ant.rx);
1445 }
f4450616
BZ		 1446 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1447 break;
1448 case 2:
1449 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1450 break;
1451 case 3:
1452 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1453 break;
1454 }
1455
1456 rt2800_bbp_write(rt2x00dev, 3, r3);
1457 rt2800_bbp_write(rt2x00dev, 1, r1);
1458}
1459EXPORT_SYMBOL_GPL(rt2800_config_ant);
1460
1461static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1462 struct rt2x00lib_conf *libconf)
1463{
1464 u16 eeprom;
1465 short lna_gain;
1466
1467 if (libconf->rf.channel <= 14) {
1468 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1469 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1470 } else if (libconf->rf.channel <= 64) {
1471 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1472 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1473 } else if (libconf->rf.channel <= 128) {
1474 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1475 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1476 } else {
1477 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1478 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1479 }
1480
1481 rt2x00dev->lna_gain = lna_gain;
1482}
1483
06855ef4
GW		 1484static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1485 struct ieee80211_conf *conf,
1486 struct rf_channel *rf,
1487 struct channel_info *info)
f4450616
BZ		 1488{
1489 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1490
d96aa640 1491 if (rt2x00dev->default_ant.tx_chain_num == 1)
f4450616
BZ		 1492 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1493
d96aa640 1494 if (rt2x00dev->default_ant.rx_chain_num == 1) {
f4450616
BZ		 1495 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1496 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
d96aa640 1497 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
f4450616
BZ		 1498 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1499
1500 if (rf->channel > 14) {
1501 /*
1502 * When TX power is below 0, we should increase it by 7 to
1503 * make it a positive value (Minumum value is -7).
1504 * However this means that values between 0 and 7 have
1505 * double meaning, and we should set a 7DBm boost flag.
1506 */
1507 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
8d1331b3 1508 (info->default_power1 >= 0));
f4450616 1509
8d1331b3
ID		 1510 if (info->default_power1 < 0)
1511 info->default_power1 += 7;
f4450616 1512
8d1331b3 1513 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
f4450616
BZ		 1514
1515 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
8d1331b3 1516 (info->default_power2 >= 0));
f4450616 1517
8d1331b3
ID		 1518 if (info->default_power2 < 0)
1519 info->default_power2 += 7;
f4450616 1520
8d1331b3 1521 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
f4450616 1522 } else {
8d1331b3
ID		 1523 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1524 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
f4450616
BZ		 1525 }
1526
1527 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1528
1529 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1530 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1531 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1532 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1533
1534 udelay(200);
1535
1536 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1537 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1538 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1539 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1540
1541 udelay(200);
1542
1543 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1544 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1545 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1546 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1547}
1548
06855ef4
GW		 1549static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1550 struct ieee80211_conf *conf,
1551 struct rf_channel *rf,
1552 struct channel_info *info)
f4450616
BZ		 1553{
1554 u8 rfcsr;
1555
1556 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
41a26170 1557 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
f4450616
BZ		 1558
1559 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 1560 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 1561 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1562
1563 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
8d1331b3 1564 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
f4450616
BZ		 1565 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1566
5a673964 1567 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
8d1331b3 1568 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
5a673964
HS		 1569 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1570
f4450616
BZ		 1571 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1572 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1573 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1574
1575 rt2800_rfcsr_write(rt2x00dev, 24,
1576 rt2x00dev->calibration[conf_is_ht40(conf)]);
1577
71976907 1578 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 1579 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 1580 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
f4450616
BZ		 1581}
1582
60687ba7
RST		 1583
1584#define RT5390_POWER_BOUND 0x27
1585#define RT5390_FREQ_OFFSET_BOUND 0x5f
1586
1587static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
1588 struct ieee80211_conf *conf,
1589 struct rf_channel *rf,
1590 struct channel_info *info)
1591{
1592 u8 rfcsr;
1593 u16 eeprom;
1594
1595 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
1596 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
1597 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
1598 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
1599 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
1600
1601 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
1602 if (info->default_power1 > RT5390_POWER_BOUND)
1603 rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT5390_POWER_BOUND);
1604 else
1605 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
1606 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
1607
1608 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1609 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1610 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
1611 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1612 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1613 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1614
1615 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1616 if (rt2x00dev->freq_offset > RT5390_FREQ_OFFSET_BOUND)
1617 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, RT5390_FREQ_OFFSET_BOUND);
1618 else
1619 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
1620 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1621
1622 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
1623 if (rf->channel <= 14) {
1624 int idx = rf->channel-1;
1625
1626 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) {
1627 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1628 /* r55/r59 value array of channel 1~14 */
1629 static const char r55_bt_rev[] = {0x83, 0x83,
1630 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
1631 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
1632 static const char r59_bt_rev[] = {0x0e, 0x0e,
1633 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
1634 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
1635
1636 rt2800_rfcsr_write(rt2x00dev, 55, r55_bt_rev[idx]);
1637 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt_rev[idx]);
1638 } else {
1639 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
1640 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
1641 0x88, 0x88, 0x86, 0x85, 0x84};
1642
1643 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
1644 }
1645 } else {
1646 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1647 static const char r55_nonbt_rev[] = {0x23, 0x23,
1648 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
1649 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
1650 static const char r59_nonbt_rev[] = {0x07, 0x07,
1651 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
1652 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
1653
1654 rt2800_rfcsr_write(rt2x00dev, 55, r55_nonbt_rev[idx]);
1655 rt2800_rfcsr_write(rt2x00dev, 59, r59_nonbt_rev[idx]);
1656 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
1657 static const char r59_non_bt[] = {0x8f, 0x8f,
1658 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
1659 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
1660
1661 rt2800_rfcsr_write(rt2x00dev, 59, r59_non_bt[idx]);
1662 }
1663 }
1664 }
1665
1666 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1667 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
1668 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
1669 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1670
1671 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1672 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1673 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1674}
1675
f4450616
BZ		 1676static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1677 struct ieee80211_conf *conf,
1678 struct rf_channel *rf,
1679 struct channel_info *info)
1680{
1681 u32 reg;
1682 unsigned int tx_pin;
1683 u8 bbp;
1684
46323e11 1685 if (rf->channel <= 14) {
8d1331b3
ID		 1686 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
1687 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
46323e11 1688 } else {
8d1331b3
ID		 1689 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
1690 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
46323e11
ID		 1691 }
1692
06855ef4
GW		 1693 if (rt2x00_rf(rt2x00dev, RF2020) ||
1694 rt2x00_rf(rt2x00dev, RF3020) ||
1695 rt2x00_rf(rt2x00dev, RF3021) ||
46323e11 1696 rt2x00_rf(rt2x00dev, RF3022) ||
f93bc9b3
GW		 1697 rt2x00_rf(rt2x00dev, RF3052) ||
1698 rt2x00_rf(rt2x00dev, RF3320))
06855ef4 1699 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
60687ba7
RST		 1700 else if (rt2x00_rf(rt2x00dev, RF5390))
1701 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
fa6f632f 1702 else
06855ef4 1703 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
f4450616
BZ		 1704
1705 /*
1706 * Change BBP settings
1707 */
1708 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1709 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1710 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1711 rt2800_bbp_write(rt2x00dev, 86, 0);
1712
1713 if (rf->channel <= 14) {
60687ba7
RST		 1714 if (!rt2x00_rt(rt2x00dev, RT5390)) {
1715 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1716 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1717 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1718 } else {
1719 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1720 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1721 }
f4450616
BZ		 1722 }
1723 } else {
1724 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1725
1726 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1727 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1728 else
1729 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1730 }
1731
1732 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 1733 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1734 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1735 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1736 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1737
1738 tx_pin = 0;
1739
1740 /* Turn on unused PA or LNA when not using 1T or 1R */
d96aa640 1741 if (rt2x00dev->default_ant.tx_chain_num == 2) {
f4450616
BZ		 1742 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1743 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1744 }
1745
1746 /* Turn on unused PA or LNA when not using 1T or 1R */
d96aa640 1747 if (rt2x00dev->default_ant.rx_chain_num == 2) {
f4450616
BZ		 1748 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1749 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1750 }
1751
1752 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1753 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1754 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1755 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1756 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1757 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1758
1759 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1760
1761 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1762 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1763 rt2800_bbp_write(rt2x00dev, 4, bbp);
1764
1765 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 1766 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1767 rt2800_bbp_write(rt2x00dev, 3, bbp);
1768
8d0c9b65 1769 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 1770 if (conf_is_ht40(conf)) {
1771 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1772 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1773 rt2800_bbp_write(rt2x00dev, 73, 0x16);
1774 } else {
1775 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1776 rt2800_bbp_write(rt2x00dev, 70, 0x08);
1777 rt2800_bbp_write(rt2x00dev, 73, 0x11);
1778 }
1779 }
1780
1781 msleep(1);
977206d7
HS		 1782
1783 /*
1784 * Clear channel statistic counters
1785 */
1786 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
1787 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
1788 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
f4450616
BZ		 1789}
1790
e90c54b2
RJH		 1791static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
1792 enum ieee80211_band band)
1793{
1794 u16 eeprom;
1795 u8 comp_en;
1796 u8 comp_type;
1797 int comp_value;
1798
1799 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
1800
1801 if (eeprom == 0xffff)
1802 return 0;
1803
1804 if (band == IEEE80211_BAND_2GHZ) {
1805 comp_en = rt2x00_get_field16(eeprom,
1806 EEPROM_TXPOWER_DELTA_ENABLE_2G);
1807 if (comp_en) {
1808 comp_type = rt2x00_get_field16(eeprom,
1809 EEPROM_TXPOWER_DELTA_TYPE_2G);
1810 comp_value = rt2x00_get_field16(eeprom,
1811 EEPROM_TXPOWER_DELTA_VALUE_2G);
1812 if (!comp_type)
1813 comp_value = -comp_value;
1814 }
1815 } else {
1816 comp_en = rt2x00_get_field16(eeprom,
1817 EEPROM_TXPOWER_DELTA_ENABLE_5G);
1818 if (comp_en) {
1819 comp_type = rt2x00_get_field16(eeprom,
1820 EEPROM_TXPOWER_DELTA_TYPE_5G);
1821 comp_value = rt2x00_get_field16(eeprom,
1822 EEPROM_TXPOWER_DELTA_VALUE_5G);
1823 if (!comp_type)
1824 comp_value = -comp_value;
1825 }
1826 }
1827
1828 return comp_value;
1829}
1830
1831static u8 rt2800_compesate_txpower(struct rt2x00_dev *rt2x00dev,
1832 int is_rate_b,
1833 enum ieee80211_band band,
1834 int power_level,
1835 u8 txpower)
1836{
1837 u32 reg;
1838 u16 eeprom;
1839 u8 criterion;
1840 u8 eirp_txpower;
1841 u8 eirp_txpower_criterion;
1842 u8 reg_limit;
1843 int bw_comp = 0;
1844
1845 if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b))
1846 return txpower;
1847
1848 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1849 bw_comp = rt2800_get_txpower_bw_comp(rt2x00dev, band);
1850
1851 if (test_bit(CONFIG_SUPPORT_POWER_LIMIT, &rt2x00dev->flags)) {
1852 /*
1853 * Check if eirp txpower exceed txpower_limit.
1854 * We use OFDM 6M as criterion and its eirp txpower
1855 * is stored at EEPROM_EIRP_MAX_TX_POWER.
1856 * .11b data rate need add additional 4dbm
1857 * when calculating eirp txpower.
1858 */
1859 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
1860 criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS);
1861
1862 rt2x00_eeprom_read(rt2x00dev,
1863 EEPROM_EIRP_MAX_TX_POWER, &eeprom);
1864
1865 if (band == IEEE80211_BAND_2GHZ)
1866 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
1867 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
1868 else
1869 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
1870 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
1871
1872 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
1873 (is_rate_b ? 4 : 0) + bw_comp;
1874
1875 reg_limit = (eirp_txpower > power_level) ?
1876 (eirp_txpower - power_level) : 0;
1877 } else
1878 reg_limit = 0;
1879
1880 return txpower + bw_comp - reg_limit;
1881}
1882
f4450616 1883static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
e90c54b2 1884 struct ieee80211_conf *conf)
f4450616 1885{
5e846004 1886 u8 txpower;
5e846004 1887 u16 eeprom;
e90c54b2 1888 int i, is_rate_b;
f4450616 1889 u32 reg;
f4450616 1890 u8 r1;
5e846004 1891 u32 offset;
e90c54b2
RJH		 1892 enum ieee80211_band band = conf->channel->band;
1893 int power_level = conf->power_level;
f4450616 1894
5e846004 1895 /*
e90c54b2 1896 * set to normal bbp tx power control mode: +/- 0dBm
5e846004 1897 */
f4450616 1898 rt2800_bbp_read(rt2x00dev, 1, &r1);
e90c54b2 1899 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0);
f4450616 1900 rt2800_bbp_write(rt2x00dev, 1, r1);
5e846004
HS		 1901 offset = TX_PWR_CFG_0;
1902
1903 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
1904 /* just to be safe */
1905 if (offset > TX_PWR_CFG_4)
1906 break;
1907
1908 rt2800_register_read(rt2x00dev, offset, &reg);
1909
1910 /* read the next four txpower values */
1911 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
1912 &eeprom);
1913
e90c54b2
RJH		 1914 is_rate_b = i ? 0 : 1;
1915 /*
1916 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
5e846004 1917 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
e90c54b2
RJH		 1918 * TX_PWR_CFG_4: unknown
1919 */
5e846004
HS		 1920 txpower = rt2x00_get_field16(eeprom,
1921 EEPROM_TXPOWER_BYRATE_RATE0);
e90c54b2
RJH		 1922 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1923 power_level, txpower);
1924 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
5e846004 1925
e90c54b2
RJH		 1926 /*
1927 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
5e846004 1928 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
e90c54b2
RJH		 1929 * TX_PWR_CFG_4: unknown
1930 */
5e846004
HS		 1931 txpower = rt2x00_get_field16(eeprom,
1932 EEPROM_TXPOWER_BYRATE_RATE1);
e90c54b2
RJH		 1933 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1934 power_level, txpower);
1935 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
5e846004 1936
e90c54b2
RJH		 1937 /*
1938 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
5e846004 1939 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
e90c54b2
RJH		 1940 * TX_PWR_CFG_4: unknown
1941 */
5e846004
HS		 1942 txpower = rt2x00_get_field16(eeprom,
1943 EEPROM_TXPOWER_BYRATE_RATE2);
e90c54b2
RJH		 1944 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1945 power_level, txpower);
1946 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
5e846004 1947
e90c54b2
RJH		 1948 /*
1949 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
5e846004 1950 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
e90c54b2
RJH		 1951 * TX_PWR_CFG_4: unknown
1952 */
5e846004
HS		 1953 txpower = rt2x00_get_field16(eeprom,
1954 EEPROM_TXPOWER_BYRATE_RATE3);
e90c54b2
RJH		 1955 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1956 power_level, txpower);
1957 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
5e846004
HS		 1958
1959 /* read the next four txpower values */
1960 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
1961 &eeprom);
1962
e90c54b2
RJH		 1963 is_rate_b = 0;
1964 /*
1965 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
5e846004 1966 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 1967 * TX_PWR_CFG_4: unknown
1968 */
5e846004
HS		 1969 txpower = rt2x00_get_field16(eeprom,
1970 EEPROM_TXPOWER_BYRATE_RATE0);
e90c54b2
RJH		 1971 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1972 power_level, txpower);
1973 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
5e846004 1974
e90c54b2
RJH		 1975 /*
1976 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
5e846004 1977 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 1978 * TX_PWR_CFG_4: unknown
1979 */
5e846004
HS		 1980 txpower = rt2x00_get_field16(eeprom,
1981 EEPROM_TXPOWER_BYRATE_RATE1);
e90c54b2
RJH		 1982 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1983 power_level, txpower);
1984 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
5e846004 1985
e90c54b2
RJH		 1986 /*
1987 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
5e846004 1988 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 1989 * TX_PWR_CFG_4: unknown
1990 */
5e846004
HS		 1991 txpower = rt2x00_get_field16(eeprom,
1992 EEPROM_TXPOWER_BYRATE_RATE2);
e90c54b2
RJH		 1993 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1994 power_level, txpower);
1995 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
5e846004 1996
e90c54b2
RJH		 1997 /*
1998 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
5e846004 1999 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 2000 * TX_PWR_CFG_4: unknown
2001 */
5e846004
HS		 2002 txpower = rt2x00_get_field16(eeprom,
2003 EEPROM_TXPOWER_BYRATE_RATE3);
e90c54b2
RJH		 2004 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
2005 power_level, txpower);
2006 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
5e846004
HS		 2007
2008 rt2800_register_write(rt2x00dev, offset, reg);
2009
2010 /* next TX_PWR_CFG register */
2011 offset += 4;
2012 }
f4450616
BZ		 2013}
2014
2015static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
2016 struct rt2x00lib_conf *libconf)
2017{
2018 u32 reg;
2019
2020 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2021 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
2022 libconf->conf->short_frame_max_tx_count);
2023 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
2024 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 2025 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2026}
2027
2028static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
2029 struct rt2x00lib_conf *libconf)
2030{
2031 enum dev_state state =
2032 (libconf->conf->flags & IEEE80211_CONF_PS) ?
2033 STATE_SLEEP : STATE_AWAKE;
2034 u32 reg;
2035
2036 if (state == STATE_SLEEP) {
2037 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
2038
2039 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2040 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
2041 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
2042 libconf->conf->listen_interval - 1);
2043 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
2044 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2045
2046 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2047 } else {
f4450616
BZ		 2048 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2049 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
2050 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
2051 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
2052 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 2053
2054 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 2055 }
2056}
2057
2058void rt2800_config(struct rt2x00_dev *rt2x00dev,
2059 struct rt2x00lib_conf *libconf,
2060 const unsigned int flags)
2061{
2062 /* Always recalculate LNA gain before changing configuration */
2063 rt2800_config_lna_gain(rt2x00dev, libconf);
2064
e90c54b2 2065 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
f4450616
BZ		 2066 rt2800_config_channel(rt2x00dev, libconf->conf,
2067 &libconf->rf, &libconf->channel);
e90c54b2
RJH		 2068 rt2800_config_txpower(rt2x00dev, libconf->conf);
2069 }
f4450616 2070 if (flags & IEEE80211_CONF_CHANGE_POWER)
e90c54b2 2071 rt2800_config_txpower(rt2x00dev, libconf->conf);
f4450616
BZ		 2072 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2073 rt2800_config_retry_limit(rt2x00dev, libconf);
2074 if (flags & IEEE80211_CONF_CHANGE_PS)
2075 rt2800_config_ps(rt2x00dev, libconf);
2076}
2077EXPORT_SYMBOL_GPL(rt2800_config);
2078
2079/*
2080 * Link tuning
2081 */
2082void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2083{
2084 u32 reg;
2085
2086 /*
2087 * Update FCS error count from register.
2088 */
2089 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2090 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
2091}
2092EXPORT_SYMBOL_GPL(rt2800_link_stats);
2093
2094static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
2095{
2096 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
d5385bfc 2097 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 2098 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 2099 rt2x00_rt(rt2x00dev, RT3090) ||
60687ba7
RST		 2100 rt2x00_rt(rt2x00dev, RT3390) ||
2101 rt2x00_rt(rt2x00dev, RT5390))
f4450616
BZ		 2102 return 0x1c + (2 * rt2x00dev->lna_gain);
2103 else
2104 return 0x2e + rt2x00dev->lna_gain;
2105 }
2106
2107 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2108 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
2109 else
2110 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
2111}
2112
2113static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
2114 struct link_qual *qual, u8 vgc_level)
2115{
2116 if (qual->vgc_level != vgc_level) {
2117 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
2118 qual->vgc_level = vgc_level;
2119 qual->vgc_level_reg = vgc_level;
2120 }
2121}
2122
2123void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2124{
2125 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
2126}
2127EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
2128
2129void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
2130 const u32 count)
2131{
8d0c9b65 2132 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616
BZ		 2133 return;
2134
2135 /*
2136 * When RSSI is better then -80 increase VGC level with 0x10
2137 */
2138 rt2800_set_vgc(rt2x00dev, qual,
2139 rt2800_get_default_vgc(rt2x00dev) +
2140 ((qual->rssi > -80) * 0x10));
2141}
2142EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 2143
2144/*
2145 * Initialization functions.
2146 */
b9a07ae9 2147static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 2148{
2149 u32 reg;
d5385bfc 2150 u16 eeprom;
fcf51541 2151 unsigned int i;
e3a896b9 2152 int ret;
fcf51541 2153
a9dce149
GW		 2154 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2155 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2156 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2157 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2158 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2159 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2160 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2161
e3a896b9
GW		 2162 ret = rt2800_drv_init_registers(rt2x00dev);
2163 if (ret)
2164 return ret;
fcf51541
BZ		 2165
2166 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
2167 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
2168 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
2169 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
2170 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
2171 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
2172
2173 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
2174 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
2175 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
2176 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
2177 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
2178 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
2179
2180 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
2181 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2182
2183 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
2184
2185 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
8544df32 2186 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
fcf51541
BZ		 2187 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2188 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
2189 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2190 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2191 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
2192 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2193
a9dce149
GW		 2194 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
2195
2196 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
2197 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
2198 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
2199 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2200
64522957 2201 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2202 rt2x00_rt(rt2x00dev, RT3090) ||
2203 rt2x00_rt(rt2x00dev, RT3390)) {
fcf51541
BZ		 2204 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2205 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 2206 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2207 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2208 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
38c8a566
RJH		 2209 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2210 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 2211 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2212 0x0000002c);
2213 else
2214 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2215 0x0000000f);
2216 } else {
2217 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2218 }
d5385bfc 2219 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 2220 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 2221
2222 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2223 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2224 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
2225 } else {
2226 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2227 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2228 }
c295a81d
HS		 2229 } else if (rt2800_is_305x_soc(rt2x00dev)) {
2230 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2231 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2232 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
60687ba7
RST		 2233 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2234 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
2235 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2236 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
fcf51541
BZ		 2237 } else {
2238 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
2239 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2240 }
2241
2242 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
2243 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
2244 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
2245 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
2246 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
2247 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
2248 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
2249 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
2250 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
2251 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
2252
2253 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
2254 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 2255 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 2256 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
2257 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
2258
2259 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
2260 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 2261 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 2262 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 2263 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 2264 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
2265 else
2266 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
2267 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
2268 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
2269 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
2270
a9dce149
GW		 2271 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
2272 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
2273 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
2274 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
2275 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
2276 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
2277 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
2278 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
2279 rt2800_register_write(rt2x00dev, LED_CFG, reg);
2280
fcf51541
BZ		 2281 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
2282
a9dce149
GW		 2283 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2284 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
2285 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
2286 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
2287 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
2288 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
2289 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
2290 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2291
fcf51541
BZ		 2292 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
2293 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 2294 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 2295 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
2296 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 2297 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 2298 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
2299 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
2300 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2301
2302 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 2303 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541 2304 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2305 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2306 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2307 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2308 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 2309 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 2310 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 2311 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2312 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 2313 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2314
2315 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 2316 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541 2317 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2318 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2319 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2320 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2321 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 2322 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 2323 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 2324 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2325 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 2326 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2327
2328 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2329 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2330 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2331 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2332 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2333 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2334 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2335 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2336 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2337 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 2338 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2339 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2340
2341 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2342 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
d13a97f0 2343 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2344 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2345 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2346 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2347 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2348 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2349 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2350 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 2351 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2352 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2353
2354 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2355 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2356 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2357 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2358 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2359 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2360 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2361 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2362 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2363 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 2364 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2365 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2366
2367 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2368 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2369 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2370 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2371 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2372 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2373 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2374 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2375 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2376 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 2377 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2378 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2379
cea90e55 2380 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 2381 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
2382
2383 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2384 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2385 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2386 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2387 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2388 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
2389 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
2390 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
2391 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
2392 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
2393 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2394 }
2395
961621ab
HS		 2396 /*
2397 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2398 * although it is reserved.
2399 */
2400 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
2401 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
2402 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
2403 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
2404 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
2405 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
2406 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
2407 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
2408 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
2409 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
2410 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
2411 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
2412
fcf51541
BZ		 2413 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
2414
2415 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2416 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
2417 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
2418 IEEE80211_MAX_RTS_THRESHOLD);
2419 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
2420 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2421
2422 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 2423
a21c2ab4
HS		 2424 /*
2425 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
2426 * time should be set to 16. However, the original Ralink driver uses
2427 * 16 for both and indeed using a value of 10 for CCK SIFS results in
2428 * connection problems with 11g + CTS protection. Hence, use the same
2429 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
2430 */
a9dce149 2431 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 2432 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
2433 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 2434 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
2435 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
2436 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
2437 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2438
fcf51541
BZ		 2439 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
2440
2441 /*
2442 * ASIC will keep garbage value after boot, clear encryption keys.
2443 */
2444 for (i = 0; i < 4; i++)
2445 rt2800_register_write(rt2x00dev,
2446 SHARED_KEY_MODE_ENTRY(i), 0);
2447
2448 for (i = 0; i < 256; i++) {
f4e16e41 2449 static const u32 wcid[2] = { 0xffffffff, 0x00ffffff };
fcf51541
BZ		 2450 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
2451 wcid, sizeof(wcid));
2452
2453 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
2454 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
2455 }
2456
2457 /*
2458 * Clear all beacons
fcf51541 2459 */
69cf36a4
HS		 2460 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
2461 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
2462 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
2463 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
2464 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
2465 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
2466 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
2467 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
fcf51541 2468
cea90e55 2469 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 2470 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2471 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
2472 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
c6fcc0e5
RJH		 2473 } else if (rt2x00_is_pcie(rt2x00dev)) {
2474 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2475 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
2476 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 2477 }
2478
2479 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
2480 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
2481 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
2482 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
2483 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
2484 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
2485 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
2486 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
2487 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
2488 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
2489
2490 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
2491 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
2492 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
2493 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
2494 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
2495 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
2496 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
2497 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
2498 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
2499 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
2500
2501 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
2502 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
2503 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
2504 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
2505 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
2506 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
2507 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
2508 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
2509 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
2510 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
2511
2512 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
2513 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
2514 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
2515 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
2516 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
2517 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
2518
47ee3eb1
HS		 2519 /*
2520 * Do not force the BA window size, we use the TXWI to set it
2521 */
2522 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
2523 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
2524 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
2525 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
2526
fcf51541
BZ		 2527 /*
2528 * We must clear the error counters.
2529 * These registers are cleared on read,
2530 * so we may pass a useless variable to store the value.
2531 */
2532 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2533 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
2534 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
2535 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
2536 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
2537 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
2538
9f926fb5
HS		 2539 /*
2540 * Setup leadtime for pre tbtt interrupt to 6ms
2541 */
2542 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
2543 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
2544 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
2545
977206d7
HS		 2546 /*
2547 * Set up channel statistics timer
2548 */
2549 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
2550 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
2551 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
2552 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
2553 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
2554 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
2555 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
2556
fcf51541
BZ		 2557 return 0;
2558}
fcf51541
BZ		 2559
2560static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
2561{
2562 unsigned int i;
2563 u32 reg;
2564
2565 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2566 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
2567 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
2568 return 0;
2569
2570 udelay(REGISTER_BUSY_DELAY);
2571 }
2572
2573 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
2574 return -EACCES;
2575}
2576
2577static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2578{
2579 unsigned int i;
2580 u8 value;
2581
2582 /*
2583 * BBP was enabled after firmware was loaded,
2584 * but we need to reactivate it now.
2585 */
2586 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2587 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2588 msleep(1);
2589
2590 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2591 rt2800_bbp_read(rt2x00dev, 0, &value);
2592 if ((value != 0xff) && (value != 0x00))
2593 return 0;
2594 udelay(REGISTER_BUSY_DELAY);
2595 }
2596
2597 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
2598 return -EACCES;
2599}
2600
b9a07ae9 2601static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 2602{
2603 unsigned int i;
2604 u16 eeprom;
2605 u8 reg_id;
2606 u8 value;
2607
2608 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
2609 rt2800_wait_bbp_ready(rt2x00dev)))
2610 return -EACCES;
2611
60687ba7
RST		 2612 if (rt2x00_rt(rt2x00dev, RT5390)) {
2613 rt2800_bbp_read(rt2x00dev, 4, &value);
2614 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
2615 rt2800_bbp_write(rt2x00dev, 4, value);
2616 }
2617
2618 if (rt2800_is_305x_soc(rt2x00dev) ||
2619 rt2x00_rt(rt2x00dev, RT5390))
baff8006
HS		 2620 rt2800_bbp_write(rt2x00dev, 31, 0x08);
2621
fcf51541
BZ		 2622 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
2623 rt2800_bbp_write(rt2x00dev, 66, 0x38);
a9dce149 2624
60687ba7
RST		 2625 if (rt2x00_rt(rt2x00dev, RT5390))
2626 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2627
a9dce149
GW		 2628 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2629 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2630 rt2800_bbp_write(rt2x00dev, 73, 0x12);
60687ba7
RST		 2631 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2632 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2633 rt2800_bbp_write(rt2x00dev, 73, 0x13);
2634 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2635 rt2800_bbp_write(rt2x00dev, 76, 0x28);
2636 rt2800_bbp_write(rt2x00dev, 77, 0x59);
a9dce149
GW		 2637 } else {
2638 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2639 rt2800_bbp_write(rt2x00dev, 73, 0x10);
2640 }
2641
fcf51541 2642 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
8cdd15e0 2643
d5385bfc 2644 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 2645 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 2646 rt2x00_rt(rt2x00dev, RT3090) ||
60687ba7
RST		 2647 rt2x00_rt(rt2x00dev, RT3390) ||
2648 rt2x00_rt(rt2x00dev, RT5390)) {
8cdd15e0
GW		 2649 rt2800_bbp_write(rt2x00dev, 79, 0x13);
2650 rt2800_bbp_write(rt2x00dev, 80, 0x05);
2651 rt2800_bbp_write(rt2x00dev, 81, 0x33);
baff8006
HS		 2652 } else if (rt2800_is_305x_soc(rt2x00dev)) {
2653 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
2654 rt2800_bbp_write(rt2x00dev, 80, 0x08);
8cdd15e0
GW		 2655 } else {
2656 rt2800_bbp_write(rt2x00dev, 81, 0x37);
2657 }
2658
fcf51541 2659 rt2800_bbp_write(rt2x00dev, 82, 0x62);
60687ba7
RST		 2660 if (rt2x00_rt(rt2x00dev, RT5390))
2661 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
2662 else
2663 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
a9dce149 2664
5ed8f458 2665 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
a9dce149 2666 rt2800_bbp_write(rt2x00dev, 84, 0x19);
60687ba7
RST		 2667 else if (rt2x00_rt(rt2x00dev, RT5390))
2668 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
a9dce149
GW		 2669 else
2670 rt2800_bbp_write(rt2x00dev, 84, 0x99);
2671
60687ba7
RST		 2672 if (rt2x00_rt(rt2x00dev, RT5390))
2673 rt2800_bbp_write(rt2x00dev, 86, 0x38);
2674 else
2675 rt2800_bbp_write(rt2x00dev, 86, 0x00);
2676
fcf51541 2677 rt2800_bbp_write(rt2x00dev, 91, 0x04);
60687ba7
RST		 2678
2679 if (rt2x00_rt(rt2x00dev, RT5390))
2680 rt2800_bbp_write(rt2x00dev, 92, 0x02);
2681 else
2682 rt2800_bbp_write(rt2x00dev, 92, 0x00);
8cdd15e0 2683
d5385bfc 2684 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 2685 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904 2686 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
baff8006 2687 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
60687ba7 2688 rt2x00_rt(rt2x00dev, RT5390) ||
baff8006 2689 rt2800_is_305x_soc(rt2x00dev))
8cdd15e0
GW		 2690 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
2691 else
2692 rt2800_bbp_write(rt2x00dev, 103, 0x00);
2693
60687ba7
RST		 2694 if (rt2x00_rt(rt2x00dev, RT5390))
2695 rt2800_bbp_write(rt2x00dev, 104, 0x92);
2696
baff8006
HS		 2697 if (rt2800_is_305x_soc(rt2x00dev))
2698 rt2800_bbp_write(rt2x00dev, 105, 0x01);
60687ba7
RST		 2699 else if (rt2x00_rt(rt2x00dev, RT5390))
2700 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
baff8006
HS		 2701 else
2702 rt2800_bbp_write(rt2x00dev, 105, 0x05);
60687ba7
RST		 2703
2704 if (rt2x00_rt(rt2x00dev, RT5390))
2705 rt2800_bbp_write(rt2x00dev, 106, 0x03);
2706 else
2707 rt2800_bbp_write(rt2x00dev, 106, 0x35);
2708
2709 if (rt2x00_rt(rt2x00dev, RT5390))
2710 rt2800_bbp_write(rt2x00dev, 128, 0x12);
fcf51541 2711
64522957 2712 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 2713 rt2x00_rt(rt2x00dev, RT3090) ||
60687ba7
RST		 2714 rt2x00_rt(rt2x00dev, RT3390) ||
2715 rt2x00_rt(rt2x00dev, RT5390)) {
d5385bfc 2716 rt2800_bbp_read(rt2x00dev, 138, &value);
fcf51541 2717
38c8a566
RJH		 2718 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
2719 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
d5385bfc 2720 value |= 0x20;
38c8a566 2721 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
d5385bfc 2722 value &= ~0x02;
fcf51541 2723
d5385bfc 2724 rt2800_bbp_write(rt2x00dev, 138, value);
fcf51541
BZ		 2725 }
2726
60687ba7
RST		 2727 if (rt2x00_rt(rt2x00dev, RT5390)) {
2728 int ant, div_mode;
2729
2730 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2731 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
2732 ant = (div_mode == 3) ? 1 : 0;
2733
2734 /* check if this is a Bluetooth combo card */
2735 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2736 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) {
2737 u32 reg;
2738
2739 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
2740 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
2741 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT6, 0);
2742 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 0);
2743 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 0);
2744 if (ant == 0)
2745 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 1);
2746 else if (ant == 1)
2747 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 1);
2748 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
2749 }
2750
2751 rt2800_bbp_read(rt2x00dev, 152, &value);
2752 if (ant == 0)
2753 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
2754 else
2755 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
2756 rt2800_bbp_write(rt2x00dev, 152, value);
2757
2758 /* Init frequency calibration */
2759 rt2800_bbp_write(rt2x00dev, 142, 1);
2760 rt2800_bbp_write(rt2x00dev, 143, 57);
2761 }
fcf51541
BZ		 2762
2763 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
2764 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
2765
2766 if (eeprom != 0xffff && eeprom != 0x0000) {
2767 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
2768 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
2769 rt2800_bbp_write(rt2x00dev, reg_id, value);
2770 }
2771 }
2772
2773 return 0;
2774}
fcf51541
BZ		 2775
2776static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
2777 bool bw40, u8 rfcsr24, u8 filter_target)
2778{
2779 unsigned int i;
2780 u8 bbp;
2781 u8 rfcsr;
2782 u8 passband;
2783 u8 stopband;
2784 u8 overtuned = 0;
2785
2786 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2787
2788 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2789 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
2790 rt2800_bbp_write(rt2x00dev, 4, bbp);
2791
80d184e6
RJH		 2792 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
2793 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
2794 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2795
fcf51541
BZ		 2796 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2797 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
2798 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2799
2800 /*
2801 * Set power & frequency of passband test tone
2802 */
2803 rt2800_bbp_write(rt2x00dev, 24, 0);
2804
2805 for (i = 0; i < 100; i++) {
2806 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2807 msleep(1);
2808
2809 rt2800_bbp_read(rt2x00dev, 55, &passband);
2810 if (passband)
2811 break;
2812 }
2813
2814 /*
2815 * Set power & frequency of stopband test tone
2816 */
2817 rt2800_bbp_write(rt2x00dev, 24, 0x06);
2818
2819 for (i = 0; i < 100; i++) {
2820 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2821 msleep(1);
2822
2823 rt2800_bbp_read(rt2x00dev, 55, &stopband);
2824
2825 if ((passband - stopband) <= filter_target) {
2826 rfcsr24++;
2827 overtuned += ((passband - stopband) == filter_target);
2828 } else
2829 break;
2830
2831 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2832 }
2833
2834 rfcsr24 -= !!overtuned;
2835
2836 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2837 return rfcsr24;
2838}
2839
b9a07ae9 2840static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 2841{
2842 u8 rfcsr;
2843 u8 bbp;
8cdd15e0
GW		 2844 u32 reg;
2845 u16 eeprom;
fcf51541 2846
d5385bfc 2847 if (!rt2x00_rt(rt2x00dev, RT3070) &&
64522957 2848 !rt2x00_rt(rt2x00dev, RT3071) &&
cc78e904 2849 !rt2x00_rt(rt2x00dev, RT3090) &&
23812383 2850 !rt2x00_rt(rt2x00dev, RT3390) &&
60687ba7 2851 !rt2x00_rt(rt2x00dev, RT5390) &&
baff8006 2852 !rt2800_is_305x_soc(rt2x00dev))
fcf51541
BZ		 2853 return 0;
2854
fcf51541
BZ		 2855 /*
2856 * Init RF calibration.
2857 */
60687ba7
RST		 2858 if (rt2x00_rt(rt2x00dev, RT5390)) {
2859 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
2860 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
2861 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
2862 msleep(1);
2863 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
2864 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
2865 } else {
2866 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2867 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2868 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2869 msleep(1);
2870 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2871 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2872 }
fcf51541 2873
d5385bfc 2874 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957
GW		 2875 rt2x00_rt(rt2x00dev, RT3071) ||
2876 rt2x00_rt(rt2x00dev, RT3090)) {
fcf51541
BZ		 2877 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2878 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2879 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
80d184e6 2880 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
fcf51541 2881 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
8cdd15e0 2882 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
fcf51541
BZ		 2883 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2884 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
2885 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2886 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2887 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2888 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2889 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2890 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2891 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2892 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2893 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
2894 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
fcf51541 2895 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
cc78e904
GW		 2896 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2897 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
2898 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
2899 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
2900 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
fcf51541 2901 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
cc78e904
GW		 2902 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
2903 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
2904 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
2905 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
2906 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2907 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
fcf51541 2908 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
cc78e904
GW		 2909 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
2910 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
fcf51541 2911 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
cc78e904
GW		 2912 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2913 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
2914 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
2915 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
2916 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
2917 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
2918 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
fcf51541 2919 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
cc78e904 2920 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
fcf51541 2921 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
cc78e904
GW		 2922 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2923 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2924 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2925 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
2926 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
2927 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
2928 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
baff8006 2929 } else if (rt2800_is_305x_soc(rt2x00dev)) {
23812383
HS		 2930 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
2931 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
2932 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
2933 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
2934 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2935 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2936 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2937 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
2938 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
2939 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2940 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
2941 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2942 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
2943 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
2944 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2945 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2946 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2947 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2948 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2949 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2950 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2951 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2952 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2953 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
2954 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2955 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2956 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
2957 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
2958 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
2959 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
baff8006
HS		 2960 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
2961 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
2962 return 0;
60687ba7
RST		 2963 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2964 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
2965 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
2966 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
2967 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
2968 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
2969 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
2970 else
2971 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
2972 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
2973 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
2974 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
2975 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
2976 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
2977 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
2978 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
2979 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
2980 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
2981 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
2982
2983 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
2984 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
2985 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
2986 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
2987 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
2988 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
2989 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2990 else
2991 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
2992 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
2993 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
2994 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
2995 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
2996
2997 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
2998 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2999 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3000 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3001 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3002 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3003 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3004 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3005 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3006 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3007
3008 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3009 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3010 else
3011 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
3012 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3013 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
3014 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
3015 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3016 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3017 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3018 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3019 else
3020 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
3021 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3022 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3023 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3024
3025 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3026 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3027 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3028 else
3029 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
3030 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3031 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
3032 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
3033 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3034 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3035 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
3036
3037 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3038 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3039 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
3040 else
3041 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
3042 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
3043 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
8cdd15e0
GW		 3044 }
3045
3046 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3047 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3048 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3049 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3050 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
64522957
GW		 3051 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3052 rt2x00_rt(rt2x00dev, RT3090)) {
80d184e6
RJH		 3053 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
3054
d5385bfc
GW		 3055 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3056 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3057 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3058
d5385bfc
GW		 3059 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3060 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
64522957
GW		 3061 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3062 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
38c8a566
RJH		 3063 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3064 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 3065 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3066 else
3067 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
3068 }
3069 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
80d184e6
RJH		 3070
3071 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3072 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3073 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
cc78e904
GW		 3074 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3075 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3076 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3077 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
fcf51541
BZ		 3078 }
3079
3080 /*
3081 * Set RX Filter calibration for 20MHz and 40MHz
3082 */
8cdd15e0
GW		 3083 if (rt2x00_rt(rt2x00dev, RT3070)) {
3084 rt2x00dev->calibration[0] =
3085 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
3086 rt2x00dev->calibration[1] =
3087 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
64522957 3088 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 3089 rt2x00_rt(rt2x00dev, RT3090) ||
3090 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 3091 rt2x00dev->calibration[0] =
3092 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
3093 rt2x00dev->calibration[1] =
3094 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
8cdd15e0 3095 }
fcf51541 3096
60687ba7
RST		 3097 if (!rt2x00_rt(rt2x00dev, RT5390)) {
3098 /*
3099 * Set back to initial state
3100 */
3101 rt2800_bbp_write(rt2x00dev, 24, 0);
fcf51541 3102
60687ba7
RST		 3103 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3104 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
3105 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
fcf51541 3106
60687ba7
RST		 3107 /*
3108 * Set BBP back to BW20
3109 */
3110 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3111 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
3112 rt2800_bbp_write(rt2x00dev, 4, bbp);
3113 }
fcf51541 3114
d5385bfc 3115 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 3116 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 3117 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3118 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
8cdd15e0
GW		 3119 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
3120
3121 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
3122 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
3123 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
3124
60687ba7
RST		 3125 if (!rt2x00_rt(rt2x00dev, RT5390)) {
3126 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
3127 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
3128 if (rt2x00_rt(rt2x00dev, RT3070) ||
3129 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3130 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3131 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3132 if (!test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
3133 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
3134 }
3135 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
3136 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
3137 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
3138 rt2x00_get_field16(eeprom,
3139 EEPROM_TXMIXER_GAIN_BG_VAL));
3140 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3141 }
8cdd15e0 3142
64522957
GW		 3143 if (rt2x00_rt(rt2x00dev, RT3090)) {
3144 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3145
80d184e6 3146 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
38c8a566
RJH		 3147 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3148 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
64522957 3149 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
38c8a566 3150 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
64522957
GW		 3151 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
3152
3153 rt2800_bbp_write(rt2x00dev, 138, bbp);
3154 }
3155
3156 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 3157 rt2x00_rt(rt2x00dev, RT3090) ||
3158 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 3159 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
3160 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3161 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
3162 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
3163 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3164 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3165 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3166
3167 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
3168 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
3169 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
3170
3171 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
3172 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
3173 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3174
3175 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
3176 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
3177 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3178 }
3179
80d184e6 3180 if (rt2x00_rt(rt2x00dev, RT3070)) {
8cdd15e0 3181 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
80d184e6 3182 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
8cdd15e0
GW		 3183 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
3184 else
3185 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
3186 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
3187 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
3188 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
3189 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
3190 }
3191
60687ba7
RST		 3192 if (rt2x00_rt(rt2x00dev, RT5390)) {
3193 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
3194 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
3195 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
3196
3197 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
3198 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
3199 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3200
3201 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3202 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
3203 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3204 }
3205
fcf51541
BZ		 3206 return 0;
3207}
b9a07ae9
ID		 3208
3209int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
3210{
3211 u32 reg;
3212 u16 word;
3213
3214 /*
3215 * Initialize all registers.
3216 */
3217 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
3218 rt2800_init_registers(rt2x00dev) ||
3219 rt2800_init_bbp(rt2x00dev) ||
3220 rt2800_init_rfcsr(rt2x00dev)))
3221 return -EIO;
3222
3223 /*
3224 * Send signal to firmware during boot time.
3225 */
3226 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
3227
3228 if (rt2x00_is_usb(rt2x00dev) &&
3229 (rt2x00_rt(rt2x00dev, RT3070) ||
3230 rt2x00_rt(rt2x00dev, RT3071) ||
3231 rt2x00_rt(rt2x00dev, RT3572))) {
3232 udelay(200);
3233 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
3234 udelay(10);
3235 }
3236
3237 /*
3238 * Enable RX.
3239 */
3240 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3241 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3242 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3243 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3244
3245 udelay(50);
3246
3247 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3248 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
3249 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
3250 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
3251 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
3252 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3253
3254 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3255 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3256 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
3257 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3258
3259 /*
3260 * Initialize LED control
3261 */
38c8a566
RJH		 3262 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
3263 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
b9a07ae9
ID		 3264 word & 0xff, (word >> 8) & 0xff);
3265
38c8a566
RJH		 3266 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
3267 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
b9a07ae9
ID		 3268 word & 0xff, (word >> 8) & 0xff);
3269
38c8a566
RJH		 3270 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
3271 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
b9a07ae9
ID		 3272 word & 0xff, (word >> 8) & 0xff);
3273
3274 return 0;
3275}
3276EXPORT_SYMBOL_GPL(rt2800_enable_radio);
3277
3278void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
3279{
3280 u32 reg;
3281
3282 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3283 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
b9a07ae9 3284 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
b9a07ae9
ID		 3285 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3286
3287 /* Wait for DMA, ignore error */
3288 rt2800_wait_wpdma_ready(rt2x00dev);
3289
3290 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3291 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
3292 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3293 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
b9a07ae9
ID		 3294}
3295EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2ce33995 3296
30e84034
BZ		 3297int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
3298{
3299 u32 reg;
3300
3301 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
3302
3303 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
3304}
3305EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
3306
3307static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
3308{
3309 u32 reg;
3310
31a4cf1f
GW		 3311 mutex_lock(&rt2x00dev->csr_mutex);
3312
3313 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
30e84034
BZ		 3314 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
3315 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
3316 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
31a4cf1f 3317 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
30e84034
BZ		 3318
3319 /* Wait until the EEPROM has been loaded */
3320 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
3321
3322 /* Apparently the data is read from end to start */
31a4cf1f
GW		 3323 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
3324 (u32 *)&rt2x00dev->eeprom[i]);
3325 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
3326 (u32 *)&rt2x00dev->eeprom[i + 2]);
3327 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
3328 (u32 *)&rt2x00dev->eeprom[i + 4]);
3329 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
3330 (u32 *)&rt2x00dev->eeprom[i + 6]);
3331
3332 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 3333}
3334
3335void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
3336{
3337 unsigned int i;
3338
3339 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
3340 rt2800_efuse_read(rt2x00dev, i);
3341}
3342EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
3343
38bd7b8a
BZ		 3344int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
3345{
3346 u16 word;
3347 u8 *mac;
3348 u8 default_lna_gain;
3349
3350 /*
3351 * Start validation of the data that has been read.
3352 */
3353 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
3354 if (!is_valid_ether_addr(mac)) {
3355 random_ether_addr(mac);
3356 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
3357 }
3358
38c8a566 3359 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
38bd7b8a 3360 if (word == 0xffff) {
38c8a566
RJH		 3361 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3362 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
3363 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
3364 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a 3365 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 3366 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 3367 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 3368 /*
3369 * There is a max of 2 RX streams for RT28x0 series
3370 */
38c8a566
RJH		 3371 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
3372 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3373 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a
BZ		 3374 }
3375
38c8a566 3376 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
38bd7b8a 3377 if (word == 0xffff) {
38c8a566
RJH		 3378 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
3379 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
3380 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
3381 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
3382 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
3383 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
3384 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
3385 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
3386 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
3387 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
3388 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
3389 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
3390 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
3391 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
3392 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
3393 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
38bd7b8a
BZ		 3394 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
3395 }
3396
3397 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
3398 if ((word & 0x00ff) == 0x00ff) {
3399 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
ec2d1791
GW		 3400 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
3401 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
3402 }
3403 if ((word & 0xff00) == 0xff00) {
38bd7b8a
BZ		 3404 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
3405 LED_MODE_TXRX_ACTIVITY);
3406 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
3407 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
38c8a566
RJH		 3408 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
3409 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
3410 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
ec2d1791 3411 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
38bd7b8a
BZ		 3412 }
3413
3414 /*
3415 * During the LNA validation we are going to use
3416 * lna0 as correct value. Note that EEPROM_LNA
3417 * is never validated.
3418 */
3419 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
3420 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
3421
3422 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
3423 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
3424 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
3425 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
3426 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
3427 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
3428
3429 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
3430 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
3431 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
3432 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
3433 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
3434 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
3435 default_lna_gain);
3436 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
3437
3438 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
3439 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
3440 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
3441 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
3442 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
3443 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
3444
3445 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
3446 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
3447 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
3448 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
3449 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
3450 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
3451 default_lna_gain);
3452 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
3453
3454 return 0;
3455}
3456EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
3457
3458int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
3459{
3460 u32 reg;
3461 u16 value;
3462 u16 eeprom;
3463
3464 /*
3465 * Read EEPROM word for configuration.
3466 */
38c8a566 3467 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
38bd7b8a
BZ		 3468
3469 /*
60687ba7
RST		 3470 * Identify RF chipset by EEPROM value
3471 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
3472 * RT53xx: defined in "EEPROM_CHIP_ID" field
38bd7b8a 3473 */
38bd7b8a 3474 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
60687ba7
RST		 3475 if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390)
3476 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
3477 else
3478 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
38bd7b8a 3479
49e721ec
GW		 3480 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
3481 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
3482
3483 if (!rt2x00_rt(rt2x00dev, RT2860) &&
49e721ec 3484 !rt2x00_rt(rt2x00dev, RT2872) &&
49e721ec 3485 !rt2x00_rt(rt2x00dev, RT2883) &&
49e721ec
GW		 3486 !rt2x00_rt(rt2x00dev, RT3070) &&
3487 !rt2x00_rt(rt2x00dev, RT3071) &&
3488 !rt2x00_rt(rt2x00dev, RT3090) &&
3489 !rt2x00_rt(rt2x00dev, RT3390) &&
60687ba7
RST		 3490 !rt2x00_rt(rt2x00dev, RT3572) &&
3491 !rt2x00_rt(rt2x00dev, RT5390)) {
49e721ec
GW		 3492 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
3493 return -ENODEV;
f273fe55 3494 }
714fa663 3495
5122d898
GW		 3496 if (!rt2x00_rf(rt2x00dev, RF2820) &&
3497 !rt2x00_rf(rt2x00dev, RF2850) &&
3498 !rt2x00_rf(rt2x00dev, RF2720) &&
3499 !rt2x00_rf(rt2x00dev, RF2750) &&
3500 !rt2x00_rf(rt2x00dev, RF3020) &&
3501 !rt2x00_rf(rt2x00dev, RF2020) &&
3502 !rt2x00_rf(rt2x00dev, RF3021) &&
6c0fe265 3503 !rt2x00_rf(rt2x00dev, RF3022) &&
f93bc9b3 3504 !rt2x00_rf(rt2x00dev, RF3052) &&
60687ba7
RST		 3505 !rt2x00_rf(rt2x00dev, RF3320) &&
3506 !rt2x00_rf(rt2x00dev, RF5390)) {
38bd7b8a
BZ		 3507 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
3508 return -ENODEV;
3509 }
3510
3511 /*
3512 * Identify default antenna configuration.
3513 */
d96aa640 3514 rt2x00dev->default_ant.tx_chain_num =
38c8a566 3515 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
d96aa640 3516 rt2x00dev->default_ant.rx_chain_num =
38c8a566 3517 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
38bd7b8a 3518
d96aa640
RJH		 3519 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3520
3521 if (rt2x00_rt(rt2x00dev, RT3070) ||
3522 rt2x00_rt(rt2x00dev, RT3090) ||
3523 rt2x00_rt(rt2x00dev, RT3390)) {
3524 value = rt2x00_get_field16(eeprom,
3525 EEPROM_NIC_CONF1_ANT_DIVERSITY);
3526 switch (value) {
3527 case 0:
3528 case 1:
3529 case 2:
3530 rt2x00dev->default_ant.tx = ANTENNA_A;
3531 rt2x00dev->default_ant.rx = ANTENNA_A;
3532 break;
3533 case 3:
3534 rt2x00dev->default_ant.tx = ANTENNA_A;
3535 rt2x00dev->default_ant.rx = ANTENNA_B;
3536 break;
3537 }
3538 } else {
3539 rt2x00dev->default_ant.tx = ANTENNA_A;
3540 rt2x00dev->default_ant.rx = ANTENNA_A;
3541 }
3542
38bd7b8a
BZ		 3543 /*
3544 * Read frequency offset and RF programming sequence.
3545 */
3546 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
3547 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
3548
3549 /*
3550 * Read external LNA informations.
3551 */
38c8a566 3552 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
38bd7b8a 3553
38c8a566 3554 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
38bd7b8a 3555 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
38c8a566 3556 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
38bd7b8a
BZ		 3557 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
3558
3559 /*
3560 * Detect if this device has an hardware controlled radio.
3561 */
38c8a566 3562 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
38bd7b8a
BZ		 3563 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
3564
3565 /*
3566 * Store led settings, for correct led behaviour.
3567 */
3568#ifdef CONFIG_RT2X00_LIB_LEDS
3569 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3570 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
3571 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
3572
3573 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
3574#endif /* CONFIG_RT2X00_LIB_LEDS */
3575
e90c54b2
RJH		 3576 /*
3577 * Check if support EIRP tx power limit feature.
3578 */
3579 rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
3580
3581 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
3582 EIRP_MAX_TX_POWER_LIMIT)
3583 __set_bit(CONFIG_SUPPORT_POWER_LIMIT, &rt2x00dev->flags);
3584
38bd7b8a
BZ		 3585 return 0;
3586}
3587EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
3588
4da2933f 3589/*
55f9321a 3590 * RF value list for rt28xx
4da2933f
BZ		 3591 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
3592 */
3593static const struct rf_channel rf_vals[] = {
3594 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
3595 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
3596 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
3597 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
3598 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
3599 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
3600 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
3601 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
3602 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
3603 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
3604 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
3605 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
3606 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
3607 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
3608
3609 /* 802.11 UNI / HyperLan 2 */
3610 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
3611 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
3612 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
3613 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
3614 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
3615 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
3616 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
3617 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
3618 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
3619 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
3620 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
3621 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
3622
3623 /* 802.11 HyperLan 2 */
3624 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
3625 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
3626 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
3627 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
3628 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
3629 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
3630 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
3631 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
3632 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
3633 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
3634 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
3635 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
3636 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
3637 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
3638 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
3639 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
3640
3641 /* 802.11 UNII */
3642 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
3643 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
3644 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
3645 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
3646 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
3647 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
3648 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
3649 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
3650 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
3651 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
3652 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
3653
3654 /* 802.11 Japan */
3655 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
3656 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
3657 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
3658 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
3659 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
3660 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
3661 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
3662};
3663
3664/*
55f9321a
ID		 3665 * RF value list for rt3xxx
3666 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4da2933f 3667 */
55f9321a 3668static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 3669 {1, 241, 2, 2 },
3670 {2, 241, 2, 7 },
3671 {3, 242, 2, 2 },
3672 {4, 242, 2, 7 },
3673 {5, 243, 2, 2 },
3674 {6, 243, 2, 7 },
3675 {7, 244, 2, 2 },
3676 {8, 244, 2, 7 },
3677 {9, 245, 2, 2 },
3678 {10, 245, 2, 7 },
3679 {11, 246, 2, 2 },
3680 {12, 246, 2, 7 },
3681 {13, 247, 2, 2 },
3682 {14, 248, 2, 4 },
55f9321a
ID		 3683
3684 /* 802.11 UNI / HyperLan 2 */
3685 {36, 0x56, 0, 4},
3686 {38, 0x56, 0, 6},
3687 {40, 0x56, 0, 8},
3688 {44, 0x57, 0, 0},
3689 {46, 0x57, 0, 2},
3690 {48, 0x57, 0, 4},
3691 {52, 0x57, 0, 8},
3692 {54, 0x57, 0, 10},
3693 {56, 0x58, 0, 0},
3694 {60, 0x58, 0, 4},
3695 {62, 0x58, 0, 6},
3696 {64, 0x58, 0, 8},
3697
3698 /* 802.11 HyperLan 2 */
3699 {100, 0x5b, 0, 8},
3700 {102, 0x5b, 0, 10},
3701 {104, 0x5c, 0, 0},
3702 {108, 0x5c, 0, 4},
3703 {110, 0x5c, 0, 6},
3704 {112, 0x5c, 0, 8},
3705 {116, 0x5d, 0, 0},
3706 {118, 0x5d, 0, 2},
3707 {120, 0x5d, 0, 4},
3708 {124, 0x5d, 0, 8},
3709 {126, 0x5d, 0, 10},
3710 {128, 0x5e, 0, 0},
3711 {132, 0x5e, 0, 4},
3712 {134, 0x5e, 0, 6},
3713 {136, 0x5e, 0, 8},
3714 {140, 0x5f, 0, 0},
3715
3716 /* 802.11 UNII */
3717 {149, 0x5f, 0, 9},
3718 {151, 0x5f, 0, 11},
3719 {153, 0x60, 0, 1},
3720 {157, 0x60, 0, 5},
3721 {159, 0x60, 0, 7},
3722 {161, 0x60, 0, 9},
3723 {165, 0x61, 0, 1},
3724 {167, 0x61, 0, 3},
3725 {169, 0x61, 0, 5},
3726 {171, 0x61, 0, 7},
3727 {173, 0x61, 0, 9},
4da2933f
BZ		 3728};
3729
3730int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
3731{
4da2933f
BZ		 3732 struct hw_mode_spec *spec = &rt2x00dev->spec;
3733 struct channel_info *info;
8d1331b3
ID		 3734 char *default_power1;
3735 char *default_power2;
4da2933f
BZ		 3736 unsigned int i;
3737 u16 eeprom;
3738
93b6bd26
GW		 3739 /*
3740 * Disable powersaving as default on PCI devices.
3741 */
cea90e55 3742 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
93b6bd26
GW		 3743 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3744
4da2933f
BZ		 3745 /*
3746 * Initialize all hw fields.
3747 */
3748 rt2x00dev->hw->flags =
4da2933f
BZ		 3749 IEEE80211_HW_SIGNAL_DBM |
3750 IEEE80211_HW_SUPPORTS_PS |
1df90809
HS		 3751 IEEE80211_HW_PS_NULLFUNC_STACK |
3752 IEEE80211_HW_AMPDU_AGGREGATION;
5a5b6ed6
HS		 3753 /*
3754 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
3755 * unless we are capable of sending the buffered frames out after the
3756 * DTIM transmission using rt2x00lib_beacondone. This will send out
3757 * multicast and broadcast traffic immediately instead of buffering it
3758 * infinitly and thus dropping it after some time.
3759 */
3760 if (!rt2x00_is_usb(rt2x00dev))
3761 rt2x00dev->hw->flags |=
3762 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
4da2933f 3763
4da2933f
BZ		 3764 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
3765 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3766 rt2x00_eeprom_addr(rt2x00dev,
3767 EEPROM_MAC_ADDR_0));
3768
3f2bee24
HS		 3769 /*
3770 * As rt2800 has a global fallback table we cannot specify
3771 * more then one tx rate per frame but since the hw will
3772 * try several rates (based on the fallback table) we should
ba3b9e5e 3773 * initialize max_report_rates to the maximum number of rates
3f2bee24
HS		 3774 * we are going to try. Otherwise mac80211 will truncate our
3775 * reported tx rates and the rc algortihm will end up with
3776 * incorrect data.
3777 */
ba3b9e5e
HS		 3778 rt2x00dev->hw->max_rates = 1;
3779 rt2x00dev->hw->max_report_rates = 7;
3f2bee24
HS		 3780 rt2x00dev->hw->max_rate_tries = 1;
3781
38c8a566 3782 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4da2933f
BZ		 3783
3784 /*
3785 * Initialize hw_mode information.
3786 */
3787 spec->supported_bands = SUPPORT_BAND_2GHZ;
3788 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
3789
5122d898 3790 if (rt2x00_rf(rt2x00dev, RF2820) ||
55f9321a 3791 rt2x00_rf(rt2x00dev, RF2720)) {
4da2933f
BZ		 3792 spec->num_channels = 14;
3793 spec->channels = rf_vals;
55f9321a
ID		 3794 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
3795 rt2x00_rf(rt2x00dev, RF2750)) {
4da2933f
BZ		 3796 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3797 spec->num_channels = ARRAY_SIZE(rf_vals);
3798 spec->channels = rf_vals;
5122d898
GW		 3799 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
3800 rt2x00_rf(rt2x00dev, RF2020) ||
3801 rt2x00_rf(rt2x00dev, RF3021) ||
f93bc9b3 3802 rt2x00_rf(rt2x00dev, RF3022) ||
60687ba7
RST		 3803 rt2x00_rf(rt2x00dev, RF3320) ||
3804 rt2x00_rf(rt2x00dev, RF5390)) {
55f9321a
ID		 3805 spec->num_channels = 14;
3806 spec->channels = rf_vals_3x;
3807 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
3808 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3809 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
3810 spec->channels = rf_vals_3x;
4da2933f
BZ		 3811 }
3812
3813 /*
3814 * Initialize HT information.
3815 */
5122d898 3816 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 3817 spec->ht.ht_supported = true;
3818 else
3819 spec->ht.ht_supported = false;
3820
4da2933f 3821 spec->ht.cap =
06443e46 3822 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 3823 IEEE80211_HT_CAP_GRN_FLD |
3824 IEEE80211_HT_CAP_SGI_20 |
aa674631 3825 IEEE80211_HT_CAP_SGI_40;
22cabaa6 3826
38c8a566 3827 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
22cabaa6
HS		 3828 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
3829
aa674631 3830 spec->ht.cap |=
38c8a566 3831 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
aa674631
ID		 3832 IEEE80211_HT_CAP_RX_STBC_SHIFT;
3833
4da2933f
BZ		 3834 spec->ht.ampdu_factor = 3;
3835 spec->ht.ampdu_density = 4;
3836 spec->ht.mcs.tx_params =
3837 IEEE80211_HT_MCS_TX_DEFINED |
3838 IEEE80211_HT_MCS_TX_RX_DIFF |
38c8a566 3839 ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
4da2933f
BZ		 3840 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
3841
38c8a566 3842 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
4da2933f
BZ		 3843 case 3:
3844 spec->ht.mcs.rx_mask[2] = 0xff;
3845 case 2:
3846 spec->ht.mcs.rx_mask[1] = 0xff;
3847 case 1:
3848 spec->ht.mcs.rx_mask[0] = 0xff;
3849 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
3850 break;
3851 }
3852
3853 /*
3854 * Create channel information array
3855 */
baeb2ffa 3856 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4da2933f
BZ		 3857 if (!info)
3858 return -ENOMEM;
3859
3860 spec->channels_info = info;
3861
8d1331b3
ID		 3862 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
3863 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4da2933f
BZ		 3864
3865 for (i = 0; i < 14; i++) {
e90c54b2
RJH		 3866 info[i].default_power1 = default_power1[i];
3867 info[i].default_power2 = default_power2[i];
4da2933f
BZ		 3868 }
3869
3870 if (spec->num_channels > 14) {
8d1331b3
ID		 3871 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
3872 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4da2933f
BZ		 3873
3874 for (i = 14; i < spec->num_channels; i++) {
e90c54b2
RJH		 3875 info[i].default_power1 = default_power1[i];
3876 info[i].default_power2 = default_power2[i];
4da2933f
BZ		 3877 }
3878 }
3879
3880 return 0;
3881}
3882EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
3883
2ce33995
BZ		 3884/*
3885 * IEEE80211 stack callback functions.
3886 */
e783619e
HS		 3887void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
3888 u16 *iv16)
2ce33995
BZ		 3889{
3890 struct rt2x00_dev *rt2x00dev = hw->priv;
3891 struct mac_iveiv_entry iveiv_entry;
3892 u32 offset;
3893
3894 offset = MAC_IVEIV_ENTRY(hw_key_idx);
3895 rt2800_register_multiread(rt2x00dev, offset,
3896 &iveiv_entry, sizeof(iveiv_entry));
3897
855da5e0
JL		 3898 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
3899 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995 3900}
e783619e 3901EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
2ce33995 3902
e783619e 3903int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2ce33995
BZ		 3904{
3905 struct rt2x00_dev *rt2x00dev = hw->priv;
3906 u32 reg;
3907 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
3908
3909 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3910 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
3911 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3912
3913 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3914 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
3915 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3916
3917 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3918 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
3919 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3920
3921 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3922 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
3923 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3924
3925 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3926 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
3927 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3928
3929 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3930 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
3931 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3932
3933 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3934 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
3935 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3936
3937 return 0;
3938}
e783619e 3939EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2ce33995 3940
e783619e
HS		 3941int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
3942 const struct ieee80211_tx_queue_params *params)
2ce33995
BZ		 3943{
3944 struct rt2x00_dev *rt2x00dev = hw->priv;
3945 struct data_queue *queue;
3946 struct rt2x00_field32 field;
3947 int retval;
3948 u32 reg;
3949 u32 offset;
3950
3951 /*
3952 * First pass the configuration through rt2x00lib, that will
3953 * update the queue settings and validate the input. After that
3954 * we are free to update the registers based on the value
3955 * in the queue parameter.
3956 */
3957 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
3958 if (retval)
3959 return retval;
3960
3961 /*
3962 * We only need to perform additional register initialization
3963 * for WMM queues/
3964 */
3965 if (queue_idx >= 4)
3966 return 0;
3967
3968 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
3969
3970 /* Update WMM TXOP register */
3971 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
3972 field.bit_offset = (queue_idx & 1) * 16;
3973 field.bit_mask = 0xffff << field.bit_offset;
3974
3975 rt2800_register_read(rt2x00dev, offset, &reg);
3976 rt2x00_set_field32(&reg, field, queue->txop);
3977 rt2800_register_write(rt2x00dev, offset, reg);
3978
3979 /* Update WMM registers */
3980 field.bit_offset = queue_idx * 4;
3981 field.bit_mask = 0xf << field.bit_offset;
3982
3983 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
3984 rt2x00_set_field32(&reg, field, queue->aifs);
3985 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
3986
3987 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
3988 rt2x00_set_field32(&reg, field, queue->cw_min);
3989 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
3990
3991 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
3992 rt2x00_set_field32(&reg, field, queue->cw_max);
3993 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
3994
3995 /* Update EDCA registers */
3996 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
3997
3998 rt2800_register_read(rt2x00dev, offset, &reg);
3999 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
4000 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
4001 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
4002 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
4003 rt2800_register_write(rt2x00dev, offset, reg);
4004
4005 return 0;
4006}
e783619e 4007EXPORT_SYMBOL_GPL(rt2800_conf_tx);
2ce33995 4008
e783619e 4009u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2ce33995
BZ		 4010{
4011 struct rt2x00_dev *rt2x00dev = hw->priv;
4012 u64 tsf;
4013 u32 reg;
4014
4015 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
4016 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
4017 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
4018 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
4019
4020 return tsf;
4021}
e783619e 4022EXPORT_SYMBOL_GPL(rt2800_get_tsf);
2ce33995 4023
e783619e
HS		 4024int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4025 enum ieee80211_ampdu_mlme_action action,
0b01f030
JB		 4026 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
4027 u8 buf_size)
1df90809 4028{
1df90809
HS		 4029 int ret = 0;
4030
4031 switch (action) {
4032 case IEEE80211_AMPDU_RX_START:
4033 case IEEE80211_AMPDU_RX_STOP:
58ed826e
HS		 4034 /*
4035 * The hw itself takes care of setting up BlockAck mechanisms.
4036 * So, we only have to allow mac80211 to nagotiate a BlockAck
4037 * agreement. Once that is done, the hw will BlockAck incoming
4038 * AMPDUs without further setup.
4039 */
1df90809
HS		 4040 break;
4041 case IEEE80211_AMPDU_TX_START:
4042 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4043 break;
4044 case IEEE80211_AMPDU_TX_STOP:
4045 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4046 break;
4047 case IEEE80211_AMPDU_TX_OPERATIONAL:
4048 break;
4049 default:
4e9e58c6 4050 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
1df90809
HS		 4051 }
4052
4053 return ret;
4054}
e783619e 4055EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
a5ea2f02 4056
977206d7
HS		 4057int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
4058 struct survey_info *survey)
4059{
4060 struct rt2x00_dev *rt2x00dev = hw->priv;
4061 struct ieee80211_conf *conf = &hw->conf;
4062 u32 idle, busy, busy_ext;
4063
4064 if (idx != 0)
4065 return -ENOENT;
4066
4067 survey->channel = conf->channel;
4068
4069 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
4070 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
4071 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
4072
4073 if (idle || busy) {
4074 survey->filled = SURVEY_INFO_CHANNEL_TIME |
4075 SURVEY_INFO_CHANNEL_TIME_BUSY |
4076 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
4077
4078 survey->channel_time = (idle + busy) / 1000;
4079 survey->channel_time_busy = busy / 1000;
4080 survey->channel_time_ext_busy = busy_ext / 1000;
4081 }
4082
4083 return 0;
4084
4085}
4086EXPORT_SYMBOL_GPL(rt2800_get_survey);
4087
a5ea2f02
ID		 4088MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
4089MODULE_VERSION(DRV_VERSION);
4090MODULE_DESCRIPTION("Ralink RT2800 library");
4091MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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