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rt2x00: rt2800lib: add default_power3 field for three-chain devices
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
CommitLineData
89297425 1/*
96481b20 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
a5ea2f02 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 6
9c9a0d14 7 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32/*
33 Module: rt2800lib
34 Abstract: rt2800 generic device routines.
35 */
36
f31c9a8c 37#include <linux/crc-ccitt.h>
89297425
BZ		 38#include <linux/kernel.h>
39#include <linux/module.h>
5a0e3ad6 40#include <linux/slab.h>
89297425
BZ		 41
42#include "rt2x00.h"
43#include "rt2800lib.h"
44#include "rt2800.h"
45
89297425
BZ		 46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60#define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64#define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66#define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
baff8006
HS		 70static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71{
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
75 return false;
76
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
81 return true;
82
ec9c4989 83 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
baff8006
HS		 84 return false;
85}
86
fcf51541
BZ		 87static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
89297425
BZ		 89{
90 u32 reg;
91
92 mutex_lock(&rt2x00dev->csr_mutex);
93
94 /*
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
97 */
98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
efc7d36f 104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 105
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107 }
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110}
89297425 111
fcf51541
BZ		 112static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
89297425
BZ		 114{
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
126 */
127 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 reg = 0;
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
efc7d36f 132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142}
89297425 143
fcf51541
BZ		 144static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
89297425
BZ		 146{
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166}
89297425 167
fcf51541
BZ		 168static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
89297425
BZ		 170{
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197}
89297425 198
fcf51541
BZ		 199static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
89297425
BZ		 201{
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222}
89297425 223
379448fe
GJ		 224static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
225 [EEPROM_CHIP_ID] = 0x0000,
226 [EEPROM_VERSION] = 0x0001,
227 [EEPROM_MAC_ADDR_0] = 0x0002,
228 [EEPROM_MAC_ADDR_1] = 0x0003,
229 [EEPROM_MAC_ADDR_2] = 0x0004,
230 [EEPROM_NIC_CONF0] = 0x001a,
231 [EEPROM_NIC_CONF1] = 0x001b,
232 [EEPROM_FREQ] = 0x001d,
233 [EEPROM_LED_AG_CONF] = 0x001e,
234 [EEPROM_LED_ACT_CONF] = 0x001f,
235 [EEPROM_LED_POLARITY] = 0x0020,
236 [EEPROM_NIC_CONF2] = 0x0021,
237 [EEPROM_LNA] = 0x0022,
238 [EEPROM_RSSI_BG] = 0x0023,
239 [EEPROM_RSSI_BG2] = 0x0024,
240 [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */
241 [EEPROM_RSSI_A] = 0x0025,
242 [EEPROM_RSSI_A2] = 0x0026,
243 [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */
244 [EEPROM_EIRP_MAX_TX_POWER] = 0x0027,
245 [EEPROM_TXPOWER_DELTA] = 0x0028,
246 [EEPROM_TXPOWER_BG1] = 0x0029,
247 [EEPROM_TXPOWER_BG2] = 0x0030,
248 [EEPROM_TSSI_BOUND_BG1] = 0x0037,
249 [EEPROM_TSSI_BOUND_BG2] = 0x0038,
250 [EEPROM_TSSI_BOUND_BG3] = 0x0039,
251 [EEPROM_TSSI_BOUND_BG4] = 0x003a,
252 [EEPROM_TSSI_BOUND_BG5] = 0x003b,
253 [EEPROM_TXPOWER_A1] = 0x003c,
254 [EEPROM_TXPOWER_A2] = 0x0053,
255 [EEPROM_TSSI_BOUND_A1] = 0x006a,
256 [EEPROM_TSSI_BOUND_A2] = 0x006b,
257 [EEPROM_TSSI_BOUND_A3] = 0x006c,
258 [EEPROM_TSSI_BOUND_A4] = 0x006d,
259 [EEPROM_TSSI_BOUND_A5] = 0x006e,
260 [EEPROM_TXPOWER_BYRATE] = 0x006f,
261 [EEPROM_BBP_START] = 0x0078,
262};
263
fa31d157
GJ		 264static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
265 [EEPROM_CHIP_ID] = 0x0000,
266 [EEPROM_VERSION] = 0x0001,
267 [EEPROM_MAC_ADDR_0] = 0x0002,
268 [EEPROM_MAC_ADDR_1] = 0x0003,
269 [EEPROM_MAC_ADDR_2] = 0x0004,
270 [EEPROM_NIC_CONF0] = 0x001a,
271 [EEPROM_NIC_CONF1] = 0x001b,
272 [EEPROM_NIC_CONF2] = 0x001c,
273 [EEPROM_EIRP_MAX_TX_POWER] = 0x0020,
274 [EEPROM_FREQ] = 0x0022,
275 [EEPROM_LED_AG_CONF] = 0x0023,
276 [EEPROM_LED_ACT_CONF] = 0x0024,
277 [EEPROM_LED_POLARITY] = 0x0025,
278 [EEPROM_LNA] = 0x0026,
279 [EEPROM_EXT_LNA2] = 0x0027,
280 [EEPROM_RSSI_BG] = 0x0028,
281 [EEPROM_TXPOWER_DELTA] = 0x0028, /* Overlaps with RSSI_BG */
282 [EEPROM_RSSI_BG2] = 0x0029,
283 [EEPROM_TXMIXER_GAIN_BG] = 0x0029, /* Overlaps with RSSI_BG2 */
284 [EEPROM_RSSI_A] = 0x002a,
285 [EEPROM_RSSI_A2] = 0x002b,
286 [EEPROM_TXMIXER_GAIN_A] = 0x002b, /* Overlaps with RSSI_A2 */
287 [EEPROM_TXPOWER_BG1] = 0x0030,
288 [EEPROM_TXPOWER_BG2] = 0x0037,
289 [EEPROM_EXT_TXPOWER_BG3] = 0x003e,
290 [EEPROM_TSSI_BOUND_BG1] = 0x0045,
291 [EEPROM_TSSI_BOUND_BG2] = 0x0046,
292 [EEPROM_TSSI_BOUND_BG3] = 0x0047,
293 [EEPROM_TSSI_BOUND_BG4] = 0x0048,
294 [EEPROM_TSSI_BOUND_BG5] = 0x0049,
295 [EEPROM_TXPOWER_A1] = 0x004b,
296 [EEPROM_TXPOWER_A2] = 0x0065,
297 [EEPROM_EXT_TXPOWER_A3] = 0x007f,
298 [EEPROM_TSSI_BOUND_A1] = 0x009a,
299 [EEPROM_TSSI_BOUND_A2] = 0x009b,
300 [EEPROM_TSSI_BOUND_A3] = 0x009c,
301 [EEPROM_TSSI_BOUND_A4] = 0x009d,
302 [EEPROM_TSSI_BOUND_A5] = 0x009e,
303 [EEPROM_TXPOWER_BYRATE] = 0x00a0,
304};
305
379448fe
GJ		 306static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
307 const enum rt2800_eeprom_word word)
308{
309 const unsigned int *map;
310 unsigned int index;
311
312 if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
313 "%s: invalid EEPROM word %d\n",
314 wiphy_name(rt2x00dev->hw->wiphy), word))
315 return 0;
316
fa31d157
GJ		 317 if (rt2x00_rt(rt2x00dev, RT3593))
318 map = rt2800_eeprom_map_ext;
319 else
320 map = rt2800_eeprom_map;
321
379448fe
GJ		 322 index = map[word];
323
324 /* Index 0 is valid only for EEPROM_CHIP_ID.
325 * Otherwise it means that the offset of the
326 * given word is not initialized in the map,
327 * or that the field is not usable on the
328 * actual chipset.
329 */
330 WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
331 "%s: invalid access of EEPROM word %d\n",
332 wiphy_name(rt2x00dev->hw->wiphy), word);
333
334 return index;
335}
336
3e38d3da
GJ		 337static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
338 const enum rt2800_eeprom_word word)
339{
379448fe
GJ		 340 unsigned int index;
341
342 index = rt2800_eeprom_word_index(rt2x00dev, word);
343 return rt2x00_eeprom_addr(rt2x00dev, index);
3e38d3da
GJ		 344}
345
346static void rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
347 const enum rt2800_eeprom_word word, u16 *data)
348{
379448fe
GJ		 349 unsigned int index;
350
351 index = rt2800_eeprom_word_index(rt2x00dev, word);
352 rt2x00_eeprom_read(rt2x00dev, index, data);
3e38d3da
GJ		 353}
354
355static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
356 const enum rt2800_eeprom_word word, u16 data)
357{
379448fe
GJ		 358 unsigned int index;
359
360 index = rt2800_eeprom_word_index(rt2x00dev, word);
361 rt2x00_eeprom_write(rt2x00dev, index, data);
3e38d3da
GJ		 362}
363
022138ca
GJ		 364static void rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
365 const enum rt2800_eeprom_word array,
366 unsigned int offset,
367 u16 *data)
368{
379448fe
GJ		 369 unsigned int index;
370
371 index = rt2800_eeprom_word_index(rt2x00dev, array);
372 rt2x00_eeprom_read(rt2x00dev, index + offset, data);
022138ca
GJ		 373}
374
16ebd608
WH		 375static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
376{
377 u32 reg;
378 int i, count;
379
380 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
381 if (rt2x00_get_field32(reg, WLAN_EN))
382 return 0;
383
384 rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
385 rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
386 rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
387 rt2x00_set_field32(&reg, WLAN_EN, 1);
388 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
389
390 udelay(REGISTER_BUSY_DELAY);
391
392 count = 0;
393 do {
394 /*
395 * Check PLL_LD & XTAL_RDY.
396 */
397 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
398 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
399 if (rt2x00_get_field32(reg, PLL_LD) &&
400 rt2x00_get_field32(reg, XTAL_RDY))
401 break;
402 udelay(REGISTER_BUSY_DELAY);
403 }
404
405 if (i >= REGISTER_BUSY_COUNT) {
406
407 if (count >= 10)
408 return -EIO;
409
410 rt2800_register_write(rt2x00dev, 0x58, 0x018);
411 udelay(REGISTER_BUSY_DELAY);
412 rt2800_register_write(rt2x00dev, 0x58, 0x418);
413 udelay(REGISTER_BUSY_DELAY);
414 rt2800_register_write(rt2x00dev, 0x58, 0x618);
415 udelay(REGISTER_BUSY_DELAY);
416 count++;
417 } else {
418 count = 0;
419 }
420
421 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
422 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
423 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
424 rt2x00_set_field32(&reg, WLAN_RESET, 1);
425 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
426 udelay(10);
427 rt2x00_set_field32(&reg, WLAN_RESET, 0);
428 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
429 udelay(10);
430 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
431 } while (count != 0);
432
433 return 0;
434}
435
89297425
BZ		 436void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
437 const u8 command, const u8 token,
438 const u8 arg0, const u8 arg1)
439{
440 u32 reg;
441
ee303e54 442 /*
cea90e55 443 * SOC devices don't support MCU requests.
ee303e54 444 */
cea90e55 445 if (rt2x00_is_soc(rt2x00dev))
ee303e54 446 return;
89297425
BZ		 447
448 mutex_lock(&rt2x00dev->csr_mutex);
449
450 /*
451 * Wait until the MCU becomes available, afterwards we
452 * can safely write the new data into the register.
453 */
454 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
455 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
456 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
457 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
458 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
459 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
460
461 reg = 0;
462 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
463 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
464 }
465
466 mutex_unlock(&rt2x00dev->csr_mutex);
467}
468EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 469
5ffddc49
ID		 470int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
471{
472 unsigned int i = 0;
473 u32 reg;
474
475 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
476 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
477 if (reg && reg != ~0)
478 return 0;
479 msleep(1);
480 }
481
ec9c4989 482 rt2x00_err(rt2x00dev, "Unstable hardware\n");
5ffddc49
ID		 483 return -EBUSY;
484}
485EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
486
67a4c1e2
GW		 487int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
488{
489 unsigned int i;
490 u32 reg;
491
08e53100
HS		 492 /*
493 * Some devices are really slow to respond here. Wait a whole second
494 * before timing out.
495 */
67a4c1e2
GW		 496 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
497 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
498 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
499 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
500 return 0;
501
08e53100 502 msleep(10);
67a4c1e2
GW		 503 }
504
ec9c4989 505 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
67a4c1e2
GW		 506 return -EACCES;
507}
508EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
509
f7b395e9
JK		 510void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
511{
512 u32 reg;
513
514 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
515 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
516 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
517 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
518 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
519 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
520 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
521}
522EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
523
f31c9a8c
ID		 524static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
525{
526 u16 fw_crc;
527 u16 crc;
528
529 /*
530 * The last 2 bytes in the firmware array are the crc checksum itself,
531 * this means that we should never pass those 2 bytes to the crc
532 * algorithm.
533 */
534 fw_crc = (data[len - 2] << 8 | data[len - 1]);
535
536 /*
537 * Use the crc ccitt algorithm.
538 * This will return the same value as the legacy driver which
539 * used bit ordering reversion on the both the firmware bytes
540 * before input input as well as on the final output.
541 * Obviously using crc ccitt directly is much more efficient.
542 */
543 crc = crc_ccitt(~0, data, len - 2);
544
545 /*
546 * There is a small difference between the crc-itu-t + bitrev and
547 * the crc-ccitt crc calculation. In the latter method the 2 bytes
548 * will be swapped, use swab16 to convert the crc to the correct
549 * value.
550 */
551 crc = swab16(crc);
552
553 return fw_crc == crc;
554}
555
556int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
557 const u8 *data, const size_t len)
558{
559 size_t offset = 0;
560 size_t fw_len;
561 bool multiple;
562
563 /*
564 * PCI(e) & SOC devices require firmware with a length
565 * of 8kb. USB devices require firmware files with a length
566 * of 4kb. Certain USB chipsets however require different firmware,
567 * which Ralink only provides attached to the original firmware
568 * file. Thus for USB devices, firmware files have a length
a89534ed
WH		 569 * which is a multiple of 4kb. The firmware for rt3290 chip also
570 * have a length which is a multiple of 4kb.
f31c9a8c 571 */
a89534ed 572 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
f31c9a8c 573 fw_len = 4096;
a89534ed 574 else
f31c9a8c 575 fw_len = 8192;
f31c9a8c 576
a89534ed 577 multiple = true;
f31c9a8c
ID		 578 /*
579 * Validate the firmware length
580 */
581 if (len != fw_len && (!multiple || (len % fw_len) != 0))
582 return FW_BAD_LENGTH;
583
584 /*
585 * Check if the chipset requires one of the upper parts
586 * of the firmware.
587 */
588 if (rt2x00_is_usb(rt2x00dev) &&
589 !rt2x00_rt(rt2x00dev, RT2860) &&
590 !rt2x00_rt(rt2x00dev, RT2872) &&
591 !rt2x00_rt(rt2x00dev, RT3070) &&
592 ((len / fw_len) == 1))
593 return FW_BAD_VERSION;
594
595 /*
596 * 8kb firmware files must be checked as if it were
597 * 2 separate firmware files.
598 */
599 while (offset < len) {
600 if (!rt2800_check_firmware_crc(data + offset, fw_len))
601 return FW_BAD_CRC;
602
603 offset += fw_len;
604 }
605
606 return FW_OK;
607}
608EXPORT_SYMBOL_GPL(rt2800_check_firmware);
609
610int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
611 const u8 *data, const size_t len)
612{
613 unsigned int i;
614 u32 reg;
16ebd608
WH		 615 int retval;
616
617 if (rt2x00_rt(rt2x00dev, RT3290)) {
618 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
619 if (retval)
620 return -EBUSY;
621 }
f31c9a8c
ID		 622
623 /*
b9eca242
ID		 624 * If driver doesn't wake up firmware here,
625 * rt2800_load_firmware will hang forever when interface is up again.
f31c9a8c 626 */
b9eca242 627 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
f31c9a8c 628
f31c9a8c
ID		 629 /*
630 * Wait for stable hardware.
631 */
5ffddc49 632 if (rt2800_wait_csr_ready(rt2x00dev))
f31c9a8c 633 return -EBUSY;
f31c9a8c 634
adde5882 635 if (rt2x00_is_pci(rt2x00dev)) {
a89534ed
WH		 636 if (rt2x00_rt(rt2x00dev, RT3290) ||
637 rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884
JL		 638 rt2x00_rt(rt2x00dev, RT5390) ||
639 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 640 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
641 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
642 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
643 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
644 }
f31c9a8c 645 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
adde5882 646 }
f31c9a8c 647
b7e1d225
JK		 648 rt2800_disable_wpdma(rt2x00dev);
649
f31c9a8c
ID		 650 /*
651 * Write firmware to the device.
652 */
653 rt2800_drv_write_firmware(rt2x00dev, data, len);
654
655 /*
656 * Wait for device to stabilize.
657 */
658 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
659 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
660 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
661 break;
662 msleep(1);
663 }
664
665 if (i == REGISTER_BUSY_COUNT) {
ec9c4989 666 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
f31c9a8c
ID		 667 return -EBUSY;
668 }
669
4ed1dd2a
SG		 670 /*
671 * Disable DMA, will be reenabled later when enabling
672 * the radio.
673 */
f7b395e9 674 rt2800_disable_wpdma(rt2x00dev);
4ed1dd2a 675
f31c9a8c
ID		 676 /*
677 * Initialize firmware.
678 */
679 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
680 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
8756130b 681 if (rt2x00_is_usb(rt2x00dev)) {
0c17cf96 682 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
8756130b
SG		 683 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
684 }
f31c9a8c
ID		 685 msleep(1);
686
687 return 0;
688}
689EXPORT_SYMBOL_GPL(rt2800_load_firmware);
690
0c5879bc
ID		 691void rt2800_write_tx_data(struct queue_entry *entry,
692 struct txentry_desc *txdesc)
59679b91 693{
0c5879bc 694 __le32 *txwi = rt2800_drv_get_txwi(entry);
59679b91 695 u32 word;
557985ae 696 int i;
59679b91
GW		 697
698 /*
699 * Initialize TX Info descriptor
700 */
701 rt2x00_desc_read(txwi, 0, &word);
702 rt2x00_set_field32(&word, TXWI_W0_FRAG,
703 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
84804cdc
ID		 704 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
705 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
59679b91
GW		 706 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
707 rt2x00_set_field32(&word, TXWI_W0_TS,
708 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
709 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
710 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
26a1d07f
HS		 711 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
712 txdesc->u.ht.mpdu_density);
713 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
714 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
59679b91
GW		 715 rt2x00_set_field32(&word, TXWI_W0_BW,
716 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
717 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
718 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
26a1d07f 719 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
59679b91
GW		 720 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
721 rt2x00_desc_write(txwi, 0, word);
722
723 rt2x00_desc_read(txwi, 1, &word);
724 rt2x00_set_field32(&word, TXWI_W1_ACK,
725 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
726 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
727 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
26a1d07f 728 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
59679b91
GW		 729 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
730 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
a2b1328a 731 txdesc->key_idx : txdesc->u.ht.wcid);
59679b91
GW		 732 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
733 txdesc->length);
2b23cdaa 734 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
bc8a979e 735 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
59679b91
GW		 736 rt2x00_desc_write(txwi, 1, word);
737
738 /*
557985ae
SG		 739 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
740 * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
59679b91
GW		 741 * When TXD_W3_WIV is set to 1 it will use the IV data
742 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
743 * crypto entry in the registers should be used to encrypt the frame.
557985ae
SG		 744 *
745 * Nulify all remaining words as well, we don't know how to program them.
59679b91 746 */
557985ae
SG		 747 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
748 _rt2x00_desc_write(txwi, i, 0);
59679b91 749}
0c5879bc 750EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
59679b91 751
ff6133be 752static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
2de64dd2 753{
7fc41755
LT		 754 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
755 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
756 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
74861922
ID		 757 u16 eeprom;
758 u8 offset0;
759 u8 offset1;
760 u8 offset2;
761
e5ef5bad 762 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
3e38d3da 763 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
74861922
ID		 764 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
765 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
3e38d3da 766 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
74861922
ID		 767 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
768 } else {
3e38d3da 769 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
74861922
ID		 770 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
771 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
3e38d3da 772 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
74861922
ID		 773 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
774 }
775
776 /*
777 * Convert the value from the descriptor into the RSSI value
778 * If the value in the descriptor is 0, it is considered invalid
779 * and the default (extremely low) rssi value is assumed
780 */
781 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
782 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
783 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
784
785 /*
786 * mac80211 only accepts a single RSSI value. Calculating the
787 * average doesn't deliver a fair answer either since -60:-60 would
788 * be considered equally good as -50:-70 while the second is the one
789 * which gives less energy...
790 */
791 rssi0 = max(rssi0, rssi1);
7fc41755 792 return (int)max(rssi0, rssi2);
74861922
ID		 793}
794
795void rt2800_process_rxwi(struct queue_entry *entry,
796 struct rxdone_entry_desc *rxdesc)
797{
798 __le32 *rxwi = (__le32 *) entry->skb->data;
2de64dd2
GW		 799 u32 word;
800
801 rt2x00_desc_read(rxwi, 0, &word);
802
803 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
804 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
805
806 rt2x00_desc_read(rxwi, 1, &word);
807
808 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
809 rxdesc->flags |= RX_FLAG_SHORT_GI;
810
811 if (rt2x00_get_field32(word, RXWI_W1_BW))
812 rxdesc->flags |= RX_FLAG_40MHZ;
813
814 /*
815 * Detect RX rate, always use MCS as signal type.
816 */
817 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
818 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
819 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
820
821 /*
822 * Mask of 0x8 bit to remove the short preamble flag.
823 */
824 if (rxdesc->rate_mode == RATE_MODE_CCK)
825 rxdesc->signal &= ~0x8;
826
827 rt2x00_desc_read(rxwi, 2, &word);
828
74861922
ID		 829 /*
830 * Convert descriptor AGC value to RSSI value.
831 */
832 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
f0bda571
SG		 833 /*
834 * Remove RXWI descriptor from start of the buffer.
835 */
836 skb_pull(entry->skb, entry->queue->winfo_size);
2de64dd2
GW		 837}
838EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
839
31937c42 840void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
14433331
HS		 841{
842 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b34793ee 843 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
14433331
HS		 844 struct txdone_entry_desc txdesc;
845 u32 word;
846 u16 mcs, real_mcs;
b34793ee 847 int aggr, ampdu;
14433331
HS		 848
849 /*
850 * Obtain the status about this packet.
851 */
852 txdesc.flags = 0;
14433331 853 rt2x00_desc_read(txwi, 0, &word);
b34793ee 854
14433331 855 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
b34793ee
HS		 856 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
857
14433331 858 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
b34793ee
HS		 859 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
860
861 /*
862 * If a frame was meant to be sent as a single non-aggregated MPDU
863 * but ended up in an aggregate the used tx rate doesn't correlate
864 * with the one specified in the TXWI as the whole aggregate is sent
865 * with the same rate.
866 *
867 * For example: two frames are sent to rt2x00, the first one sets
868 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
869 * and requests MCS15. If the hw aggregates both frames into one
870 * AMDPU the tx status for both frames will contain MCS7 although
871 * the frame was sent successfully.
872 *
873 * Hence, replace the requested rate with the real tx rate to not
874 * confuse the rate control algortihm by providing clearly wrong
875 * data.
876 */
5356d963 877 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
b34793ee
HS		 878 skbdesc->tx_rate_idx = real_mcs;
879 mcs = real_mcs;
880 }
14433331 881
f16d2db7
HS		 882 if (aggr == 1 || ampdu == 1)
883 __set_bit(TXDONE_AMPDU, &txdesc.flags);
884
14433331
HS		 885 /*
886 * Ralink has a retry mechanism using a global fallback
887 * table. We setup this fallback table to try the immediate
888 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
889 * always contains the MCS used for the last transmission, be
890 * it successful or not.
891 */
892 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
893 /*
894 * Transmission succeeded. The number of retries is
895 * mcs - real_mcs
896 */
897 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
898 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
899 } else {
900 /*
901 * Transmission failed. The number of retries is
902 * always 7 in this case (for a total number of 8
903 * frames sent).
904 */
905 __set_bit(TXDONE_FAILURE, &txdesc.flags);
906 txdesc.retry = rt2x00dev->long_retry;
907 }
908
909 /*
910 * the frame was retried at least once
911 * -> hw used fallback rates
912 */
913 if (txdesc.retry)
914 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
915
916 rt2x00lib_txdone(entry, &txdesc);
917}
918EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
919
f0194b2d
GW		 920void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
921{
922 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
923 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
924 unsigned int beacon_base;
739fd940 925 unsigned int padding_len;
d76dfc61 926 u32 orig_reg, reg;
f0bda571 927 const int txwi_desc_size = entry->queue->winfo_size;
f0194b2d
GW		 928
929 /*
930 * Disable beaconing while we are reloading the beacon data,
931 * otherwise we might be sending out invalid data.
932 */
933 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
d76dfc61 934 orig_reg = reg;
f0194b2d
GW		 935 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
936 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
937
938 /*
939 * Add space for the TXWI in front of the skb.
940 */
f0bda571 941 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
f0194b2d
GW		 942
943 /*
944 * Register descriptor details in skb frame descriptor.
945 */
946 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
947 skbdesc->desc = entry->skb->data;
f0bda571 948 skbdesc->desc_len = txwi_desc_size;
f0194b2d
GW		 949
950 /*
951 * Add the TXWI for the beacon to the skb.
952 */
0c5879bc 953 rt2800_write_tx_data(entry, txdesc);
f0194b2d
GW		 954
955 /*
956 * Dump beacon to userspace through debugfs.
957 */
958 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
959
960 /*
739fd940 961 * Write entire beacon with TXWI and padding to register.
f0194b2d 962 */
739fd940 963 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
d76dfc61 964 if (padding_len && skb_pad(entry->skb, padding_len)) {
ec9c4989 965 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
d76dfc61
SF		 966 /* skb freed by skb_pad() on failure */
967 entry->skb = NULL;
968 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
969 return;
970 }
971
f0194b2d 972 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
739fd940
WK		 973 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
974 entry->skb->len + padding_len);
f0194b2d
GW		 975
976 /*
977 * Enable beaconing again.
978 */
f0194b2d
GW		 979 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
980 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
981
982 /*
983 * Clean up beacon skb.
984 */
985 dev_kfree_skb_any(entry->skb);
986 entry->skb = NULL;
987}
50e888ea 988EXPORT_SYMBOL_GPL(rt2800_write_beacon);
f0194b2d 989
69cf36a4
HS		 990static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
991 unsigned int beacon_base)
fdb87251
HS		 992{
993 int i;
0879f875 994 const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
fdb87251
HS		 995
996 /*
997 * For the Beacon base registers we only need to clear
998 * the whole TXWI which (when set to 0) will invalidate
999 * the entire beacon.
1000 */
f0bda571 1001 for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
fdb87251
HS		 1002 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1003}
1004
69cf36a4
HS		 1005void rt2800_clear_beacon(struct queue_entry *entry)
1006{
1007 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1008 u32 reg;
1009
1010 /*
1011 * Disable beaconing while we are reloading the beacon data,
1012 * otherwise we might be sending out invalid data.
1013 */
1014 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1015 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1016 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1017
1018 /*
1019 * Clear beacon.
1020 */
1021 rt2800_clear_beacon_register(rt2x00dev,
1022 HW_BEACON_OFFSET(entry->entry_idx));
1023
1024 /*
1025 * Enabled beaconing again.
1026 */
1027 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
1028 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1029}
1030EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
1031
f4450616
BZ		 1032#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1033const struct rt2x00debug rt2800_rt2x00debug = {
1034 .owner = THIS_MODULE,
1035 .csr = {
1036 .read = rt2800_register_read,
1037 .write = rt2800_register_write,
1038 .flags = RT2X00DEBUGFS_OFFSET,
1039 .word_base = CSR_REG_BASE,
1040 .word_size = sizeof(u32),
1041 .word_count = CSR_REG_SIZE / sizeof(u32),
1042 },
1043 .eeprom = {
3e38d3da
GJ		 1044 /* NOTE: The local EEPROM access functions can't
1045 * be used here, use the generic versions instead.
1046 */
f4450616
BZ		 1047 .read = rt2x00_eeprom_read,
1048 .write = rt2x00_eeprom_write,
1049 .word_base = EEPROM_BASE,
1050 .word_size = sizeof(u16),
1051 .word_count = EEPROM_SIZE / sizeof(u16),
1052 },
1053 .bbp = {
1054 .read = rt2800_bbp_read,
1055 .write = rt2800_bbp_write,
1056 .word_base = BBP_BASE,
1057 .word_size = sizeof(u8),
1058 .word_count = BBP_SIZE / sizeof(u8),
1059 },
1060 .rf = {
1061 .read = rt2x00_rf_read,
1062 .write = rt2800_rf_write,
1063 .word_base = RF_BASE,
1064 .word_size = sizeof(u32),
1065 .word_count = RF_SIZE / sizeof(u32),
1066 },
f2bd7f16
AA		 1067 .rfcsr = {
1068 .read = rt2800_rfcsr_read,
1069 .write = rt2800_rfcsr_write,
1070 .word_base = RFCSR_BASE,
1071 .word_size = sizeof(u8),
1072 .word_count = RFCSR_SIZE / sizeof(u8),
1073 },
f4450616
BZ		 1074};
1075EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
1076#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1077
1078int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1079{
1080 u32 reg;
1081
a89534ed
WH		 1082 if (rt2x00_rt(rt2x00dev, RT3290)) {
1083 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
1084 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
1085 } else {
99bdf51a
GW		 1086 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1087 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
a89534ed 1088 }
f4450616
BZ		 1089}
1090EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
1091
1092#ifdef CONFIG_RT2X00_LIB_LEDS
1093static void rt2800_brightness_set(struct led_classdev *led_cdev,
1094 enum led_brightness brightness)
1095{
1096 struct rt2x00_led *led =
1097 container_of(led_cdev, struct rt2x00_led, led_dev);
1098 unsigned int enabled = brightness != LED_OFF;
1099 unsigned int bg_mode =
1100 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
1101 unsigned int polarity =
1102 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1103 EEPROM_FREQ_LED_POLARITY);
1104 unsigned int ledmode =
1105 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1106 EEPROM_FREQ_LED_MODE);
44704e5d 1107 u32 reg;
f4450616 1108
44704e5d
LE		 1109 /* Check for SoC (SOC devices don't support MCU requests) */
1110 if (rt2x00_is_soc(led->rt2x00dev)) {
1111 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
1112
1113 /* Set LED Polarity */
1114 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
1115
1116 /* Set LED Mode */
1117 if (led->type == LED_TYPE_RADIO) {
1118 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
1119 enabled ? 3 : 0);
1120 } else if (led->type == LED_TYPE_ASSOC) {
1121 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
1122 enabled ? 3 : 0);
1123 } else if (led->type == LED_TYPE_QUALITY) {
1124 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
1125 enabled ? 3 : 0);
1126 }
1127
1128 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1129
1130 } else {
1131 if (led->type == LED_TYPE_RADIO) {
1132 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1133 enabled ? 0x20 : 0);
1134 } else if (led->type == LED_TYPE_ASSOC) {
1135 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1136 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
1137 } else if (led->type == LED_TYPE_QUALITY) {
1138 /*
1139 * The brightness is divided into 6 levels (0 - 5),
1140 * The specs tell us the following levels:
1141 * 0, 1 ,3, 7, 15, 31
1142 * to determine the level in a simple way we can simply
1143 * work with bitshifting:
1144 * (1 << level) - 1
1145 */
1146 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1147 (1 << brightness / (LED_FULL / 6)) - 1,
1148 polarity);
1149 }
f4450616
BZ		 1150 }
1151}
1152
b3579d6a 1153static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 1154 struct rt2x00_led *led, enum led_type type)
1155{
1156 led->rt2x00dev = rt2x00dev;
1157 led->type = type;
1158 led->led_dev.brightness_set = rt2800_brightness_set;
f4450616
BZ		 1159 led->flags = LED_INITIALIZED;
1160}
f4450616
BZ		 1161#endif /* CONFIG_RT2X00_LIB_LEDS */
1162
1163/*
1164 * Configuration handlers.
1165 */
a2b1328a
HS		 1166static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1167 const u8 *address,
1168 int wcid)
f4450616
BZ		 1169{
1170 struct mac_wcid_entry wcid_entry;
a2b1328a
HS		 1171 u32 offset;
1172
1173 offset = MAC_WCID_ENTRY(wcid);
1174
1175 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1176 if (address)
1177 memcpy(wcid_entry.mac, address, ETH_ALEN);
1178
1179 rt2800_register_multiwrite(rt2x00dev, offset,
1180 &wcid_entry, sizeof(wcid_entry));
1181}
1182
1183static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1184{
1185 u32 offset;
1186 offset = MAC_WCID_ATTR_ENTRY(wcid);
1187 rt2800_register_write(rt2x00dev, offset, 0);
1188}
1189
1190static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1191 int wcid, u32 bssidx)
1192{
1193 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1194 u32 reg;
1195
1196 /*
1197 * The BSS Idx numbers is split in a main value of 3 bits,
1198 * and a extended field for adding one additional bit to the value.
1199 */
1200 rt2800_register_read(rt2x00dev, offset, &reg);
1201 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1202 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1203 (bssidx & 0x8) >> 3);
1204 rt2800_register_write(rt2x00dev, offset, reg);
1205}
1206
1207static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1208 struct rt2x00lib_crypto *crypto,
1209 struct ieee80211_key_conf *key)
1210{
f4450616
BZ		 1211 struct mac_iveiv_entry iveiv_entry;
1212 u32 offset;
1213 u32 reg;
1214
1215 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1216
e4a0ab34
ID		 1217 if (crypto->cmd == SET_KEY) {
1218 rt2800_register_read(rt2x00dev, offset, &reg);
1219 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1220 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1221 /*
1222 * Both the cipher as the BSS Idx numbers are split in a main
1223 * value of 3 bits, and a extended field for adding one additional
1224 * bit to the value.
1225 */
1226 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1227 (crypto->cipher & 0x7));
1228 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1229 (crypto->cipher & 0x8) >> 3);
e4a0ab34
ID		 1230 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1231 rt2800_register_write(rt2x00dev, offset, reg);
1232 } else {
a2b1328a
HS		 1233 /* Delete the cipher without touching the bssidx */
1234 rt2800_register_read(rt2x00dev, offset, &reg);
1235 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1236 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1237 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1238 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1239 rt2800_register_write(rt2x00dev, offset, reg);
e4a0ab34 1240 }
f4450616
BZ		 1241
1242 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1243
1244 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1245 if ((crypto->cipher == CIPHER_TKIP) ||
1246 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1247 (crypto->cipher == CIPHER_AES))
1248 iveiv_entry.iv[3] |= 0x20;
1249 iveiv_entry.iv[3] |= key->keyidx << 6;
1250 rt2800_register_multiwrite(rt2x00dev, offset,
1251 &iveiv_entry, sizeof(iveiv_entry));
f4450616
BZ		 1252}
1253
1254int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1255 struct rt2x00lib_crypto *crypto,
1256 struct ieee80211_key_conf *key)
1257{
1258 struct hw_key_entry key_entry;
1259 struct rt2x00_field32 field;
1260 u32 offset;
1261 u32 reg;
1262
1263 if (crypto->cmd == SET_KEY) {
1264 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1265
1266 memcpy(key_entry.key, crypto->key,
1267 sizeof(key_entry.key));
1268 memcpy(key_entry.tx_mic, crypto->tx_mic,
1269 sizeof(key_entry.tx_mic));
1270 memcpy(key_entry.rx_mic, crypto->rx_mic,
1271 sizeof(key_entry.rx_mic));
1272
1273 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1274 rt2800_register_multiwrite(rt2x00dev, offset,
1275 &key_entry, sizeof(key_entry));
1276 }
1277
1278 /*
1279 * The cipher types are stored over multiple registers
1280 * starting with SHARED_KEY_MODE_BASE each word will have
1281 * 32 bits and contains the cipher types for 2 bssidx each.
1282 * Using the correct defines correctly will cause overhead,
1283 * so just calculate the correct offset.
1284 */
1285 field.bit_offset = 4 * (key->hw_key_idx % 8);
1286 field.bit_mask = 0x7 << field.bit_offset;
1287
1288 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1289
1290 rt2800_register_read(rt2x00dev, offset, &reg);
1291 rt2x00_set_field32(&reg, field,
1292 (crypto->cmd == SET_KEY) * crypto->cipher);
1293 rt2800_register_write(rt2x00dev, offset, reg);
1294
1295 /*
1296 * Update WCID information
1297 */
a2b1328a
HS		 1298 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1299 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1300 crypto->bssidx);
1301 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1302
1303 return 0;
1304}
1305EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1306
a2b1328a 1307static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1ed3811c 1308{
a2b1328a 1309 struct mac_wcid_entry wcid_entry;
1ed3811c 1310 int idx;
a2b1328a 1311 u32 offset;
1ed3811c
HS		 1312
1313 /*
a2b1328a
HS		 1314 * Search for the first free WCID entry and return the corresponding
1315 * index.
1ed3811c
HS		 1316 *
1317 * Make sure the WCID starts _after_ the last possible shared key
1318 * entry (>32).
1319 *
1320 * Since parts of the pairwise key table might be shared with
1321 * the beacon frame buffers 6 & 7 we should only write into the
1322 * first 222 entries.
1323 */
1324 for (idx = 33; idx <= 222; idx++) {
a2b1328a
HS		 1325 offset = MAC_WCID_ENTRY(idx);
1326 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1327 sizeof(wcid_entry));
1328 if (is_broadcast_ether_addr(wcid_entry.mac))
1ed3811c
HS		 1329 return idx;
1330 }
a2b1328a
HS		 1331
1332 /*
1333 * Use -1 to indicate that we don't have any more space in the WCID
1334 * table.
1335 */
1ed3811c
HS		 1336 return -1;
1337}
1338
f4450616
BZ		 1339int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1340 struct rt2x00lib_crypto *crypto,
1341 struct ieee80211_key_conf *key)
1342{
1343 struct hw_key_entry key_entry;
1344 u32 offset;
1345
1346 if (crypto->cmd == SET_KEY) {
a2b1328a
HS		 1347 /*
1348 * Allow key configuration only for STAs that are
1349 * known by the hw.
1350 */
1351 if (crypto->wcid < 0)
f4450616 1352 return -ENOSPC;
a2b1328a 1353 key->hw_key_idx = crypto->wcid;
f4450616
BZ		 1354
1355 memcpy(key_entry.key, crypto->key,
1356 sizeof(key_entry.key));
1357 memcpy(key_entry.tx_mic, crypto->tx_mic,
1358 sizeof(key_entry.tx_mic));
1359 memcpy(key_entry.rx_mic, crypto->rx_mic,
1360 sizeof(key_entry.rx_mic));
1361
1362 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1363 rt2800_register_multiwrite(rt2x00dev, offset,
1364 &key_entry, sizeof(key_entry));
1365 }
1366
1367 /*
1368 * Update WCID information
1369 */
a2b1328a 1370 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1371
1372 return 0;
1373}
1374EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1375
a2b1328a
HS		 1376int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1377 struct ieee80211_sta *sta)
1378{
1379 int wcid;
1380 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1381
1382 /*
1383 * Find next free WCID.
1384 */
1385 wcid = rt2800_find_wcid(rt2x00dev);
1386
1387 /*
1388 * Store selected wcid even if it is invalid so that we can
1389 * later decide if the STA is uploaded into the hw.
1390 */
1391 sta_priv->wcid = wcid;
1392
1393 /*
1394 * No space left in the device, however, we can still communicate
1395 * with the STA -> No error.
1396 */
1397 if (wcid < 0)
1398 return 0;
1399
1400 /*
1401 * Clean up WCID attributes and write STA address to the device.
1402 */
1403 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1404 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1405 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1406 rt2x00lib_get_bssidx(rt2x00dev, vif));
1407 return 0;
1408}
1409EXPORT_SYMBOL_GPL(rt2800_sta_add);
1410
1411int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1412{
1413 /*
1414 * Remove WCID entry, no need to clean the attributes as they will
1415 * get renewed when the WCID is reused.
1416 */
1417 rt2800_config_wcid(rt2x00dev, NULL, wcid);
1418
1419 return 0;
1420}
1421EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1422
f4450616
BZ		 1423void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1424 const unsigned int filter_flags)
1425{
1426 u32 reg;
1427
1428 /*
1429 * Start configuration steps.
1430 * Note that the version error will always be dropped
1431 * and broadcast frames will always be accepted since
1432 * there is no filter for it at this time.
1433 */
1434 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1435 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1436 !(filter_flags & FIF_FCSFAIL));
1437 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1438 !(filter_flags & FIF_PLCPFAIL));
1439 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1440 !(filter_flags & FIF_PROMISC_IN_BSS));
1441 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1442 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1443 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1444 !(filter_flags & FIF_ALLMULTI));
1445 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1446 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1447 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1448 !(filter_flags & FIF_CONTROL));
1449 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1450 !(filter_flags & FIF_CONTROL));
1451 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1452 !(filter_flags & FIF_CONTROL));
1453 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1454 !(filter_flags & FIF_CONTROL));
1455 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1456 !(filter_flags & FIF_CONTROL));
1457 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1458 !(filter_flags & FIF_PSPOLL));
84e9e8eb 1459 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
48839938
HS		 1460 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1461 !(filter_flags & FIF_CONTROL));
f4450616
BZ		 1462 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1463 !(filter_flags & FIF_CONTROL));
1464 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1465}
1466EXPORT_SYMBOL_GPL(rt2800_config_filter);
1467
1468void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1469 struct rt2x00intf_conf *conf, const unsigned int flags)
1470{
f4450616 1471 u32 reg;
fa8b4b22 1472 bool update_bssid = false;
f4450616
BZ		 1473
1474 if (flags & CONFIG_UPDATE_TYPE) {
f4450616
BZ		 1475 /*
1476 * Enable synchronisation.
1477 */
1478 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
f4450616 1479 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
f4450616 1480 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
15a533c4
HS		 1481
1482 if (conf->sync == TSF_SYNC_AP_NONE) {
1483 /*
1484 * Tune beacon queue transmit parameters for AP mode
1485 */
1486 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1487 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1488 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1489 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1490 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1491 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1492 } else {
1493 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1494 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1495 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1496 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1497 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1498 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1499 }
f4450616
BZ		 1500 }
1501
1502 if (flags & CONFIG_UPDATE_MAC) {
fa8b4b22
HS		 1503 if (flags & CONFIG_UPDATE_TYPE &&
1504 conf->sync == TSF_SYNC_AP_NONE) {
1505 /*
1506 * The BSSID register has to be set to our own mac
1507 * address in AP mode.
1508 */
1509 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1510 update_bssid = true;
1511 }
1512
c600c826
ID		 1513 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1514 reg = le32_to_cpu(conf->mac[1]);
1515 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1516 conf->mac[1] = cpu_to_le32(reg);
1517 }
f4450616
BZ		 1518
1519 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1520 conf->mac, sizeof(conf->mac));
1521 }
1522
fa8b4b22 1523 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
c600c826
ID		 1524 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1525 reg = le32_to_cpu(conf->bssid[1]);
1526 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1527 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1528 conf->bssid[1] = cpu_to_le32(reg);
1529 }
f4450616
BZ		 1530
1531 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1532 conf->bssid, sizeof(conf->bssid));
1533 }
1534}
1535EXPORT_SYMBOL_GPL(rt2800_config_intf);
1536
87c1915d
HS		 1537static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1538 struct rt2x00lib_erp *erp)
1539{
1540 bool any_sta_nongf = !!(erp->ht_opmode &
1541 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1542 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1543 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1544 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1545 u32 reg;
1546
1547 /* default protection rate for HT20: OFDM 24M */
1548 mm20_rate = gf20_rate = 0x4004;
1549
1550 /* default protection rate for HT40: duplicate OFDM 24M */
1551 mm40_rate = gf40_rate = 0x4084;
1552
1553 switch (protection) {
1554 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1555 /*
1556 * All STAs in this BSS are HT20/40 but there might be
1557 * STAs not supporting greenfield mode.
1558 * => Disable protection for HT transmissions.
1559 */
1560 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1561
1562 break;
1563 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1564 /*
1565 * All STAs in this BSS are HT20 or HT20/40 but there
1566 * might be STAs not supporting greenfield mode.
1567 * => Protect all HT40 transmissions.
1568 */
1569 mm20_mode = gf20_mode = 0;
1570 mm40_mode = gf40_mode = 2;
1571
1572 break;
1573 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1574 /*
1575 * Nonmember protection:
1576 * According to 802.11n we _should_ protect all
1577 * HT transmissions (but we don't have to).
1578 *
1579 * But if cts_protection is enabled we _shall_ protect
1580 * all HT transmissions using a CCK rate.
1581 *
1582 * And if any station is non GF we _shall_ protect
1583 * GF transmissions.
1584 *
1585 * We decide to protect everything
1586 * -> fall through to mixed mode.
1587 */
1588 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1589 /*
1590 * Legacy STAs are present
1591 * => Protect all HT transmissions.
1592 */
1593 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1594
1595 /*
1596 * If erp protection is needed we have to protect HT
1597 * transmissions with CCK 11M long preamble.
1598 */
1599 if (erp->cts_protection) {
1600 /* don't duplicate RTS/CTS in CCK mode */
1601 mm20_rate = mm40_rate = 0x0003;
1602 gf20_rate = gf40_rate = 0x0003;
1603 }
1604 break;
6403eab1 1605 }
87c1915d
HS		 1606
1607 /* check for STAs not supporting greenfield mode */
1608 if (any_sta_nongf)
1609 gf20_mode = gf40_mode = 2;
1610
1611 /* Update HT protection config */
1612 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1613 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1614 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1615 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1616
1617 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1618 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1619 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1620 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1621
1622 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1623 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1624 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1625 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1626
1627 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1628 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1629 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1630 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1631}
1632
02044643
HS		 1633void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1634 u32 changed)
f4450616
BZ		 1635{
1636 u32 reg;
1637
02044643
HS		 1638 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1639 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1640 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1641 !!erp->short_preamble);
1642 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1643 !!erp->short_preamble);
1644 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1645 }
f4450616 1646
02044643
HS		 1647 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1648 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1649 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1650 erp->cts_protection ? 2 : 0);
1651 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1652 }
f4450616 1653
02044643
HS		 1654 if (changed & BSS_CHANGED_BASIC_RATES) {
1655 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1656 erp->basic_rates);
1657 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1658 }
f4450616 1659
02044643
HS		 1660 if (changed & BSS_CHANGED_ERP_SLOT) {
1661 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1662 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1663 erp->slot_time);
1664 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
f4450616 1665
02044643
HS		 1666 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1667 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1668 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1669 }
f4450616 1670
02044643
HS		 1671 if (changed & BSS_CHANGED_BEACON_INT) {
1672 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1673 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1674 erp->beacon_int * 16);
1675 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1676 }
87c1915d
HS		 1677
1678 if (changed & BSS_CHANGED_HT)
1679 rt2800_config_ht_opmode(rt2x00dev, erp);
f4450616
BZ		 1680}
1681EXPORT_SYMBOL_GPL(rt2800_config_erp);
1682
872834df
GW		 1683static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1684{
1685 u32 reg;
1686 u16 eeprom;
1687 u8 led_ctrl, led_g_mode, led_r_mode;
1688
1689 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1690 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1691 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1692 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1693 } else {
1694 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1695 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1696 }
1697 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1698
1699 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1700 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1701 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1702 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1703 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
3e38d3da 1704 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
872834df
GW		 1705 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1706 if (led_ctrl == 0 || led_ctrl > 0x40) {
1707 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1708 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1709 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1710 } else {
1711 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1712 (led_g_mode << 2) | led_r_mode, 1);
1713 }
1714 }
1715}
1716
d96aa640
RJH		 1717static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1718 enum antenna ant)
1719{
1720 u32 reg;
1721 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1722 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1723
1724 if (rt2x00_is_pci(rt2x00dev)) {
1725 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1726 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1727 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1728 } else if (rt2x00_is_usb(rt2x00dev))
1729 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1730 eesk_pin, 0);
1731
99bdf51a
GW		 1732 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1733 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1734 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1735 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
d96aa640
RJH		 1736}
1737
f4450616
BZ		 1738void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1739{
1740 u8 r1;
1741 u8 r3;
d96aa640 1742 u16 eeprom;
f4450616
BZ		 1743
1744 rt2800_bbp_read(rt2x00dev, 1, &r1);
1745 rt2800_bbp_read(rt2x00dev, 3, &r3);
1746
872834df
GW		 1747 if (rt2x00_rt(rt2x00dev, RT3572) &&
1748 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1749 rt2800_config_3572bt_ant(rt2x00dev);
1750
f4450616
BZ		 1751 /*
1752 * Configure the TX antenna.
1753 */
d96aa640 1754 switch (ant->tx_chain_num) {
f4450616
BZ		 1755 case 1:
1756 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1757 break;
1758 case 2:
872834df
GW		 1759 if (rt2x00_rt(rt2x00dev, RT3572) &&
1760 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1761 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1762 else
1763 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
f4450616
BZ		 1764 break;
1765 case 3:
4788ac1e 1766 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
f4450616
BZ		 1767 break;
1768 }
1769
1770 /*
1771 * Configure the RX antenna.
1772 */
d96aa640 1773 switch (ant->rx_chain_num) {
f4450616 1774 case 1:
d96aa640
RJH		 1775 if (rt2x00_rt(rt2x00dev, RT3070) ||
1776 rt2x00_rt(rt2x00dev, RT3090) ||
03839951 1777 rt2x00_rt(rt2x00dev, RT3352) ||
d96aa640 1778 rt2x00_rt(rt2x00dev, RT3390)) {
3e38d3da 1779 rt2800_eeprom_read(rt2x00dev,
d96aa640
RJH		 1780 EEPROM_NIC_CONF1, &eeprom);
1781 if (rt2x00_get_field16(eeprom,
1782 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1783 rt2800_set_ant_diversity(rt2x00dev,
1784 rt2x00dev->default_ant.rx);
1785 }
f4450616
BZ		 1786 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1787 break;
1788 case 2:
872834df
GW		 1789 if (rt2x00_rt(rt2x00dev, RT3572) &&
1790 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1791 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1792 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1793 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1794 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1795 } else {
1796 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1797 }
f4450616
BZ		 1798 break;
1799 case 3:
1800 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1801 break;
1802 }
1803
1804 rt2800_bbp_write(rt2x00dev, 3, r3);
1805 rt2800_bbp_write(rt2x00dev, 1, r1);
5cddb3c2
GJ		 1806
1807 if (rt2x00_rt(rt2x00dev, RT3593)) {
1808 if (ant->rx_chain_num == 1)
1809 rt2800_bbp_write(rt2x00dev, 86, 0x00);
1810 else
1811 rt2800_bbp_write(rt2x00dev, 86, 0x46);
1812 }
f4450616
BZ		 1813}
1814EXPORT_SYMBOL_GPL(rt2800_config_ant);
1815
1816static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1817 struct rt2x00lib_conf *libconf)
1818{
1819 u16 eeprom;
1820 short lna_gain;
1821
1822 if (libconf->rf.channel <= 14) {
3e38d3da 1823 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
f4450616
BZ		 1824 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1825 } else if (libconf->rf.channel <= 64) {
3e38d3da 1826 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
f4450616
BZ		 1827 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1828 } else if (libconf->rf.channel <= 128) {
f36bb0ca
GJ		 1829 if (rt2x00_rt(rt2x00dev, RT3593)) {
1830 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1831 lna_gain = rt2x00_get_field16(eeprom,
1832 EEPROM_EXT_LNA2_A1);
1833 } else {
1834 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1835 lna_gain = rt2x00_get_field16(eeprom,
1836 EEPROM_RSSI_BG2_LNA_A1);
1837 }
f4450616 1838 } else {
f36bb0ca
GJ		 1839 if (rt2x00_rt(rt2x00dev, RT3593)) {
1840 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1841 lna_gain = rt2x00_get_field16(eeprom,
1842 EEPROM_EXT_LNA2_A2);
1843 } else {
1844 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1845 lna_gain = rt2x00_get_field16(eeprom,
1846 EEPROM_RSSI_A2_LNA_A2);
1847 }
f4450616
BZ		 1848 }
1849
1850 rt2x00dev->lna_gain = lna_gain;
1851}
1852
06855ef4
GW		 1853static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1854 struct ieee80211_conf *conf,
1855 struct rf_channel *rf,
1856 struct channel_info *info)
f4450616
BZ		 1857{
1858 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1859
d96aa640 1860 if (rt2x00dev->default_ant.tx_chain_num == 1)
f4450616
BZ		 1861 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1862
d96aa640 1863 if (rt2x00dev->default_ant.rx_chain_num == 1) {
f4450616
BZ		 1864 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1865 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
d96aa640 1866 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
f4450616
BZ		 1867 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1868
1869 if (rf->channel > 14) {
1870 /*
1871 * When TX power is below 0, we should increase it by 7 to
25985edc 1872 * make it a positive value (Minimum value is -7).
f4450616
BZ		 1873 * However this means that values between 0 and 7 have
1874 * double meaning, and we should set a 7DBm boost flag.
1875 */
1876 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
8d1331b3 1877 (info->default_power1 >= 0));
f4450616 1878
8d1331b3
ID		 1879 if (info->default_power1 < 0)
1880 info->default_power1 += 7;
f4450616 1881
8d1331b3 1882 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
f4450616
BZ		 1883
1884 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
8d1331b3 1885 (info->default_power2 >= 0));
f4450616 1886
8d1331b3
ID		 1887 if (info->default_power2 < 0)
1888 info->default_power2 += 7;
f4450616 1889
8d1331b3 1890 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
f4450616 1891 } else {
8d1331b3
ID		 1892 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1893 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
f4450616
BZ		 1894 }
1895
1896 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1897
1898 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1899 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1900 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1901 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1902
1903 udelay(200);
1904
1905 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1906 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1907 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1908 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1909
1910 udelay(200);
1911
1912 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1913 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1914 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1915 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1916}
1917
06855ef4
GW		 1918static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1919 struct ieee80211_conf *conf,
1920 struct rf_channel *rf,
1921 struct channel_info *info)
f4450616 1922{
3a1c0128 1923 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
f1f12f98 1924 u8 rfcsr, calib_tx, calib_rx;
f4450616
BZ		 1925
1926 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
7f4666ab
SG		 1927
1928 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1929 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
1930 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
f4450616
BZ		 1931
1932 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 1933 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 1934 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1935
1936 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
8d1331b3 1937 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
f4450616
BZ		 1938 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1939
5a673964 1940 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
8d1331b3 1941 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
5a673964 1942 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
e3bab197
SG		 1943
1944 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1945 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
7ad63035
GW		 1946 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
1947 rt2x00dev->default_ant.rx_chain_num <= 1);
1948 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
1949 rt2x00dev->default_ant.rx_chain_num <= 2);
e3bab197 1950 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
7ad63035
GW		 1951 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
1952 rt2x00dev->default_ant.tx_chain_num <= 1);
1953 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
1954 rt2x00dev->default_ant.tx_chain_num <= 2);
e3bab197 1955 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5a673964 1956
3e0c7643
SG		 1957 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1958 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1959 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1960 msleep(1);
1961 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1962 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1963
f4450616
BZ		 1964 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1965 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1966 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1967
f1f12f98
SG		 1968 if (rt2x00_rt(rt2x00dev, RT3390)) {
1969 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
1970 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
1971 } else {
3a1c0128
GW		 1972 if (conf_is_ht40(conf)) {
1973 calib_tx = drv_data->calibration_bw40;
1974 calib_rx = drv_data->calibration_bw40;
1975 } else {
1976 calib_tx = drv_data->calibration_bw20;
1977 calib_rx = drv_data->calibration_bw20;
1978 }
f1f12f98
SG		 1979 }
1980
1981 rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
1982 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
1983 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
1984
1985 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
1986 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
1987 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
f4450616 1988
71976907 1989 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 1990 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 1991 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
3e0c7643
SG		 1992
1993 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1994 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1995 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1996 msleep(1);
1997 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1998 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
f4450616
BZ		 1999}
2000
872834df
GW		 2001static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
2002 struct ieee80211_conf *conf,
2003 struct rf_channel *rf,
2004 struct channel_info *info)
2005{
3a1c0128 2006 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
872834df
GW		 2007 u8 rfcsr;
2008 u32 reg;
2009
2010 if (rf->channel <= 14) {
5d137dff
GW		 2011 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2012 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
872834df
GW		 2013 } else {
2014 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2015 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2016 }
2017
2018 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2019 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2020
2021 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2022 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2023 if (rf->channel <= 14)
2024 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
2025 else
2026 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
2027 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2028
2029 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
2030 if (rf->channel <= 14)
2031 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
2032 else
2033 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
2034 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2035
2036 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2037 if (rf->channel <= 14) {
2038 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
2039 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
569ffa56 2040 info->default_power1);
872834df
GW		 2041 } else {
2042 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
2043 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2044 (info->default_power1 & 0x3) |
2045 ((info->default_power1 & 0xC) << 1));
2046 }
2047 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2048
2049 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
2050 if (rf->channel <= 14) {
2051 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
2052 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
569ffa56 2053 info->default_power2);
872834df
GW		 2054 } else {
2055 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
2056 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2057 (info->default_power2 & 0x3) |
2058 ((info->default_power2 & 0xC) << 1));
2059 }
2060 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2061
2062 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
872834df
GW		 2063 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2064 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2065 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2066 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
0cd461ef
GW		 2067 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2068 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
872834df
GW		 2069 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
2070 if (rf->channel <= 14) {
2071 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2072 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2073 }
2074 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2075 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2076 } else {
2077 switch (rt2x00dev->default_ant.tx_chain_num) {
2078 case 1:
2079 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2080 case 2:
2081 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2082 break;
2083 }
2084
2085 switch (rt2x00dev->default_ant.rx_chain_num) {
2086 case 1:
2087 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2088 case 2:
2089 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2090 break;
2091 }
2092 }
2093 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2094
2095 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2096 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2097 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2098
3a1c0128
GW		 2099 if (conf_is_ht40(conf)) {
2100 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2101 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2102 } else {
2103 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2104 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2105 }
872834df
GW		 2106
2107 if (rf->channel <= 14) {
2108 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2109 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2110 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2111 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2112 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
77c06c2c
GW		 2113 rfcsr = 0x4c;
2114 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2115 drv_data->txmixer_gain_24g);
2116 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
872834df
GW		 2117 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2118 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2119 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2120 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2121 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2122 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2123 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2124 } else {
58b8ae14
GW		 2125 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2126 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
2127 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
2128 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
2129 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
2130 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
872834df
GW		 2131 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2132 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2133 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2134 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
77c06c2c
GW		 2135 rfcsr = 0x7a;
2136 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2137 drv_data->txmixer_gain_5g);
2138 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
872834df
GW		 2139 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2140 if (rf->channel <= 64) {
2141 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2142 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2143 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2144 } else if (rf->channel <= 128) {
2145 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2146 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2147 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2148 } else {
2149 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2150 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2151 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2152 }
2153 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2154 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2155 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2156 }
2157
99bdf51a
GW		 2158 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
2159 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
872834df 2160 if (rf->channel <= 14)
99bdf51a 2161 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
872834df 2162 else
99bdf51a
GW		 2163 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
2164 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
872834df
GW		 2165
2166 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2167 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2168 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2169}
60687ba7 2170
7573cb5b 2171#define POWER_BOUND 0x27
8f821098 2172#define POWER_BOUND_5G 0x2b
7573cb5b 2173#define FREQ_OFFSET_BOUND 0x5f
60687ba7 2174
0c9e5fb9
SG		 2175static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev)
2176{
2177 u8 rfcsr;
2178
2179 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2180 if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
2181 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
2182 else
2183 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2184 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2185}
2186
a89534ed
WH		 2187static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2188 struct ieee80211_conf *conf,
2189 struct rf_channel *rf,
2190 struct channel_info *info)
2191{
2192 u8 rfcsr;
2193
2194 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2195 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2196 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2197 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2198 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2199
2200 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
7573cb5b
SG		 2201 if (info->default_power1 > POWER_BOUND)
2202 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
a89534ed
WH		 2203 else
2204 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2205 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2206
0c9e5fb9 2207 rt2800_adjust_freq_offset(rt2x00dev);
a89534ed
WH		 2208
2209 if (rf->channel <= 14) {
2210 if (rf->channel == 6)
2211 rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2212 else
2213 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2214
2215 if (rf->channel >= 1 && rf->channel <= 6)
2216 rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2217 else if (rf->channel >= 7 && rf->channel <= 11)
2218 rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2219 else if (rf->channel >= 12 && rf->channel <= 14)
2220 rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2221 }
2222}
2223
03839951
DG		 2224static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2225 struct ieee80211_conf *conf,
2226 struct rf_channel *rf,
2227 struct channel_info *info)
2228{
2229 u8 rfcsr;
2230
2231 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2232 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2233
2234 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2235 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2236 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2237
2238 if (info->default_power1 > POWER_BOUND)
2239 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2240 else
2241 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2242
2243 if (info->default_power2 > POWER_BOUND)
2244 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2245 else
2246 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2247
0c9e5fb9 2248 rt2800_adjust_freq_offset(rt2x00dev);
03839951
DG		 2249
2250 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2251 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2252 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2253
2254 if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2255 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2256 else
2257 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2258
2259 if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2260 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2261 else
2262 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2263
2264 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2265 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2266
2267 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2268
2269 rt2800_rfcsr_write(rt2x00dev, 31, 80);
2270}
2271
60687ba7 2272static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
adde5882
GJ		 2273 struct ieee80211_conf *conf,
2274 struct rf_channel *rf,
2275 struct channel_info *info)
2276{
2277 u8 rfcsr;
adde5882
GJ		 2278
2279 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2280 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2281 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2282 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2283 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2284
2285 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
7573cb5b
SG		 2286 if (info->default_power1 > POWER_BOUND)
2287 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
adde5882
GJ		 2288 else
2289 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2290 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2291
cff3d1f0
ZL		 2292 if (rt2x00_rt(rt2x00dev, RT5392)) {
2293 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
7573cb5b
SG		 2294 if (info->default_power1 > POWER_BOUND)
2295 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
cff3d1f0
ZL		 2296 else
2297 rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2298 info->default_power2);
2299 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2300 }
2301
adde5882 2302 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
cff3d1f0
ZL		 2303 if (rt2x00_rt(rt2x00dev, RT5392)) {
2304 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2305 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2306 }
adde5882
GJ		 2307 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2308 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2309 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2310 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2311 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2312
0c9e5fb9 2313 rt2800_adjust_freq_offset(rt2x00dev);
adde5882 2314
adde5882
GJ		 2315 if (rf->channel <= 14) {
2316 int idx = rf->channel-1;
2317
fdbc7b0a 2318 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
adde5882
GJ		 2319 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2320 /* r55/r59 value array of channel 1~14 */
2321 static const char r55_bt_rev[] = {0x83, 0x83,
2322 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2323 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2324 static const char r59_bt_rev[] = {0x0e, 0x0e,
2325 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2326 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2327
2328 rt2800_rfcsr_write(rt2x00dev, 55,
2329 r55_bt_rev[idx]);
2330 rt2800_rfcsr_write(rt2x00dev, 59,
2331 r59_bt_rev[idx]);
2332 } else {
2333 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2334 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2335 0x88, 0x88, 0x86, 0x85, 0x84};
2336
2337 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2338 }
2339 } else {
2340 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2341 static const char r55_nonbt_rev[] = {0x23, 0x23,
2342 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2343 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2344 static const char r59_nonbt_rev[] = {0x07, 0x07,
2345 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2346 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2347
2348 rt2800_rfcsr_write(rt2x00dev, 55,
2349 r55_nonbt_rev[idx]);
2350 rt2800_rfcsr_write(rt2x00dev, 59,
2351 r59_nonbt_rev[idx]);
2ed71884 2352 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
e6d227b9 2353 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 2354 static const char r59_non_bt[] = {0x8f, 0x8f,
2355 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2356 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2357
2358 rt2800_rfcsr_write(rt2x00dev, 59,
2359 r59_non_bt[idx]);
2360 }
2361 }
2362 }
60687ba7
RST		 2363}
2364
8f821098
SG		 2365static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2366 struct ieee80211_conf *conf,
2367 struct rf_channel *rf,
2368 struct channel_info *info)
2369{
2370 u8 rfcsr, ep_reg;
d5ae7a6b 2371 u32 reg;
8f821098
SG		 2372 int power_bound;
2373
2374 /* TODO */
2375 const bool is_11b = false;
2376 const bool is_type_ep = false;
2377
d5ae7a6b
SG		 2378 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2379 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
2380 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
2381 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
8f821098
SG		 2382
2383 /* Order of values on rf_channel entry: N, K, mod, R */
2384 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2385
2386 rt2800_rfcsr_read(rt2x00dev, 9, &rfcsr);
2387 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2388 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2389 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2390 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2391
2392 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2393 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2394 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2395 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2396
2397 if (rf->channel <= 14) {
2398 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2399 /* FIXME: RF11 owerwrite ? */
2400 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2401 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2402 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2403 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2404 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2405 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2406 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2407 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2408 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2409 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2410 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2411 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2412 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2413 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2414 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2415 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2416 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2417 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2418 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2419 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2420 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2421 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2422 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2423 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2424 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2425 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2426 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2427 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2428
2429 /* TODO RF27 <- tssi */
2430
2431 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2432 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2433 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2434
2435 if (is_11b) {
2436 /* CCK */
2437 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2438 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2439 if (is_type_ep)
2440 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2441 else
2442 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2443 } else {
2444 /* OFDM */
2445 if (is_type_ep)
2446 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2447 else
2448 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2449 }
2450
2451 power_bound = POWER_BOUND;
2452 ep_reg = 0x2;
2453 } else {
2454 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2455 /* FIMXE: RF11 overwrite */
2456 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2457 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
2458 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2459 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
2460 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
2461 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
2462 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
2463 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
2464 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
2465 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
2466 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
2467 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
2468 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
2469 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
2470
2471 /* TODO RF27 <- tssi */
2472
2473 if (rf->channel >= 36 && rf->channel <= 64) {
2474
2475 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
2476 rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
2477 rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
2478 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
2479 if (rf->channel <= 50)
2480 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
2481 else if (rf->channel >= 52)
2482 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
2483 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
2484 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
2485 rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
2486 rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
2487 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
2488 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
2489 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
2490 if (rf->channel <= 50) {
2491 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
2492 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
2493 } else if (rf->channel >= 52) {
2494 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
2495 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2496 }
2497
2498 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2499 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
2500 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2501
2502 } else if (rf->channel >= 100 && rf->channel <= 165) {
2503
2504 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
2505 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2506 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2507 if (rf->channel <= 153) {
2508 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
2509 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
2510 } else if (rf->channel >= 155) {
2511 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
2512 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
2513 }
2514 if (rf->channel <= 138) {
2515 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
2516 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
2517 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
2518 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
2519 } else if (rf->channel >= 140) {
2520 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
2521 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
2522 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
2523 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
2524 }
2525 if (rf->channel <= 124)
2526 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
2527 else if (rf->channel >= 126)
2528 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
2529 if (rf->channel <= 138)
2530 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2531 else if (rf->channel >= 140)
2532 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2533 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
2534 if (rf->channel <= 138)
2535 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
2536 else if (rf->channel >= 140)
2537 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
2538 if (rf->channel <= 128)
2539 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2540 else if (rf->channel >= 130)
2541 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
2542 if (rf->channel <= 116)
2543 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
2544 else if (rf->channel >= 118)
2545 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2546 if (rf->channel <= 138)
2547 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
2548 else if (rf->channel >= 140)
2549 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
2550 if (rf->channel <= 116)
2551 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
2552 else if (rf->channel >= 118)
2553 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2554 }
2555
2556 power_bound = POWER_BOUND_5G;
2557 ep_reg = 0x3;
2558 }
2559
2560 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2561 if (info->default_power1 > power_bound)
2562 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
2563 else
2564 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2565 if (is_type_ep)
2566 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
2567 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2568
2569 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
0847beb2 2570 if (info->default_power2 > power_bound)
8f821098
SG		 2571 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
2572 else
2573 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
2574 if (is_type_ep)
2575 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
2576 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2577
2578 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2579 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2580 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2581
2582 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
2583 rt2x00dev->default_ant.tx_chain_num >= 1);
2584 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2585 rt2x00dev->default_ant.tx_chain_num == 2);
2586 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2587
2588 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
2589 rt2x00dev->default_ant.rx_chain_num >= 1);
2590 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2591 rt2x00dev->default_ant.rx_chain_num == 2);
2592 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2593
2594 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2595 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
2596
2597 if (conf_is_ht40(conf))
2598 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
2599 else
2600 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
2601
2602 if (!is_11b) {
2603 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2604 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
2605 }
2606
2607 /* TODO proper frequency adjustment */
0c9e5fb9 2608 rt2800_adjust_freq_offset(rt2x00dev);
8f821098
SG		 2609
2610 /* TODO merge with others */
2611 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2612 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2613 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
6803141b
SG		 2614
2615 /* BBP settings */
2616 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2617 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2618 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2619
2620 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
2621 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
2622 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
2623 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
2624
2625 /* GLRT band configuration */
2626 rt2800_bbp_write(rt2x00dev, 195, 128);
2627 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
2628 rt2800_bbp_write(rt2x00dev, 195, 129);
2629 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
2630 rt2800_bbp_write(rt2x00dev, 195, 130);
2631 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
2632 rt2800_bbp_write(rt2x00dev, 195, 131);
2633 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
2634 rt2800_bbp_write(rt2x00dev, 195, 133);
2635 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
2636 rt2800_bbp_write(rt2x00dev, 195, 124);
2637 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
8f821098
SG		 2638}
2639
5bc2dd06
SG		 2640static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
2641 const unsigned int word,
2642 const u8 value)
2643{
2644 u8 chain, reg;
2645
2646 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
2647 rt2800_bbp_read(rt2x00dev, 27, &reg);
2648 rt2x00_set_field8(&reg, BBP27_RX_CHAIN_SEL, chain);
2649 rt2800_bbp_write(rt2x00dev, 27, reg);
2650
2651 rt2800_bbp_write(rt2x00dev, word, value);
2652 }
2653}
2654
8756130b
SG		 2655static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
2656{
2657 u8 cal;
2658
415e3f2f 2659 /* TX0 IQ Gain */
8756130b 2660 rt2800_bbp_write(rt2x00dev, 158, 0x2c);
415e3f2f
SG		 2661 if (channel <= 14)
2662 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
2663 else if (channel >= 36 && channel <= 64)
2664 cal = rt2x00_eeprom_byte(rt2x00dev,
2665 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
2666 else if (channel >= 100 && channel <= 138)
2667 cal = rt2x00_eeprom_byte(rt2x00dev,
2668 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
2669 else if (channel >= 140 && channel <= 165)
2670 cal = rt2x00_eeprom_byte(rt2x00dev,
2671 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
2672 else
2673 cal = 0;
8756130b
SG		 2674 rt2800_bbp_write(rt2x00dev, 159, cal);
2675
415e3f2f 2676 /* TX0 IQ Phase */
8756130b 2677 rt2800_bbp_write(rt2x00dev, 158, 0x2d);
415e3f2f
SG		 2678 if (channel <= 14)
2679 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
2680 else if (channel >= 36 && channel <= 64)
2681 cal = rt2x00_eeprom_byte(rt2x00dev,
2682 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
2683 else if (channel >= 100 && channel <= 138)
2684 cal = rt2x00_eeprom_byte(rt2x00dev,
2685 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
2686 else if (channel >= 140 && channel <= 165)
2687 cal = rt2x00_eeprom_byte(rt2x00dev,
2688 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
2689 else
2690 cal = 0;
8756130b
SG		 2691 rt2800_bbp_write(rt2x00dev, 159, cal);
2692
415e3f2f 2693 /* TX1 IQ Gain */
8756130b 2694 rt2800_bbp_write(rt2x00dev, 158, 0x4a);
415e3f2f
SG		 2695 if (channel <= 14)
2696 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
2697 else if (channel >= 36 && channel <= 64)
2698 cal = rt2x00_eeprom_byte(rt2x00dev,
2699 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
2700 else if (channel >= 100 && channel <= 138)
2701 cal = rt2x00_eeprom_byte(rt2x00dev,
2702 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
2703 else if (channel >= 140 && channel <= 165)
2704 cal = rt2x00_eeprom_byte(rt2x00dev,
2705 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
2706 else
2707 cal = 0;
8756130b
SG		 2708 rt2800_bbp_write(rt2x00dev, 159, cal);
2709
415e3f2f 2710 /* TX1 IQ Phase */
8756130b 2711 rt2800_bbp_write(rt2x00dev, 158, 0x4b);
415e3f2f
SG		 2712 if (channel <= 14)
2713 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
2714 else if (channel >= 36 && channel <= 64)
2715 cal = rt2x00_eeprom_byte(rt2x00dev,
2716 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
2717 else if (channel >= 100 && channel <= 138)
2718 cal = rt2x00_eeprom_byte(rt2x00dev,
2719 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
2720 else if (channel >= 140 && channel <= 165)
2721 cal = rt2x00_eeprom_byte(rt2x00dev,
2722 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
2723 else
2724 cal = 0;
8756130b
SG		 2725 rt2800_bbp_write(rt2x00dev, 159, cal);
2726
415e3f2f
SG		 2727 /* FIXME: possible RX0, RX1 callibration ? */
2728
8756130b
SG		 2729 /* RF IQ compensation control */
2730 rt2800_bbp_write(rt2x00dev, 158, 0x04);
2731 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
2732 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
2733
2734 /* RF IQ imbalance compensation control */
2735 rt2800_bbp_write(rt2x00dev, 158, 0x03);
415e3f2f
SG		 2736 cal = rt2x00_eeprom_byte(rt2x00dev,
2737 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
8756130b
SG		 2738 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
2739}
2740
97aa03f1
GJ		 2741static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
2742 unsigned int channel,
2743 char txpower)
2744{
fc739cfe
GJ		 2745 if (rt2x00_rt(rt2x00dev, RT3593))
2746 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
2747
97aa03f1
GJ		 2748 if (channel <= 14)
2749 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
fc739cfe
GJ		 2750
2751 if (rt2x00_rt(rt2x00dev, RT3593))
2752 return clamp_t(char, txpower, MIN_A_TXPOWER_3593,
2753 MAX_A_TXPOWER_3593);
97aa03f1
GJ		 2754 else
2755 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
2756}
2757
f4450616
BZ		 2758static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2759 struct ieee80211_conf *conf,
2760 struct rf_channel *rf,
2761 struct channel_info *info)
2762{
2763 u32 reg;
2764 unsigned int tx_pin;
a89534ed 2765 u8 bbp, rfcsr;
f4450616 2766
97aa03f1
GJ		 2767 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
2768 info->default_power1);
2769 info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
2770 info->default_power2);
c0a14369
GJ		 2771 if (rt2x00dev->default_ant.tx_chain_num > 2)
2772 info->default_power3 =
2773 rt2800_txpower_to_dev(rt2x00dev, rf->channel,
2774 info->default_power3);
46323e11 2775
5aa57015
GW		 2776 switch (rt2x00dev->chip.rf) {
2777 case RF2020:
2778 case RF3020:
2779 case RF3021:
2780 case RF3022:
2781 case RF3320:
06855ef4 2782 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
5aa57015
GW		 2783 break;
2784 case RF3052:
872834df 2785 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
5aa57015 2786 break;
a89534ed
WH		 2787 case RF3290:
2788 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
2789 break;
03839951
DG		 2790 case RF3322:
2791 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
2792 break;
ccf91bd6 2793 case RF5360:
5aa57015 2794 case RF5370:
2ed71884 2795 case RF5372:
5aa57015 2796 case RF5390:
cff3d1f0 2797 case RF5392:
adde5882 2798 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
5aa57015 2799 break;
8f821098
SG		 2800 case RF5592:
2801 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
2802 break;
5aa57015 2803 default:
06855ef4 2804 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
5aa57015 2805 }
f4450616 2806
a89534ed 2807 if (rt2x00_rf(rt2x00dev, RF3290) ||
03839951 2808 rt2x00_rf(rt2x00dev, RF3322) ||
a89534ed
WH		 2809 rt2x00_rf(rt2x00dev, RF5360) ||
2810 rt2x00_rf(rt2x00dev, RF5370) ||
2811 rt2x00_rf(rt2x00dev, RF5372) ||
2812 rt2x00_rf(rt2x00dev, RF5390) ||
2813 rt2x00_rf(rt2x00dev, RF5392)) {
2814 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2815 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
2816 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
2817 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2818
2819 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
d6d82020 2820 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
a89534ed
WH		 2821 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2822 }
2823
f4450616
BZ		 2824 /*
2825 * Change BBP settings
2826 */
03839951
DG		 2827 if (rt2x00_rt(rt2x00dev, RT3352)) {
2828 rt2800_bbp_write(rt2x00dev, 27, 0x0);
cf193f6d 2829 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
03839951 2830 rt2800_bbp_write(rt2x00dev, 27, 0x20);
cf193f6d 2831 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
03839951
DG		 2832 } else {
2833 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2834 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2835 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2836 rt2800_bbp_write(rt2x00dev, 86, 0);
2837 }
f4450616
BZ		 2838
2839 if (rf->channel <= 14) {
2ed71884 2840 if (!rt2x00_rt(rt2x00dev, RT5390) &&
e6d227b9 2841 !rt2x00_rt(rt2x00dev, RT5392)) {
7dab73b3
ID		 2842 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
2843 &rt2x00dev->cap_flags)) {
adde5882
GJ		 2844 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2845 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2846 } else {
2847 rt2800_bbp_write(rt2x00dev, 82, 0x84);
2848 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2849 }
f4450616
BZ		 2850 }
2851 } else {
872834df
GW		 2852 if (rt2x00_rt(rt2x00dev, RT3572))
2853 rt2800_bbp_write(rt2x00dev, 82, 0x94);
2854 else
2855 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
f4450616 2856
7dab73b3 2857 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
f4450616
BZ		 2858 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2859 else
2860 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2861 }
2862
2863 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 2864 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 2865 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
2866 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
2867 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
2868
872834df
GW		 2869 if (rt2x00_rt(rt2x00dev, RT3572))
2870 rt2800_rfcsr_write(rt2x00dev, 8, 0);
2871
f4450616
BZ		 2872 tx_pin = 0;
2873
bb16d488
GJ		 2874 switch (rt2x00dev->default_ant.tx_chain_num) {
2875 case 3:
2876 /* Turn on tertiary PAs */
2877 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
2878 rf->channel > 14);
2879 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
2880 rf->channel <= 14);
2881 /* fall-through */
2882 case 2:
2883 /* Turn on secondary PAs */
65f31b5e
GW		 2884 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
2885 rf->channel > 14);
2886 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
2887 rf->channel <= 14);
bb16d488
GJ		 2888 /* fall-through */
2889 case 1:
2890 /* Turn on primary PAs */
2891 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
2892 rf->channel > 14);
2893 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
2894 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2895 else
2896 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
2897 rf->channel <= 14);
2898 break;
f4450616
BZ		 2899 }
2900
bb16d488
GJ		 2901 switch (rt2x00dev->default_ant.rx_chain_num) {
2902 case 3:
2903 /* Turn on tertiary LNAs */
2904 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1);
2905 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1);
2906 /* fall-through */
2907 case 2:
2908 /* Turn on secondary LNAs */
f4450616
BZ		 2909 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
2910 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
bb16d488
GJ		 2911 /* fall-through */
2912 case 1:
2913 /* Turn on primary LNAs */
2914 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
2915 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
2916 break;
f4450616
BZ		 2917 }
2918
f4450616
BZ		 2919 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
2920 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
f4450616
BZ		 2921
2922 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2923
872834df
GW		 2924 if (rt2x00_rt(rt2x00dev, RT3572))
2925 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
2926
6803141b
SG		 2927 if (rt2x00_rt(rt2x00dev, RT5592)) {
2928 rt2800_bbp_write(rt2x00dev, 195, 141);
2929 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
2930
8ba0ebf3
SG		 2931 /* AGC init */
2932 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain;
2933 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
2934
8756130b 2935 rt2800_iq_calibrate(rt2x00dev, rf->channel);
6803141b
SG		 2936 }
2937
f4450616
BZ		 2938 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2939 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
2940 rt2800_bbp_write(rt2x00dev, 4, bbp);
2941
2942 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 2943 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 2944 rt2800_bbp_write(rt2x00dev, 3, bbp);
2945
8d0c9b65 2946 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 2947 if (conf_is_ht40(conf)) {
2948 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
2949 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2950 rt2800_bbp_write(rt2x00dev, 73, 0x16);
2951 } else {
2952 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2953 rt2800_bbp_write(rt2x00dev, 70, 0x08);
2954 rt2800_bbp_write(rt2x00dev, 73, 0x11);
2955 }
2956 }
2957
2958 msleep(1);
977206d7
HS		 2959
2960 /*
2961 * Clear channel statistic counters
2962 */
2963 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
2964 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
2965 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
03839951
DG		 2966
2967 /*
2968 * Clear update flag
2969 */
2970 if (rt2x00_rt(rt2x00dev, RT3352)) {
2971 rt2800_bbp_read(rt2x00dev, 49, &bbp);
2972 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
2973 rt2800_bbp_write(rt2x00dev, 49, bbp);
2974 }
f4450616
BZ		 2975}
2976
9e33a355
HS		 2977static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
2978{
2979 u8 tssi_bounds[9];
2980 u8 current_tssi;
2981 u16 eeprom;
2982 u8 step;
2983 int i;
2984
2985 /*
2986 * Read TSSI boundaries for temperature compensation from
2987 * the EEPROM.
2988 *
2989 * Array idx 0 1 2 3 4 5 6 7 8
2990 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
2991 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2992 */
2993 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
3e38d3da 2994 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
9e33a355
HS		 2995 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2996 EEPROM_TSSI_BOUND_BG1_MINUS4);
2997 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2998 EEPROM_TSSI_BOUND_BG1_MINUS3);
2999
3e38d3da 3000 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
9e33a355
HS		 3001 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3002 EEPROM_TSSI_BOUND_BG2_MINUS2);
3003 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3004 EEPROM_TSSI_BOUND_BG2_MINUS1);
3005
3e38d3da 3006 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
9e33a355
HS		 3007 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3008 EEPROM_TSSI_BOUND_BG3_REF);
3009 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3010 EEPROM_TSSI_BOUND_BG3_PLUS1);
3011
3e38d3da 3012 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
9e33a355
HS		 3013 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3014 EEPROM_TSSI_BOUND_BG4_PLUS2);
3015 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3016 EEPROM_TSSI_BOUND_BG4_PLUS3);
3017
3e38d3da 3018 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
9e33a355
HS		 3019 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3020 EEPROM_TSSI_BOUND_BG5_PLUS4);
3021
3022 step = rt2x00_get_field16(eeprom,
3023 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
3024 } else {
3e38d3da 3025 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
9e33a355
HS		 3026 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3027 EEPROM_TSSI_BOUND_A1_MINUS4);
3028 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3029 EEPROM_TSSI_BOUND_A1_MINUS3);
3030
3e38d3da 3031 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
9e33a355
HS		 3032 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3033 EEPROM_TSSI_BOUND_A2_MINUS2);
3034 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3035 EEPROM_TSSI_BOUND_A2_MINUS1);
3036
3e38d3da 3037 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
9e33a355
HS		 3038 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3039 EEPROM_TSSI_BOUND_A3_REF);
3040 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3041 EEPROM_TSSI_BOUND_A3_PLUS1);
3042
3e38d3da 3043 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
9e33a355
HS		 3044 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3045 EEPROM_TSSI_BOUND_A4_PLUS2);
3046 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3047 EEPROM_TSSI_BOUND_A4_PLUS3);
3048
3e38d3da 3049 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
9e33a355
HS		 3050 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3051 EEPROM_TSSI_BOUND_A5_PLUS4);
3052
3053 step = rt2x00_get_field16(eeprom,
3054 EEPROM_TSSI_BOUND_A5_AGC_STEP);
3055 }
3056
3057 /*
3058 * Check if temperature compensation is supported.
3059 */
bf7e1abe 3060 if (tssi_bounds[4] == 0xff || step == 0xff)
9e33a355
HS		 3061 return 0;
3062
3063 /*
3064 * Read current TSSI (BBP 49).
3065 */
3066 rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
3067
3068 /*
3069 * Compare TSSI value (BBP49) with the compensation boundaries
3070 * from the EEPROM and increase or decrease tx power.
3071 */
3072 for (i = 0; i <= 3; i++) {
3073 if (current_tssi > tssi_bounds[i])
3074 break;
3075 }
3076
3077 if (i == 4) {
3078 for (i = 8; i >= 5; i--) {
3079 if (current_tssi < tssi_bounds[i])
3080 break;
3081 }
3082 }
3083
3084 return (i - 4) * step;
3085}
3086
e90c54b2
RJH		 3087static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
3088 enum ieee80211_band band)
3089{
3090 u16 eeprom;
3091 u8 comp_en;
3092 u8 comp_type;
75faae8b 3093 int comp_value = 0;
e90c54b2 3094
3e38d3da 3095 rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
e90c54b2 3096
75faae8b
HS		 3097 /*
3098 * HT40 compensation not required.
3099 */
3100 if (eeprom == 0xffff ||
3101 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
e90c54b2
RJH		 3102 return 0;
3103
3104 if (band == IEEE80211_BAND_2GHZ) {
3105 comp_en = rt2x00_get_field16(eeprom,
3106 EEPROM_TXPOWER_DELTA_ENABLE_2G);
3107 if (comp_en) {
3108 comp_type = rt2x00_get_field16(eeprom,
3109 EEPROM_TXPOWER_DELTA_TYPE_2G);
3110 comp_value = rt2x00_get_field16(eeprom,
3111 EEPROM_TXPOWER_DELTA_VALUE_2G);
3112 if (!comp_type)
3113 comp_value = -comp_value;
3114 }
3115 } else {
3116 comp_en = rt2x00_get_field16(eeprom,
3117 EEPROM_TXPOWER_DELTA_ENABLE_5G);
3118 if (comp_en) {
3119 comp_type = rt2x00_get_field16(eeprom,
3120 EEPROM_TXPOWER_DELTA_TYPE_5G);
3121 comp_value = rt2x00_get_field16(eeprom,
3122 EEPROM_TXPOWER_DELTA_VALUE_5G);
3123 if (!comp_type)
3124 comp_value = -comp_value;
3125 }
3126 }
3127
3128 return comp_value;
3129}
3130
1e4cf249
SG		 3131static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
3132 int power_level, int max_power)
3133{
3134 int delta;
3135
3136 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags))
3137 return 0;
3138
3139 /*
3140 * XXX: We don't know the maximum transmit power of our hardware since
3141 * the EEPROM doesn't expose it. We only know that we are calibrated
3142 * to 100% tx power.
3143 *
3144 * Hence, we assume the regulatory limit that cfg80211 calulated for
3145 * the current channel is our maximum and if we are requested to lower
3146 * the value we just reduce our tx power accordingly.
3147 */
3148 delta = power_level - max_power;
3149 return min(delta, 0);
3150}
3151
fa71a160
HS		 3152static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
3153 enum ieee80211_band band, int power_level,
3154 u8 txpower, int delta)
e90c54b2 3155{
e90c54b2
RJH		 3156 u16 eeprom;
3157 u8 criterion;
3158 u8 eirp_txpower;
3159 u8 eirp_txpower_criterion;
3160 u8 reg_limit;
e90c54b2 3161
34542ff5
GJ		 3162 if (rt2x00_rt(rt2x00dev, RT3593))
3163 return min_t(u8, txpower, 0xc);
3164
7dab73b3 3165 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
e90c54b2
RJH		 3166 /*
3167 * Check if eirp txpower exceed txpower_limit.
3168 * We use OFDM 6M as criterion and its eirp txpower
3169 * is stored at EEPROM_EIRP_MAX_TX_POWER.
3170 * .11b data rate need add additional 4dbm
3171 * when calculating eirp txpower.
3172 */
022138ca
GJ		 3173 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3174 1, &eeprom);
d9bceaeb
SG		 3175 criterion = rt2x00_get_field16(eeprom,
3176 EEPROM_TXPOWER_BYRATE_RATE0);
e90c54b2 3177
3e38d3da 3178 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
d9bceaeb 3179 &eeprom);
e90c54b2
RJH		 3180
3181 if (band == IEEE80211_BAND_2GHZ)
3182 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3183 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
3184 else
3185 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3186 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
3187
3188 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2af242e1 3189 (is_rate_b ? 4 : 0) + delta;
e90c54b2
RJH		 3190
3191 reg_limit = (eirp_txpower > power_level) ?
3192 (eirp_txpower - power_level) : 0;
3193 } else
3194 reg_limit = 0;
3195
19f3fa24
SG		 3196 txpower = max(0, txpower + delta - reg_limit);
3197 return min_t(u8, txpower, 0xc);
e90c54b2
RJH		 3198}
3199
34542ff5
GJ		 3200
3201enum {
3202 TX_PWR_CFG_0_IDX,
3203 TX_PWR_CFG_1_IDX,
3204 TX_PWR_CFG_2_IDX,
3205 TX_PWR_CFG_3_IDX,
3206 TX_PWR_CFG_4_IDX,
3207 TX_PWR_CFG_5_IDX,
3208 TX_PWR_CFG_6_IDX,
3209 TX_PWR_CFG_7_IDX,
3210 TX_PWR_CFG_8_IDX,
3211 TX_PWR_CFG_9_IDX,
3212 TX_PWR_CFG_0_EXT_IDX,
3213 TX_PWR_CFG_1_EXT_IDX,
3214 TX_PWR_CFG_2_EXT_IDX,
3215 TX_PWR_CFG_3_EXT_IDX,
3216 TX_PWR_CFG_4_EXT_IDX,
3217 TX_PWR_CFG_IDX_COUNT,
3218};
3219
3220static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
3221 struct ieee80211_channel *chan,
3222 int power_level)
3223{
3224 u8 txpower;
3225 u16 eeprom;
3226 u32 regs[TX_PWR_CFG_IDX_COUNT];
3227 unsigned int offset;
3228 enum ieee80211_band band = chan->band;
3229 int delta;
3230 int i;
3231
3232 memset(regs, '\0', sizeof(regs));
3233
3234 /* TODO: adapt TX power reduction from the rt28xx code */
3235
3236 /* calculate temperature compensation delta */
3237 delta = rt2800_get_gain_calibration_delta(rt2x00dev);
3238
3239 if (band == IEEE80211_BAND_5GHZ)
3240 offset = 16;
3241 else
3242 offset = 0;
3243
3244 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3245 offset += 8;
3246
3247 /* read the next four txpower values */
3248 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3249 offset, &eeprom);
3250
3251 /* CCK 1MBS,2MBS */
3252 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3253 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3254 txpower, delta);
3255 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3256 TX_PWR_CFG_0_CCK1_CH0, txpower);
3257 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3258 TX_PWR_CFG_0_CCK1_CH1, txpower);
3259 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3260 TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
3261
3262 /* CCK 5.5MBS,11MBS */
3263 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3264 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3265 txpower, delta);
3266 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3267 TX_PWR_CFG_0_CCK5_CH0, txpower);
3268 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3269 TX_PWR_CFG_0_CCK5_CH1, txpower);
3270 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3271 TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
3272
3273 /* OFDM 6MBS,9MBS */
3274 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3275 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3276 txpower, delta);
3277 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3278 TX_PWR_CFG_0_OFDM6_CH0, txpower);
3279 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3280 TX_PWR_CFG_0_OFDM6_CH1, txpower);
3281 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3282 TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
3283
3284 /* OFDM 12MBS,18MBS */
3285 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3286 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3287 txpower, delta);
3288 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3289 TX_PWR_CFG_0_OFDM12_CH0, txpower);
3290 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3291 TX_PWR_CFG_0_OFDM12_CH1, txpower);
3292 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3293 TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
3294
3295 /* read the next four txpower values */
3296 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3297 offset + 1, &eeprom);
3298
3299 /* OFDM 24MBS,36MBS */
3300 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3301 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3302 txpower, delta);
3303 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3304 TX_PWR_CFG_1_OFDM24_CH0, txpower);
3305 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3306 TX_PWR_CFG_1_OFDM24_CH1, txpower);
3307 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3308 TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
3309
3310 /* OFDM 48MBS */
3311 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3312 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3313 txpower, delta);
3314 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3315 TX_PWR_CFG_1_OFDM48_CH0, txpower);
3316 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3317 TX_PWR_CFG_1_OFDM48_CH1, txpower);
3318 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3319 TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
3320
3321 /* OFDM 54MBS */
3322 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3323 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3324 txpower, delta);
3325 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3326 TX_PWR_CFG_7_OFDM54_CH0, txpower);
3327 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3328 TX_PWR_CFG_7_OFDM54_CH1, txpower);
3329 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3330 TX_PWR_CFG_7_OFDM54_CH2, txpower);
3331
3332 /* read the next four txpower values */
3333 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3334 offset + 2, &eeprom);
3335
3336 /* MCS 0,1 */
3337 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3338 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3339 txpower, delta);
3340 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3341 TX_PWR_CFG_1_MCS0_CH0, txpower);
3342 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3343 TX_PWR_CFG_1_MCS0_CH1, txpower);
3344 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3345 TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
3346
3347 /* MCS 2,3 */
3348 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3349 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3350 txpower, delta);
3351 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3352 TX_PWR_CFG_1_MCS2_CH0, txpower);
3353 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3354 TX_PWR_CFG_1_MCS2_CH1, txpower);
3355 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3356 TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
3357
3358 /* MCS 4,5 */
3359 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3360 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3361 txpower, delta);
3362 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3363 TX_PWR_CFG_2_MCS4_CH0, txpower);
3364 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3365 TX_PWR_CFG_2_MCS4_CH1, txpower);
3366 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3367 TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
3368
3369 /* MCS 6 */
3370 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3371 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3372 txpower, delta);
3373 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3374 TX_PWR_CFG_2_MCS6_CH0, txpower);
3375 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3376 TX_PWR_CFG_2_MCS6_CH1, txpower);
3377 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3378 TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
3379
3380 /* read the next four txpower values */
3381 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3382 offset + 3, &eeprom);
3383
3384 /* MCS 7 */
3385 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3386 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3387 txpower, delta);
3388 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3389 TX_PWR_CFG_7_MCS7_CH0, txpower);
3390 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3391 TX_PWR_CFG_7_MCS7_CH1, txpower);
3392 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3393 TX_PWR_CFG_7_MCS7_CH2, txpower);
3394
3395 /* MCS 8,9 */
3396 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3397 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3398 txpower, delta);
3399 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3400 TX_PWR_CFG_2_MCS8_CH0, txpower);
3401 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3402 TX_PWR_CFG_2_MCS8_CH1, txpower);
3403 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3404 TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
3405
3406 /* MCS 10,11 */
3407 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3408 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3409 txpower, delta);
3410 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3411 TX_PWR_CFG_2_MCS10_CH0, txpower);
3412 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3413 TX_PWR_CFG_2_MCS10_CH1, txpower);
3414 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3415 TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
3416
3417 /* MCS 12,13 */
3418 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3419 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3420 txpower, delta);
3421 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3422 TX_PWR_CFG_3_MCS12_CH0, txpower);
3423 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3424 TX_PWR_CFG_3_MCS12_CH1, txpower);
3425 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3426 TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
3427
3428 /* read the next four txpower values */
3429 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3430 offset + 4, &eeprom);
3431
3432 /* MCS 14 */
3433 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3434 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3435 txpower, delta);
3436 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3437 TX_PWR_CFG_3_MCS14_CH0, txpower);
3438 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3439 TX_PWR_CFG_3_MCS14_CH1, txpower);
3440 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3441 TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
3442
3443 /* MCS 15 */
3444 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3445 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3446 txpower, delta);
3447 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3448 TX_PWR_CFG_8_MCS15_CH0, txpower);
3449 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3450 TX_PWR_CFG_8_MCS15_CH1, txpower);
3451 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3452 TX_PWR_CFG_8_MCS15_CH2, txpower);
3453
3454 /* MCS 16,17 */
3455 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3456 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3457 txpower, delta);
3458 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3459 TX_PWR_CFG_5_MCS16_CH0, txpower);
3460 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3461 TX_PWR_CFG_5_MCS16_CH1, txpower);
3462 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3463 TX_PWR_CFG_5_MCS16_CH2, txpower);
3464
3465 /* MCS 18,19 */
3466 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3467 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3468 txpower, delta);
3469 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3470 TX_PWR_CFG_5_MCS18_CH0, txpower);
3471 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3472 TX_PWR_CFG_5_MCS18_CH1, txpower);
3473 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3474 TX_PWR_CFG_5_MCS18_CH2, txpower);
3475
3476 /* read the next four txpower values */
3477 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3478 offset + 5, &eeprom);
3479
3480 /* MCS 20,21 */
3481 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3482 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3483 txpower, delta);
3484 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3485 TX_PWR_CFG_6_MCS20_CH0, txpower);
3486 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3487 TX_PWR_CFG_6_MCS20_CH1, txpower);
3488 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3489 TX_PWR_CFG_6_MCS20_CH2, txpower);
3490
3491 /* MCS 22 */
3492 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3493 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3494 txpower, delta);
3495 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3496 TX_PWR_CFG_6_MCS22_CH0, txpower);
3497 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3498 TX_PWR_CFG_6_MCS22_CH1, txpower);
3499 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3500 TX_PWR_CFG_6_MCS22_CH2, txpower);
3501
3502 /* MCS 23 */
3503 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3504 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3505 txpower, delta);
3506 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3507 TX_PWR_CFG_8_MCS23_CH0, txpower);
3508 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3509 TX_PWR_CFG_8_MCS23_CH1, txpower);
3510 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3511 TX_PWR_CFG_8_MCS23_CH2, txpower);
3512
3513 /* read the next four txpower values */
3514 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3515 offset + 6, &eeprom);
3516
3517 /* STBC, MCS 0,1 */
3518 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3519 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3520 txpower, delta);
3521 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3522 TX_PWR_CFG_3_STBC0_CH0, txpower);
3523 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3524 TX_PWR_CFG_3_STBC0_CH1, txpower);
3525 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3526 TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
3527
3528 /* STBC, MCS 2,3 */
3529 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3530 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3531 txpower, delta);
3532 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3533 TX_PWR_CFG_3_STBC2_CH0, txpower);
3534 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3535 TX_PWR_CFG_3_STBC2_CH1, txpower);
3536 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3537 TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
3538
3539 /* STBC, MCS 4,5 */
3540 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3541 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3542 txpower, delta);
3543 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
3544 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
3545 rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
3546 txpower);
3547
3548 /* STBC, MCS 6 */
3549 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3550 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3551 txpower, delta);
3552 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
3553 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
3554 rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
3555 txpower);
3556
3557 /* read the next four txpower values */
3558 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3559 offset + 7, &eeprom);
3560
3561 /* STBC, MCS 7 */
3562 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3563 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3564 txpower, delta);
3565 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
3566 TX_PWR_CFG_9_STBC7_CH0, txpower);
3567 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
3568 TX_PWR_CFG_9_STBC7_CH1, txpower);
3569 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
3570 TX_PWR_CFG_9_STBC7_CH2, txpower);
3571
3572 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
3573 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
3574 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
3575 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
3576 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
3577 rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
3578 rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
3579 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
3580 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
3581 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
3582
3583 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
3584 regs[TX_PWR_CFG_0_EXT_IDX]);
3585 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
3586 regs[TX_PWR_CFG_1_EXT_IDX]);
3587 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
3588 regs[TX_PWR_CFG_2_EXT_IDX]);
3589 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
3590 regs[TX_PWR_CFG_3_EXT_IDX]);
3591 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
3592 regs[TX_PWR_CFG_4_EXT_IDX]);
3593
3594 for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
3595 rt2x00_dbg(rt2x00dev,
3596 "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
3597 (band == IEEE80211_BAND_5GHZ) ? '5' : '2',
3598 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
3599 '4' : '2',
3600 (i > TX_PWR_CFG_9_IDX) ?
3601 (i - TX_PWR_CFG_9_IDX - 1) : i,
3602 (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
3603 (unsigned long) regs[i]);
3604}
3605
7a66205a
SG		 3606/*
3607 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
3608 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
3609 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
3610 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
3611 * Reference per rate transmit power values are located in the EEPROM at
3612 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
3613 * current conditions (i.e. band, bandwidth, temperature, user settings).
3614 */
34542ff5
GJ		 3615static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
3616 struct ieee80211_channel *chan,
3617 int power_level)
f4450616 3618{
cee2c731 3619 u8 txpower, r1;
5e846004 3620 u16 eeprom;
cee2c731
SG		 3621 u32 reg, offset;
3622 int i, is_rate_b, delta, power_ctrl;
146c3b0c 3623 enum ieee80211_band band = chan->band;
2af242e1
HS		 3624
3625 /*
7a66205a
SG		 3626 * Calculate HT40 compensation. For 40MHz we need to add or subtract
3627 * value read from EEPROM (different for 2GHz and for 5GHz).
2af242e1
HS		 3628 */
3629 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
f4450616 3630
9e33a355 3631 /*
7a66205a
SG		 3632 * Calculate temperature compensation. Depends on measurement of current
3633 * TSSI (Transmitter Signal Strength Indication) we know TX power (due
3634 * to temperature or maybe other factors) is smaller or bigger than
3635 * expected. We adjust it, based on TSSI reference and boundaries values
3636 * provided in EEPROM.
9e33a355
HS		 3637 */
3638 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
f4450616 3639
1e4cf249 3640 /*
7a66205a
SG		 3641 * Decrease power according to user settings, on devices with unknown
3642 * maximum tx power. For other devices we take user power_level into
3643 * consideration on rt2800_compensate_txpower().
1e4cf249
SG		 3644 */
3645 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
3646 chan->max_power);
3647
5e846004 3648 /*
cee2c731
SG		 3649 * BBP_R1 controls TX power for all rates, it allow to set the following
3650 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
3651 *
3652 * TODO: we do not use +6 dBm option to do not increase power beyond
3653 * regulatory limit, however this could be utilized for devices with
3654 * CAPABILITY_POWER_LIMIT.
8c8d2017
SG		 3655 *
3656 * TODO: add different temperature compensation code for RT3290 & RT5390
3657 * to allow to use BBP_R1 for those chips.
3658 */
3659 if (!rt2x00_rt(rt2x00dev, RT3290) &&
3660 !rt2x00_rt(rt2x00dev, RT5390)) {
3661 rt2800_bbp_read(rt2x00dev, 1, &r1);
3662 if (delta <= -12) {
3663 power_ctrl = 2;
3664 delta += 12;
3665 } else if (delta <= -6) {
3666 power_ctrl = 1;
3667 delta += 6;
3668 } else {
3669 power_ctrl = 0;
3670 }
3671 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
3672 rt2800_bbp_write(rt2x00dev, 1, r1);
cee2c731 3673 }
8c8d2017 3674
5e846004
HS		 3675 offset = TX_PWR_CFG_0;
3676
3677 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
3678 /* just to be safe */
3679 if (offset > TX_PWR_CFG_4)
3680 break;
3681
3682 rt2800_register_read(rt2x00dev, offset, &reg);
3683
3684 /* read the next four txpower values */
022138ca
GJ		 3685 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3686 i, &eeprom);
5e846004 3687
e90c54b2
RJH		 3688 is_rate_b = i ? 0 : 1;
3689 /*
3690 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
5e846004 3691 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
e90c54b2
RJH		 3692 * TX_PWR_CFG_4: unknown
3693 */
5e846004
HS		 3694 txpower = rt2x00_get_field16(eeprom,
3695 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 3696 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 3697 power_level, txpower, delta);
e90c54b2 3698 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
5e846004 3699
e90c54b2
RJH		 3700 /*
3701 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
5e846004 3702 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
e90c54b2
RJH		 3703 * TX_PWR_CFG_4: unknown
3704 */
5e846004
HS		 3705 txpower = rt2x00_get_field16(eeprom,
3706 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 3707 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 3708 power_level, txpower, delta);
e90c54b2 3709 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
5e846004 3710
e90c54b2
RJH		 3711 /*
3712 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
5e846004 3713 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
e90c54b2
RJH		 3714 * TX_PWR_CFG_4: unknown
3715 */
5e846004
HS		 3716 txpower = rt2x00_get_field16(eeprom,
3717 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 3718 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 3719 power_level, txpower, delta);
e90c54b2 3720 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
5e846004 3721
e90c54b2
RJH		 3722 /*
3723 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
5e846004 3724 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
e90c54b2
RJH		 3725 * TX_PWR_CFG_4: unknown
3726 */
5e846004
HS		 3727 txpower = rt2x00_get_field16(eeprom,
3728 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 3729 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 3730 power_level, txpower, delta);
e90c54b2 3731 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
5e846004
HS		 3732
3733 /* read the next four txpower values */
022138ca
GJ		 3734 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3735 i + 1, &eeprom);
5e846004 3736
e90c54b2
RJH		 3737 is_rate_b = 0;
3738 /*
3739 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
5e846004 3740 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 3741 * TX_PWR_CFG_4: unknown
3742 */
5e846004
HS		 3743 txpower = rt2x00_get_field16(eeprom,
3744 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 3745 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 3746 power_level, txpower, delta);
e90c54b2 3747 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
5e846004 3748
e90c54b2
RJH		 3749 /*
3750 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
5e846004 3751 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 3752 * TX_PWR_CFG_4: unknown
3753 */
5e846004
HS		 3754 txpower = rt2x00_get_field16(eeprom,
3755 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 3756 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 3757 power_level, txpower, delta);
e90c54b2 3758 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
5e846004 3759
e90c54b2
RJH		 3760 /*
3761 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
5e846004 3762 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 3763 * TX_PWR_CFG_4: unknown
3764 */
5e846004
HS		 3765 txpower = rt2x00_get_field16(eeprom,
3766 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 3767 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 3768 power_level, txpower, delta);
e90c54b2 3769 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
5e846004 3770
e90c54b2
RJH		 3771 /*
3772 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
5e846004 3773 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 3774 * TX_PWR_CFG_4: unknown
3775 */
5e846004
HS		 3776 txpower = rt2x00_get_field16(eeprom,
3777 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 3778 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 3779 power_level, txpower, delta);
e90c54b2 3780 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
5e846004
HS		 3781
3782 rt2800_register_write(rt2x00dev, offset, reg);
3783
3784 /* next TX_PWR_CFG register */
3785 offset += 4;
3786 }
f4450616
BZ		 3787}
3788
34542ff5
GJ		 3789static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
3790 struct ieee80211_channel *chan,
3791 int power_level)
3792{
3793 if (rt2x00_rt(rt2x00dev, RT3593))
3794 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
3795 else
3796 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
3797}
3798
9e33a355
HS		 3799void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
3800{
675a0b04 3801 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
9e33a355
HS		 3802 rt2x00dev->tx_power);
3803}
3804EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
3805
2e9c43dd
JL		 3806void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
3807{
3808 u32 tx_pin;
3809 u8 rfcsr;
3810
3811 /*
3812 * A voltage-controlled oscillator(VCO) is an electronic oscillator
3813 * designed to be controlled in oscillation frequency by a voltage
3814 * input. Maybe the temperature will affect the frequency of
3815 * oscillation to be shifted. The VCO calibration will be called
3816 * periodically to adjust the frequency to be precision.
3817 */
3818
3819 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
3820 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
3821 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3822
3823 switch (rt2x00dev->chip.rf) {
3824 case RF2020:
3825 case RF3020:
3826 case RF3021:
3827 case RF3022:
3828 case RF3320:
3829 case RF3052:
3830 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
3831 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
3832 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
3833 break;
a89534ed 3834 case RF3290:
ccf91bd6 3835 case RF5360:
2e9c43dd
JL		 3836 case RF5370:
3837 case RF5372:
3838 case RF5390:
cff3d1f0 3839 case RF5392:
2e9c43dd 3840 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
d6d82020 3841 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2e9c43dd
JL		 3842 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3843 break;
3844 default:
3845 return;
3846 }
3847
3848 mdelay(1);
3849
3850 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
3851 if (rt2x00dev->rf_channel <= 14) {
3852 switch (rt2x00dev->default_ant.tx_chain_num) {
3853 case 3:
3854 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
3855 /* fall through */
3856 case 2:
3857 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
3858 /* fall through */
3859 case 1:
3860 default:
3861 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3862 break;
3863 }
3864 } else {
3865 switch (rt2x00dev->default_ant.tx_chain_num) {
3866 case 3:
3867 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
3868 /* fall through */
3869 case 2:
3870 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
3871 /* fall through */
3872 case 1:
3873 default:
3874 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
3875 break;
3876 }
3877 }
3878 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3879
3880}
3881EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
3882
f4450616
BZ		 3883static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
3884 struct rt2x00lib_conf *libconf)
3885{
3886 u32 reg;
3887
3888 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
3889 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
3890 libconf->conf->short_frame_max_tx_count);
3891 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
3892 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 3893 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
3894}
3895
3896static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
3897 struct rt2x00lib_conf *libconf)
3898{
3899 enum dev_state state =
3900 (libconf->conf->flags & IEEE80211_CONF_PS) ?
3901 STATE_SLEEP : STATE_AWAKE;
3902 u32 reg;
3903
3904 if (state == STATE_SLEEP) {
3905 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
3906
3907 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
3908 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
3909 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
3910 libconf->conf->listen_interval - 1);
3911 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
3912 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
3913
3914 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
3915 } else {
f4450616
BZ		 3916 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
3917 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
3918 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
3919 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
3920 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 3921
3922 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 3923 }
3924}
3925
3926void rt2800_config(struct rt2x00_dev *rt2x00dev,
3927 struct rt2x00lib_conf *libconf,
3928 const unsigned int flags)
3929{
3930 /* Always recalculate LNA gain before changing configuration */
3931 rt2800_config_lna_gain(rt2x00dev, libconf);
3932
e90c54b2 3933 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
f4450616
BZ		 3934 rt2800_config_channel(rt2x00dev, libconf->conf,
3935 &libconf->rf, &libconf->channel);
675a0b04 3936 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
9e33a355 3937 libconf->conf->power_level);
e90c54b2 3938 }
f4450616 3939 if (flags & IEEE80211_CONF_CHANGE_POWER)
675a0b04 3940 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
9e33a355 3941 libconf->conf->power_level);
f4450616
BZ		 3942 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3943 rt2800_config_retry_limit(rt2x00dev, libconf);
3944 if (flags & IEEE80211_CONF_CHANGE_PS)
3945 rt2800_config_ps(rt2x00dev, libconf);
3946}
3947EXPORT_SYMBOL_GPL(rt2800_config);
3948
3949/*
3950 * Link tuning
3951 */
3952void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
3953{
3954 u32 reg;
3955
3956 /*
3957 * Update FCS error count from register.
3958 */
3959 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3960 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
3961}
3962EXPORT_SYMBOL_GPL(rt2800_link_stats);
3963
3964static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
3965{
8c6728b0
GW		 3966 u8 vgc;
3967
f4450616 3968 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
d5385bfc 3969 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 3970 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 3971 rt2x00_rt(rt2x00dev, RT3090) ||
a89534ed 3972 rt2x00_rt(rt2x00dev, RT3290) ||
adde5882 3973 rt2x00_rt(rt2x00dev, RT3390) ||
d961e447 3974 rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884 3975 rt2x00_rt(rt2x00dev, RT5390) ||
3d81535e
SG		 3976 rt2x00_rt(rt2x00dev, RT5392) ||
3977 rt2x00_rt(rt2x00dev, RT5592))
8c6728b0
GW		 3978 vgc = 0x1c + (2 * rt2x00dev->lna_gain);
3979 else
3980 vgc = 0x2e + rt2x00dev->lna_gain;
3981 } else { /* 5GHZ band */
d961e447
GW		 3982 if (rt2x00_rt(rt2x00dev, RT3572))
3983 vgc = 0x22 + (rt2x00dev->lna_gain * 5) / 3;
3d81535e
SG		 3984 else if (rt2x00_rt(rt2x00dev, RT5592))
3985 vgc = 0x24 + (2 * rt2x00dev->lna_gain);
d961e447
GW		 3986 else {
3987 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3988 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
3989 else
3990 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
3991 }
f4450616
BZ		 3992 }
3993
8c6728b0 3994 return vgc;
f4450616
BZ		 3995}
3996
3997static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
3998 struct link_qual *qual, u8 vgc_level)
3999{
4000 if (qual->vgc_level != vgc_level) {
3d81535e
SG		 4001 if (rt2x00_rt(rt2x00dev, RT5592)) {
4002 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
4003 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
4004 } else
4005 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
f4450616
BZ		 4006 qual->vgc_level = vgc_level;
4007 qual->vgc_level_reg = vgc_level;
4008 }
4009}
4010
4011void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
4012{
4013 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
4014}
4015EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
4016
4017void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
4018 const u32 count)
4019{
3d81535e
SG		 4020 u8 vgc;
4021
8d0c9b65 4022 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616 4023 return;
f4450616 4024 /*
3d81535e
SG		 4025 * When RSSI is better then -80 increase VGC level with 0x10, except
4026 * for rt5592 chip.
f4450616 4027 */
3d81535e
SG		 4028
4029 vgc = rt2800_get_default_vgc(rt2x00dev);
4030
4031 if (rt2x00_rt(rt2x00dev, RT5592) && qual->rssi > -65)
4032 vgc += 0x20;
4033 else if (qual->rssi > -80)
4034 vgc += 0x10;
4035
4036 rt2800_set_vgc(rt2x00dev, qual, vgc);
f4450616
BZ		 4037}
4038EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 4039
4040/*
4041 * Initialization functions.
4042 */
b9a07ae9 4043static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 4044{
4045 u32 reg;
d5385bfc 4046 u16 eeprom;
fcf51541 4047 unsigned int i;
e3a896b9 4048 int ret;
fcf51541 4049
f7b395e9 4050 rt2800_disable_wpdma(rt2x00dev);
a9dce149 4051
e3a896b9
GW		 4052 ret = rt2800_drv_init_registers(rt2x00dev);
4053 if (ret)
4054 return ret;
fcf51541
BZ		 4055
4056 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
4057 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
4058 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
4059 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
4060 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
4061 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
4062
4063 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
4064 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
4065 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
4066 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
4067 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
4068 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
4069
4070 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
4071 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
4072
4073 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
4074
4075 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
8544df32 4076 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
fcf51541
BZ		 4077 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
4078 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
4079 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
4080 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
4081 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
4082 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
4083
a9dce149
GW		 4084 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
4085
4086 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
4087 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
4088 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
4089 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
4090
a89534ed
WH		 4091 if (rt2x00_rt(rt2x00dev, RT3290)) {
4092 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
4093 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
4094 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
4095 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
4096 }
4097
4098 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
4099 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
4100 rt2x00_set_field32(&reg, LDO0_EN, 1);
4101 rt2x00_set_field32(&reg, LDO_BGSEL, 3);
4102 rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
4103 }
4104
4105 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
4106 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
4107 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
4108 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
4109 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
4110
4111 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
4112 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
4113 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
4114
4115 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
4116 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
4117 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
4118 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
4119 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
4120 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
4121
4122 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
4123 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
4124 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
4125 }
4126
64522957 4127 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 4128 rt2x00_rt(rt2x00dev, RT3090) ||
a89534ed 4129 rt2x00_rt(rt2x00dev, RT3290) ||
cc78e904 4130 rt2x00_rt(rt2x00dev, RT3390)) {
a89534ed
WH		 4131
4132 if (rt2x00_rt(rt2x00dev, RT3290))
4133 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4134 0x00000404);
4135 else
4136 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4137 0x00000400);
4138
fcf51541 4139 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 4140 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 4141 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4142 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3e38d3da
GJ		 4143 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4144 &eeprom);
38c8a566 4145 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 4146 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4147 0x0000002c);
4148 else
4149 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4150 0x0000000f);
4151 } else {
4152 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4153 }
d5385bfc 4154 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 4155 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 4156
4157 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4158 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4159 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
4160 } else {
4161 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4162 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4163 }
c295a81d
HS		 4164 } else if (rt2800_is_305x_soc(rt2x00dev)) {
4165 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4166 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
961636ba 4167 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
03839951
DG		 4168 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
4169 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4170 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4171 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
872834df
GW		 4172 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
4173 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4174 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1706d15d
GJ		 4175 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
4176 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4177 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4178 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
4179 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4180 &eeprom);
4181 if (rt2x00_get_field16(eeprom,
4182 EEPROM_NIC_CONF1_DAC_TEST))
4183 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4184 0x0000001f);
4185 else
4186 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4187 0x0000000f);
4188 } else {
4189 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4190 0x00000000);
4191 }
2ed71884 4192 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
7641328d
SG		 4193 rt2x00_rt(rt2x00dev, RT5392) ||
4194 rt2x00_rt(rt2x00dev, RT5592)) {
adde5882
GJ		 4195 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
4196 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4197 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
fcf51541
BZ		 4198 } else {
4199 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
4200 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4201 }
4202
4203 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
4204 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
4205 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
4206 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
4207 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
4208 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
4209 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
4210 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
4211 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
4212 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
4213
4214 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
4215 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 4216 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 4217 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
4218 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
4219
4220 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
4221 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 4222 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 4223 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 4224 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 4225 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
4226 else
4227 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
4228 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
4229 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
4230 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
4231
a9dce149
GW		 4232 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
4233 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
4234 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
4235 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
4236 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
4237 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
4238 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
4239 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
4240 rt2800_register_write(rt2x00dev, LED_CFG, reg);
4241
fcf51541
BZ		 4242 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
4243
a9dce149
GW		 4244 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4245 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
4246 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
4247 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
4248 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
4249 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
4250 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
4251 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4252
fcf51541
BZ		 4253 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
4254 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 4255 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 4256 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
4257 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 4258 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 4259 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
4260 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
4261 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
4262
4263 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 4264 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541 4265 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4266 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4267 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4268 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4269 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 4270 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 4271 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 4272 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4273 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 4274 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4275
4276 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 4277 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541 4278 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4279 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4280 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4281 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4282 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 4283 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 4284 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 4285 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4286 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 4287 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4288
4289 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4290 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
4291 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4292 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4293 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4294 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4295 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4296 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4297 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4298 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 4299 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 4300 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4301
4302 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4303 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
d13a97f0 4304 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4305 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4306 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4307 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4308 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4309 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4310 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4311 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 4312 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 4313 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4314
4315 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4316 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
4317 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4318 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4319 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4320 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4321 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4322 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4323 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4324 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 4325 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 4326 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4327
4328 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4329 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
4330 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4331 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4332 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4333 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4334 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4335 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4336 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4337 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 4338 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 4339 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4340
cea90e55 4341 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 4342 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
4343
4344 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
4345 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
4346 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
4347 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
4348 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
4349 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
4350 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
4351 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
4352 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
4353 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
4354 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
4355 }
4356
961621ab
HS		 4357 /*
4358 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
4359 * although it is reserved.
4360 */
4361 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
4362 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
4363 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
4364 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
4365 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
4366 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
4367 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
4368 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
4369 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
4370 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
4371 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
4372 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
4373
7641328d
SG		 4374 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
4375 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
fcf51541
BZ		 4376
4377 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4378 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
4379 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
4380 IEEE80211_MAX_RTS_THRESHOLD);
4381 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
4382 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4383
4384 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 4385
a21c2ab4
HS		 4386 /*
4387 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
4388 * time should be set to 16. However, the original Ralink driver uses
4389 * 16 for both and indeed using a value of 10 for CCK SIFS results in
4390 * connection problems with 11g + CTS protection. Hence, use the same
4391 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
4392 */
a9dce149 4393 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 4394 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
4395 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 4396 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
4397 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
4398 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
4399 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
4400
fcf51541
BZ		 4401 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
4402
4403 /*
4404 * ASIC will keep garbage value after boot, clear encryption keys.
4405 */
4406 for (i = 0; i < 4; i++)
4407 rt2800_register_write(rt2x00dev,
4408 SHARED_KEY_MODE_ENTRY(i), 0);
4409
4410 for (i = 0; i < 256; i++) {
d7d259d3
HS		 4411 rt2800_config_wcid(rt2x00dev, NULL, i);
4412 rt2800_delete_wcid_attr(rt2x00dev, i);
fcf51541
BZ		 4413 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
4414 }
4415
4416 /*
4417 * Clear all beacons
fcf51541 4418 */
69cf36a4
HS		 4419 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
4420 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
4421 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
4422 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
4423 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
4424 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
4425 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
4426 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
fcf51541 4427
cea90e55 4428 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 4429 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4430 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
4431 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
c6fcc0e5
RJH		 4432 } else if (rt2x00_is_pcie(rt2x00dev)) {
4433 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4434 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
4435 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 4436 }
4437
4438 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
4439 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
4440 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
4441 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
4442 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
4443 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
4444 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
4445 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
4446 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
4447 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
4448
4449 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
4450 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
4451 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
4452 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
4453 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
4454 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
4455 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
4456 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
4457 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
4458 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
4459
4460 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
4461 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
4462 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
4463 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
4464 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
4465 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
4466 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
4467 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
4468 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
4469 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
4470
4471 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
4472 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
4473 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
4474 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
4475 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
4476 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
4477
47ee3eb1
HS		 4478 /*
4479 * Do not force the BA window size, we use the TXWI to set it
4480 */
4481 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
4482 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
4483 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
4484 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
4485
fcf51541
BZ		 4486 /*
4487 * We must clear the error counters.
4488 * These registers are cleared on read,
4489 * so we may pass a useless variable to store the value.
4490 */
4491 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
4492 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
4493 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
4494 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
4495 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
4496 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
4497
9f926fb5
HS		 4498 /*
4499 * Setup leadtime for pre tbtt interrupt to 6ms
4500 */
4501 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
4502 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
4503 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
4504
977206d7
HS		 4505 /*
4506 * Set up channel statistics timer
4507 */
4508 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
4509 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
4510 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
4511 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
4512 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
4513 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
4514 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
4515
fcf51541
BZ		 4516 return 0;
4517}
fcf51541
BZ		 4518
4519static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
4520{
4521 unsigned int i;
4522 u32 reg;
4523
4524 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
4525 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
4526 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
4527 return 0;
4528
4529 udelay(REGISTER_BUSY_DELAY);
4530 }
4531
ec9c4989 4532 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
fcf51541
BZ		 4533 return -EACCES;
4534}
4535
4536static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
4537{
4538 unsigned int i;
4539 u8 value;
4540
4541 /*
4542 * BBP was enabled after firmware was loaded,
4543 * but we need to reactivate it now.
4544 */
4545 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
4546 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
4547 msleep(1);
4548
4549 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
4550 rt2800_bbp_read(rt2x00dev, 0, &value);
4551 if ((value != 0xff) && (value != 0x00))
4552 return 0;
4553 udelay(REGISTER_BUSY_DELAY);
4554 }
4555
ec9c4989 4556 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
fcf51541
BZ		 4557 return -EACCES;
4558}
4559
a7bbbe5c
SG		 4560static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
4561{
4562 u8 value;
4563
4564 rt2800_bbp_read(rt2x00dev, 4, &value);
4565 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
4566 rt2800_bbp_write(rt2x00dev, 4, value);
4567}
4568
c2675487
SG		 4569static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
4570{
4571 rt2800_bbp_write(rt2x00dev, 142, 1);
4572 rt2800_bbp_write(rt2x00dev, 143, 57);
4573}
4574
a7bbbe5c
SG		 4575static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
4576{
4577 const u8 glrt_table[] = {
4578 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
4579 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
4580 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
4581 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
4582 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
4583 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
4584 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
4585 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
4586 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */
4587 };
4588 int i;
4589
4590 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
4591 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
4592 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
4593 }
4594};
4595
624708b8 4596static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
a4969d0d
SG		 4597{
4598 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
4599 rt2800_bbp_write(rt2x00dev, 66, 0x38);
4600 rt2800_bbp_write(rt2x00dev, 68, 0x0B);
4601 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4602 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4603 rt2800_bbp_write(rt2x00dev, 73, 0x10);
4604 rt2800_bbp_write(rt2x00dev, 81, 0x37);
4605 rt2800_bbp_write(rt2x00dev, 82, 0x62);
4606 rt2800_bbp_write(rt2x00dev, 83, 0x6A);
4607 rt2800_bbp_write(rt2x00dev, 84, 0x99);
4608 rt2800_bbp_write(rt2x00dev, 86, 0x00);
4609 rt2800_bbp_write(rt2x00dev, 91, 0x04);
4610 rt2800_bbp_write(rt2x00dev, 92, 0x00);
4611 rt2800_bbp_write(rt2x00dev, 103, 0x00);
4612 rt2800_bbp_write(rt2x00dev, 105, 0x05);
4613 rt2800_bbp_write(rt2x00dev, 106, 0x35);
4614}
4615
5df1ff3a
SG		 4616static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
4617{
4618 u16 eeprom;
4619 u8 value;
4620
4621 rt2800_bbp_read(rt2x00dev, 138, &value);
3e38d3da 4622 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5df1ff3a
SG		 4623 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4624 value |= 0x20;
4625 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4626 value &= ~0x02;
4627 rt2800_bbp_write(rt2x00dev, 138, value);
4628}
4629
dae62957
SG		 4630static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
4631{
b2f8e0bd 4632 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 4633
4634 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4635 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 4636
4637 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4638 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 4639
4640 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 4641
4642 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
4643 rt2800_bbp_write(rt2x00dev, 80, 0x08);
fa1e3424
SG		 4644
4645 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 4646
4647 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 4648
4649 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 4650
4651 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 4652
4653 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 4654
4655 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 4656
4657 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
49d61118
SG		 4658
4659 rt2800_bbp_write(rt2x00dev, 105, 0x01);
f867085e
SG		 4660
4661 rt2800_bbp_write(rt2x00dev, 106, 0x35);
dae62957
SG		 4662}
4663
39ab3e8b
SG		 4664static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
4665{
e379de12
SG		 4666 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4667 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 4668
4669 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
4670 rt2800_bbp_write(rt2x00dev, 69, 0x16);
4671 rt2800_bbp_write(rt2x00dev, 73, 0x12);
4672 } else {
4673 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4674 rt2800_bbp_write(rt2x00dev, 73, 0x10);
4675 }
8d97be38
SG		 4676
4677 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 4678
4679 rt2800_bbp_write(rt2x00dev, 81, 0x37);
fa1e3424
SG		 4680
4681 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 4682
4683 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 4684
4685 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
4686 rt2800_bbp_write(rt2x00dev, 84, 0x19);
4687 else
4688 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 4689
4690 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 4691
4692 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 4693
4694 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 4695
4696 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 4697
4698 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 4699
4700 rt2800_bbp_write(rt2x00dev, 106, 0x35);
39ab3e8b
SG		 4701}
4702
4703static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
4704{
e379de12
SG		 4705 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4706 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 4707
4708 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4709 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 4710
4711 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 4712
4713 rt2800_bbp_write(rt2x00dev, 79, 0x13);
4714 rt2800_bbp_write(rt2x00dev, 80, 0x05);
4715 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 4716
4717 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 4718
4719 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 4720
4721 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 4722
4723 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 4724
4725 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 4726
4727 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 4728
4729 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
4730 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
4731 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
4732 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4733 else
4734 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 4735
4736 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 4737
4738 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 4739
4740 if (rt2x00_rt(rt2x00dev, RT3071) ||
4741 rt2x00_rt(rt2x00dev, RT3090))
4742 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 4743}
4744
4745static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
4746{
6addb24e
SG		 4747 u8 value;
4748
c3223573 4749 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
b2f8e0bd
SG		 4750
4751 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 4752
4753 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4754 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 4755
4756 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142
SG		 4757
4758 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4759 rt2800_bbp_write(rt2x00dev, 73, 0x13);
4760 rt2800_bbp_write(rt2x00dev, 75, 0x46);
4761 rt2800_bbp_write(rt2x00dev, 76, 0x28);
4762
4763 rt2800_bbp_write(rt2x00dev, 77, 0x58);
8d97be38
SG		 4764
4765 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 4766
4767 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
4768 rt2800_bbp_write(rt2x00dev, 79, 0x18);
4769 rt2800_bbp_write(rt2x00dev, 80, 0x09);
4770 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 4771
4772 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 4773
4774 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3c20a122
SG		 4775
4776 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
aef9f38b
SG		 4777
4778 rt2800_bbp_write(rt2x00dev, 86, 0x38);
7af98742
SG		 4779
4780 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 4781
4782 rt2800_bbp_write(rt2x00dev, 92, 0x02);
672d1188
SG		 4783
4784 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 4785
4786 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118
SG		 4787
4788 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
f867085e
SG		 4789
4790 rt2800_bbp_write(rt2x00dev, 106, 0x03);
f2b6777c
SG		 4791
4792 rt2800_bbp_write(rt2x00dev, 128, 0x12);
6addb24e
SG		 4793
4794 rt2800_bbp_write(rt2x00dev, 67, 0x24);
4795 rt2800_bbp_write(rt2x00dev, 143, 0x04);
4796 rt2800_bbp_write(rt2x00dev, 142, 0x99);
4797 rt2800_bbp_write(rt2x00dev, 150, 0x30);
4798 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
4799 rt2800_bbp_write(rt2x00dev, 152, 0x20);
4800 rt2800_bbp_write(rt2x00dev, 153, 0x34);
4801 rt2800_bbp_write(rt2x00dev, 154, 0x40);
4802 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
4803 rt2800_bbp_write(rt2x00dev, 253, 0x04);
4804
4805 rt2800_bbp_read(rt2x00dev, 47, &value);
4806 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
4807 rt2800_bbp_write(rt2x00dev, 47, value);
4808
4809 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
4810 rt2800_bbp_read(rt2x00dev, 3, &value);
4811 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
4812 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
4813 rt2800_bbp_write(rt2x00dev, 3, value);
39ab3e8b
SG		 4814}
4815
4816static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
4817{
29f3a58b
SG		 4818 rt2800_bbp_write(rt2x00dev, 3, 0x00);
4819 rt2800_bbp_write(rt2x00dev, 4, 0x50);
b2f8e0bd
SG		 4820
4821 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3420f797
SG		 4822
4823 rt2800_bbp_write(rt2x00dev, 47, 0x48);
e379de12
SG		 4824
4825 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4826 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 4827
4828 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142
SG		 4829
4830 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4831 rt2800_bbp_write(rt2x00dev, 73, 0x13);
4832 rt2800_bbp_write(rt2x00dev, 75, 0x46);
4833 rt2800_bbp_write(rt2x00dev, 76, 0x28);
4834
4835 rt2800_bbp_write(rt2x00dev, 77, 0x59);
8d97be38
SG		 4836
4837 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 4838
4839 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
4840 rt2800_bbp_write(rt2x00dev, 80, 0x08);
4841 rt2800_bbp_write(rt2x00dev, 81, 0x37);
fa1e3424
SG		 4842
4843 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 4844
4845 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 4846
4847 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 4848
4849 rt2800_bbp_write(rt2x00dev, 86, 0x38);
9400fa87
SG		 4850
4851 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7af98742
SG		 4852
4853 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 4854
4855 rt2800_bbp_write(rt2x00dev, 92, 0x02);
672d1188
SG		 4856
4857 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 4858
4859 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118
SG		 4860
4861 rt2800_bbp_write(rt2x00dev, 105, 0x34);
f867085e
SG		 4862
4863 rt2800_bbp_write(rt2x00dev, 106, 0x05);
46b90d32
SG		 4864
4865 rt2800_bbp_write(rt2x00dev, 120, 0x50);
b7feb9ba
SG		 4866
4867 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
c2da5273
SG		 4868
4869 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
4870 /* Set ITxBF timeout to 0x9c40=1000msec */
4871 rt2800_bbp_write(rt2x00dev, 179, 0x02);
4872 rt2800_bbp_write(rt2x00dev, 180, 0x00);
4873 rt2800_bbp_write(rt2x00dev, 182, 0x40);
4874 rt2800_bbp_write(rt2x00dev, 180, 0x01);
4875 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
4876 rt2800_bbp_write(rt2x00dev, 179, 0x00);
4877 /* Reprogram the inband interface to put right values in RXWI */
4878 rt2800_bbp_write(rt2x00dev, 142, 0x04);
4879 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
4880 rt2800_bbp_write(rt2x00dev, 142, 0x06);
4881 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
4882 rt2800_bbp_write(rt2x00dev, 142, 0x07);
4883 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
4884 rt2800_bbp_write(rt2x00dev, 142, 0x08);
4885 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
4886
4887 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
39ab3e8b
SG		 4888}
4889
4890static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
4891{
e379de12
SG		 4892 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4893 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 4894
4895 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4896 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 4897
4898 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 4899
4900 rt2800_bbp_write(rt2x00dev, 79, 0x13);
4901 rt2800_bbp_write(rt2x00dev, 80, 0x05);
4902 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 4903
4904 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 4905
4906 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 4907
4908 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 4909
4910 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 4911
4912 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 4913
4914 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 4915
4916 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
4917 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4918 else
4919 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 4920
4921 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 4922
4923 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 4924
4925 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 4926}
4927
4928static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
4929{
b2f8e0bd 4930 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 4931
4932 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4933 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 4934
4935 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4936 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 4937
4938 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 4939
4940 rt2800_bbp_write(rt2x00dev, 79, 0x13);
4941 rt2800_bbp_write(rt2x00dev, 80, 0x05);
4942 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 4943
4944 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 4945
4946 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 4947
4948 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 4949
4950 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 4951
4952 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 4953
4954 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 4955
4956 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
49d61118
SG		 4957
4958 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 4959
4960 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 4961
4962 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 4963}
4964
b189a181
GJ		 4965static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
4966{
4967 rt2800_init_bbp_early(rt2x00dev);
4968
4969 rt2800_bbp_write(rt2x00dev, 79, 0x13);
4970 rt2800_bbp_write(rt2x00dev, 80, 0x05);
4971 rt2800_bbp_write(rt2x00dev, 81, 0x33);
4972 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
4973
4974 rt2800_bbp_write(rt2x00dev, 84, 0x19);
4975
4976 /* Enable DC filter */
4977 if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
4978 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4979}
4980
39ab3e8b
SG		 4981static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
4982{
32ef8f49
SG		 4983 int ant, div_mode;
4984 u16 eeprom;
4985 u8 value;
4986
c3223573 4987 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
b2f8e0bd
SG		 4988
4989 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 4990
4991 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4992 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 4993
4994 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142
SG		 4995
4996 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4997 rt2800_bbp_write(rt2x00dev, 73, 0x13);
4998 rt2800_bbp_write(rt2x00dev, 75, 0x46);
4999 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5000
5001 rt2800_bbp_write(rt2x00dev, 77, 0x59);
8d97be38
SG		 5002
5003 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5004
5005 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5006 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5007 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5008
5009 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5010
5011 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3c20a122
SG		 5012
5013 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
aef9f38b
SG		 5014
5015 rt2800_bbp_write(rt2x00dev, 86, 0x38);
9400fa87
SG		 5016
5017 if (rt2x00_rt(rt2x00dev, RT5392))
5018 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7af98742
SG		 5019
5020 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5021
5022 rt2800_bbp_write(rt2x00dev, 92, 0x02);
90fed535
SG		 5023
5024 if (rt2x00_rt(rt2x00dev, RT5392)) {
5025 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5026 rt2800_bbp_write(rt2x00dev, 98, 0x12);
5027 }
672d1188
SG		 5028
5029 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 5030
5031 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118
SG		 5032
5033 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
f867085e
SG		 5034
5035 if (rt2x00_rt(rt2x00dev, RT5390))
5036 rt2800_bbp_write(rt2x00dev, 106, 0x03);
5037 else if (rt2x00_rt(rt2x00dev, RT5392))
5038 rt2800_bbp_write(rt2x00dev, 106, 0x12);
5039 else
5040 WARN_ON(1);
f2b6777c
SG		 5041
5042 rt2800_bbp_write(rt2x00dev, 128, 0x12);
72917140
SG		 5043
5044 if (rt2x00_rt(rt2x00dev, RT5392)) {
5045 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
5046 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
5047 }
5df1ff3a
SG		 5048
5049 rt2800_disable_unused_dac_adc(rt2x00dev);
32ef8f49 5050
3e38d3da 5051 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
32ef8f49
SG		 5052 div_mode = rt2x00_get_field16(eeprom,
5053 EEPROM_NIC_CONF1_ANT_DIVERSITY);
5054 ant = (div_mode == 3) ? 1 : 0;
5055
5056 /* check if this is a Bluetooth combo card */
5057 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
5058 u32 reg;
5059
5060 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
5061 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
5062 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
5063 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
5064 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
5065 if (ant == 0)
5066 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
5067 else if (ant == 1)
5068 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
5069 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
5070 }
5071
5072 /* This chip has hardware antenna diversity*/
5073 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
5074 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
5075 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
5076 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
5077 }
5078
5079 rt2800_bbp_read(rt2x00dev, 152, &value);
5080 if (ant == 0)
5081 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5082 else
5083 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5084 rt2800_bbp_write(rt2x00dev, 152, value);
5085
5086 rt2800_init_freq_calibration(rt2x00dev);
39ab3e8b
SG		 5087}
5088
a7bbbe5c
SG		 5089static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
5090{
5091 int ant, div_mode;
5092 u16 eeprom;
5093 u8 value;
5094
624708b8 5095 rt2800_init_bbp_early(rt2x00dev);
a4969d0d 5096
a7bbbe5c
SG		 5097 rt2800_bbp_read(rt2x00dev, 105, &value);
5098 rt2x00_set_field8(&value, BBP105_MLD,
5099 rt2x00dev->default_ant.rx_chain_num == 2);
5100 rt2800_bbp_write(rt2x00dev, 105, value);
5101
5102 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5103
5104 rt2800_bbp_write(rt2x00dev, 20, 0x06);
5105 rt2800_bbp_write(rt2x00dev, 31, 0x08);
5106 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5107 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
5108 rt2800_bbp_write(rt2x00dev, 69, 0x1A);
5109 rt2800_bbp_write(rt2x00dev, 70, 0x05);
5110 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5111 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
5112 rt2800_bbp_write(rt2x00dev, 75, 0x4F);
5113 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5114 rt2800_bbp_write(rt2x00dev, 77, 0x59);
5115 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
5116 rt2800_bbp_write(rt2x00dev, 86, 0x38);
5117 rt2800_bbp_write(rt2x00dev, 88, 0x90);
5118 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5119 rt2800_bbp_write(rt2x00dev, 92, 0x02);
5120 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5121 rt2800_bbp_write(rt2x00dev, 98, 0x12);
5122 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
5123 rt2800_bbp_write(rt2x00dev, 104, 0x92);
5124 /* FIXME BBP105 owerwrite */
5125 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
5126 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5127 rt2800_bbp_write(rt2x00dev, 128, 0x12);
5128 rt2800_bbp_write(rt2x00dev, 134, 0xD0);
5129 rt2800_bbp_write(rt2x00dev, 135, 0xF6);
5130 rt2800_bbp_write(rt2x00dev, 137, 0x0F);
5131
5132 /* Initialize GLRT (Generalized Likehood Radio Test) */
5133 rt2800_init_bbp_5592_glrt(rt2x00dev);
5134
5135 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5136
3e38d3da 5137 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
a7bbbe5c
SG		 5138 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
5139 ant = (div_mode == 3) ? 1 : 0;
5140 rt2800_bbp_read(rt2x00dev, 152, &value);
5141 if (ant == 0) {
5142 /* Main antenna */
5143 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5144 } else {
5145 /* Auxiliary antenna */
5146 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5147 }
5148 rt2800_bbp_write(rt2x00dev, 152, value);
5149
5150 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
5151 rt2800_bbp_read(rt2x00dev, 254, &value);
5152 rt2x00_set_field8(&value, BBP254_BIT7, 1);
5153 rt2800_bbp_write(rt2x00dev, 254, value);
5154 }
5155
c2675487
SG		 5156 rt2800_init_freq_calibration(rt2x00dev);
5157
a7bbbe5c 5158 rt2800_bbp_write(rt2x00dev, 84, 0x19);
6e04f253
SG		 5159 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
5160 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
a7bbbe5c
SG		 5161}
5162
a1ef5039 5163static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 5164{
5165 unsigned int i;
5166 u16 eeprom;
5167 u8 reg_id;
5168 u8 value;
5169
dae62957
SG		 5170 if (rt2800_is_305x_soc(rt2x00dev))
5171 rt2800_init_bbp_305x_soc(rt2x00dev);
5172
39ab3e8b
SG		 5173 switch (rt2x00dev->chip.rt) {
5174 case RT2860:
5175 case RT2872:
5176 case RT2883:
5177 rt2800_init_bbp_28xx(rt2x00dev);
5178 break;
5179 case RT3070:
5180 case RT3071:
5181 case RT3090:
5182 rt2800_init_bbp_30xx(rt2x00dev);
5183 break;
5184 case RT3290:
5185 rt2800_init_bbp_3290(rt2x00dev);
5186 break;
5187 case RT3352:
5188 rt2800_init_bbp_3352(rt2x00dev);
5189 break;
5190 case RT3390:
5191 rt2800_init_bbp_3390(rt2x00dev);
5192 break;
5193 case RT3572:
5194 rt2800_init_bbp_3572(rt2x00dev);
5195 break;
b189a181
GJ		 5196 case RT3593:
5197 rt2800_init_bbp_3593(rt2x00dev);
5198 return;
39ab3e8b
SG		 5199 case RT5390:
5200 case RT5392:
5201 rt2800_init_bbp_53xx(rt2x00dev);
5202 break;
5203 case RT5592:
a7bbbe5c 5204 rt2800_init_bbp_5592(rt2x00dev);
a1ef5039 5205 return;
a7bbbe5c
SG		 5206 }
5207
fcf51541 5208 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
022138ca
GJ		 5209 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_BBP_START, i,
5210 &eeprom);
fcf51541
BZ		 5211
5212 if (eeprom != 0xffff && eeprom != 0x0000) {
5213 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
5214 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
5215 rt2800_bbp_write(rt2x00dev, reg_id, value);
5216 }
5217 }
fcf51541 5218}
fcf51541 5219
d9517f2f
SG		 5220static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
5221{
5222 u32 reg;
5223
5224 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
5225 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
5226 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
5227}
5228
c5b3c350
SG		 5229static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
5230 u8 filter_target)
fcf51541
BZ		 5231{
5232 unsigned int i;
5233 u8 bbp;
5234 u8 rfcsr;
5235 u8 passband;
5236 u8 stopband;
5237 u8 overtuned = 0;
c5b3c350 5238 u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
fcf51541
BZ		 5239
5240 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5241
5242 rt2800_bbp_read(rt2x00dev, 4, &bbp);
5243 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
5244 rt2800_bbp_write(rt2x00dev, 4, bbp);
5245
80d184e6
RJH		 5246 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
5247 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
5248 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
5249
fcf51541
BZ		 5250 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5251 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
5252 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5253
5254 /*
5255 * Set power & frequency of passband test tone
5256 */
5257 rt2800_bbp_write(rt2x00dev, 24, 0);
5258
5259 for (i = 0; i < 100; i++) {
5260 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5261 msleep(1);
5262
5263 rt2800_bbp_read(rt2x00dev, 55, &passband);
5264 if (passband)
5265 break;
5266 }
5267
5268 /*
5269 * Set power & frequency of stopband test tone
5270 */
5271 rt2800_bbp_write(rt2x00dev, 24, 0x06);
5272
5273 for (i = 0; i < 100; i++) {
5274 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5275 msleep(1);
5276
5277 rt2800_bbp_read(rt2x00dev, 55, &stopband);
5278
5279 if ((passband - stopband) <= filter_target) {
5280 rfcsr24++;
5281 overtuned += ((passband - stopband) == filter_target);
5282 } else
5283 break;
5284
5285 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5286 }
5287
5288 rfcsr24 -= !!overtuned;
5289
5290 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5291 return rfcsr24;
5292}
5293
ce94ede9
SG		 5294static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
5295 const unsigned int rf_reg)
5296{
5297 u8 rfcsr;
5298
5299 rt2800_rfcsr_read(rt2x00dev, rf_reg, &rfcsr);
5300 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
5301 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5302 msleep(1);
5303 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
5304 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5305}
5306
c5b3c350
SG		 5307static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
5308{
5309 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5310 u8 filter_tgt_bw20;
5311 u8 filter_tgt_bw40;
5312 u8 rfcsr, bbp;
5313
5314 /*
5315 * TODO: sync filter_tgt values with vendor driver
5316 */
5317 if (rt2x00_rt(rt2x00dev, RT3070)) {
5318 filter_tgt_bw20 = 0x16;
5319 filter_tgt_bw40 = 0x19;
5320 } else {
5321 filter_tgt_bw20 = 0x13;
5322 filter_tgt_bw40 = 0x15;
5323 }
5324
5325 drv_data->calibration_bw20 =
5326 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
5327 drv_data->calibration_bw40 =
5328 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
5329
5330 /*
5331 * Save BBP 25 & 26 values for later use in channel switching (for 3052)
5332 */
5333 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
5334 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
5335
5336 /*
5337 * Set back to initial state
5338 */
5339 rt2800_bbp_write(rt2x00dev, 24, 0);
5340
5341 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5342 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
5343 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5344
5345 /*
5346 * Set BBP back to BW20
5347 */
5348 rt2800_bbp_read(rt2x00dev, 4, &bbp);
5349 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
5350 rt2800_bbp_write(rt2x00dev, 4, bbp);
5351}
5352
da8064c2
SG		 5353static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
5354{
5355 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5356 u8 min_gain, rfcsr, bbp;
5357 u16 eeprom;
5358
5359 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
5360
5361 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
5362 if (rt2x00_rt(rt2x00dev, RT3070) ||
5363 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5364 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5365 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
5366 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags))
5367 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
5368 }
5369
5370 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
5371 if (drv_data->txmixer_gain_24g >= min_gain) {
5372 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
5373 drv_data->txmixer_gain_24g);
5374 }
5375
5376 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
5377
5378 if (rt2x00_rt(rt2x00dev, RT3090)) {
5379 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
5380 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3e38d3da 5381 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
da8064c2
SG		 5382 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5383 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
5384 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5385 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
5386 rt2800_bbp_write(rt2x00dev, 138, bbp);
5387 }
5388
5389 if (rt2x00_rt(rt2x00dev, RT3070)) {
5390 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
5391 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
5392 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
5393 else
5394 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
5395 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
5396 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
5397 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
5398 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
5399 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
5400 rt2x00_rt(rt2x00dev, RT3090) ||
5401 rt2x00_rt(rt2x00dev, RT3390)) {
5402 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5403 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5404 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
5405 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
5406 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
5407 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
5408 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5409
5410 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
5411 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
5412 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
5413
5414 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
5415 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
5416 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
5417
5418 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
5419 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
5420 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
5421 }
5422}
5423
ab7078ac
GJ		 5424static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
5425{
5426 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5427 u8 rfcsr;
5428 u8 tx_gain;
5429
5430 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
5431 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
5432 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
5433
5434 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
5435 tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
5436 RFCSR17_TXMIXER_GAIN);
5437 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
5438 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
5439
5440 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
5441 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
5442 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
5443
5444 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
5445 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
5446 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
5447
5448 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5449 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5450 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
5451 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5452
5453 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
5454 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
5455 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
5456
5457 /* TODO: enable stream mode */
5458}
5459
f7df8fe5
SG		 5460static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
5461{
5462 u8 reg;
5463 u16 eeprom;
5464
5465 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
5466 rt2800_bbp_read(rt2x00dev, 138, &reg);
3e38d3da 5467 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
f7df8fe5
SG		 5468 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5469 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
5470 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5471 rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
5472 rt2800_bbp_write(rt2x00dev, 138, reg);
5473
5474 rt2800_rfcsr_read(rt2x00dev, 38, &reg);
5475 rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
5476 rt2800_rfcsr_write(rt2x00dev, 38, reg);
5477
5478 rt2800_rfcsr_read(rt2x00dev, 39, &reg);
5479 rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
5480 rt2800_rfcsr_write(rt2x00dev, 39, reg);
5481
5482 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5483
5484 rt2800_rfcsr_read(rt2x00dev, 30, &reg);
5485 rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
5486 rt2800_rfcsr_write(rt2x00dev, 30, reg);
5487}
5488
d5374ef1
SG		 5489static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
5490{
ce94ede9
SG		 5491 rt2800_rf_init_calibration(rt2x00dev, 30);
5492
d5374ef1
SG		 5493 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
5494 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
5495 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
5496 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
5497 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
5498 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
5499 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
5500 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
5501 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
5502 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
5503 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
5504 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
5505 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
5506 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
5507 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
5508 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
5509 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
5510 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
5511 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
5512 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
5513 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
5514 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
5515 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
5516 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
5517 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
5518 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
5519 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
5520 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
5521 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
5522 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
5523 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
5524 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
5525}
5526
5527static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
5528{
c9a221b2
SG		 5529 u8 rfcsr;
5530 u16 eeprom;
5531 u32 reg;
5532
ce94ede9
SG		 5533 /* XXX vendor driver do this only for 3070 */
5534 rt2800_rf_init_calibration(rt2x00dev, 30);
5535
d5374ef1
SG		 5536 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
5537 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
5538 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
5539 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
5540 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
5541 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
5542 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
5543 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
5544 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
5545 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
5546 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
5547 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
5548 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
5549 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
5550 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
5551 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
5552 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
5553 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
5554 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
c9a221b2
SG		 5555
5556 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
5557 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
5558 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
5559 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
5560 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
5561 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
5562 rt2x00_rt(rt2x00dev, RT3090)) {
5563 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
5564
5565 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
5566 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
5567 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
5568
5569 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
5570 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
5571 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5572 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
3e38d3da
GJ		 5573 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
5574 &eeprom);
c9a221b2
SG		 5575 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
5576 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
5577 else
5578 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
5579 }
5580 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
5581
5582 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
5583 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
5584 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
5585 }
c5b3c350
SG		 5586
5587 rt2800_rx_filter_calibration(rt2x00dev);
5de5a1f4
SG		 5588
5589 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
5590 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5591 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
5592 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 5593
5594 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 5595 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 5596}
5597
5598static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
5599{
f9cdcbb1
SG		 5600 u8 rfcsr;
5601
ce94ede9
SG		 5602 rt2800_rf_init_calibration(rt2x00dev, 2);
5603
d5374ef1
SG		 5604 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
5605 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
5606 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
5607 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
5608 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
5609 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
5610 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
5611 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
5612 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
5613 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
5614 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
5615 rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
5616 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
5617 rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
5618 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
5619 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
5620 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
5621 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
5622 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
5623 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
5624 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
5625 rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
5626 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
5627 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
5628 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
5629 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
5630 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
5631 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
5632 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
5633 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
5634 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
5635 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
5636 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
5637 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
5638 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
5639 rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
5640 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
5641 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
5642 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
5643 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
5644 rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
5645 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
5646 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
5647 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
5648 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
5649 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
f9cdcbb1
SG		 5650
5651 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
5652 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
5653 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
d9517f2f
SG		 5654
5655 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 5656 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 5657}
5658
5659static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
5660{
ce94ede9
SG		 5661 rt2800_rf_init_calibration(rt2x00dev, 30);
5662
d5374ef1
SG		 5663 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
5664 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
5665 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
5666 rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
5667 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
5668 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
5669 rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
5670 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
5671 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
5672 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
5673 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
5674 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
5675 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
5676 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
5677 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
5678 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
5679 rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
5680 rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
5681 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
5682 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
5683 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
5684 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
5685 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
5686 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
5687 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
5688 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
5689 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
5690 rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
5691 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
5692 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
5693 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
5694 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
5695 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
5696 rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
5697 rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
5698 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
5699 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
5700 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
5701 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
5702 rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
5703 rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
5704 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
5705 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
5706 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
5707 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
5708 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
5709 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
5710 rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
5711 rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
5712 rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
5713 rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
5714 rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
5715 rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
5716 rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
5717 rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
5718 rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
5719 rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
5720 rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
5721 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
5722 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
5723 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
5724 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
5725 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
c5b3c350
SG		 5726
5727 rt2800_rx_filter_calibration(rt2x00dev);
d9517f2f 5728 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 5729 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 5730}
5731
5732static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
5733{
2971e66f
SG		 5734 u32 reg;
5735
ce94ede9
SG		 5736 rt2800_rf_init_calibration(rt2x00dev, 30);
5737
d5374ef1
SG		 5738 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
5739 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
5740 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
5741 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
5742 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
5743 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
5744 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
5745 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
5746 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
5747 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
5748 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
5749 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
5750 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
5751 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
5752 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
5753 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
5754 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
5755 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
5756 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
5757 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
5758 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
5759 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
5760 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
5761 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
5762 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
5763 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
5764 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
5765 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
5766 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
5767 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
5768 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
5769 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
2971e66f
SG		 5770
5771 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
5772 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
5773 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
c5b3c350
SG		 5774
5775 rt2800_rx_filter_calibration(rt2x00dev);
5de5a1f4
SG		 5776
5777 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
5778 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 5779
5780 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 5781 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 5782}
5783
5784static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
5785{
87d91db9
SG		 5786 u8 rfcsr;
5787 u32 reg;
5788
ce94ede9
SG		 5789 rt2800_rf_init_calibration(rt2x00dev, 30);
5790
d5374ef1
SG		 5791 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
5792 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
5793 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
5794 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
5795 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
5796 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
5797 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
5798 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
5799 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
5800 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
5801 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
5802 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
5803 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
5804 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
5805 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
5806 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
5807 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
5808 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
5809 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
5810 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
5811 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
5812 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
5813 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
5814 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
5815 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
5816 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
5817 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
5818 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
5819 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
5820 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
5821 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
87d91db9
SG		 5822
5823 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
5824 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
5825 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
5826
5827 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
5828 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
5829 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
5830 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
5831 msleep(1);
5832 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
5833 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
5834 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
5835 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
c5b3c350
SG		 5836
5837 rt2800_rx_filter_calibration(rt2x00dev);
d9517f2f 5838 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 5839 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 5840}
5841
d63f7e8c
GJ		 5842static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
5843{
5844 u8 bbp;
5845 bool txbf_enabled = false; /* FIXME */
5846
5847 rt2800_bbp_read(rt2x00dev, 105, &bbp);
5848 if (rt2x00dev->default_ant.rx_chain_num == 1)
5849 rt2x00_set_field8(&bbp, BBP105_MLD, 0);
5850 else
5851 rt2x00_set_field8(&bbp, BBP105_MLD, 1);
5852 rt2800_bbp_write(rt2x00dev, 105, bbp);
5853
5854 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5855
5856 rt2800_bbp_write(rt2x00dev, 92, 0x02);
5857 rt2800_bbp_write(rt2x00dev, 82, 0x82);
5858 rt2800_bbp_write(rt2x00dev, 106, 0x05);
5859 rt2800_bbp_write(rt2x00dev, 104, 0x92);
5860 rt2800_bbp_write(rt2x00dev, 88, 0x90);
5861 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
5862 rt2800_bbp_write(rt2x00dev, 47, 0x48);
5863 rt2800_bbp_write(rt2x00dev, 120, 0x50);
5864
5865 if (txbf_enabled)
5866 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
5867 else
5868 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
5869
5870 /* SNR mapping */
5871 rt2800_bbp_write(rt2x00dev, 142, 6);
5872 rt2800_bbp_write(rt2x00dev, 143, 160);
5873 rt2800_bbp_write(rt2x00dev, 142, 7);
5874 rt2800_bbp_write(rt2x00dev, 143, 161);
5875 rt2800_bbp_write(rt2x00dev, 142, 8);
5876 rt2800_bbp_write(rt2x00dev, 143, 162);
5877
5878 /* ADC/DAC control */
5879 rt2800_bbp_write(rt2x00dev, 31, 0x08);
5880
5881 /* RX AGC energy lower bound in log2 */
5882 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5883
5884 /* FIXME: BBP 105 owerwrite? */
5885 rt2800_bbp_write(rt2x00dev, 105, 0x04);
5886}
5887
ab7078ac
GJ		 5888static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
5889{
5890 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5891 u32 reg;
5892 u8 rfcsr;
5893
5894 /* Disable GPIO #4 and #7 function for LAN PE control */
5895 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
5896 rt2x00_set_field32(&reg, GPIO_SWITCH_4, 0);
5897 rt2x00_set_field32(&reg, GPIO_SWITCH_7, 0);
5898 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
5899
5900 /* Initialize default register values */
5901 rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
5902 rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
5903 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
5904 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
5905 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
5906 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
5907 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
5908 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
5909 rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
5910 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
5911 rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
5912 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
5913 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
5914 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
5915 rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
5916 rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
5917 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
5918 rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
5919 rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
5920 rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
5921 rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
5922 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
5923 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
5924 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
5925 rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
5926 rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
5927 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
5928 rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
5929 rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
5930 rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
5931 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
5932 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
5933
5934 /* Initiate calibration */
5935 /* TODO: use rt2800_rf_init_calibration ? */
5936 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
5937 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
5938 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
5939
5940 rt2800_adjust_freq_offset(rt2x00dev);
5941
5942 rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr);
5943 rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
5944 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
5945
5946 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
5947 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
5948 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
5949 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
5950 usleep_range(1000, 1500);
5951 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
5952 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
5953 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
5954
5955 /* Set initial values for RX filter calibration */
5956 drv_data->calibration_bw20 = 0x1f;
5957 drv_data->calibration_bw40 = 0x2f;
5958
5959 /* Save BBP 25 & 26 values for later use in channel switching */
5960 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
5961 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
5962
5963 rt2800_led_open_drain_enable(rt2x00dev);
5964 rt2800_normal_mode_setup_3593(rt2x00dev);
5965
d63f7e8c 5966 rt3593_post_bbp_init(rt2x00dev);
ab7078ac
GJ		 5967
5968 /* TODO: enable stream mode support */
5969}
5970
d5374ef1
SG		 5971static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
5972{
ce94ede9
SG		 5973 rt2800_rf_init_calibration(rt2x00dev, 2);
5974
d5374ef1
SG		 5975 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
5976 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
5977 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
5978 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
5979 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
5980 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
5981 else
5982 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
5983 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
5984 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
5985 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
5986 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
5987 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
5988 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
5989 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
5990 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
5991 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
5992 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
5993
5994 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
5995 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
5996 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
5997 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
5998 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
5999 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6000 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6001 else
6002 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
6003 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
6004 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6005 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6006 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6007
6008 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
6009 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6010 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6011 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6012 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6013 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6014 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6015 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6016 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
6017 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6018
6019 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6020 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
6021 else
6022 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
6023 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6024 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
6025 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
6026 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6027 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6028 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6029 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6030 else
6031 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
6032 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
6033 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6034 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6035
6036 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
6037 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6038 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6039 else
6040 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
6041 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6042 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
6043 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
6044 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6045 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
6046 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
6047
6048 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6049 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6050 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
6051 else
6052 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
6053 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6054 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
f7df8fe5
SG		 6055
6056 rt2800_normal_mode_setup_5xxx(rt2x00dev);
d9517f2f
SG		 6057
6058 rt2800_led_open_drain_enable(rt2x00dev);
d5374ef1
SG		 6059}
6060
6061static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
6062{
ce94ede9
SG		 6063 rt2800_rf_init_calibration(rt2x00dev, 2);
6064
d5374ef1
SG		 6065 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
6066 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6067 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6068 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6069 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6070 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6071 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6072 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6073 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6074 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6075 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6076 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6077 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6078 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6079 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
6080 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6081 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
6082 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6083 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
6084 rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
6085 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6086 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6087 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6088 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6089 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6090 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6091 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6092 rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
6093 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6094 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6095 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6096 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6097 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6098 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
6099 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6100 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
6101 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6102 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6103 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
6104 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6105 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6106 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6107 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
6108 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6109 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6110 rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
6111 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
6112 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
6113 rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
6114 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
6115 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6116 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
6117 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
6118 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
6119 rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
6120 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6121 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
6122 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
6123 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
f7df8fe5
SG		 6124
6125 rt2800_normal_mode_setup_5xxx(rt2x00dev);
d9517f2f
SG		 6126
6127 rt2800_led_open_drain_enable(rt2x00dev);
d5374ef1
SG		 6128}
6129
0c9e5fb9
SG		 6130static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
6131{
ce94ede9
SG		 6132 rt2800_rf_init_calibration(rt2x00dev, 30);
6133
0c9e5fb9
SG		 6134 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
6135 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6136 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6137 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6138 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
6139 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6140 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6141 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6142 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6143 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6144 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
6145 rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
6146 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
6147 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6148 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6149 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6150 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6151 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6152 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6153 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
6154 rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
6155 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
6156
6157 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6158 msleep(1);
6159
6160 rt2800_adjust_freq_offset(rt2x00dev);
c630ccf1 6161
c630ccf1
SG		 6162 /* Enable DC filter */
6163 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
6164 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6165
f7df8fe5 6166 rt2800_normal_mode_setup_5xxx(rt2x00dev);
5de5a1f4
SG		 6167
6168 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
6169 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 6170
6171 rt2800_led_open_drain_enable(rt2x00dev);
0c9e5fb9
SG		 6172}
6173
074f2529 6174static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
fcf51541 6175{
d5374ef1
SG		 6176 if (rt2800_is_305x_soc(rt2x00dev)) {
6177 rt2800_init_rfcsr_305x_soc(rt2x00dev);
074f2529 6178 return;
d5374ef1
SG		 6179 }
6180
6181 switch (rt2x00dev->chip.rt) {
6182 case RT3070:
6183 case RT3071:
6184 case RT3090:
6185 rt2800_init_rfcsr_30xx(rt2x00dev);
6186 break;
6187 case RT3290:
6188 rt2800_init_rfcsr_3290(rt2x00dev);
6189 break;
6190 case RT3352:
6191 rt2800_init_rfcsr_3352(rt2x00dev);
6192 break;
6193 case RT3390:
6194 rt2800_init_rfcsr_3390(rt2x00dev);
6195 break;
6196 case RT3572:
6197 rt2800_init_rfcsr_3572(rt2x00dev);
6198 break;
ab7078ac
GJ		 6199 case RT3593:
6200 rt2800_init_rfcsr_3593(rt2x00dev);
6201 break;
d5374ef1
SG		 6202 case RT5390:
6203 rt2800_init_rfcsr_5390(rt2x00dev);
6204 break;
6205 case RT5392:
6206 rt2800_init_rfcsr_5392(rt2x00dev);
6207 break;
0c9e5fb9
SG		 6208 case RT5592:
6209 rt2800_init_rfcsr_5592(rt2x00dev);
074f2529 6210 break;
8cdd15e0 6211 }
fcf51541 6212}
b9a07ae9
ID		 6213
6214int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
6215{
6216 u32 reg;
6217 u16 word;
6218
6219 /*
6220 * Initialize all registers.
6221 */
6222 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
c630ccf1 6223 rt2800_init_registers(rt2x00dev)))
b9a07ae9
ID		 6224 return -EIO;
6225
6226 /*
6227 * Send signal to firmware during boot time.
6228 */
c630ccf1
SG		 6229 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
6230 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
6231 if (rt2x00_is_usb(rt2x00dev)) {
6232 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
6233 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
6234 }
6235 msleep(1);
6236
a1ef5039
SG		 6237 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
6238 rt2800_wait_bbp_ready(rt2x00dev)))
c630ccf1 6239 return -EIO;
b9a07ae9 6240
a1ef5039 6241 rt2800_init_bbp(rt2x00dev);
074f2529
SG		 6242 rt2800_init_rfcsr(rt2x00dev);
6243
b9a07ae9
ID		 6244 if (rt2x00_is_usb(rt2x00dev) &&
6245 (rt2x00_rt(rt2x00dev, RT3070) ||
6246 rt2x00_rt(rt2x00dev, RT3071) ||
6247 rt2x00_rt(rt2x00dev, RT3572))) {
6248 udelay(200);
6249 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
6250 udelay(10);
6251 }
6252
6253 /*
6254 * Enable RX.
6255 */
6256 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6257 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6258 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6259 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6260
6261 udelay(50);
6262
6263 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
6264 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
6265 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
6266 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
6267 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
6268 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
6269
6270 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6271 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6272 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
6273 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6274
6275 /*
6276 * Initialize LED control
6277 */
3e38d3da 6278 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
38c8a566 6279 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
b9a07ae9
ID		 6280 word & 0xff, (word >> 8) & 0xff);
6281
3e38d3da 6282 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
38c8a566 6283 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
b9a07ae9
ID		 6284 word & 0xff, (word >> 8) & 0xff);
6285
3e38d3da 6286 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
38c8a566 6287 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
b9a07ae9
ID		 6288 word & 0xff, (word >> 8) & 0xff);
6289
6290 return 0;
6291}
6292EXPORT_SYMBOL_GPL(rt2800_enable_radio);
6293
6294void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
6295{
6296 u32 reg;
6297
f7b395e9 6298 rt2800_disable_wpdma(rt2x00dev);
b9a07ae9
ID		 6299
6300 /* Wait for DMA, ignore error */
6301 rt2800_wait_wpdma_ready(rt2x00dev);
6302
6303 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6304 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
6305 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6306 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
b9a07ae9
ID		 6307}
6308EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2ce33995 6309
30e84034
BZ		 6310int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
6311{
6312 u32 reg;
a89534ed 6313 u16 efuse_ctrl_reg;
30e84034 6314
a89534ed
WH		 6315 if (rt2x00_rt(rt2x00dev, RT3290))
6316 efuse_ctrl_reg = EFUSE_CTRL_3290;
6317 else
6318 efuse_ctrl_reg = EFUSE_CTRL;
30e84034 6319
a89534ed 6320 rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
30e84034
BZ		 6321 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
6322}
6323EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
6324
6325static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
6326{
6327 u32 reg;
a89534ed
WH		 6328 u16 efuse_ctrl_reg;
6329 u16 efuse_data0_reg;
6330 u16 efuse_data1_reg;
6331 u16 efuse_data2_reg;
6332 u16 efuse_data3_reg;
6333
6334 if (rt2x00_rt(rt2x00dev, RT3290)) {
6335 efuse_ctrl_reg = EFUSE_CTRL_3290;
6336 efuse_data0_reg = EFUSE_DATA0_3290;
6337 efuse_data1_reg = EFUSE_DATA1_3290;
6338 efuse_data2_reg = EFUSE_DATA2_3290;
6339 efuse_data3_reg = EFUSE_DATA3_3290;
6340 } else {
6341 efuse_ctrl_reg = EFUSE_CTRL;
6342 efuse_data0_reg = EFUSE_DATA0;
6343 efuse_data1_reg = EFUSE_DATA1;
6344 efuse_data2_reg = EFUSE_DATA2;
6345 efuse_data3_reg = EFUSE_DATA3;
6346 }
31a4cf1f
GW		 6347 mutex_lock(&rt2x00dev->csr_mutex);
6348
a89534ed 6349 rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
30e84034
BZ		 6350 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
6351 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
6352 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
a89534ed 6353 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
30e84034
BZ		 6354
6355 /* Wait until the EEPROM has been loaded */
a89534ed 6356 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
30e84034 6357 /* Apparently the data is read from end to start */
a89534ed 6358 rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
daabead1 6359 /* The returned value is in CPU order, but eeprom is le */
68fa64ef 6360 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
a89534ed 6361 rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
daabead1 6362 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
a89534ed 6363 rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
daabead1 6364 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
a89534ed 6365 rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
daabead1 6366 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
31a4cf1f
GW		 6367
6368 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 6369}
6370
a02308e9 6371int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
30e84034
BZ		 6372{
6373 unsigned int i;
6374
6375 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
6376 rt2800_efuse_read(rt2x00dev, i);
a02308e9
GJ		 6377
6378 return 0;
30e84034
BZ		 6379}
6380EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
6381
a3f1625d
GJ		 6382static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
6383{
6384 u16 word;
6385
6316c786
GJ		 6386 if (rt2x00_rt(rt2x00dev, RT3593))
6387 return 0;
6388
a3f1625d
GJ		 6389 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
6390 if ((word & 0x00ff) != 0x00ff)
6391 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
6392
6393 return 0;
6394}
6395
6396static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
6397{
6398 u16 word;
6399
6316c786
GJ		 6400 if (rt2x00_rt(rt2x00dev, RT3593))
6401 return 0;
6402
a3f1625d
GJ		 6403 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
6404 if ((word & 0x00ff) != 0x00ff)
6405 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
6406
6407 return 0;
6408}
6409
ad417a53 6410static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
38bd7b8a 6411{
77c06c2c 6412 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
38bd7b8a
BZ		 6413 u16 word;
6414 u8 *mac;
6415 u8 default_lna_gain;
a02308e9 6416 int retval;
38bd7b8a 6417
ad417a53
GW		 6418 /*
6419 * Read the EEPROM.
6420 */
a02308e9
GJ		 6421 retval = rt2800_read_eeprom(rt2x00dev);
6422 if (retval)
6423 return retval;
ad417a53 6424
38bd7b8a
BZ		 6425 /*
6426 * Start validation of the data that has been read.
6427 */
3e38d3da 6428 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
38bd7b8a 6429 if (!is_valid_ether_addr(mac)) {
f4f7f414 6430 eth_random_addr(mac);
ec9c4989 6431 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
38bd7b8a
BZ		 6432 }
6433
3e38d3da 6434 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
38bd7b8a 6435 if (word == 0xffff) {
38c8a566
RJH		 6436 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
6437 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
6438 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
3e38d3da 6439 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
ec9c4989 6440 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 6441 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 6442 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 6443 /*
6444 * There is a max of 2 RX streams for RT28x0 series
6445 */
38c8a566
RJH		 6446 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
6447 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3e38d3da 6448 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a
BZ		 6449 }
6450
3e38d3da 6451 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
38bd7b8a 6452 if (word == 0xffff) {
38c8a566
RJH		 6453 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
6454 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
6455 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
6456 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
6457 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
6458 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
6459 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
6460 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
6461 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
6462 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
6463 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
6464 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
6465 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
6466 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
6467 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
3e38d3da 6468 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
ec9c4989 6469 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
38bd7b8a
BZ		 6470 }
6471
3e38d3da 6472 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
38bd7b8a
BZ		 6473 if ((word & 0x00ff) == 0x00ff) {
6474 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
3e38d3da 6475 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
ec9c4989 6476 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
ec2d1791
GW		 6477 }
6478 if ((word & 0xff00) == 0xff00) {
38bd7b8a
BZ		 6479 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
6480 LED_MODE_TXRX_ACTIVITY);
6481 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
3e38d3da
GJ		 6482 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
6483 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
6484 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
6485 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
ec9c4989 6486 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
38bd7b8a
BZ		 6487 }
6488
6489 /*
6490 * During the LNA validation we are going to use
6491 * lna0 as correct value. Note that EEPROM_LNA
6492 * is never validated.
6493 */
3e38d3da 6494 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
38bd7b8a
BZ		 6495 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
6496
3e38d3da 6497 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
38bd7b8a
BZ		 6498 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
6499 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
6500 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
6501 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
3e38d3da 6502 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
38bd7b8a 6503
a3f1625d 6504 drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
77c06c2c 6505
3e38d3da 6506 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
38bd7b8a
BZ		 6507 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
6508 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
f36bb0ca
GJ		 6509 if (!rt2x00_rt(rt2x00dev, RT3593)) {
6510 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
6511 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
6512 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
6513 default_lna_gain);
6514 }
3e38d3da 6515 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
38bd7b8a 6516
a3f1625d 6517 drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
77c06c2c 6518
3e38d3da 6519 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
38bd7b8a
BZ		 6520 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
6521 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
6522 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
6523 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
3e38d3da 6524 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
38bd7b8a 6525
3e38d3da 6526 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
38bd7b8a
BZ		 6527 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
6528 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
f36bb0ca
GJ		 6529 if (!rt2x00_rt(rt2x00dev, RT3593)) {
6530 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
6531 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
6532 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
6533 default_lna_gain);
6534 }
3e38d3da 6535 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
38bd7b8a 6536
f36bb0ca
GJ		 6537 if (rt2x00_rt(rt2x00dev, RT3593)) {
6538 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &word);
6539 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
6540 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
6541 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
6542 default_lna_gain);
6543 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 ||
6544 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff)
6545 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
6546 default_lna_gain);
6547 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
6548 }
6549
38bd7b8a
BZ		 6550 return 0;
6551}
38bd7b8a 6552
ad417a53 6553static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
38bd7b8a 6554{
38bd7b8a
BZ		 6555 u16 value;
6556 u16 eeprom;
86868b26 6557 u16 rf;
38bd7b8a 6558
86868b26
GJ		 6559 /*
6560 * Read EEPROM word for configuration.
6561 */
3e38d3da 6562 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
86868b26
GJ		 6563
6564 /*
6565 * Identify RF chipset by EEPROM value
6566 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
6567 * RT53xx: defined in "EEPROM_CHIP_ID" field
6568 */
6569 if (rt2x00_rt(rt2x00dev, RT3290) ||
6570 rt2x00_rt(rt2x00dev, RT5390) ||
6571 rt2x00_rt(rt2x00dev, RT5392))
3e38d3da 6572 rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf);
86868b26
GJ		 6573 else
6574 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
6575
6576 switch (rf) {
d331eb51
LF		 6577 case RF2820:
6578 case RF2850:
6579 case RF2720:
6580 case RF2750:
6581 case RF3020:
6582 case RF2020:
6583 case RF3021:
6584 case RF3022:
6585 case RF3052:
a89534ed 6586 case RF3290:
d331eb51 6587 case RF3320:
03839951 6588 case RF3322:
ccf91bd6 6589 case RF5360:
d331eb51 6590 case RF5370:
2ed71884 6591 case RF5372:
d331eb51 6592 case RF5390:
cff3d1f0 6593 case RF5392:
b8863f8b 6594 case RF5592:
d331eb51
LF		 6595 break;
6596 default:
ec9c4989
JP		 6597 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
6598 rf);
38bd7b8a
BZ		 6599 return -ENODEV;
6600 }
6601
86868b26
GJ		 6602 rt2x00_set_rf(rt2x00dev, rf);
6603
38bd7b8a
BZ		 6604 /*
6605 * Identify default antenna configuration.
6606 */
d96aa640 6607 rt2x00dev->default_ant.tx_chain_num =
38c8a566 6608 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
d96aa640 6609 rt2x00dev->default_ant.rx_chain_num =
38c8a566 6610 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
38bd7b8a 6611
3e38d3da 6612 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
d96aa640
RJH		 6613
6614 if (rt2x00_rt(rt2x00dev, RT3070) ||
6615 rt2x00_rt(rt2x00dev, RT3090) ||
03839951 6616 rt2x00_rt(rt2x00dev, RT3352) ||
d96aa640
RJH		 6617 rt2x00_rt(rt2x00dev, RT3390)) {
6618 value = rt2x00_get_field16(eeprom,
6619 EEPROM_NIC_CONF1_ANT_DIVERSITY);
6620 switch (value) {
6621 case 0:
6622 case 1:
6623 case 2:
6624 rt2x00dev->default_ant.tx = ANTENNA_A;
6625 rt2x00dev->default_ant.rx = ANTENNA_A;
6626 break;
6627 case 3:
6628 rt2x00dev->default_ant.tx = ANTENNA_A;
6629 rt2x00dev->default_ant.rx = ANTENNA_B;
6630 break;
6631 }
6632 } else {
6633 rt2x00dev->default_ant.tx = ANTENNA_A;
6634 rt2x00dev->default_ant.rx = ANTENNA_A;
6635 }
6636
0586a11b
AA		 6637 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
6638 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
6639 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
6640 }
6641
38bd7b8a 6642 /*
9328fdac 6643 * Determine external LNA informations.
38bd7b8a 6644 */
38c8a566 6645 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
7dab73b3 6646 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
38c8a566 6647 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
7dab73b3 6648 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
38bd7b8a
BZ		 6649
6650 /*
6651 * Detect if this device has an hardware controlled radio.
6652 */
38c8a566 6653 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
7dab73b3 6654 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
38bd7b8a 6655
fdbc7b0a
GW		 6656 /*
6657 * Detect if this device has Bluetooth co-existence.
6658 */
6659 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
6660 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
6661
9328fdac
GW		 6662 /*
6663 * Read frequency offset and RF programming sequence.
6664 */
3e38d3da 6665 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
9328fdac
GW		 6666 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
6667
38bd7b8a
BZ		 6668 /*
6669 * Store led settings, for correct led behaviour.
6670 */
6671#ifdef CONFIG_RT2X00_LIB_LEDS
6672 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
6673 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
6674 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
6675
9328fdac 6676 rt2x00dev->led_mcu_reg = eeprom;
38bd7b8a
BZ		 6677#endif /* CONFIG_RT2X00_LIB_LEDS */
6678
e90c54b2
RJH		 6679 /*
6680 * Check if support EIRP tx power limit feature.
6681 */
3e38d3da 6682 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
e90c54b2
RJH		 6683
6684 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
6685 EIRP_MAX_TX_POWER_LIMIT)
7dab73b3 6686 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
e90c54b2 6687
38bd7b8a
BZ		 6688 return 0;
6689}
38bd7b8a 6690
4da2933f 6691/*
55f9321a 6692 * RF value list for rt28xx
4da2933f
BZ		 6693 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
6694 */
6695static const struct rf_channel rf_vals[] = {
6696 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
6697 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
6698 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
6699 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
6700 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
6701 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
6702 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
6703 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
6704 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
6705 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
6706 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
6707 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
6708 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
6709 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
6710
6711 /* 802.11 UNI / HyperLan 2 */
6712 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
6713 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
6714 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
6715 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
6716 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
6717 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
6718 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
6719 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
6720 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
6721 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
6722 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
6723 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
6724
6725 /* 802.11 HyperLan 2 */
6726 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
6727 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
6728 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
6729 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
6730 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
6731 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
6732 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
6733 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
6734 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
6735 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
6736 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
6737 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
6738 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
6739 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
6740 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
6741 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
6742
6743 /* 802.11 UNII */
6744 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
6745 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
6746 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
6747 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
6748 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
6749 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
6750 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
6751 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
6752 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
6753 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
6754 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
6755
6756 /* 802.11 Japan */
6757 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
6758 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
6759 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
6760 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
6761 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
6762 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
6763 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
6764};
6765
6766/*
55f9321a
ID		 6767 * RF value list for rt3xxx
6768 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4da2933f 6769 */
55f9321a 6770static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 6771 {1, 241, 2, 2 },
6772 {2, 241, 2, 7 },
6773 {3, 242, 2, 2 },
6774 {4, 242, 2, 7 },
6775 {5, 243, 2, 2 },
6776 {6, 243, 2, 7 },
6777 {7, 244, 2, 2 },
6778 {8, 244, 2, 7 },
6779 {9, 245, 2, 2 },
6780 {10, 245, 2, 7 },
6781 {11, 246, 2, 2 },
6782 {12, 246, 2, 7 },
6783 {13, 247, 2, 2 },
6784 {14, 248, 2, 4 },
55f9321a
ID		 6785
6786 /* 802.11 UNI / HyperLan 2 */
6787 {36, 0x56, 0, 4},
6788 {38, 0x56, 0, 6},
6789 {40, 0x56, 0, 8},
6790 {44, 0x57, 0, 0},
6791 {46, 0x57, 0, 2},
6792 {48, 0x57, 0, 4},
6793 {52, 0x57, 0, 8},
6794 {54, 0x57, 0, 10},
6795 {56, 0x58, 0, 0},
6796 {60, 0x58, 0, 4},
6797 {62, 0x58, 0, 6},
6798 {64, 0x58, 0, 8},
6799
6800 /* 802.11 HyperLan 2 */
6801 {100, 0x5b, 0, 8},
6802 {102, 0x5b, 0, 10},
6803 {104, 0x5c, 0, 0},
6804 {108, 0x5c, 0, 4},
6805 {110, 0x5c, 0, 6},
6806 {112, 0x5c, 0, 8},
6807 {116, 0x5d, 0, 0},
6808 {118, 0x5d, 0, 2},
6809 {120, 0x5d, 0, 4},
6810 {124, 0x5d, 0, 8},
6811 {126, 0x5d, 0, 10},
6812 {128, 0x5e, 0, 0},
6813 {132, 0x5e, 0, 4},
6814 {134, 0x5e, 0, 6},
6815 {136, 0x5e, 0, 8},
6816 {140, 0x5f, 0, 0},
6817
6818 /* 802.11 UNII */
6819 {149, 0x5f, 0, 9},
6820 {151, 0x5f, 0, 11},
6821 {153, 0x60, 0, 1},
6822 {157, 0x60, 0, 5},
6823 {159, 0x60, 0, 7},
6824 {161, 0x60, 0, 9},
6825 {165, 0x61, 0, 1},
6826 {167, 0x61, 0, 3},
6827 {169, 0x61, 0, 5},
6828 {171, 0x61, 0, 7},
6829 {173, 0x61, 0, 9},
4da2933f
BZ		 6830};
6831
7848b231
SG		 6832static const struct rf_channel rf_vals_5592_xtal20[] = {
6833 /* Channel, N, K, mod, R */
6834 {1, 482, 4, 10, 3},
6835 {2, 483, 4, 10, 3},
6836 {3, 484, 4, 10, 3},
6837 {4, 485, 4, 10, 3},
6838 {5, 486, 4, 10, 3},
6839 {6, 487, 4, 10, 3},
6840 {7, 488, 4, 10, 3},
6841 {8, 489, 4, 10, 3},
6842 {9, 490, 4, 10, 3},
6843 {10, 491, 4, 10, 3},
6844 {11, 492, 4, 10, 3},
6845 {12, 493, 4, 10, 3},
6846 {13, 494, 4, 10, 3},
6847 {14, 496, 8, 10, 3},
6848 {36, 172, 8, 12, 1},
6849 {38, 173, 0, 12, 1},
6850 {40, 173, 4, 12, 1},
6851 {42, 173, 8, 12, 1},
6852 {44, 174, 0, 12, 1},
6853 {46, 174, 4, 12, 1},
6854 {48, 174, 8, 12, 1},
6855 {50, 175, 0, 12, 1},
6856 {52, 175, 4, 12, 1},
6857 {54, 175, 8, 12, 1},
6858 {56, 176, 0, 12, 1},
6859 {58, 176, 4, 12, 1},
6860 {60, 176, 8, 12, 1},
6861 {62, 177, 0, 12, 1},
6862 {64, 177, 4, 12, 1},
6863 {100, 183, 4, 12, 1},
6864 {102, 183, 8, 12, 1},
6865 {104, 184, 0, 12, 1},
6866 {106, 184, 4, 12, 1},
6867 {108, 184, 8, 12, 1},
6868 {110, 185, 0, 12, 1},
6869 {112, 185, 4, 12, 1},
6870 {114, 185, 8, 12, 1},
6871 {116, 186, 0, 12, 1},
6872 {118, 186, 4, 12, 1},
6873 {120, 186, 8, 12, 1},
6874 {122, 187, 0, 12, 1},
6875 {124, 187, 4, 12, 1},
6876 {126, 187, 8, 12, 1},
6877 {128, 188, 0, 12, 1},
6878 {130, 188, 4, 12, 1},
6879 {132, 188, 8, 12, 1},
6880 {134, 189, 0, 12, 1},
6881 {136, 189, 4, 12, 1},
6882 {138, 189, 8, 12, 1},
6883 {140, 190, 0, 12, 1},
6884 {149, 191, 6, 12, 1},
6885 {151, 191, 10, 12, 1},
6886 {153, 192, 2, 12, 1},
6887 {155, 192, 6, 12, 1},
6888 {157, 192, 10, 12, 1},
6889 {159, 193, 2, 12, 1},
6890 {161, 193, 6, 12, 1},
6891 {165, 194, 2, 12, 1},
6892 {184, 164, 0, 12, 1},
6893 {188, 164, 4, 12, 1},
6894 {192, 165, 8, 12, 1},
6895 {196, 166, 0, 12, 1},
6896};
6897
6898static const struct rf_channel rf_vals_5592_xtal40[] = {
6899 /* Channel, N, K, mod, R */
6900 {1, 241, 2, 10, 3},
6901 {2, 241, 7, 10, 3},
6902 {3, 242, 2, 10, 3},
6903 {4, 242, 7, 10, 3},
6904 {5, 243, 2, 10, 3},
6905 {6, 243, 7, 10, 3},
6906 {7, 244, 2, 10, 3},
6907 {8, 244, 7, 10, 3},
6908 {9, 245, 2, 10, 3},
6909 {10, 245, 7, 10, 3},
6910 {11, 246, 2, 10, 3},
6911 {12, 246, 7, 10, 3},
6912 {13, 247, 2, 10, 3},
6913 {14, 248, 4, 10, 3},
6914 {36, 86, 4, 12, 1},
6915 {38, 86, 6, 12, 1},
6916 {40, 86, 8, 12, 1},
6917 {42, 86, 10, 12, 1},
6918 {44, 87, 0, 12, 1},
6919 {46, 87, 2, 12, 1},
6920 {48, 87, 4, 12, 1},
6921 {50, 87, 6, 12, 1},
6922 {52, 87, 8, 12, 1},
6923 {54, 87, 10, 12, 1},
6924 {56, 88, 0, 12, 1},
6925 {58, 88, 2, 12, 1},
6926 {60, 88, 4, 12, 1},
6927 {62, 88, 6, 12, 1},
6928 {64, 88, 8, 12, 1},
6929 {100, 91, 8, 12, 1},
6930 {102, 91, 10, 12, 1},
6931 {104, 92, 0, 12, 1},
6932 {106, 92, 2, 12, 1},
6933 {108, 92, 4, 12, 1},
6934 {110, 92, 6, 12, 1},
6935 {112, 92, 8, 12, 1},
6936 {114, 92, 10, 12, 1},
6937 {116, 93, 0, 12, 1},
6938 {118, 93, 2, 12, 1},
6939 {120, 93, 4, 12, 1},
6940 {122, 93, 6, 12, 1},
6941 {124, 93, 8, 12, 1},
6942 {126, 93, 10, 12, 1},
6943 {128, 94, 0, 12, 1},
6944 {130, 94, 2, 12, 1},
6945 {132, 94, 4, 12, 1},
6946 {134, 94, 6, 12, 1},
6947 {136, 94, 8, 12, 1},
6948 {138, 94, 10, 12, 1},
6949 {140, 95, 0, 12, 1},
6950 {149, 95, 9, 12, 1},
6951 {151, 95, 11, 12, 1},
6952 {153, 96, 1, 12, 1},
6953 {155, 96, 3, 12, 1},
6954 {157, 96, 5, 12, 1},
6955 {159, 96, 7, 12, 1},
6956 {161, 96, 9, 12, 1},
6957 {165, 97, 1, 12, 1},
6958 {184, 82, 0, 12, 1},
6959 {188, 82, 4, 12, 1},
6960 {192, 82, 8, 12, 1},
6961 {196, 83, 0, 12, 1},
6962};
6963
ad417a53 6964static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4da2933f 6965{
4da2933f
BZ		 6966 struct hw_mode_spec *spec = &rt2x00dev->spec;
6967 struct channel_info *info;
8d1331b3
ID		 6968 char *default_power1;
6969 char *default_power2;
c0a14369 6970 char *default_power3;
4da2933f
BZ		 6971 unsigned int i;
6972 u16 eeprom;
7848b231 6973 u32 reg;
4da2933f 6974
93b6bd26
GW		 6975 /*
6976 * Disable powersaving as default on PCI devices.
6977 */
cea90e55 6978 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
93b6bd26
GW		 6979 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
6980
4da2933f
BZ		 6981 /*
6982 * Initialize all hw fields.
6983 */
6984 rt2x00dev->hw->flags =
4da2933f
BZ		 6985 IEEE80211_HW_SIGNAL_DBM |
6986 IEEE80211_HW_SUPPORTS_PS |
1df90809 6987 IEEE80211_HW_PS_NULLFUNC_STACK |
9d4f09b8 6988 IEEE80211_HW_AMPDU_AGGREGATION |
84e9e8eb 6989 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
9d4f09b8 6990
5a5b6ed6
HS		 6991 /*
6992 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
6993 * unless we are capable of sending the buffered frames out after the
6994 * DTIM transmission using rt2x00lib_beacondone. This will send out
6995 * multicast and broadcast traffic immediately instead of buffering it
6996 * infinitly and thus dropping it after some time.
6997 */
6998 if (!rt2x00_is_usb(rt2x00dev))
6999 rt2x00dev->hw->flags |=
7000 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
4da2933f 7001
4da2933f
BZ		 7002 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
7003 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3e38d3da 7004 rt2800_eeprom_addr(rt2x00dev,
4da2933f
BZ		 7005 EEPROM_MAC_ADDR_0));
7006
3f2bee24
HS		 7007 /*
7008 * As rt2800 has a global fallback table we cannot specify
7009 * more then one tx rate per frame but since the hw will
7010 * try several rates (based on the fallback table) we should
ba3b9e5e 7011 * initialize max_report_rates to the maximum number of rates
3f2bee24
HS		 7012 * we are going to try. Otherwise mac80211 will truncate our
7013 * reported tx rates and the rc algortihm will end up with
7014 * incorrect data.
7015 */
ba3b9e5e
HS		 7016 rt2x00dev->hw->max_rates = 1;
7017 rt2x00dev->hw->max_report_rates = 7;
3f2bee24
HS		 7018 rt2x00dev->hw->max_rate_tries = 1;
7019
3e38d3da 7020 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4da2933f
BZ		 7021
7022 /*
7023 * Initialize hw_mode information.
7024 */
7025 spec->supported_bands = SUPPORT_BAND_2GHZ;
7026 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
7027
5122d898 7028 if (rt2x00_rf(rt2x00dev, RF2820) ||
55f9321a 7029 rt2x00_rf(rt2x00dev, RF2720)) {
4da2933f
BZ		 7030 spec->num_channels = 14;
7031 spec->channels = rf_vals;
55f9321a
ID		 7032 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
7033 rt2x00_rf(rt2x00dev, RF2750)) {
4da2933f
BZ		 7034 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7035 spec->num_channels = ARRAY_SIZE(rf_vals);
7036 spec->channels = rf_vals;
5122d898
GW		 7037 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
7038 rt2x00_rf(rt2x00dev, RF2020) ||
7039 rt2x00_rf(rt2x00dev, RF3021) ||
f93bc9b3 7040 rt2x00_rf(rt2x00dev, RF3022) ||
a89534ed 7041 rt2x00_rf(rt2x00dev, RF3290) ||
adde5882 7042 rt2x00_rf(rt2x00dev, RF3320) ||
03839951 7043 rt2x00_rf(rt2x00dev, RF3322) ||
ccf91bd6 7044 rt2x00_rf(rt2x00dev, RF5360) ||
aca355b9 7045 rt2x00_rf(rt2x00dev, RF5370) ||
2ed71884 7046 rt2x00_rf(rt2x00dev, RF5372) ||
cff3d1f0
ZL		 7047 rt2x00_rf(rt2x00dev, RF5390) ||
7048 rt2x00_rf(rt2x00dev, RF5392)) {
55f9321a
ID		 7049 spec->num_channels = 14;
7050 spec->channels = rf_vals_3x;
7051 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
7052 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7053 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
7054 spec->channels = rf_vals_3x;
7848b231
SG		 7055 } else if (rt2x00_rf(rt2x00dev, RF5592)) {
7056 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7057
7058 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, &reg);
7059 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
7060 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
7061 spec->channels = rf_vals_5592_xtal40;
7062 } else {
7063 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
7064 spec->channels = rf_vals_5592_xtal20;
7065 }
4da2933f
BZ		 7066 }
7067
53216d6a
SG		 7068 if (WARN_ON_ONCE(!spec->channels))
7069 return -ENODEV;
7070
4da2933f
BZ		 7071 /*
7072 * Initialize HT information.
7073 */
5122d898 7074 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 7075 spec->ht.ht_supported = true;
7076 else
7077 spec->ht.ht_supported = false;
7078
4da2933f 7079 spec->ht.cap =
06443e46 7080 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 7081 IEEE80211_HT_CAP_GRN_FLD |
7082 IEEE80211_HT_CAP_SGI_20 |
aa674631 7083 IEEE80211_HT_CAP_SGI_40;
22cabaa6 7084
38c8a566 7085 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
22cabaa6
HS		 7086 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
7087
aa674631 7088 spec->ht.cap |=
38c8a566 7089 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
aa674631
ID		 7090 IEEE80211_HT_CAP_RX_STBC_SHIFT;
7091
4da2933f
BZ		 7092 spec->ht.ampdu_factor = 3;
7093 spec->ht.ampdu_density = 4;
7094 spec->ht.mcs.tx_params =
7095 IEEE80211_HT_MCS_TX_DEFINED |
7096 IEEE80211_HT_MCS_TX_RX_DIFF |
38c8a566 7097 ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
4da2933f
BZ		 7098 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
7099
38c8a566 7100 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
4da2933f
BZ		 7101 case 3:
7102 spec->ht.mcs.rx_mask[2] = 0xff;
7103 case 2:
7104 spec->ht.mcs.rx_mask[1] = 0xff;
7105 case 1:
7106 spec->ht.mcs.rx_mask[0] = 0xff;
7107 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
7108 break;
7109 }
7110
7111 /*
7112 * Create channel information array
7113 */
baeb2ffa 7114 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4da2933f
BZ		 7115 if (!info)
7116 return -ENOMEM;
7117
7118 spec->channels_info = info;
7119
3e38d3da
GJ		 7120 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
7121 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4da2933f 7122
c0a14369
GJ		 7123 if (rt2x00dev->default_ant.tx_chain_num > 2)
7124 default_power3 = rt2800_eeprom_addr(rt2x00dev,
7125 EEPROM_EXT_TXPOWER_BG3);
7126 else
7127 default_power3 = NULL;
7128
4da2933f 7129 for (i = 0; i < 14; i++) {
e90c54b2
RJH		 7130 info[i].default_power1 = default_power1[i];
7131 info[i].default_power2 = default_power2[i];
c0a14369
GJ		 7132 if (default_power3)
7133 info[i].default_power3 = default_power3[i];
4da2933f
BZ		 7134 }
7135
7136 if (spec->num_channels > 14) {
3e38d3da
GJ		 7137 default_power1 = rt2800_eeprom_addr(rt2x00dev,
7138 EEPROM_TXPOWER_A1);
7139 default_power2 = rt2800_eeprom_addr(rt2x00dev,
7140 EEPROM_TXPOWER_A2);
4da2933f 7141
c0a14369
GJ		 7142 if (rt2x00dev->default_ant.tx_chain_num > 2)
7143 default_power3 =
7144 rt2800_eeprom_addr(rt2x00dev,
7145 EEPROM_EXT_TXPOWER_A3);
7146 else
7147 default_power3 = NULL;
7148
4da2933f 7149 for (i = 14; i < spec->num_channels; i++) {
0a6f3a8e
GJ		 7150 info[i].default_power1 = default_power1[i - 14];
7151 info[i].default_power2 = default_power2[i - 14];
c0a14369
GJ		 7152 if (default_power3)
7153 info[i].default_power3 = default_power3[i - 14];
4da2933f
BZ		 7154 }
7155 }
7156
2e9c43dd
JL		 7157 switch (rt2x00dev->chip.rf) {
7158 case RF2020:
7159 case RF3020:
7160 case RF3021:
7161 case RF3022:
7162 case RF3320:
7163 case RF3052:
a89534ed 7164 case RF3290:
ccf91bd6 7165 case RF5360:
2e9c43dd
JL		 7166 case RF5370:
7167 case RF5372:
7168 case RF5390:
cff3d1f0 7169 case RF5392:
2e9c43dd
JL		 7170 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
7171 break;
7172 }
7173
4da2933f
BZ		 7174 return 0;
7175}
ad417a53 7176
cbafb601
GJ		 7177static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
7178{
7179 u32 reg;
7180 u32 rt;
7181 u32 rev;
7182
7183 if (rt2x00_rt(rt2x00dev, RT3290))
7184 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
7185 else
7186 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
7187
7188 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
7189 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
7190
7191 switch (rt) {
7192 case RT2860:
7193 case RT2872:
7194 case RT2883:
7195 case RT3070:
7196 case RT3071:
7197 case RT3090:
7198 case RT3290:
7199 case RT3352:
7200 case RT3390:
7201 case RT3572:
7202 case RT5390:
7203 case RT5392:
7204 case RT5592:
7205 break;
7206 default:
ec9c4989
JP		 7207 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
7208 rt, rev);
cbafb601
GJ		 7209 return -ENODEV;
7210 }
7211
7212 rt2x00_set_rt(rt2x00dev, rt, rev);
7213
7214 return 0;
7215}
7216
ad417a53
GW		 7217int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
7218{
7219 int retval;
7220 u32 reg;
7221
cbafb601
GJ		 7222 retval = rt2800_probe_rt(rt2x00dev);
7223 if (retval)
7224 return retval;
7225
ad417a53
GW		 7226 /*
7227 * Allocate eeprom data.
7228 */
7229 retval = rt2800_validate_eeprom(rt2x00dev);
7230 if (retval)
7231 return retval;
7232
7233 retval = rt2800_init_eeprom(rt2x00dev);
7234 if (retval)
7235 return retval;
7236
7237 /*
7238 * Enable rfkill polling by setting GPIO direction of the
7239 * rfkill switch GPIO pin correctly.
7240 */
7241 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
7242 rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
7243 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
7244
7245 /*
7246 * Initialize hw specifications.
7247 */
7248 retval = rt2800_probe_hw_mode(rt2x00dev);
7249 if (retval)
7250 return retval;
7251
7252 /*
7253 * Set device capabilities.
7254 */
7255 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
7256 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
7257 if (!rt2x00_is_usb(rt2x00dev))
7258 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
7259
7260 /*
7261 * Set device requirements.
7262 */
7263 if (!rt2x00_is_soc(rt2x00dev))
7264 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
7265 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
7266 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
7267 if (!rt2800_hwcrypt_disabled(rt2x00dev))
7268 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
7269 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
7270 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
7271 if (rt2x00_is_usb(rt2x00dev))
7272 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
7273 else {
7274 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
7275 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
7276 }
7277
7278 /*
7279 * Set the rssi offset.
7280 */
7281 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
7282
7283 return 0;
7284}
7285EXPORT_SYMBOL_GPL(rt2800_probe_hw);
4da2933f 7286
2ce33995
BZ		 7287/*
7288 * IEEE80211 stack callback functions.
7289 */
e783619e
HS		 7290void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
7291 u16 *iv16)
2ce33995
BZ		 7292{
7293 struct rt2x00_dev *rt2x00dev = hw->priv;
7294 struct mac_iveiv_entry iveiv_entry;
7295 u32 offset;
7296
7297 offset = MAC_IVEIV_ENTRY(hw_key_idx);
7298 rt2800_register_multiread(rt2x00dev, offset,
7299 &iveiv_entry, sizeof(iveiv_entry));
7300
855da5e0
JL		 7301 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
7302 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995 7303}
e783619e 7304EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
2ce33995 7305
e783619e 7306int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2ce33995
BZ		 7307{
7308 struct rt2x00_dev *rt2x00dev = hw->priv;
7309 u32 reg;
7310 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
7311
7312 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
7313 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
7314 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
7315
7316 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
7317 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
7318 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
7319
7320 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
7321 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
7322 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
7323
7324 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
7325 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
7326 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
7327
7328 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
7329 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
7330 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
7331
7332 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
7333 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
7334 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
7335
7336 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
7337 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
7338 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
7339
7340 return 0;
7341}
e783619e 7342EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2ce33995 7343
8a3a3c85
EP		 7344int rt2800_conf_tx(struct ieee80211_hw *hw,
7345 struct ieee80211_vif *vif, u16 queue_idx,
e783619e 7346 const struct ieee80211_tx_queue_params *params)
2ce33995
BZ		 7347{
7348 struct rt2x00_dev *rt2x00dev = hw->priv;
7349 struct data_queue *queue;
7350 struct rt2x00_field32 field;
7351 int retval;
7352 u32 reg;
7353 u32 offset;
7354
7355 /*
7356 * First pass the configuration through rt2x00lib, that will
7357 * update the queue settings and validate the input. After that
7358 * we are free to update the registers based on the value
7359 * in the queue parameter.
7360 */
8a3a3c85 7361 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
2ce33995
BZ		 7362 if (retval)
7363 return retval;
7364
7365 /*
7366 * We only need to perform additional register initialization
7367 * for WMM queues/
7368 */
7369 if (queue_idx >= 4)
7370 return 0;
7371
11f818e0 7372 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2ce33995
BZ		 7373
7374 /* Update WMM TXOP register */
7375 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
7376 field.bit_offset = (queue_idx & 1) * 16;
7377 field.bit_mask = 0xffff << field.bit_offset;
7378
7379 rt2800_register_read(rt2x00dev, offset, &reg);
7380 rt2x00_set_field32(&reg, field, queue->txop);
7381 rt2800_register_write(rt2x00dev, offset, reg);
7382
7383 /* Update WMM registers */
7384 field.bit_offset = queue_idx * 4;
7385 field.bit_mask = 0xf << field.bit_offset;
7386
7387 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
7388 rt2x00_set_field32(&reg, field, queue->aifs);
7389 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
7390
7391 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
7392 rt2x00_set_field32(&reg, field, queue->cw_min);
7393 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
7394
7395 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
7396 rt2x00_set_field32(&reg, field, queue->cw_max);
7397 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
7398
7399 /* Update EDCA registers */
7400 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
7401
7402 rt2800_register_read(rt2x00dev, offset, &reg);
7403 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
7404 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
7405 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
7406 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
7407 rt2800_register_write(rt2x00dev, offset, reg);
7408
7409 return 0;
7410}
e783619e 7411EXPORT_SYMBOL_GPL(rt2800_conf_tx);
2ce33995 7412
37a41b4a 7413u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2ce33995
BZ		 7414{
7415 struct rt2x00_dev *rt2x00dev = hw->priv;
7416 u64 tsf;
7417 u32 reg;
7418
7419 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
7420 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
7421 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
7422 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
7423
7424 return tsf;
7425}
e783619e 7426EXPORT_SYMBOL_GPL(rt2800_get_tsf);
2ce33995 7427
e783619e
HS		 7428int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
7429 enum ieee80211_ampdu_mlme_action action,
0b01f030
JB		 7430 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
7431 u8 buf_size)
1df90809 7432{
af35323d 7433 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
1df90809
HS		 7434 int ret = 0;
7435
af35323d
HS		 7436 /*
7437 * Don't allow aggregation for stations the hardware isn't aware
7438 * of because tx status reports for frames to an unknown station
7439 * always contain wcid=255 and thus we can't distinguish between
7440 * multiple stations which leads to unwanted situations when the
7441 * hw reorders frames due to aggregation.
7442 */
7443 if (sta_priv->wcid < 0)
7444 return 1;
7445
1df90809
HS		 7446 switch (action) {
7447 case IEEE80211_AMPDU_RX_START:
7448 case IEEE80211_AMPDU_RX_STOP:
58ed826e
HS		 7449 /*
7450 * The hw itself takes care of setting up BlockAck mechanisms.
7451 * So, we only have to allow mac80211 to nagotiate a BlockAck
7452 * agreement. Once that is done, the hw will BlockAck incoming
7453 * AMPDUs without further setup.
7454 */
1df90809
HS		 7455 break;
7456 case IEEE80211_AMPDU_TX_START:
7457 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7458 break;
18b559d5
JB		 7459 case IEEE80211_AMPDU_TX_STOP_CONT:
7460 case IEEE80211_AMPDU_TX_STOP_FLUSH:
7461 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
1df90809
HS		 7462 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7463 break;
7464 case IEEE80211_AMPDU_TX_OPERATIONAL:
7465 break;
7466 default:
ec9c4989
JP		 7467 rt2x00_warn((struct rt2x00_dev *)hw->priv,
7468 "Unknown AMPDU action\n");
1df90809
HS		 7469 }
7470
7471 return ret;
7472}
e783619e 7473EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
a5ea2f02 7474
977206d7
HS		 7475int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
7476 struct survey_info *survey)
7477{
7478 struct rt2x00_dev *rt2x00dev = hw->priv;
7479 struct ieee80211_conf *conf = &hw->conf;
7480 u32 idle, busy, busy_ext;
7481
7482 if (idx != 0)
7483 return -ENOENT;
7484
675a0b04 7485 survey->channel = conf->chandef.chan;
977206d7
HS		 7486
7487 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
7488 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
7489 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
7490
7491 if (idle || busy) {
7492 survey->filled = SURVEY_INFO_CHANNEL_TIME |
7493 SURVEY_INFO_CHANNEL_TIME_BUSY |
7494 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
7495
7496 survey->channel_time = (idle + busy) / 1000;
7497 survey->channel_time_busy = busy / 1000;
7498 survey->channel_time_ext_busy = busy_ext / 1000;
7499 }
7500
9931df26
HS		 7501 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
7502 survey->filled |= SURVEY_INFO_IN_USE;
7503
977206d7
HS		 7504 return 0;
7505
7506}
7507EXPORT_SYMBOL_GPL(rt2800_get_survey);
7508
a5ea2f02
ID		 7509MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
7510MODULE_VERSION(DRV_VERSION);
7511MODULE_DESCRIPTION("Ralink RT2800 library");
7512MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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