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rt2x00: remove stray semicolon
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
CommitLineData
89297425 1/*
96481b20 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
a5ea2f02 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 6
9c9a0d14 7 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32/*
33 Module: rt2800lib
34 Abstract: rt2800 generic device routines.
35 */
36
f31c9a8c 37#include <linux/crc-ccitt.h>
89297425
BZ		 38#include <linux/kernel.h>
39#include <linux/module.h>
5a0e3ad6 40#include <linux/slab.h>
89297425
BZ		 41
42#include "rt2x00.h"
43#include "rt2800lib.h"
44#include "rt2800.h"
45
89297425
BZ		 46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60#define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64#define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66#define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
baff8006
HS		 70static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71{
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
75 return false;
76
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
81 return true;
82
83 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
84 return false;
85}
86
fcf51541
BZ		 87static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
89297425
BZ		 89{
90 u32 reg;
91
92 mutex_lock(&rt2x00dev->csr_mutex);
93
94 /*
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
97 */
98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
efc7d36f 104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 105
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107 }
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110}
89297425 111
fcf51541
BZ		 112static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
89297425
BZ		 114{
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
126 */
127 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 reg = 0;
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
efc7d36f 132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142}
89297425 143
fcf51541
BZ		 144static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
89297425
BZ		 146{
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166}
89297425 167
fcf51541
BZ		 168static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
89297425
BZ		 170{
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197}
89297425 198
fcf51541
BZ		 199static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
89297425
BZ		 201{
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222}
89297425
BZ		 223
224void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
225 const u8 command, const u8 token,
226 const u8 arg0, const u8 arg1)
227{
228 u32 reg;
229
ee303e54 230 /*
cea90e55 231 * SOC devices don't support MCU requests.
ee303e54 232 */
cea90e55 233 if (rt2x00_is_soc(rt2x00dev))
ee303e54 234 return;
89297425
BZ		 235
236 mutex_lock(&rt2x00dev->csr_mutex);
237
238 /*
239 * Wait until the MCU becomes available, afterwards we
240 * can safely write the new data into the register.
241 */
242 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
243 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
244 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
245 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
246 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
247 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
248
249 reg = 0;
250 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
251 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
252 }
253
254 mutex_unlock(&rt2x00dev->csr_mutex);
255}
256EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 257
5ffddc49
ID		 258int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
259{
260 unsigned int i = 0;
261 u32 reg;
262
263 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
264 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
265 if (reg && reg != ~0)
266 return 0;
267 msleep(1);
268 }
269
270 ERROR(rt2x00dev, "Unstable hardware.\n");
271 return -EBUSY;
272}
273EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
274
67a4c1e2
GW		 275int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
276{
277 unsigned int i;
278 u32 reg;
279
08e53100
HS		 280 /*
281 * Some devices are really slow to respond here. Wait a whole second
282 * before timing out.
283 */
67a4c1e2
GW		 284 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
285 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
286 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
287 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
288 return 0;
289
08e53100 290 msleep(10);
67a4c1e2
GW		 291 }
292
293 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
294 return -EACCES;
295}
296EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
297
f31c9a8c
ID		 298static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
299{
300 u16 fw_crc;
301 u16 crc;
302
303 /*
304 * The last 2 bytes in the firmware array are the crc checksum itself,
305 * this means that we should never pass those 2 bytes to the crc
306 * algorithm.
307 */
308 fw_crc = (data[len - 2] << 8 | data[len - 1]);
309
310 /*
311 * Use the crc ccitt algorithm.
312 * This will return the same value as the legacy driver which
313 * used bit ordering reversion on the both the firmware bytes
314 * before input input as well as on the final output.
315 * Obviously using crc ccitt directly is much more efficient.
316 */
317 crc = crc_ccitt(~0, data, len - 2);
318
319 /*
320 * There is a small difference between the crc-itu-t + bitrev and
321 * the crc-ccitt crc calculation. In the latter method the 2 bytes
322 * will be swapped, use swab16 to convert the crc to the correct
323 * value.
324 */
325 crc = swab16(crc);
326
327 return fw_crc == crc;
328}
329
330int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
331 const u8 *data, const size_t len)
332{
333 size_t offset = 0;
334 size_t fw_len;
335 bool multiple;
336
337 /*
338 * PCI(e) & SOC devices require firmware with a length
339 * of 8kb. USB devices require firmware files with a length
340 * of 4kb. Certain USB chipsets however require different firmware,
341 * which Ralink only provides attached to the original firmware
342 * file. Thus for USB devices, firmware files have a length
343 * which is a multiple of 4kb.
344 */
345 if (rt2x00_is_usb(rt2x00dev)) {
346 fw_len = 4096;
347 multiple = true;
348 } else {
349 fw_len = 8192;
350 multiple = true;
351 }
352
353 /*
354 * Validate the firmware length
355 */
356 if (len != fw_len && (!multiple || (len % fw_len) != 0))
357 return FW_BAD_LENGTH;
358
359 /*
360 * Check if the chipset requires one of the upper parts
361 * of the firmware.
362 */
363 if (rt2x00_is_usb(rt2x00dev) &&
364 !rt2x00_rt(rt2x00dev, RT2860) &&
365 !rt2x00_rt(rt2x00dev, RT2872) &&
366 !rt2x00_rt(rt2x00dev, RT3070) &&
367 ((len / fw_len) == 1))
368 return FW_BAD_VERSION;
369
370 /*
371 * 8kb firmware files must be checked as if it were
372 * 2 separate firmware files.
373 */
374 while (offset < len) {
375 if (!rt2800_check_firmware_crc(data + offset, fw_len))
376 return FW_BAD_CRC;
377
378 offset += fw_len;
379 }
380
381 return FW_OK;
382}
383EXPORT_SYMBOL_GPL(rt2800_check_firmware);
384
385int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
386 const u8 *data, const size_t len)
387{
388 unsigned int i;
389 u32 reg;
390
391 /*
b9eca242
ID		 392 * If driver doesn't wake up firmware here,
393 * rt2800_load_firmware will hang forever when interface is up again.
f31c9a8c 394 */
b9eca242 395 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
f31c9a8c 396
f31c9a8c
ID		 397 /*
398 * Wait for stable hardware.
399 */
5ffddc49 400 if (rt2800_wait_csr_ready(rt2x00dev))
f31c9a8c 401 return -EBUSY;
f31c9a8c
ID		 402
403 if (rt2x00_is_pci(rt2x00dev))
404 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
405
406 /*
407 * Disable DMA, will be reenabled later when enabling
408 * the radio.
409 */
410 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
411 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
412 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
413 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
414 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
415 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
416 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
417
418 /*
419 * Write firmware to the device.
420 */
421 rt2800_drv_write_firmware(rt2x00dev, data, len);
422
423 /*
424 * Wait for device to stabilize.
425 */
426 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
427 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
428 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
429 break;
430 msleep(1);
431 }
432
433 if (i == REGISTER_BUSY_COUNT) {
434 ERROR(rt2x00dev, "PBF system register not ready.\n");
435 return -EBUSY;
436 }
437
438 /*
439 * Initialize firmware.
440 */
441 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
442 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
443 msleep(1);
444
445 return 0;
446}
447EXPORT_SYMBOL_GPL(rt2800_load_firmware);
448
0c5879bc
ID		 449void rt2800_write_tx_data(struct queue_entry *entry,
450 struct txentry_desc *txdesc)
59679b91 451{
0c5879bc 452 __le32 *txwi = rt2800_drv_get_txwi(entry);
59679b91
GW		 453 u32 word;
454
455 /*
456 * Initialize TX Info descriptor
457 */
458 rt2x00_desc_read(txwi, 0, &word);
459 rt2x00_set_field32(&word, TXWI_W0_FRAG,
460 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
84804cdc
ID		 461 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
462 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
59679b91
GW		 463 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
464 rt2x00_set_field32(&word, TXWI_W0_TS,
465 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
466 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
467 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
468 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
469 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop);
470 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
471 rt2x00_set_field32(&word, TXWI_W0_BW,
472 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
473 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
474 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
475 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
476 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
477 rt2x00_desc_write(txwi, 0, word);
478
479 rt2x00_desc_read(txwi, 1, &word);
480 rt2x00_set_field32(&word, TXWI_W1_ACK,
481 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
482 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
483 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
484 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
485 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
486 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
487 txdesc->key_idx : 0xff);
488 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
489 txdesc->length);
2b23cdaa 490 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
bc8a979e 491 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
59679b91
GW		 492 rt2x00_desc_write(txwi, 1, word);
493
494 /*
495 * Always write 0 to IV/EIV fields, hardware will insert the IV
496 * from the IVEIV register when TXD_W3_WIV is set to 0.
497 * When TXD_W3_WIV is set to 1 it will use the IV data
498 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
499 * crypto entry in the registers should be used to encrypt the frame.
500 */
501 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
502 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
503}
0c5879bc 504EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
59679b91 505
ff6133be 506static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
2de64dd2 507{
74861922
ID		 508 int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
509 int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
510 int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
511 u16 eeprom;
512 u8 offset0;
513 u8 offset1;
514 u8 offset2;
515
e5ef5bad 516 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
74861922
ID		 517 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
518 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
519 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
520 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
521 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
522 } else {
523 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
524 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
525 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
526 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
527 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
528 }
529
530 /*
531 * Convert the value from the descriptor into the RSSI value
532 * If the value in the descriptor is 0, it is considered invalid
533 * and the default (extremely low) rssi value is assumed
534 */
535 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
536 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
537 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
538
539 /*
540 * mac80211 only accepts a single RSSI value. Calculating the
541 * average doesn't deliver a fair answer either since -60:-60 would
542 * be considered equally good as -50:-70 while the second is the one
543 * which gives less energy...
544 */
545 rssi0 = max(rssi0, rssi1);
546 return max(rssi0, rssi2);
547}
548
549void rt2800_process_rxwi(struct queue_entry *entry,
550 struct rxdone_entry_desc *rxdesc)
551{
552 __le32 *rxwi = (__le32 *) entry->skb->data;
2de64dd2
GW		 553 u32 word;
554
555 rt2x00_desc_read(rxwi, 0, &word);
556
557 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
558 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
559
560 rt2x00_desc_read(rxwi, 1, &word);
561
562 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
563 rxdesc->flags |= RX_FLAG_SHORT_GI;
564
565 if (rt2x00_get_field32(word, RXWI_W1_BW))
566 rxdesc->flags |= RX_FLAG_40MHZ;
567
568 /*
569 * Detect RX rate, always use MCS as signal type.
570 */
571 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
572 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
573 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
574
575 /*
576 * Mask of 0x8 bit to remove the short preamble flag.
577 */
578 if (rxdesc->rate_mode == RATE_MODE_CCK)
579 rxdesc->signal &= ~0x8;
580
581 rt2x00_desc_read(rxwi, 2, &word);
582
74861922
ID		 583 /*
584 * Convert descriptor AGC value to RSSI value.
585 */
586 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
2de64dd2
GW		 587
588 /*
589 * Remove RXWI descriptor from start of buffer.
590 */
74861922 591 skb_pull(entry->skb, RXWI_DESC_SIZE);
2de64dd2
GW		 592}
593EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
594
3613884d
ID		 595static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)
596{
597 __le32 *txwi;
598 u32 word;
599 int wcid, ack, pid;
600 int tx_wcid, tx_ack, tx_pid;
601
602 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
603 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
604 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
605
606 /*
607 * This frames has returned with an IO error,
608 * so the status report is not intended for this
609 * frame.
610 */
611 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) {
612 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
613 return false;
614 }
615
616 /*
617 * Validate if this TX status report is intended for
618 * this entry by comparing the WCID/ACK/PID fields.
619 */
620 txwi = rt2800_drv_get_txwi(entry);
621
622 rt2x00_desc_read(txwi, 1, &word);
623 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
624 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK);
625 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID);
626
627 if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid)) {
628 WARNING(entry->queue->rt2x00dev,
629 "TX status report missed for queue %d entry %d\n",
630 entry->queue->qid, entry->entry_idx);
631 rt2x00lib_txdone_noinfo(entry, TXDONE_UNKNOWN);
632 return false;
633 }
634
635 return true;
636}
637
14433331
HS		 638void rt2800_txdone_entry(struct queue_entry *entry, u32 status)
639{
640 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b34793ee 641 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
14433331
HS		 642 struct txdone_entry_desc txdesc;
643 u32 word;
644 u16 mcs, real_mcs;
b34793ee 645 int aggr, ampdu;
14433331
HS		 646 __le32 *txwi;
647
648 /*
649 * Obtain the status about this packet.
650 */
651 txdesc.flags = 0;
652 txwi = rt2800_drv_get_txwi(entry);
653 rt2x00_desc_read(txwi, 0, &word);
b34793ee 654
14433331 655 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
b34793ee
HS		 656 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
657
14433331 658 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
b34793ee
HS		 659 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
660
661 /*
662 * If a frame was meant to be sent as a single non-aggregated MPDU
663 * but ended up in an aggregate the used tx rate doesn't correlate
664 * with the one specified in the TXWI as the whole aggregate is sent
665 * with the same rate.
666 *
667 * For example: two frames are sent to rt2x00, the first one sets
668 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
669 * and requests MCS15. If the hw aggregates both frames into one
670 * AMDPU the tx status for both frames will contain MCS7 although
671 * the frame was sent successfully.
672 *
673 * Hence, replace the requested rate with the real tx rate to not
674 * confuse the rate control algortihm by providing clearly wrong
675 * data.
676 */
677 if (aggr == 1 && ampdu == 0 && real_mcs != mcs) {
678 skbdesc->tx_rate_idx = real_mcs;
679 mcs = real_mcs;
680 }
14433331
HS		 681
682 /*
683 * Ralink has a retry mechanism using a global fallback
684 * table. We setup this fallback table to try the immediate
685 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
686 * always contains the MCS used for the last transmission, be
687 * it successful or not.
688 */
689 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
690 /*
691 * Transmission succeeded. The number of retries is
692 * mcs - real_mcs
693 */
694 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
695 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
696 } else {
697 /*
698 * Transmission failed. The number of retries is
699 * always 7 in this case (for a total number of 8
700 * frames sent).
701 */
702 __set_bit(TXDONE_FAILURE, &txdesc.flags);
703 txdesc.retry = rt2x00dev->long_retry;
704 }
705
706 /*
707 * the frame was retried at least once
708 * -> hw used fallback rates
709 */
710 if (txdesc.retry)
711 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
712
713 rt2x00lib_txdone(entry, &txdesc);
714}
715EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
716
96481b20
ID		 717void rt2800_txdone(struct rt2x00_dev *rt2x00dev)
718{
719 struct data_queue *queue;
720 struct queue_entry *entry;
96481b20 721 u32 reg;
3613884d 722 u8 pid;
96481b20
ID		 723 int i;
724
725 /*
726 * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
727 * at most X times and also stop processing once the TX_STA_FIFO_VALID
728 * flag is not set anymore.
729 *
730 * The legacy drivers use X=TX_RING_SIZE but state in a comment
731 * that the TX_STA_FIFO stack has a size of 16. We stick to our
732 * tx ring size for now.
733 */
efd2f271 734 for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
96481b20
ID		 735 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
736 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
737 break;
738
96481b20
ID		 739 /*
740 * Skip this entry when it contains an invalid
741 * queue identication number.
742 */
bc8a979e 743 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE);
3613884d 744 if (pid >= QID_RX)
96481b20
ID		 745 continue;
746
3613884d 747 queue = rt2x00queue_get_queue(rt2x00dev, pid);
96481b20
ID		 748 if (unlikely(!queue))
749 continue;
750
751 /*
752 * Inside each queue, we process each entry in a chronological
753 * order. We first check that the queue is not empty.
754 */
755 entry = NULL;
756 while (!rt2x00queue_empty(queue)) {
757 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
3613884d 758 if (rt2800_txdone_entry_check(entry, reg))
96481b20 759 break;
96481b20
ID		 760 }
761
762 if (!entry || rt2x00queue_empty(queue))
763 break;
764
14433331 765 rt2800_txdone_entry(entry, reg);
96481b20
ID		 766 }
767}
768EXPORT_SYMBOL_GPL(rt2800_txdone);
769
f0194b2d
GW		 770void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
771{
772 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
773 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
774 unsigned int beacon_base;
775 u32 reg;
776
777 /*
778 * Disable beaconing while we are reloading the beacon data,
779 * otherwise we might be sending out invalid data.
780 */
781 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
782 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
783 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
784
785 /*
786 * Add space for the TXWI in front of the skb.
787 */
788 skb_push(entry->skb, TXWI_DESC_SIZE);
789 memset(entry->skb, 0, TXWI_DESC_SIZE);
790
791 /*
792 * Register descriptor details in skb frame descriptor.
793 */
794 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
795 skbdesc->desc = entry->skb->data;
796 skbdesc->desc_len = TXWI_DESC_SIZE;
797
798 /*
799 * Add the TXWI for the beacon to the skb.
800 */
0c5879bc 801 rt2800_write_tx_data(entry, txdesc);
f0194b2d
GW		 802
803 /*
804 * Dump beacon to userspace through debugfs.
805 */
806 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
807
808 /*
809 * Write entire beacon with TXWI to register.
810 */
811 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
812 rt2800_register_multiwrite(rt2x00dev, beacon_base,
813 entry->skb->data, entry->skb->len);
814
815 /*
816 * Enable beaconing again.
817 */
818 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
819 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
820 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
821 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
822
823 /*
824 * Clean up beacon skb.
825 */
826 dev_kfree_skb_any(entry->skb);
827 entry->skb = NULL;
828}
50e888ea 829EXPORT_SYMBOL_GPL(rt2800_write_beacon);
f0194b2d 830
bf1b1512 831static inline void rt2800_clear_beacon(struct rt2x00_dev *rt2x00dev,
fdb87251
HS		 832 unsigned int beacon_base)
833{
834 int i;
835
836 /*
837 * For the Beacon base registers we only need to clear
838 * the whole TXWI which (when set to 0) will invalidate
839 * the entire beacon.
840 */
841 for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
842 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
843}
844
f4450616
BZ		 845#ifdef CONFIG_RT2X00_LIB_DEBUGFS
846const struct rt2x00debug rt2800_rt2x00debug = {
847 .owner = THIS_MODULE,
848 .csr = {
849 .read = rt2800_register_read,
850 .write = rt2800_register_write,
851 .flags = RT2X00DEBUGFS_OFFSET,
852 .word_base = CSR_REG_BASE,
853 .word_size = sizeof(u32),
854 .word_count = CSR_REG_SIZE / sizeof(u32),
855 },
856 .eeprom = {
857 .read = rt2x00_eeprom_read,
858 .write = rt2x00_eeprom_write,
859 .word_base = EEPROM_BASE,
860 .word_size = sizeof(u16),
861 .word_count = EEPROM_SIZE / sizeof(u16),
862 },
863 .bbp = {
864 .read = rt2800_bbp_read,
865 .write = rt2800_bbp_write,
866 .word_base = BBP_BASE,
867 .word_size = sizeof(u8),
868 .word_count = BBP_SIZE / sizeof(u8),
869 },
870 .rf = {
871 .read = rt2x00_rf_read,
872 .write = rt2800_rf_write,
873 .word_base = RF_BASE,
874 .word_size = sizeof(u32),
875 .word_count = RF_SIZE / sizeof(u32),
876 },
877};
878EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
879#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
880
881int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
882{
883 u32 reg;
884
885 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
886 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
887}
888EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
889
890#ifdef CONFIG_RT2X00_LIB_LEDS
891static void rt2800_brightness_set(struct led_classdev *led_cdev,
892 enum led_brightness brightness)
893{
894 struct rt2x00_led *led =
895 container_of(led_cdev, struct rt2x00_led, led_dev);
896 unsigned int enabled = brightness != LED_OFF;
897 unsigned int bg_mode =
898 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
899 unsigned int polarity =
900 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
901 EEPROM_FREQ_LED_POLARITY);
902 unsigned int ledmode =
903 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
904 EEPROM_FREQ_LED_MODE);
905
906 if (led->type == LED_TYPE_RADIO) {
907 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
908 enabled ? 0x20 : 0);
909 } else if (led->type == LED_TYPE_ASSOC) {
910 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
911 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
912 } else if (led->type == LED_TYPE_QUALITY) {
913 /*
914 * The brightness is divided into 6 levels (0 - 5),
915 * The specs tell us the following levels:
916 * 0, 1 ,3, 7, 15, 31
917 * to determine the level in a simple way we can simply
918 * work with bitshifting:
919 * (1 << level) - 1
920 */
921 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
922 (1 << brightness / (LED_FULL / 6)) - 1,
923 polarity);
924 }
925}
926
927static int rt2800_blink_set(struct led_classdev *led_cdev,
928 unsigned long *delay_on, unsigned long *delay_off)
929{
930 struct rt2x00_led *led =
931 container_of(led_cdev, struct rt2x00_led, led_dev);
932 u32 reg;
933
934 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
935 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
936 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
f4450616
BZ		 937 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
938
939 return 0;
940}
941
b3579d6a 942static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 943 struct rt2x00_led *led, enum led_type type)
944{
945 led->rt2x00dev = rt2x00dev;
946 led->type = type;
947 led->led_dev.brightness_set = rt2800_brightness_set;
948 led->led_dev.blink_set = rt2800_blink_set;
949 led->flags = LED_INITIALIZED;
950}
f4450616
BZ		 951#endif /* CONFIG_RT2X00_LIB_LEDS */
952
953/*
954 * Configuration handlers.
955 */
956static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
957 struct rt2x00lib_crypto *crypto,
958 struct ieee80211_key_conf *key)
959{
960 struct mac_wcid_entry wcid_entry;
961 struct mac_iveiv_entry iveiv_entry;
962 u32 offset;
963 u32 reg;
964
965 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
966
e4a0ab34
ID		 967 if (crypto->cmd == SET_KEY) {
968 rt2800_register_read(rt2x00dev, offset, &reg);
969 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
970 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
971 /*
972 * Both the cipher as the BSS Idx numbers are split in a main
973 * value of 3 bits, and a extended field for adding one additional
974 * bit to the value.
975 */
976 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
977 (crypto->cipher & 0x7));
978 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
979 (crypto->cipher & 0x8) >> 3);
980 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
981 (crypto->bssidx & 0x7));
982 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
983 (crypto->bssidx & 0x8) >> 3);
984 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
985 rt2800_register_write(rt2x00dev, offset, reg);
986 } else {
987 rt2800_register_write(rt2x00dev, offset, 0);
988 }
f4450616
BZ		 989
990 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
991
992 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
993 if ((crypto->cipher == CIPHER_TKIP) ||
994 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
995 (crypto->cipher == CIPHER_AES))
996 iveiv_entry.iv[3] |= 0x20;
997 iveiv_entry.iv[3] |= key->keyidx << 6;
998 rt2800_register_multiwrite(rt2x00dev, offset,
999 &iveiv_entry, sizeof(iveiv_entry));
1000
1001 offset = MAC_WCID_ENTRY(key->hw_key_idx);
1002
1003 memset(&wcid_entry, 0, sizeof(wcid_entry));
1004 if (crypto->cmd == SET_KEY)
1005 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
1006 rt2800_register_multiwrite(rt2x00dev, offset,
1007 &wcid_entry, sizeof(wcid_entry));
1008}
1009
1010int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1011 struct rt2x00lib_crypto *crypto,
1012 struct ieee80211_key_conf *key)
1013{
1014 struct hw_key_entry key_entry;
1015 struct rt2x00_field32 field;
1016 u32 offset;
1017 u32 reg;
1018
1019 if (crypto->cmd == SET_KEY) {
1020 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1021
1022 memcpy(key_entry.key, crypto->key,
1023 sizeof(key_entry.key));
1024 memcpy(key_entry.tx_mic, crypto->tx_mic,
1025 sizeof(key_entry.tx_mic));
1026 memcpy(key_entry.rx_mic, crypto->rx_mic,
1027 sizeof(key_entry.rx_mic));
1028
1029 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1030 rt2800_register_multiwrite(rt2x00dev, offset,
1031 &key_entry, sizeof(key_entry));
1032 }
1033
1034 /*
1035 * The cipher types are stored over multiple registers
1036 * starting with SHARED_KEY_MODE_BASE each word will have
1037 * 32 bits and contains the cipher types for 2 bssidx each.
1038 * Using the correct defines correctly will cause overhead,
1039 * so just calculate the correct offset.
1040 */
1041 field.bit_offset = 4 * (key->hw_key_idx % 8);
1042 field.bit_mask = 0x7 << field.bit_offset;
1043
1044 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1045
1046 rt2800_register_read(rt2x00dev, offset, &reg);
1047 rt2x00_set_field32(&reg, field,
1048 (crypto->cmd == SET_KEY) * crypto->cipher);
1049 rt2800_register_write(rt2x00dev, offset, reg);
1050
1051 /*
1052 * Update WCID information
1053 */
1054 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1055
1056 return 0;
1057}
1058EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1059
1060int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1061 struct rt2x00lib_crypto *crypto,
1062 struct ieee80211_key_conf *key)
1063{
1064 struct hw_key_entry key_entry;
1065 u32 offset;
1066
1067 if (crypto->cmd == SET_KEY) {
1068 /*
1069 * 1 pairwise key is possible per AID, this means that the AID
1070 * equals our hw_key_idx. Make sure the WCID starts _after_ the
1071 * last possible shared key entry.
2a0cfeb8
HS		 1072 *
1073 * Since parts of the pairwise key table might be shared with
1074 * the beacon frame buffers 6 & 7 we should only write into the
1075 * first 222 entries.
f4450616 1076 */
2a0cfeb8 1077 if (crypto->aid > (222 - 32))
f4450616
BZ		 1078 return -ENOSPC;
1079
1080 key->hw_key_idx = 32 + crypto->aid;
1081
1082 memcpy(key_entry.key, crypto->key,
1083 sizeof(key_entry.key));
1084 memcpy(key_entry.tx_mic, crypto->tx_mic,
1085 sizeof(key_entry.tx_mic));
1086 memcpy(key_entry.rx_mic, crypto->rx_mic,
1087 sizeof(key_entry.rx_mic));
1088
1089 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1090 rt2800_register_multiwrite(rt2x00dev, offset,
1091 &key_entry, sizeof(key_entry));
1092 }
1093
1094 /*
1095 * Update WCID information
1096 */
1097 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1098
1099 return 0;
1100}
1101EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1102
1103void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1104 const unsigned int filter_flags)
1105{
1106 u32 reg;
1107
1108 /*
1109 * Start configuration steps.
1110 * Note that the version error will always be dropped
1111 * and broadcast frames will always be accepted since
1112 * there is no filter for it at this time.
1113 */
1114 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1115 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1116 !(filter_flags & FIF_FCSFAIL));
1117 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1118 !(filter_flags & FIF_PLCPFAIL));
1119 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1120 !(filter_flags & FIF_PROMISC_IN_BSS));
1121 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1122 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1123 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1124 !(filter_flags & FIF_ALLMULTI));
1125 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1126 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1127 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1128 !(filter_flags & FIF_CONTROL));
1129 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1130 !(filter_flags & FIF_CONTROL));
1131 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1132 !(filter_flags & FIF_CONTROL));
1133 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1134 !(filter_flags & FIF_CONTROL));
1135 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1136 !(filter_flags & FIF_CONTROL));
1137 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1138 !(filter_flags & FIF_PSPOLL));
1139 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
1140 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
1141 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1142 !(filter_flags & FIF_CONTROL));
1143 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1144}
1145EXPORT_SYMBOL_GPL(rt2800_config_filter);
1146
1147void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1148 struct rt2x00intf_conf *conf, const unsigned int flags)
1149{
f4450616 1150 u32 reg;
fa8b4b22 1151 bool update_bssid = false;
f4450616
BZ		 1152
1153 if (flags & CONFIG_UPDATE_TYPE) {
1154 /*
1155 * Clear current synchronisation setup.
f4450616 1156 */
fdb87251
HS		 1157 rt2800_clear_beacon(rt2x00dev,
1158 HW_BEACON_OFFSET(intf->beacon->entry_idx));
f4450616
BZ		 1159 /*
1160 * Enable synchronisation.
1161 */
1162 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1163 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
1164 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
6a62e5ef 1165 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
ab8966dd
HS		 1166 (conf->sync == TSF_SYNC_ADHOC ||
1167 conf->sync == TSF_SYNC_AP_NONE));
f4450616 1168 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
9f926fb5
HS		 1169
1170 /*
1171 * Enable pre tbtt interrupt for beaconing modes
1172 */
1173 rt2800_register_read(rt2x00dev, INT_TIMER_EN, &reg);
1174 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER,
ab8966dd 1175 (conf->sync == TSF_SYNC_AP_NONE));
9f926fb5
HS		 1176 rt2800_register_write(rt2x00dev, INT_TIMER_EN, reg);
1177
f4450616
BZ		 1178 }
1179
1180 if (flags & CONFIG_UPDATE_MAC) {
fa8b4b22
HS		 1181 if (flags & CONFIG_UPDATE_TYPE &&
1182 conf->sync == TSF_SYNC_AP_NONE) {
1183 /*
1184 * The BSSID register has to be set to our own mac
1185 * address in AP mode.
1186 */
1187 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1188 update_bssid = true;
1189 }
1190
c600c826
ID		 1191 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1192 reg = le32_to_cpu(conf->mac[1]);
1193 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1194 conf->mac[1] = cpu_to_le32(reg);
1195 }
f4450616
BZ		 1196
1197 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1198 conf->mac, sizeof(conf->mac));
1199 }
1200
fa8b4b22 1201 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
c600c826
ID		 1202 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1203 reg = le32_to_cpu(conf->bssid[1]);
1204 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1205 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1206 conf->bssid[1] = cpu_to_le32(reg);
1207 }
f4450616
BZ		 1208
1209 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1210 conf->bssid, sizeof(conf->bssid));
1211 }
1212}
1213EXPORT_SYMBOL_GPL(rt2800_config_intf);
1214
87c1915d
HS		 1215static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1216 struct rt2x00lib_erp *erp)
1217{
1218 bool any_sta_nongf = !!(erp->ht_opmode &
1219 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1220 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1221 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1222 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1223 u32 reg;
1224
1225 /* default protection rate for HT20: OFDM 24M */
1226 mm20_rate = gf20_rate = 0x4004;
1227
1228 /* default protection rate for HT40: duplicate OFDM 24M */
1229 mm40_rate = gf40_rate = 0x4084;
1230
1231 switch (protection) {
1232 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1233 /*
1234 * All STAs in this BSS are HT20/40 but there might be
1235 * STAs not supporting greenfield mode.
1236 * => Disable protection for HT transmissions.
1237 */
1238 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1239
1240 break;
1241 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1242 /*
1243 * All STAs in this BSS are HT20 or HT20/40 but there
1244 * might be STAs not supporting greenfield mode.
1245 * => Protect all HT40 transmissions.
1246 */
1247 mm20_mode = gf20_mode = 0;
1248 mm40_mode = gf40_mode = 2;
1249
1250 break;
1251 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1252 /*
1253 * Nonmember protection:
1254 * According to 802.11n we _should_ protect all
1255 * HT transmissions (but we don't have to).
1256 *
1257 * But if cts_protection is enabled we _shall_ protect
1258 * all HT transmissions using a CCK rate.
1259 *
1260 * And if any station is non GF we _shall_ protect
1261 * GF transmissions.
1262 *
1263 * We decide to protect everything
1264 * -> fall through to mixed mode.
1265 */
1266 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1267 /*
1268 * Legacy STAs are present
1269 * => Protect all HT transmissions.
1270 */
1271 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1272
1273 /*
1274 * If erp protection is needed we have to protect HT
1275 * transmissions with CCK 11M long preamble.
1276 */
1277 if (erp->cts_protection) {
1278 /* don't duplicate RTS/CTS in CCK mode */
1279 mm20_rate = mm40_rate = 0x0003;
1280 gf20_rate = gf40_rate = 0x0003;
1281 }
1282 break;
1283 };
1284
1285 /* check for STAs not supporting greenfield mode */
1286 if (any_sta_nongf)
1287 gf20_mode = gf40_mode = 2;
1288
1289 /* Update HT protection config */
1290 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1291 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1292 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1293 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1294
1295 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1296 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1297 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1298 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1299
1300 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1301 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1302 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1303 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1304
1305 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1306 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1307 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1308 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1309}
1310
02044643
HS		 1311void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1312 u32 changed)
f4450616
BZ		 1313{
1314 u32 reg;
1315
02044643
HS		 1316 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1317 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1318 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1319 !!erp->short_preamble);
1320 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1321 !!erp->short_preamble);
1322 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1323 }
f4450616 1324
02044643
HS		 1325 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1326 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1327 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1328 erp->cts_protection ? 2 : 0);
1329 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1330 }
f4450616 1331
02044643
HS		 1332 if (changed & BSS_CHANGED_BASIC_RATES) {
1333 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1334 erp->basic_rates);
1335 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1336 }
f4450616 1337
02044643
HS		 1338 if (changed & BSS_CHANGED_ERP_SLOT) {
1339 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1340 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1341 erp->slot_time);
1342 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
f4450616 1343
02044643
HS		 1344 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1345 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1346 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1347 }
f4450616 1348
02044643
HS		 1349 if (changed & BSS_CHANGED_BEACON_INT) {
1350 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1351 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1352 erp->beacon_int * 16);
1353 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1354 }
87c1915d
HS		 1355
1356 if (changed & BSS_CHANGED_HT)
1357 rt2800_config_ht_opmode(rt2x00dev, erp);
f4450616
BZ		 1358}
1359EXPORT_SYMBOL_GPL(rt2800_config_erp);
1360
1361void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1362{
1363 u8 r1;
1364 u8 r3;
1365
1366 rt2800_bbp_read(rt2x00dev, 1, &r1);
1367 rt2800_bbp_read(rt2x00dev, 3, &r3);
1368
1369 /*
1370 * Configure the TX antenna.
1371 */
1372 switch ((int)ant->tx) {
1373 case 1:
1374 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1375 break;
1376 case 2:
1377 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1378 break;
1379 case 3:
e22557f2 1380 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1381 break;
1382 }
1383
1384 /*
1385 * Configure the RX antenna.
1386 */
1387 switch ((int)ant->rx) {
1388 case 1:
1389 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1390 break;
1391 case 2:
1392 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1393 break;
1394 case 3:
1395 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1396 break;
1397 }
1398
1399 rt2800_bbp_write(rt2x00dev, 3, r3);
1400 rt2800_bbp_write(rt2x00dev, 1, r1);
1401}
1402EXPORT_SYMBOL_GPL(rt2800_config_ant);
1403
1404static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1405 struct rt2x00lib_conf *libconf)
1406{
1407 u16 eeprom;
1408 short lna_gain;
1409
1410 if (libconf->rf.channel <= 14) {
1411 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1412 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1413 } else if (libconf->rf.channel <= 64) {
1414 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1415 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1416 } else if (libconf->rf.channel <= 128) {
1417 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1418 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1419 } else {
1420 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1421 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1422 }
1423
1424 rt2x00dev->lna_gain = lna_gain;
1425}
1426
06855ef4
GW		 1427static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1428 struct ieee80211_conf *conf,
1429 struct rf_channel *rf,
1430 struct channel_info *info)
f4450616
BZ		 1431{
1432 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1433
1434 if (rt2x00dev->default_ant.tx == 1)
1435 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1436
1437 if (rt2x00dev->default_ant.rx == 1) {
1438 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1439 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1440 } else if (rt2x00dev->default_ant.rx == 2)
1441 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1442
1443 if (rf->channel > 14) {
1444 /*
1445 * When TX power is below 0, we should increase it by 7 to
1446 * make it a positive value (Minumum value is -7).
1447 * However this means that values between 0 and 7 have
1448 * double meaning, and we should set a 7DBm boost flag.
1449 */
1450 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
8d1331b3 1451 (info->default_power1 >= 0));
f4450616 1452
8d1331b3
ID		 1453 if (info->default_power1 < 0)
1454 info->default_power1 += 7;
f4450616 1455
8d1331b3 1456 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
f4450616
BZ		 1457
1458 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
8d1331b3 1459 (info->default_power2 >= 0));
f4450616 1460
8d1331b3
ID		 1461 if (info->default_power2 < 0)
1462 info->default_power2 += 7;
f4450616 1463
8d1331b3 1464 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
f4450616 1465 } else {
8d1331b3
ID		 1466 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1467 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
f4450616
BZ		 1468 }
1469
1470 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1471
1472 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1473 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1474 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1475 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1476
1477 udelay(200);
1478
1479 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1480 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1481 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1482 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1483
1484 udelay(200);
1485
1486 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1487 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1488 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1489 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1490}
1491
06855ef4
GW		 1492static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1493 struct ieee80211_conf *conf,
1494 struct rf_channel *rf,
1495 struct channel_info *info)
f4450616
BZ		 1496{
1497 u8 rfcsr;
1498
1499 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
41a26170 1500 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
f4450616
BZ		 1501
1502 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 1503 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 1504 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1505
1506 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
8d1331b3 1507 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
f4450616
BZ		 1508 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1509
5a673964 1510 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
8d1331b3 1511 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
5a673964
HS		 1512 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1513
f4450616
BZ		 1514 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1515 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1516 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1517
1518 rt2800_rfcsr_write(rt2x00dev, 24,
1519 rt2x00dev->calibration[conf_is_ht40(conf)]);
1520
71976907 1521 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 1522 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 1523 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
f4450616
BZ		 1524}
1525
1526static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1527 struct ieee80211_conf *conf,
1528 struct rf_channel *rf,
1529 struct channel_info *info)
1530{
1531 u32 reg;
1532 unsigned int tx_pin;
1533 u8 bbp;
1534
46323e11 1535 if (rf->channel <= 14) {
8d1331b3
ID		 1536 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
1537 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
46323e11 1538 } else {
8d1331b3
ID		 1539 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
1540 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
46323e11
ID		 1541 }
1542
06855ef4
GW		 1543 if (rt2x00_rf(rt2x00dev, RF2020) ||
1544 rt2x00_rf(rt2x00dev, RF3020) ||
1545 rt2x00_rf(rt2x00dev, RF3021) ||
46323e11 1546 rt2x00_rf(rt2x00dev, RF3022) ||
f93bc9b3
GW		 1547 rt2x00_rf(rt2x00dev, RF3052) ||
1548 rt2x00_rf(rt2x00dev, RF3320))
06855ef4 1549 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
fa6f632f 1550 else
06855ef4 1551 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
f4450616
BZ		 1552
1553 /*
1554 * Change BBP settings
1555 */
1556 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1557 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1558 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1559 rt2800_bbp_write(rt2x00dev, 86, 0);
1560
1561 if (rf->channel <= 14) {
1562 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1563 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1564 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1565 } else {
1566 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1567 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1568 }
1569 } else {
1570 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1571
1572 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1573 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1574 else
1575 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1576 }
1577
1578 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 1579 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1580 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1581 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1582 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1583
1584 tx_pin = 0;
1585
1586 /* Turn on unused PA or LNA when not using 1T or 1R */
1587 if (rt2x00dev->default_ant.tx != 1) {
1588 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1589 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1590 }
1591
1592 /* Turn on unused PA or LNA when not using 1T or 1R */
1593 if (rt2x00dev->default_ant.rx != 1) {
1594 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1595 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1596 }
1597
1598 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1599 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1600 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1601 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1602 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1603 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1604
1605 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1606
1607 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1608 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1609 rt2800_bbp_write(rt2x00dev, 4, bbp);
1610
1611 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 1612 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1613 rt2800_bbp_write(rt2x00dev, 3, bbp);
1614
8d0c9b65 1615 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 1616 if (conf_is_ht40(conf)) {
1617 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1618 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1619 rt2800_bbp_write(rt2x00dev, 73, 0x16);
1620 } else {
1621 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1622 rt2800_bbp_write(rt2x00dev, 70, 0x08);
1623 rt2800_bbp_write(rt2x00dev, 73, 0x11);
1624 }
1625 }
1626
1627 msleep(1);
977206d7
HS		 1628
1629 /*
1630 * Clear channel statistic counters
1631 */
1632 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
1633 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
1634 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
f4450616
BZ		 1635}
1636
1637static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
5e846004 1638 const int max_txpower)
f4450616 1639{
5e846004
HS		 1640 u8 txpower;
1641 u8 max_value = (u8)max_txpower;
1642 u16 eeprom;
1643 int i;
f4450616 1644 u32 reg;
f4450616 1645 u8 r1;
5e846004 1646 u32 offset;
f4450616 1647
5e846004
HS		 1648 /*
1649 * set to normal tx power mode: +/- 0dBm
1650 */
f4450616 1651 rt2800_bbp_read(rt2x00dev, 1, &r1);
a3f84ca4 1652 rt2x00_set_field8(&r1, BBP1_TX_POWER, 0);
f4450616
BZ		 1653 rt2800_bbp_write(rt2x00dev, 1, r1);
1654
5e846004
HS		 1655 /*
1656 * The eeprom contains the tx power values for each rate. These
1657 * values map to 100% tx power. Each 16bit word contains four tx
1658 * power values and the order is the same as used in the TX_PWR_CFG
1659 * registers.
1660 */
1661 offset = TX_PWR_CFG_0;
1662
1663 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
1664 /* just to be safe */
1665 if (offset > TX_PWR_CFG_4)
1666 break;
1667
1668 rt2800_register_read(rt2x00dev, offset, &reg);
1669
1670 /* read the next four txpower values */
1671 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
1672 &eeprom);
1673
1674 /* TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
1675 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
1676 * TX_PWR_CFG_4: unknown */
1677 txpower = rt2x00_get_field16(eeprom,
1678 EEPROM_TXPOWER_BYRATE_RATE0);
1679 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0,
1680 min(txpower, max_value));
1681
1682 /* TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
1683 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
1684 * TX_PWR_CFG_4: unknown */
1685 txpower = rt2x00_get_field16(eeprom,
1686 EEPROM_TXPOWER_BYRATE_RATE1);
1687 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1,
1688 min(txpower, max_value));
1689
1690 /* TX_PWR_CFG_0: 55MBS, TX_PWR_CFG_1: 48MBS,
1691 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
1692 * TX_PWR_CFG_4: unknown */
1693 txpower = rt2x00_get_field16(eeprom,
1694 EEPROM_TXPOWER_BYRATE_RATE2);
1695 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2,
1696 min(txpower, max_value));
1697
1698 /* TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
1699 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
1700 * TX_PWR_CFG_4: unknown */
1701 txpower = rt2x00_get_field16(eeprom,
1702 EEPROM_TXPOWER_BYRATE_RATE3);
1703 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3,
1704 min(txpower, max_value));
1705
1706 /* read the next four txpower values */
1707 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
1708 &eeprom);
1709
1710 /* TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
1711 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
1712 * TX_PWR_CFG_4: unknown */
1713 txpower = rt2x00_get_field16(eeprom,
1714 EEPROM_TXPOWER_BYRATE_RATE0);
1715 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4,
1716 min(txpower, max_value));
1717
1718 /* TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
1719 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
1720 * TX_PWR_CFG_4: unknown */
1721 txpower = rt2x00_get_field16(eeprom,
1722 EEPROM_TXPOWER_BYRATE_RATE1);
1723 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5,
1724 min(txpower, max_value));
1725
1726 /* TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
1727 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
1728 * TX_PWR_CFG_4: unknown */
1729 txpower = rt2x00_get_field16(eeprom,
1730 EEPROM_TXPOWER_BYRATE_RATE2);
1731 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6,
1732 min(txpower, max_value));
1733
1734 /* TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
1735 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
1736 * TX_PWR_CFG_4: unknown */
1737 txpower = rt2x00_get_field16(eeprom,
1738 EEPROM_TXPOWER_BYRATE_RATE3);
1739 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7,
1740 min(txpower, max_value));
1741
1742 rt2800_register_write(rt2x00dev, offset, reg);
1743
1744 /* next TX_PWR_CFG register */
1745 offset += 4;
1746 }
f4450616
BZ		 1747}
1748
1749static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1750 struct rt2x00lib_conf *libconf)
1751{
1752 u32 reg;
1753
1754 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1755 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1756 libconf->conf->short_frame_max_tx_count);
1757 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1758 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 1759 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1760}
1761
1762static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
1763 struct rt2x00lib_conf *libconf)
1764{
1765 enum dev_state state =
1766 (libconf->conf->flags & IEEE80211_CONF_PS) ?
1767 STATE_SLEEP : STATE_AWAKE;
1768 u32 reg;
1769
1770 if (state == STATE_SLEEP) {
1771 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1772
1773 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1774 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1775 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1776 libconf->conf->listen_interval - 1);
1777 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1778 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1779
1780 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1781 } else {
f4450616
BZ		 1782 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1783 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1784 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1785 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1786 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 1787
1788 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 1789 }
1790}
1791
1792void rt2800_config(struct rt2x00_dev *rt2x00dev,
1793 struct rt2x00lib_conf *libconf,
1794 const unsigned int flags)
1795{
1796 /* Always recalculate LNA gain before changing configuration */
1797 rt2800_config_lna_gain(rt2x00dev, libconf);
1798
1799 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1800 rt2800_config_channel(rt2x00dev, libconf->conf,
1801 &libconf->rf, &libconf->channel);
1802 if (flags & IEEE80211_CONF_CHANGE_POWER)
1803 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1804 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1805 rt2800_config_retry_limit(rt2x00dev, libconf);
1806 if (flags & IEEE80211_CONF_CHANGE_PS)
1807 rt2800_config_ps(rt2x00dev, libconf);
1808}
1809EXPORT_SYMBOL_GPL(rt2800_config);
1810
1811/*
1812 * Link tuning
1813 */
1814void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1815{
1816 u32 reg;
1817
1818 /*
1819 * Update FCS error count from register.
1820 */
1821 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1822 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1823}
1824EXPORT_SYMBOL_GPL(rt2800_link_stats);
1825
1826static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1827{
1828 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
d5385bfc 1829 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 1830 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1831 rt2x00_rt(rt2x00dev, RT3090) ||
1832 rt2x00_rt(rt2x00dev, RT3390))
f4450616
BZ		 1833 return 0x1c + (2 * rt2x00dev->lna_gain);
1834 else
1835 return 0x2e + rt2x00dev->lna_gain;
1836 }
1837
1838 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1839 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1840 else
1841 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1842}
1843
1844static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1845 struct link_qual *qual, u8 vgc_level)
1846{
1847 if (qual->vgc_level != vgc_level) {
1848 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1849 qual->vgc_level = vgc_level;
1850 qual->vgc_level_reg = vgc_level;
1851 }
1852}
1853
1854void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1855{
1856 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1857}
1858EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1859
1860void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1861 const u32 count)
1862{
8d0c9b65 1863 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616
BZ		 1864 return;
1865
1866 /*
1867 * When RSSI is better then -80 increase VGC level with 0x10
1868 */
1869 rt2800_set_vgc(rt2x00dev, qual,
1870 rt2800_get_default_vgc(rt2x00dev) +
1871 ((qual->rssi > -80) * 0x10));
1872}
1873EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 1874
1875/*
1876 * Initialization functions.
1877 */
b9a07ae9 1878static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 1879{
1880 u32 reg;
d5385bfc 1881 u16 eeprom;
fcf51541 1882 unsigned int i;
e3a896b9 1883 int ret;
fcf51541 1884
a9dce149
GW		 1885 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1886 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1887 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1888 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1889 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1890 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1891 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1892
e3a896b9
GW		 1893 ret = rt2800_drv_init_registers(rt2x00dev);
1894 if (ret)
1895 return ret;
fcf51541
BZ		 1896
1897 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1898 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1899 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1900 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1901 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1902 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1903
1904 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1905 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1906 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1907 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1908 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1909 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1910
1911 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1912 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1913
1914 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1915
1916 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
8544df32 1917 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
fcf51541
BZ		 1918 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1919 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1920 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1921 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1922 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1923 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1924
a9dce149
GW		 1925 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
1926
1927 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1928 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
1929 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1930 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1931
64522957 1932 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1933 rt2x00_rt(rt2x00dev, RT3090) ||
1934 rt2x00_rt(rt2x00dev, RT3390)) {
fcf51541
BZ		 1935 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1936 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 1937 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 1938 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1939 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
38c8a566
RJH		 1940 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
1941 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 1942 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1943 0x0000002c);
1944 else
1945 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1946 0x0000000f);
1947 } else {
1948 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1949 }
d5385bfc 1950 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 1951 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 1952
1953 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1954 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1955 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
1956 } else {
1957 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1958 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1959 }
c295a81d
HS		 1960 } else if (rt2800_is_305x_soc(rt2x00dev)) {
1961 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1962 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1963 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
fcf51541
BZ		 1964 } else {
1965 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1966 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1967 }
1968
1969 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1970 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1971 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1972 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1973 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1974 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1975 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1976 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1977 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1978 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1979
1980 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1981 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 1982 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 1983 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1984 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1985
1986 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1987 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 1988 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 1989 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 1990 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 1991 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1992 else
1993 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1994 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1995 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1996 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1997
a9dce149
GW		 1998 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1999 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
2000 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
2001 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
2002 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
2003 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
2004 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
2005 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
2006 rt2800_register_write(rt2x00dev, LED_CFG, reg);
2007
fcf51541
BZ		 2008 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
2009
a9dce149
GW		 2010 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2011 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
2012 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
2013 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
2014 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
2015 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
2016 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
2017 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2018
fcf51541
BZ		 2019 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
2020 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 2021 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 2022 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
2023 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 2024 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 2025 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
2026 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
2027 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2028
2029 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 2030 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541
BZ		 2031 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
2032 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
2033 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2034 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2035 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 2036 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 2037 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 2038 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2039 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 2040 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2041
2042 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 2043 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541
BZ		 2044 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
2045 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
2046 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2047 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2048 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 2049 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 2050 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 2051 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2052 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 2053 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2054
2055 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2056 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2057 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
2058 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
2059 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2060 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2061 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2062 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2063 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2064 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 2065 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2066 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2067
2068 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2069 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
d13a97f0 2070 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
fcf51541
BZ		 2071 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
2072 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2073 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2074 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2075 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2076 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2077 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 2078 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2079 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2080
2081 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2082 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2083 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
2084 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
2085 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2086 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2087 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2088 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2089 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2090 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 2091 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2092 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2093
2094 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2095 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2096 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
2097 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
2098 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2099 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2100 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2101 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2102 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2103 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 2104 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2105 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2106
cea90e55 2107 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 2108 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
2109
2110 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2111 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2112 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2113 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2114 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2115 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
2116 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
2117 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
2118 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
2119 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
2120 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2121 }
2122
961621ab
HS		 2123 /*
2124 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2125 * although it is reserved.
2126 */
2127 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
2128 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
2129 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
2130 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
2131 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
2132 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
2133 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
2134 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
2135 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
2136 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
2137 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
2138 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
2139
fcf51541
BZ		 2140 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
2141
2142 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2143 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
2144 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
2145 IEEE80211_MAX_RTS_THRESHOLD);
2146 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
2147 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2148
2149 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 2150
a21c2ab4
HS		 2151 /*
2152 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
2153 * time should be set to 16. However, the original Ralink driver uses
2154 * 16 for both and indeed using a value of 10 for CCK SIFS results in
2155 * connection problems with 11g + CTS protection. Hence, use the same
2156 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
2157 */
a9dce149 2158 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 2159 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
2160 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 2161 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
2162 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
2163 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
2164 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2165
fcf51541
BZ		 2166 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
2167
2168 /*
2169 * ASIC will keep garbage value after boot, clear encryption keys.
2170 */
2171 for (i = 0; i < 4; i++)
2172 rt2800_register_write(rt2x00dev,
2173 SHARED_KEY_MODE_ENTRY(i), 0);
2174
2175 for (i = 0; i < 256; i++) {
f4e16e41 2176 static const u32 wcid[2] = { 0xffffffff, 0x00ffffff };
fcf51541
BZ		 2177 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
2178 wcid, sizeof(wcid));
2179
2180 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
2181 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
2182 }
2183
2184 /*
2185 * Clear all beacons
fcf51541 2186 */
fdb87251
HS		 2187 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE0);
2188 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE1);
2189 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE2);
2190 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE3);
2191 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE4);
2192 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE5);
2193 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE6);
2194 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE7);
fcf51541 2195
cea90e55 2196 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 2197 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2198 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
2199 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 2200 }
2201
2202 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
2203 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
2204 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
2205 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
2206 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
2207 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
2208 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
2209 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
2210 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
2211 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
2212
2213 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
2214 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
2215 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
2216 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
2217 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
2218 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
2219 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
2220 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
2221 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
2222 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
2223
2224 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
2225 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
2226 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
2227 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
2228 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
2229 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
2230 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
2231 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
2232 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
2233 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
2234
2235 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
2236 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
2237 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
2238 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
2239 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
2240 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
2241
47ee3eb1
HS		 2242 /*
2243 * Do not force the BA window size, we use the TXWI to set it
2244 */
2245 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
2246 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
2247 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
2248 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
2249
fcf51541
BZ		 2250 /*
2251 * We must clear the error counters.
2252 * These registers are cleared on read,
2253 * so we may pass a useless variable to store the value.
2254 */
2255 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2256 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
2257 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
2258 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
2259 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
2260 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
2261
9f926fb5
HS		 2262 /*
2263 * Setup leadtime for pre tbtt interrupt to 6ms
2264 */
2265 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
2266 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
2267 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
2268
977206d7
HS		 2269 /*
2270 * Set up channel statistics timer
2271 */
2272 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
2273 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
2274 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
2275 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
2276 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
2277 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
2278 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
2279
fcf51541
BZ		 2280 return 0;
2281}
fcf51541
BZ		 2282
2283static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
2284{
2285 unsigned int i;
2286 u32 reg;
2287
2288 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2289 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
2290 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
2291 return 0;
2292
2293 udelay(REGISTER_BUSY_DELAY);
2294 }
2295
2296 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
2297 return -EACCES;
2298}
2299
2300static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2301{
2302 unsigned int i;
2303 u8 value;
2304
2305 /*
2306 * BBP was enabled after firmware was loaded,
2307 * but we need to reactivate it now.
2308 */
2309 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2310 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2311 msleep(1);
2312
2313 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2314 rt2800_bbp_read(rt2x00dev, 0, &value);
2315 if ((value != 0xff) && (value != 0x00))
2316 return 0;
2317 udelay(REGISTER_BUSY_DELAY);
2318 }
2319
2320 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
2321 return -EACCES;
2322}
2323
b9a07ae9 2324static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 2325{
2326 unsigned int i;
2327 u16 eeprom;
2328 u8 reg_id;
2329 u8 value;
2330
2331 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
2332 rt2800_wait_bbp_ready(rt2x00dev)))
2333 return -EACCES;
2334
baff8006
HS		 2335 if (rt2800_is_305x_soc(rt2x00dev))
2336 rt2800_bbp_write(rt2x00dev, 31, 0x08);
2337
fcf51541
BZ		 2338 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
2339 rt2800_bbp_write(rt2x00dev, 66, 0x38);
a9dce149
GW		 2340
2341 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2342 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2343 rt2800_bbp_write(rt2x00dev, 73, 0x12);
2344 } else {
2345 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2346 rt2800_bbp_write(rt2x00dev, 73, 0x10);
2347 }
2348
fcf51541 2349 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
8cdd15e0 2350
d5385bfc 2351 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 2352 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2353 rt2x00_rt(rt2x00dev, RT3090) ||
2354 rt2x00_rt(rt2x00dev, RT3390)) {
8cdd15e0
GW		 2355 rt2800_bbp_write(rt2x00dev, 79, 0x13);
2356 rt2800_bbp_write(rt2x00dev, 80, 0x05);
2357 rt2800_bbp_write(rt2x00dev, 81, 0x33);
baff8006
HS		 2358 } else if (rt2800_is_305x_soc(rt2x00dev)) {
2359 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
2360 rt2800_bbp_write(rt2x00dev, 80, 0x08);
8cdd15e0
GW		 2361 } else {
2362 rt2800_bbp_write(rt2x00dev, 81, 0x37);
2363 }
2364
fcf51541
BZ		 2365 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2366 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
a9dce149 2367
5ed8f458 2368 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
a9dce149
GW		 2369 rt2800_bbp_write(rt2x00dev, 84, 0x19);
2370 else
2371 rt2800_bbp_write(rt2x00dev, 84, 0x99);
2372
fcf51541
BZ		 2373 rt2800_bbp_write(rt2x00dev, 86, 0x00);
2374 rt2800_bbp_write(rt2x00dev, 91, 0x04);
2375 rt2800_bbp_write(rt2x00dev, 92, 0x00);
8cdd15e0 2376
d5385bfc 2377 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 2378 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904 2379 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
baff8006
HS		 2380 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
2381 rt2800_is_305x_soc(rt2x00dev))
8cdd15e0
GW		 2382 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
2383 else
2384 rt2800_bbp_write(rt2x00dev, 103, 0x00);
2385
baff8006
HS		 2386 if (rt2800_is_305x_soc(rt2x00dev))
2387 rt2800_bbp_write(rt2x00dev, 105, 0x01);
2388 else
2389 rt2800_bbp_write(rt2x00dev, 105, 0x05);
a9dce149 2390 rt2800_bbp_write(rt2x00dev, 106, 0x35);
fcf51541 2391
64522957 2392 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2393 rt2x00_rt(rt2x00dev, RT3090) ||
2394 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc 2395 rt2800_bbp_read(rt2x00dev, 138, &value);
fcf51541 2396
38c8a566
RJH		 2397 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
2398 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
d5385bfc 2399 value |= 0x20;
38c8a566 2400 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
d5385bfc 2401 value &= ~0x02;
fcf51541 2402
d5385bfc 2403 rt2800_bbp_write(rt2x00dev, 138, value);
fcf51541
BZ		 2404 }
2405
fcf51541
BZ		 2406
2407 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
2408 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
2409
2410 if (eeprom != 0xffff && eeprom != 0x0000) {
2411 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
2412 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
2413 rt2800_bbp_write(rt2x00dev, reg_id, value);
2414 }
2415 }
2416
2417 return 0;
2418}
fcf51541
BZ		 2419
2420static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
2421 bool bw40, u8 rfcsr24, u8 filter_target)
2422{
2423 unsigned int i;
2424 u8 bbp;
2425 u8 rfcsr;
2426 u8 passband;
2427 u8 stopband;
2428 u8 overtuned = 0;
2429
2430 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2431
2432 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2433 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
2434 rt2800_bbp_write(rt2x00dev, 4, bbp);
2435
2436 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2437 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
2438 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2439
2440 /*
2441 * Set power & frequency of passband test tone
2442 */
2443 rt2800_bbp_write(rt2x00dev, 24, 0);
2444
2445 for (i = 0; i < 100; i++) {
2446 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2447 msleep(1);
2448
2449 rt2800_bbp_read(rt2x00dev, 55, &passband);
2450 if (passband)
2451 break;
2452 }
2453
2454 /*
2455 * Set power & frequency of stopband test tone
2456 */
2457 rt2800_bbp_write(rt2x00dev, 24, 0x06);
2458
2459 for (i = 0; i < 100; i++) {
2460 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2461 msleep(1);
2462
2463 rt2800_bbp_read(rt2x00dev, 55, &stopband);
2464
2465 if ((passband - stopband) <= filter_target) {
2466 rfcsr24++;
2467 overtuned += ((passband - stopband) == filter_target);
2468 } else
2469 break;
2470
2471 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2472 }
2473
2474 rfcsr24 -= !!overtuned;
2475
2476 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2477 return rfcsr24;
2478}
2479
b9a07ae9 2480static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 2481{
2482 u8 rfcsr;
2483 u8 bbp;
8cdd15e0
GW		 2484 u32 reg;
2485 u16 eeprom;
fcf51541 2486
d5385bfc 2487 if (!rt2x00_rt(rt2x00dev, RT3070) &&
64522957 2488 !rt2x00_rt(rt2x00dev, RT3071) &&
cc78e904 2489 !rt2x00_rt(rt2x00dev, RT3090) &&
23812383 2490 !rt2x00_rt(rt2x00dev, RT3390) &&
baff8006 2491 !rt2800_is_305x_soc(rt2x00dev))
fcf51541
BZ		 2492 return 0;
2493
fcf51541
BZ		 2494 /*
2495 * Init RF calibration.
2496 */
2497 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2498 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2499 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2500 msleep(1);
2501 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2502 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2503
d5385bfc 2504 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957
GW		 2505 rt2x00_rt(rt2x00dev, RT3071) ||
2506 rt2x00_rt(rt2x00dev, RT3090)) {
fcf51541
BZ		 2507 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2508 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2509 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2510 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
2511 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
8cdd15e0 2512 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
fcf51541
BZ		 2513 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2514 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
2515 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2516 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2517 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2518 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2519 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2520 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2521 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2522 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2523 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
2524 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
fcf51541 2525 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
cc78e904
GW		 2526 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2527 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
2528 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
2529 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
2530 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
fcf51541 2531 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
cc78e904
GW		 2532 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
2533 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
2534 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
2535 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
2536 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2537 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
fcf51541 2538 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
cc78e904
GW		 2539 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
2540 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
fcf51541 2541 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
cc78e904
GW		 2542 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2543 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
2544 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
2545 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
2546 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
2547 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
2548 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
fcf51541 2549 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
cc78e904 2550 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
fcf51541 2551 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
cc78e904
GW		 2552 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2553 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2554 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2555 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
2556 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
2557 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
2558 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
baff8006 2559 } else if (rt2800_is_305x_soc(rt2x00dev)) {
23812383
HS		 2560 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
2561 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
2562 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
2563 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
2564 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2565 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2566 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2567 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
2568 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
2569 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2570 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
2571 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2572 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
2573 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
2574 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2575 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2576 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2577 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2578 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2579 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2580 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2581 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2582 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2583 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
2584 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2585 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2586 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
2587 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
2588 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
2589 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
baff8006
HS		 2590 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
2591 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
2592 return 0;
8cdd15e0
GW		 2593 }
2594
2595 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2596 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2597 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
2598 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2599 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
64522957
GW		 2600 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2601 rt2x00_rt(rt2x00dev, RT3090)) {
d5385bfc
GW		 2602 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2603 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
2604 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2605
2606 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
2607
2608 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2609 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
64522957
GW		 2610 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2611 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
38c8a566
RJH		 2612 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2613 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 2614 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2615 else
2616 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
2617 }
2618 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
cc78e904
GW		 2619 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2620 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
2621 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
2622 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
fcf51541
BZ		 2623 }
2624
2625 /*
2626 * Set RX Filter calibration for 20MHz and 40MHz
2627 */
8cdd15e0
GW		 2628 if (rt2x00_rt(rt2x00dev, RT3070)) {
2629 rt2x00dev->calibration[0] =
2630 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
2631 rt2x00dev->calibration[1] =
2632 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
64522957 2633 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2634 rt2x00_rt(rt2x00dev, RT3090) ||
2635 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 2636 rt2x00dev->calibration[0] =
2637 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
2638 rt2x00dev->calibration[1] =
2639 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
8cdd15e0 2640 }
fcf51541
BZ		 2641
2642 /*
2643 * Set back to initial state
2644 */
2645 rt2800_bbp_write(rt2x00dev, 24, 0);
2646
2647 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2648 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
2649 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2650
2651 /*
2652 * set BBP back to BW20
2653 */
2654 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2655 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
2656 rt2800_bbp_write(rt2x00dev, 4, bbp);
2657
d5385bfc 2658 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 2659 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2660 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2661 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
8cdd15e0
GW		 2662 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
2663
2664 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
2665 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
2666 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
2667
2668 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2669 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
64522957 2670 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2671 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2672 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
8440c292 2673 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
d5385bfc
GW		 2674 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
2675 }
8cdd15e0
GW		 2676 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
2677 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
2678 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
2679 rt2x00_get_field16(eeprom,
2680 EEPROM_TXMIXER_GAIN_BG_VAL));
2681 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2682
64522957
GW		 2683 if (rt2x00_rt(rt2x00dev, RT3090)) {
2684 rt2800_bbp_read(rt2x00dev, 138, &bbp);
2685
38c8a566
RJH		 2686 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
2687 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
64522957 2688 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
38c8a566 2689 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
64522957
GW		 2690 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
2691
2692 rt2800_bbp_write(rt2x00dev, 138, bbp);
2693 }
2694
2695 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2696 rt2x00_rt(rt2x00dev, RT3090) ||
2697 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 2698 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2699 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2700 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2701 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2702 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2703 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2704 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2705
2706 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
2707 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
2708 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
2709
2710 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
2711 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
2712 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
2713
2714 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
2715 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
2716 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
2717 }
2718
2719 if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) {
8cdd15e0 2720 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
d5385bfc
GW		 2721 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2722 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
8cdd15e0
GW		 2723 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
2724 else
2725 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
2726 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
2727 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
2728 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
2729 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
2730 }
2731
fcf51541
BZ		 2732 return 0;
2733}
b9a07ae9
ID		 2734
2735int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
2736{
2737 u32 reg;
2738 u16 word;
2739
2740 /*
2741 * Initialize all registers.
2742 */
2743 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
2744 rt2800_init_registers(rt2x00dev) ||
2745 rt2800_init_bbp(rt2x00dev) ||
2746 rt2800_init_rfcsr(rt2x00dev)))
2747 return -EIO;
2748
2749 /*
2750 * Send signal to firmware during boot time.
2751 */
2752 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
2753
2754 if (rt2x00_is_usb(rt2x00dev) &&
2755 (rt2x00_rt(rt2x00dev, RT3070) ||
2756 rt2x00_rt(rt2x00dev, RT3071) ||
2757 rt2x00_rt(rt2x00dev, RT3572))) {
2758 udelay(200);
2759 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
2760 udelay(10);
2761 }
2762
2763 /*
2764 * Enable RX.
2765 */
2766 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2767 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2768 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2769 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2770
2771 udelay(50);
2772
2773 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2774 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
2775 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
2776 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
2777 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2778 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2779
2780 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2781 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2782 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
2783 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2784
2785 /*
2786 * Initialize LED control
2787 */
38c8a566
RJH		 2788 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
2789 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
b9a07ae9
ID		 2790 word & 0xff, (word >> 8) & 0xff);
2791
38c8a566
RJH		 2792 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
2793 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
b9a07ae9
ID		 2794 word & 0xff, (word >> 8) & 0xff);
2795
38c8a566
RJH		 2796 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
2797 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
b9a07ae9
ID		 2798 word & 0xff, (word >> 8) & 0xff);
2799
2800 return 0;
2801}
2802EXPORT_SYMBOL_GPL(rt2800_enable_radio);
2803
2804void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
2805{
2806 u32 reg;
2807
2808 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2809 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2810 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2811 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2812 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2813 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2814 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2815
2816 /* Wait for DMA, ignore error */
2817 rt2800_wait_wpdma_ready(rt2x00dev);
2818
2819 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2820 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
2821 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2822 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2823
2824 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
2825 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
2826}
2827EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2ce33995 2828
30e84034
BZ		 2829int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
2830{
2831 u32 reg;
2832
2833 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
2834
2835 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
2836}
2837EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
2838
2839static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
2840{
2841 u32 reg;
2842
31a4cf1f
GW		 2843 mutex_lock(&rt2x00dev->csr_mutex);
2844
2845 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
30e84034
BZ		 2846 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
2847 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
2848 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
31a4cf1f 2849 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
30e84034
BZ		 2850
2851 /* Wait until the EEPROM has been loaded */
2852 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
2853
2854 /* Apparently the data is read from end to start */
31a4cf1f
GW		 2855 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
2856 (u32 *)&rt2x00dev->eeprom[i]);
2857 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
2858 (u32 *)&rt2x00dev->eeprom[i + 2]);
2859 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
2860 (u32 *)&rt2x00dev->eeprom[i + 4]);
2861 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
2862 (u32 *)&rt2x00dev->eeprom[i + 6]);
2863
2864 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 2865}
2866
2867void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
2868{
2869 unsigned int i;
2870
2871 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
2872 rt2800_efuse_read(rt2x00dev, i);
2873}
2874EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
2875
38bd7b8a
BZ		 2876int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2877{
2878 u16 word;
2879 u8 *mac;
2880 u8 default_lna_gain;
2881
2882 /*
2883 * Start validation of the data that has been read.
2884 */
2885 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2886 if (!is_valid_ether_addr(mac)) {
2887 random_ether_addr(mac);
2888 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2889 }
2890
38c8a566 2891 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
38bd7b8a 2892 if (word == 0xffff) {
38c8a566
RJH		 2893 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
2894 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
2895 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
2896 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a 2897 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 2898 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 2899 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 2900 /*
2901 * There is a max of 2 RX streams for RT28x0 series
2902 */
38c8a566
RJH		 2903 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
2904 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
2905 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a
BZ		 2906 }
2907
38c8a566 2908 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
38bd7b8a 2909 if (word == 0xffff) {
38c8a566
RJH		 2910 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
2911 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
2912 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
2913 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
2914 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
2915 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
2916 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
2917 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
2918 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
2919 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
2920 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
2921 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
2922 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
2923 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
2924 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
2925 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
38bd7b8a
BZ		 2926 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2927 }
2928
2929 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2930 if ((word & 0x00ff) == 0x00ff) {
2931 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
ec2d1791
GW		 2932 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2933 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2934 }
2935 if ((word & 0xff00) == 0xff00) {
38bd7b8a
BZ		 2936 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2937 LED_MODE_TXRX_ACTIVITY);
2938 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2939 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
38c8a566
RJH		 2940 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
2941 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
2942 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
ec2d1791 2943 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
38bd7b8a
BZ		 2944 }
2945
2946 /*
2947 * During the LNA validation we are going to use
2948 * lna0 as correct value. Note that EEPROM_LNA
2949 * is never validated.
2950 */
2951 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2952 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2953
2954 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2955 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2956 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2957 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2958 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2959 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2960
2961 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2962 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2963 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2964 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2965 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2966 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2967 default_lna_gain);
2968 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2969
2970 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2971 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2972 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2973 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2974 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2975 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2976
2977 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2978 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2979 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2980 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2981 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2982 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2983 default_lna_gain);
2984 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2985
8d1331b3
ID		 2986 rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &word);
2987 if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_24GHZ) == 0xff)
2988 rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_24GHZ, MAX_G_TXPOWER);
2989 if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_5GHZ) == 0xff)
2990 rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_5GHZ, MAX_A_TXPOWER);
2991 rt2x00_eeprom_write(rt2x00dev, EEPROM_MAX_TX_POWER, word);
2992
38bd7b8a
BZ		 2993 return 0;
2994}
2995EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
2996
2997int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
2998{
2999 u32 reg;
3000 u16 value;
3001 u16 eeprom;
3002
3003 /*
3004 * Read EEPROM word for configuration.
3005 */
38c8a566 3006 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
38bd7b8a
BZ		 3007
3008 /*
3009 * Identify RF chipset.
3010 */
38c8a566 3011 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
38bd7b8a
BZ		 3012 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
3013
49e721ec
GW		 3014 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
3015 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
3016
3017 if (!rt2x00_rt(rt2x00dev, RT2860) &&
49e721ec 3018 !rt2x00_rt(rt2x00dev, RT2872) &&
49e721ec 3019 !rt2x00_rt(rt2x00dev, RT2883) &&
49e721ec
GW		 3020 !rt2x00_rt(rt2x00dev, RT3070) &&
3021 !rt2x00_rt(rt2x00dev, RT3071) &&
3022 !rt2x00_rt(rt2x00dev, RT3090) &&
3023 !rt2x00_rt(rt2x00dev, RT3390) &&
3024 !rt2x00_rt(rt2x00dev, RT3572)) {
3025 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
3026 return -ENODEV;
f273fe55 3027 }
714fa663 3028
5122d898
GW		 3029 if (!rt2x00_rf(rt2x00dev, RF2820) &&
3030 !rt2x00_rf(rt2x00dev, RF2850) &&
3031 !rt2x00_rf(rt2x00dev, RF2720) &&
3032 !rt2x00_rf(rt2x00dev, RF2750) &&
3033 !rt2x00_rf(rt2x00dev, RF3020) &&
3034 !rt2x00_rf(rt2x00dev, RF2020) &&
3035 !rt2x00_rf(rt2x00dev, RF3021) &&
6c0fe265 3036 !rt2x00_rf(rt2x00dev, RF3022) &&
f93bc9b3
GW		 3037 !rt2x00_rf(rt2x00dev, RF3052) &&
3038 !rt2x00_rf(rt2x00dev, RF3320)) {
38bd7b8a
BZ		 3039 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
3040 return -ENODEV;
3041 }
3042
3043 /*
3044 * Identify default antenna configuration.
3045 */
3046 rt2x00dev->default_ant.tx =
38c8a566 3047 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
38bd7b8a 3048 rt2x00dev->default_ant.rx =
38c8a566 3049 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
38bd7b8a
BZ		 3050
3051 /*
3052 * Read frequency offset and RF programming sequence.
3053 */
3054 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
3055 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
3056
3057 /*
3058 * Read external LNA informations.
3059 */
38c8a566 3060 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
38bd7b8a 3061
38c8a566 3062 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
38bd7b8a 3063 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
38c8a566 3064 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
38bd7b8a
BZ		 3065 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
3066
3067 /*
3068 * Detect if this device has an hardware controlled radio.
3069 */
38c8a566 3070 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
38bd7b8a
BZ		 3071 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
3072
3073 /*
3074 * Store led settings, for correct led behaviour.
3075 */
3076#ifdef CONFIG_RT2X00_LIB_LEDS
3077 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3078 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
3079 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
3080
3081 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
3082#endif /* CONFIG_RT2X00_LIB_LEDS */
3083
3084 return 0;
3085}
3086EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
3087
4da2933f 3088/*
55f9321a 3089 * RF value list for rt28xx
4da2933f
BZ		 3090 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
3091 */
3092static const struct rf_channel rf_vals[] = {
3093 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
3094 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
3095 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
3096 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
3097 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
3098 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
3099 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
3100 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
3101 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
3102 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
3103 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
3104 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
3105 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
3106 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
3107
3108 /* 802.11 UNI / HyperLan 2 */
3109 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
3110 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
3111 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
3112 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
3113 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
3114 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
3115 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
3116 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
3117 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
3118 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
3119 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
3120 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
3121
3122 /* 802.11 HyperLan 2 */
3123 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
3124 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
3125 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
3126 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
3127 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
3128 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
3129 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
3130 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
3131 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
3132 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
3133 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
3134 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
3135 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
3136 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
3137 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
3138 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
3139
3140 /* 802.11 UNII */
3141 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
3142 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
3143 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
3144 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
3145 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
3146 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
3147 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
3148 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
3149 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
3150 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
3151 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
3152
3153 /* 802.11 Japan */
3154 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
3155 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
3156 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
3157 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
3158 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
3159 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
3160 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
3161};
3162
3163/*
55f9321a
ID		 3164 * RF value list for rt3xxx
3165 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4da2933f 3166 */
55f9321a 3167static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 3168 {1, 241, 2, 2 },
3169 {2, 241, 2, 7 },
3170 {3, 242, 2, 2 },
3171 {4, 242, 2, 7 },
3172 {5, 243, 2, 2 },
3173 {6, 243, 2, 7 },
3174 {7, 244, 2, 2 },
3175 {8, 244, 2, 7 },
3176 {9, 245, 2, 2 },
3177 {10, 245, 2, 7 },
3178 {11, 246, 2, 2 },
3179 {12, 246, 2, 7 },
3180 {13, 247, 2, 2 },
3181 {14, 248, 2, 4 },
55f9321a
ID		 3182
3183 /* 802.11 UNI / HyperLan 2 */
3184 {36, 0x56, 0, 4},
3185 {38, 0x56, 0, 6},
3186 {40, 0x56, 0, 8},
3187 {44, 0x57, 0, 0},
3188 {46, 0x57, 0, 2},
3189 {48, 0x57, 0, 4},
3190 {52, 0x57, 0, 8},
3191 {54, 0x57, 0, 10},
3192 {56, 0x58, 0, 0},
3193 {60, 0x58, 0, 4},
3194 {62, 0x58, 0, 6},
3195 {64, 0x58, 0, 8},
3196
3197 /* 802.11 HyperLan 2 */
3198 {100, 0x5b, 0, 8},
3199 {102, 0x5b, 0, 10},
3200 {104, 0x5c, 0, 0},
3201 {108, 0x5c, 0, 4},
3202 {110, 0x5c, 0, 6},
3203 {112, 0x5c, 0, 8},
3204 {116, 0x5d, 0, 0},
3205 {118, 0x5d, 0, 2},
3206 {120, 0x5d, 0, 4},
3207 {124, 0x5d, 0, 8},
3208 {126, 0x5d, 0, 10},
3209 {128, 0x5e, 0, 0},
3210 {132, 0x5e, 0, 4},
3211 {134, 0x5e, 0, 6},
3212 {136, 0x5e, 0, 8},
3213 {140, 0x5f, 0, 0},
3214
3215 /* 802.11 UNII */
3216 {149, 0x5f, 0, 9},
3217 {151, 0x5f, 0, 11},
3218 {153, 0x60, 0, 1},
3219 {157, 0x60, 0, 5},
3220 {159, 0x60, 0, 7},
3221 {161, 0x60, 0, 9},
3222 {165, 0x61, 0, 1},
3223 {167, 0x61, 0, 3},
3224 {169, 0x61, 0, 5},
3225 {171, 0x61, 0, 7},
3226 {173, 0x61, 0, 9},
4da2933f
BZ		 3227};
3228
3229int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
3230{
4da2933f
BZ		 3231 struct hw_mode_spec *spec = &rt2x00dev->spec;
3232 struct channel_info *info;
8d1331b3
ID		 3233 char *default_power1;
3234 char *default_power2;
4da2933f 3235 unsigned int i;
8d1331b3 3236 unsigned short max_power;
4da2933f
BZ		 3237 u16 eeprom;
3238
93b6bd26
GW		 3239 /*
3240 * Disable powersaving as default on PCI devices.
3241 */
cea90e55 3242 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
93b6bd26
GW		 3243 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3244
4da2933f
BZ		 3245 /*
3246 * Initialize all hw fields.
3247 */
3248 rt2x00dev->hw->flags =
4da2933f
BZ		 3249 IEEE80211_HW_SIGNAL_DBM |
3250 IEEE80211_HW_SUPPORTS_PS |
1df90809
HS		 3251 IEEE80211_HW_PS_NULLFUNC_STACK |
3252 IEEE80211_HW_AMPDU_AGGREGATION;
5a5b6ed6
HS		 3253 /*
3254 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
3255 * unless we are capable of sending the buffered frames out after the
3256 * DTIM transmission using rt2x00lib_beacondone. This will send out
3257 * multicast and broadcast traffic immediately instead of buffering it
3258 * infinitly and thus dropping it after some time.
3259 */
3260 if (!rt2x00_is_usb(rt2x00dev))
3261 rt2x00dev->hw->flags |=
3262 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
4da2933f 3263
4da2933f
BZ		 3264 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
3265 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3266 rt2x00_eeprom_addr(rt2x00dev,
3267 EEPROM_MAC_ADDR_0));
3268
3f2bee24
HS		 3269 /*
3270 * As rt2800 has a global fallback table we cannot specify
3271 * more then one tx rate per frame but since the hw will
3272 * try several rates (based on the fallback table) we should
ba3b9e5e 3273 * initialize max_report_rates to the maximum number of rates
3f2bee24
HS		 3274 * we are going to try. Otherwise mac80211 will truncate our
3275 * reported tx rates and the rc algortihm will end up with
3276 * incorrect data.
3277 */
ba3b9e5e
HS		 3278 rt2x00dev->hw->max_rates = 1;
3279 rt2x00dev->hw->max_report_rates = 7;
3f2bee24
HS		 3280 rt2x00dev->hw->max_rate_tries = 1;
3281
38c8a566 3282 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4da2933f
BZ		 3283
3284 /*
3285 * Initialize hw_mode information.
3286 */
3287 spec->supported_bands = SUPPORT_BAND_2GHZ;
3288 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
3289
5122d898 3290 if (rt2x00_rf(rt2x00dev, RF2820) ||
55f9321a 3291 rt2x00_rf(rt2x00dev, RF2720)) {
4da2933f
BZ		 3292 spec->num_channels = 14;
3293 spec->channels = rf_vals;
55f9321a
ID		 3294 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
3295 rt2x00_rf(rt2x00dev, RF2750)) {
4da2933f
BZ		 3296 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3297 spec->num_channels = ARRAY_SIZE(rf_vals);
3298 spec->channels = rf_vals;
5122d898
GW		 3299 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
3300 rt2x00_rf(rt2x00dev, RF2020) ||
3301 rt2x00_rf(rt2x00dev, RF3021) ||
f93bc9b3
GW		 3302 rt2x00_rf(rt2x00dev, RF3022) ||
3303 rt2x00_rf(rt2x00dev, RF3320)) {
55f9321a
ID		 3304 spec->num_channels = 14;
3305 spec->channels = rf_vals_3x;
3306 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
3307 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3308 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
3309 spec->channels = rf_vals_3x;
4da2933f
BZ		 3310 }
3311
3312 /*
3313 * Initialize HT information.
3314 */
5122d898 3315 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 3316 spec->ht.ht_supported = true;
3317 else
3318 spec->ht.ht_supported = false;
3319
4da2933f 3320 spec->ht.cap =
06443e46 3321 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 3322 IEEE80211_HT_CAP_GRN_FLD |
3323 IEEE80211_HT_CAP_SGI_20 |
aa674631 3324 IEEE80211_HT_CAP_SGI_40;
22cabaa6 3325
38c8a566 3326 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
22cabaa6
HS		 3327 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
3328
aa674631 3329 spec->ht.cap |=
38c8a566 3330 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
aa674631
ID		 3331 IEEE80211_HT_CAP_RX_STBC_SHIFT;
3332
4da2933f
BZ		 3333 spec->ht.ampdu_factor = 3;
3334 spec->ht.ampdu_density = 4;
3335 spec->ht.mcs.tx_params =
3336 IEEE80211_HT_MCS_TX_DEFINED |
3337 IEEE80211_HT_MCS_TX_RX_DIFF |
38c8a566 3338 ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
4da2933f
BZ		 3339 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
3340
38c8a566 3341 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
4da2933f
BZ		 3342 case 3:
3343 spec->ht.mcs.rx_mask[2] = 0xff;
3344 case 2:
3345 spec->ht.mcs.rx_mask[1] = 0xff;
3346 case 1:
3347 spec->ht.mcs.rx_mask[0] = 0xff;
3348 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
3349 break;
3350 }
3351
3352 /*
3353 * Create channel information array
3354 */
baeb2ffa 3355 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4da2933f
BZ		 3356 if (!info)
3357 return -ENOMEM;
3358
3359 spec->channels_info = info;
3360
8d1331b3
ID		 3361 rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &eeprom);
3362 max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_24GHZ);
3363 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
3364 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4da2933f
BZ		 3365
3366 for (i = 0; i < 14; i++) {
8d1331b3
ID		 3367 info[i].max_power = max_power;
3368 info[i].default_power1 = TXPOWER_G_FROM_DEV(default_power1[i]);
3369 info[i].default_power2 = TXPOWER_G_FROM_DEV(default_power2[i]);
4da2933f
BZ		 3370 }
3371
3372 if (spec->num_channels > 14) {
8d1331b3
ID		 3373 max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_5GHZ);
3374 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
3375 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4da2933f
BZ		 3376
3377 for (i = 14; i < spec->num_channels; i++) {
8d1331b3
ID		 3378 info[i].max_power = max_power;
3379 info[i].default_power1 = TXPOWER_A_FROM_DEV(default_power1[i]);
3380 info[i].default_power2 = TXPOWER_A_FROM_DEV(default_power2[i]);
4da2933f
BZ		 3381 }
3382 }
3383
3384 return 0;
3385}
3386EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
3387
2ce33995
BZ		 3388/*
3389 * IEEE80211 stack callback functions.
3390 */
e783619e
HS		 3391void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
3392 u16 *iv16)
2ce33995
BZ		 3393{
3394 struct rt2x00_dev *rt2x00dev = hw->priv;
3395 struct mac_iveiv_entry iveiv_entry;
3396 u32 offset;
3397
3398 offset = MAC_IVEIV_ENTRY(hw_key_idx);
3399 rt2800_register_multiread(rt2x00dev, offset,
3400 &iveiv_entry, sizeof(iveiv_entry));
3401
855da5e0
JL		 3402 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
3403 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995 3404}
e783619e 3405EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
2ce33995 3406
e783619e 3407int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2ce33995
BZ		 3408{
3409 struct rt2x00_dev *rt2x00dev = hw->priv;
3410 u32 reg;
3411 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
3412
3413 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3414 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
3415 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3416
3417 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3418 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
3419 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3420
3421 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3422 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
3423 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3424
3425 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3426 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
3427 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3428
3429 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3430 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
3431 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3432
3433 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3434 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
3435 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3436
3437 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3438 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
3439 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3440
3441 return 0;
3442}
e783619e 3443EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2ce33995 3444
e783619e
HS		 3445int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
3446 const struct ieee80211_tx_queue_params *params)
2ce33995
BZ		 3447{
3448 struct rt2x00_dev *rt2x00dev = hw->priv;
3449 struct data_queue *queue;
3450 struct rt2x00_field32 field;
3451 int retval;
3452 u32 reg;
3453 u32 offset;
3454
3455 /*
3456 * First pass the configuration through rt2x00lib, that will
3457 * update the queue settings and validate the input. After that
3458 * we are free to update the registers based on the value
3459 * in the queue parameter.
3460 */
3461 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
3462 if (retval)
3463 return retval;
3464
3465 /*
3466 * We only need to perform additional register initialization
3467 * for WMM queues/
3468 */
3469 if (queue_idx >= 4)
3470 return 0;
3471
3472 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
3473
3474 /* Update WMM TXOP register */
3475 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
3476 field.bit_offset = (queue_idx & 1) * 16;
3477 field.bit_mask = 0xffff << field.bit_offset;
3478
3479 rt2800_register_read(rt2x00dev, offset, &reg);
3480 rt2x00_set_field32(&reg, field, queue->txop);
3481 rt2800_register_write(rt2x00dev, offset, reg);
3482
3483 /* Update WMM registers */
3484 field.bit_offset = queue_idx * 4;
3485 field.bit_mask = 0xf << field.bit_offset;
3486
3487 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
3488 rt2x00_set_field32(&reg, field, queue->aifs);
3489 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
3490
3491 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
3492 rt2x00_set_field32(&reg, field, queue->cw_min);
3493 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
3494
3495 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
3496 rt2x00_set_field32(&reg, field, queue->cw_max);
3497 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
3498
3499 /* Update EDCA registers */
3500 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
3501
3502 rt2800_register_read(rt2x00dev, offset, &reg);
3503 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
3504 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
3505 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
3506 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
3507 rt2800_register_write(rt2x00dev, offset, reg);
3508
3509 return 0;
3510}
e783619e 3511EXPORT_SYMBOL_GPL(rt2800_conf_tx);
2ce33995 3512
e783619e 3513u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2ce33995
BZ		 3514{
3515 struct rt2x00_dev *rt2x00dev = hw->priv;
3516 u64 tsf;
3517 u32 reg;
3518
3519 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
3520 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
3521 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
3522 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
3523
3524 return tsf;
3525}
e783619e 3526EXPORT_SYMBOL_GPL(rt2800_get_tsf);
2ce33995 3527
e783619e
HS		 3528int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3529 enum ieee80211_ampdu_mlme_action action,
3530 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
1df90809 3531{
1df90809
HS		 3532 int ret = 0;
3533
3534 switch (action) {
3535 case IEEE80211_AMPDU_RX_START:
3536 case IEEE80211_AMPDU_RX_STOP:
58ed826e
HS		 3537 /*
3538 * The hw itself takes care of setting up BlockAck mechanisms.
3539 * So, we only have to allow mac80211 to nagotiate a BlockAck
3540 * agreement. Once that is done, the hw will BlockAck incoming
3541 * AMPDUs without further setup.
3542 */
1df90809
HS		 3543 break;
3544 case IEEE80211_AMPDU_TX_START:
3545 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3546 break;
3547 case IEEE80211_AMPDU_TX_STOP:
3548 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3549 break;
3550 case IEEE80211_AMPDU_TX_OPERATIONAL:
3551 break;
3552 default:
4e9e58c6 3553 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
1df90809
HS		 3554 }
3555
3556 return ret;
3557}
e783619e 3558EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
a5ea2f02 3559
977206d7
HS		 3560int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
3561 struct survey_info *survey)
3562{
3563 struct rt2x00_dev *rt2x00dev = hw->priv;
3564 struct ieee80211_conf *conf = &hw->conf;
3565 u32 idle, busy, busy_ext;
3566
3567 if (idx != 0)
3568 return -ENOENT;
3569
3570 survey->channel = conf->channel;
3571
3572 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
3573 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
3574 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
3575
3576 if (idle || busy) {
3577 survey->filled = SURVEY_INFO_CHANNEL_TIME |
3578 SURVEY_INFO_CHANNEL_TIME_BUSY |
3579 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
3580
3581 survey->channel_time = (idle + busy) / 1000;
3582 survey->channel_time_busy = busy / 1000;
3583 survey->channel_time_ext_busy = busy_ext / 1000;
3584 }
3585
3586 return 0;
3587
3588}
3589EXPORT_SYMBOL_GPL(rt2800_get_survey);
3590
a5ea2f02
ID		 3591MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
3592MODULE_VERSION(DRV_VERSION);
3593MODULE_DESCRIPTION("Ralink RT2800 library");
3594MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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