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rt2x00: Add WCID to HT TX descriptor
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
CommitLineData
89297425 1/*
96481b20 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
a5ea2f02 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 6
9c9a0d14 7 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32/*
33 Module: rt2800lib
34 Abstract: rt2800 generic device routines.
35 */
36
f31c9a8c 37#include <linux/crc-ccitt.h>
89297425
BZ		 38#include <linux/kernel.h>
39#include <linux/module.h>
5a0e3ad6 40#include <linux/slab.h>
89297425
BZ		 41
42#include "rt2x00.h"
43#include "rt2800lib.h"
44#include "rt2800.h"
45
89297425
BZ		 46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60#define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64#define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66#define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
baff8006
HS		 70static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71{
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
75 return false;
76
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
81 return true;
82
83 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
84 return false;
85}
86
fcf51541
BZ		 87static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
89297425
BZ		 89{
90 u32 reg;
91
92 mutex_lock(&rt2x00dev->csr_mutex);
93
94 /*
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
97 */
98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
efc7d36f 104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 105
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107 }
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110}
89297425 111
fcf51541
BZ		 112static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
89297425
BZ		 114{
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
126 */
127 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 reg = 0;
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
efc7d36f 132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142}
89297425 143
fcf51541
BZ		 144static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
89297425
BZ		 146{
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166}
89297425 167
fcf51541
BZ		 168static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
89297425
BZ		 170{
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197}
89297425 198
fcf51541
BZ		 199static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
89297425
BZ		 201{
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222}
89297425
BZ		 223
224void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
225 const u8 command, const u8 token,
226 const u8 arg0, const u8 arg1)
227{
228 u32 reg;
229
ee303e54 230 /*
cea90e55 231 * SOC devices don't support MCU requests.
ee303e54 232 */
cea90e55 233 if (rt2x00_is_soc(rt2x00dev))
ee303e54 234 return;
89297425
BZ		 235
236 mutex_lock(&rt2x00dev->csr_mutex);
237
238 /*
239 * Wait until the MCU becomes available, afterwards we
240 * can safely write the new data into the register.
241 */
242 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
243 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
244 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
245 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
246 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
247 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
248
249 reg = 0;
250 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
251 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
252 }
253
254 mutex_unlock(&rt2x00dev->csr_mutex);
255}
256EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 257
5ffddc49
ID		 258int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
259{
260 unsigned int i = 0;
261 u32 reg;
262
263 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
264 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
265 if (reg && reg != ~0)
266 return 0;
267 msleep(1);
268 }
269
270 ERROR(rt2x00dev, "Unstable hardware.\n");
271 return -EBUSY;
272}
273EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
274
67a4c1e2
GW		 275int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
276{
277 unsigned int i;
278 u32 reg;
279
08e53100
HS		 280 /*
281 * Some devices are really slow to respond here. Wait a whole second
282 * before timing out.
283 */
67a4c1e2
GW		 284 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
285 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
286 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
287 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
288 return 0;
289
08e53100 290 msleep(10);
67a4c1e2
GW		 291 }
292
293 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
294 return -EACCES;
295}
296EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
297
f31c9a8c
ID		 298static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
299{
300 u16 fw_crc;
301 u16 crc;
302
303 /*
304 * The last 2 bytes in the firmware array are the crc checksum itself,
305 * this means that we should never pass those 2 bytes to the crc
306 * algorithm.
307 */
308 fw_crc = (data[len - 2] << 8 | data[len - 1]);
309
310 /*
311 * Use the crc ccitt algorithm.
312 * This will return the same value as the legacy driver which
313 * used bit ordering reversion on the both the firmware bytes
314 * before input input as well as on the final output.
315 * Obviously using crc ccitt directly is much more efficient.
316 */
317 crc = crc_ccitt(~0, data, len - 2);
318
319 /*
320 * There is a small difference between the crc-itu-t + bitrev and
321 * the crc-ccitt crc calculation. In the latter method the 2 bytes
322 * will be swapped, use swab16 to convert the crc to the correct
323 * value.
324 */
325 crc = swab16(crc);
326
327 return fw_crc == crc;
328}
329
330int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
331 const u8 *data, const size_t len)
332{
333 size_t offset = 0;
334 size_t fw_len;
335 bool multiple;
336
337 /*
338 * PCI(e) & SOC devices require firmware with a length
339 * of 8kb. USB devices require firmware files with a length
340 * of 4kb. Certain USB chipsets however require different firmware,
341 * which Ralink only provides attached to the original firmware
342 * file. Thus for USB devices, firmware files have a length
343 * which is a multiple of 4kb.
344 */
345 if (rt2x00_is_usb(rt2x00dev)) {
346 fw_len = 4096;
347 multiple = true;
348 } else {
349 fw_len = 8192;
350 multiple = true;
351 }
352
353 /*
354 * Validate the firmware length
355 */
356 if (len != fw_len && (!multiple || (len % fw_len) != 0))
357 return FW_BAD_LENGTH;
358
359 /*
360 * Check if the chipset requires one of the upper parts
361 * of the firmware.
362 */
363 if (rt2x00_is_usb(rt2x00dev) &&
364 !rt2x00_rt(rt2x00dev, RT2860) &&
365 !rt2x00_rt(rt2x00dev, RT2872) &&
366 !rt2x00_rt(rt2x00dev, RT3070) &&
367 ((len / fw_len) == 1))
368 return FW_BAD_VERSION;
369
370 /*
371 * 8kb firmware files must be checked as if it were
372 * 2 separate firmware files.
373 */
374 while (offset < len) {
375 if (!rt2800_check_firmware_crc(data + offset, fw_len))
376 return FW_BAD_CRC;
377
378 offset += fw_len;
379 }
380
381 return FW_OK;
382}
383EXPORT_SYMBOL_GPL(rt2800_check_firmware);
384
385int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
386 const u8 *data, const size_t len)
387{
388 unsigned int i;
389 u32 reg;
390
391 /*
b9eca242
ID		 392 * If driver doesn't wake up firmware here,
393 * rt2800_load_firmware will hang forever when interface is up again.
f31c9a8c 394 */
b9eca242 395 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
f31c9a8c 396
f31c9a8c
ID		 397 /*
398 * Wait for stable hardware.
399 */
5ffddc49 400 if (rt2800_wait_csr_ready(rt2x00dev))
f31c9a8c 401 return -EBUSY;
f31c9a8c 402
adde5882 403 if (rt2x00_is_pci(rt2x00dev)) {
872834df
GW		 404 if (rt2x00_rt(rt2x00dev, RT3572) ||
405 rt2x00_rt(rt2x00dev, RT5390)) {
adde5882
GJ		 406 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
407 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
408 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
409 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
410 }
f31c9a8c 411 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
adde5882 412 }
f31c9a8c
ID		 413
414 /*
415 * Disable DMA, will be reenabled later when enabling
416 * the radio.
417 */
418 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
419 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
420 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
421 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
422 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
423 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
424 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
425
426 /*
427 * Write firmware to the device.
428 */
429 rt2800_drv_write_firmware(rt2x00dev, data, len);
430
431 /*
432 * Wait for device to stabilize.
433 */
434 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
435 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
436 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
437 break;
438 msleep(1);
439 }
440
441 if (i == REGISTER_BUSY_COUNT) {
442 ERROR(rt2x00dev, "PBF system register not ready.\n");
443 return -EBUSY;
444 }
445
446 /*
447 * Initialize firmware.
448 */
449 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
450 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
451 msleep(1);
452
453 return 0;
454}
455EXPORT_SYMBOL_GPL(rt2800_load_firmware);
456
0c5879bc
ID		 457void rt2800_write_tx_data(struct queue_entry *entry,
458 struct txentry_desc *txdesc)
59679b91 459{
0c5879bc 460 __le32 *txwi = rt2800_drv_get_txwi(entry);
59679b91
GW		 461 u32 word;
462
463 /*
464 * Initialize TX Info descriptor
465 */
466 rt2x00_desc_read(txwi, 0, &word);
467 rt2x00_set_field32(&word, TXWI_W0_FRAG,
468 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
84804cdc
ID		 469 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
470 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
59679b91
GW		 471 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
472 rt2x00_set_field32(&word, TXWI_W0_TS,
473 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
474 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
475 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
26a1d07f
HS		 476 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
477 txdesc->u.ht.mpdu_density);
478 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
479 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
59679b91
GW		 480 rt2x00_set_field32(&word, TXWI_W0_BW,
481 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
482 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
483 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
26a1d07f 484 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
59679b91
GW		 485 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
486 rt2x00_desc_write(txwi, 0, word);
487
488 rt2x00_desc_read(txwi, 1, &word);
489 rt2x00_set_field32(&word, TXWI_W1_ACK,
490 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
491 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
492 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
26a1d07f 493 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
59679b91
GW		 494 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
495 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
496 txdesc->key_idx : 0xff);
497 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
498 txdesc->length);
2b23cdaa 499 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
bc8a979e 500 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
59679b91
GW		 501 rt2x00_desc_write(txwi, 1, word);
502
503 /*
504 * Always write 0 to IV/EIV fields, hardware will insert the IV
505 * from the IVEIV register when TXD_W3_WIV is set to 0.
506 * When TXD_W3_WIV is set to 1 it will use the IV data
507 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
508 * crypto entry in the registers should be used to encrypt the frame.
509 */
510 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
511 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
512}
0c5879bc 513EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
59679b91 514
ff6133be 515static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
2de64dd2 516{
74861922
ID		 517 int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
518 int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
519 int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
520 u16 eeprom;
521 u8 offset0;
522 u8 offset1;
523 u8 offset2;
524
e5ef5bad 525 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
74861922
ID		 526 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
527 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
528 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
529 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
530 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
531 } else {
532 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
533 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
534 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
535 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
536 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
537 }
538
539 /*
540 * Convert the value from the descriptor into the RSSI value
541 * If the value in the descriptor is 0, it is considered invalid
542 * and the default (extremely low) rssi value is assumed
543 */
544 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
545 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
546 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
547
548 /*
549 * mac80211 only accepts a single RSSI value. Calculating the
550 * average doesn't deliver a fair answer either since -60:-60 would
551 * be considered equally good as -50:-70 while the second is the one
552 * which gives less energy...
553 */
554 rssi0 = max(rssi0, rssi1);
555 return max(rssi0, rssi2);
556}
557
558void rt2800_process_rxwi(struct queue_entry *entry,
559 struct rxdone_entry_desc *rxdesc)
560{
561 __le32 *rxwi = (__le32 *) entry->skb->data;
2de64dd2
GW		 562 u32 word;
563
564 rt2x00_desc_read(rxwi, 0, &word);
565
566 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
567 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
568
569 rt2x00_desc_read(rxwi, 1, &word);
570
571 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
572 rxdesc->flags |= RX_FLAG_SHORT_GI;
573
574 if (rt2x00_get_field32(word, RXWI_W1_BW))
575 rxdesc->flags |= RX_FLAG_40MHZ;
576
577 /*
578 * Detect RX rate, always use MCS as signal type.
579 */
580 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
581 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
582 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
583
584 /*
585 * Mask of 0x8 bit to remove the short preamble flag.
586 */
587 if (rxdesc->rate_mode == RATE_MODE_CCK)
588 rxdesc->signal &= ~0x8;
589
590 rt2x00_desc_read(rxwi, 2, &word);
591
74861922
ID		 592 /*
593 * Convert descriptor AGC value to RSSI value.
594 */
595 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
2de64dd2
GW		 596
597 /*
598 * Remove RXWI descriptor from start of buffer.
599 */
74861922 600 skb_pull(entry->skb, RXWI_DESC_SIZE);
2de64dd2
GW		 601}
602EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
603
31937c42 604void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
14433331
HS		 605{
606 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b34793ee 607 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
14433331
HS		 608 struct txdone_entry_desc txdesc;
609 u32 word;
610 u16 mcs, real_mcs;
b34793ee 611 int aggr, ampdu;
14433331
HS		 612
613 /*
614 * Obtain the status about this packet.
615 */
616 txdesc.flags = 0;
14433331 617 rt2x00_desc_read(txwi, 0, &word);
b34793ee 618
14433331 619 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
b34793ee
HS		 620 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
621
14433331 622 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
b34793ee
HS		 623 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
624
625 /*
626 * If a frame was meant to be sent as a single non-aggregated MPDU
627 * but ended up in an aggregate the used tx rate doesn't correlate
628 * with the one specified in the TXWI as the whole aggregate is sent
629 * with the same rate.
630 *
631 * For example: two frames are sent to rt2x00, the first one sets
632 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
633 * and requests MCS15. If the hw aggregates both frames into one
634 * AMDPU the tx status for both frames will contain MCS7 although
635 * the frame was sent successfully.
636 *
637 * Hence, replace the requested rate with the real tx rate to not
638 * confuse the rate control algortihm by providing clearly wrong
639 * data.
640 */
5356d963 641 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
b34793ee
HS		 642 skbdesc->tx_rate_idx = real_mcs;
643 mcs = real_mcs;
644 }
14433331 645
f16d2db7
HS		 646 if (aggr == 1 || ampdu == 1)
647 __set_bit(TXDONE_AMPDU, &txdesc.flags);
648
14433331
HS		 649 /*
650 * Ralink has a retry mechanism using a global fallback
651 * table. We setup this fallback table to try the immediate
652 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
653 * always contains the MCS used for the last transmission, be
654 * it successful or not.
655 */
656 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
657 /*
658 * Transmission succeeded. The number of retries is
659 * mcs - real_mcs
660 */
661 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
662 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
663 } else {
664 /*
665 * Transmission failed. The number of retries is
666 * always 7 in this case (for a total number of 8
667 * frames sent).
668 */
669 __set_bit(TXDONE_FAILURE, &txdesc.flags);
670 txdesc.retry = rt2x00dev->long_retry;
671 }
672
673 /*
674 * the frame was retried at least once
675 * -> hw used fallback rates
676 */
677 if (txdesc.retry)
678 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
679
680 rt2x00lib_txdone(entry, &txdesc);
681}
682EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
683
f0194b2d
GW		 684void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
685{
686 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
687 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
688 unsigned int beacon_base;
739fd940 689 unsigned int padding_len;
d76dfc61 690 u32 orig_reg, reg;
f0194b2d
GW		 691
692 /*
693 * Disable beaconing while we are reloading the beacon data,
694 * otherwise we might be sending out invalid data.
695 */
696 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
d76dfc61 697 orig_reg = reg;
f0194b2d
GW		 698 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
699 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
700
701 /*
702 * Add space for the TXWI in front of the skb.
703 */
b52398b6 704 memset(skb_push(entry->skb, TXWI_DESC_SIZE), 0, TXWI_DESC_SIZE);
f0194b2d
GW		 705
706 /*
707 * Register descriptor details in skb frame descriptor.
708 */
709 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
710 skbdesc->desc = entry->skb->data;
711 skbdesc->desc_len = TXWI_DESC_SIZE;
712
713 /*
714 * Add the TXWI for the beacon to the skb.
715 */
0c5879bc 716 rt2800_write_tx_data(entry, txdesc);
f0194b2d
GW		 717
718 /*
719 * Dump beacon to userspace through debugfs.
720 */
721 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
722
723 /*
739fd940 724 * Write entire beacon with TXWI and padding to register.
f0194b2d 725 */
739fd940 726 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
d76dfc61
SF		 727 if (padding_len && skb_pad(entry->skb, padding_len)) {
728 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
729 /* skb freed by skb_pad() on failure */
730 entry->skb = NULL;
731 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
732 return;
733 }
734
f0194b2d 735 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
739fd940
WK		 736 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
737 entry->skb->len + padding_len);
f0194b2d
GW		 738
739 /*
740 * Enable beaconing again.
741 */
f0194b2d
GW		 742 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
743 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
744
745 /*
746 * Clean up beacon skb.
747 */
748 dev_kfree_skb_any(entry->skb);
749 entry->skb = NULL;
750}
50e888ea 751EXPORT_SYMBOL_GPL(rt2800_write_beacon);
f0194b2d 752
69cf36a4
HS		 753static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
754 unsigned int beacon_base)
fdb87251
HS		 755{
756 int i;
757
758 /*
759 * For the Beacon base registers we only need to clear
760 * the whole TXWI which (when set to 0) will invalidate
761 * the entire beacon.
762 */
763 for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
764 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
765}
766
69cf36a4
HS		 767void rt2800_clear_beacon(struct queue_entry *entry)
768{
769 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
770 u32 reg;
771
772 /*
773 * Disable beaconing while we are reloading the beacon data,
774 * otherwise we might be sending out invalid data.
775 */
776 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
777 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
778 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
779
780 /*
781 * Clear beacon.
782 */
783 rt2800_clear_beacon_register(rt2x00dev,
784 HW_BEACON_OFFSET(entry->entry_idx));
785
786 /*
787 * Enabled beaconing again.
788 */
789 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
790 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
791}
792EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
793
f4450616
BZ		 794#ifdef CONFIG_RT2X00_LIB_DEBUGFS
795const struct rt2x00debug rt2800_rt2x00debug = {
796 .owner = THIS_MODULE,
797 .csr = {
798 .read = rt2800_register_read,
799 .write = rt2800_register_write,
800 .flags = RT2X00DEBUGFS_OFFSET,
801 .word_base = CSR_REG_BASE,
802 .word_size = sizeof(u32),
803 .word_count = CSR_REG_SIZE / sizeof(u32),
804 },
805 .eeprom = {
806 .read = rt2x00_eeprom_read,
807 .write = rt2x00_eeprom_write,
808 .word_base = EEPROM_BASE,
809 .word_size = sizeof(u16),
810 .word_count = EEPROM_SIZE / sizeof(u16),
811 },
812 .bbp = {
813 .read = rt2800_bbp_read,
814 .write = rt2800_bbp_write,
815 .word_base = BBP_BASE,
816 .word_size = sizeof(u8),
817 .word_count = BBP_SIZE / sizeof(u8),
818 },
819 .rf = {
820 .read = rt2x00_rf_read,
821 .write = rt2800_rf_write,
822 .word_base = RF_BASE,
823 .word_size = sizeof(u32),
824 .word_count = RF_SIZE / sizeof(u32),
825 },
826};
827EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
828#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
829
830int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
831{
832 u32 reg;
833
834 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
835 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
836}
837EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
838
839#ifdef CONFIG_RT2X00_LIB_LEDS
840static void rt2800_brightness_set(struct led_classdev *led_cdev,
841 enum led_brightness brightness)
842{
843 struct rt2x00_led *led =
844 container_of(led_cdev, struct rt2x00_led, led_dev);
845 unsigned int enabled = brightness != LED_OFF;
846 unsigned int bg_mode =
847 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
848 unsigned int polarity =
849 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
850 EEPROM_FREQ_LED_POLARITY);
851 unsigned int ledmode =
852 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
853 EEPROM_FREQ_LED_MODE);
44704e5d 854 u32 reg;
f4450616 855
44704e5d
LE		 856 /* Check for SoC (SOC devices don't support MCU requests) */
857 if (rt2x00_is_soc(led->rt2x00dev)) {
858 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
859
860 /* Set LED Polarity */
861 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
862
863 /* Set LED Mode */
864 if (led->type == LED_TYPE_RADIO) {
865 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
866 enabled ? 3 : 0);
867 } else if (led->type == LED_TYPE_ASSOC) {
868 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
869 enabled ? 3 : 0);
870 } else if (led->type == LED_TYPE_QUALITY) {
871 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
872 enabled ? 3 : 0);
873 }
874
875 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
876
877 } else {
878 if (led->type == LED_TYPE_RADIO) {
879 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
880 enabled ? 0x20 : 0);
881 } else if (led->type == LED_TYPE_ASSOC) {
882 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
883 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
884 } else if (led->type == LED_TYPE_QUALITY) {
885 /*
886 * The brightness is divided into 6 levels (0 - 5),
887 * The specs tell us the following levels:
888 * 0, 1 ,3, 7, 15, 31
889 * to determine the level in a simple way we can simply
890 * work with bitshifting:
891 * (1 << level) - 1
892 */
893 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
894 (1 << brightness / (LED_FULL / 6)) - 1,
895 polarity);
896 }
f4450616
BZ		 897 }
898}
899
b3579d6a 900static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 901 struct rt2x00_led *led, enum led_type type)
902{
903 led->rt2x00dev = rt2x00dev;
904 led->type = type;
905 led->led_dev.brightness_set = rt2800_brightness_set;
f4450616
BZ		 906 led->flags = LED_INITIALIZED;
907}
f4450616
BZ		 908#endif /* CONFIG_RT2X00_LIB_LEDS */
909
910/*
911 * Configuration handlers.
912 */
913static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
914 struct rt2x00lib_crypto *crypto,
915 struct ieee80211_key_conf *key)
916{
917 struct mac_wcid_entry wcid_entry;
918 struct mac_iveiv_entry iveiv_entry;
919 u32 offset;
920 u32 reg;
921
922 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
923
e4a0ab34
ID		 924 if (crypto->cmd == SET_KEY) {
925 rt2800_register_read(rt2x00dev, offset, &reg);
926 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
927 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
928 /*
929 * Both the cipher as the BSS Idx numbers are split in a main
930 * value of 3 bits, and a extended field for adding one additional
931 * bit to the value.
932 */
933 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
934 (crypto->cipher & 0x7));
935 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
936 (crypto->cipher & 0x8) >> 3);
937 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
938 (crypto->bssidx & 0x7));
939 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
940 (crypto->bssidx & 0x8) >> 3);
941 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
942 rt2800_register_write(rt2x00dev, offset, reg);
943 } else {
944 rt2800_register_write(rt2x00dev, offset, 0);
945 }
f4450616
BZ		 946
947 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
948
949 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
950 if ((crypto->cipher == CIPHER_TKIP) ||
951 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
952 (crypto->cipher == CIPHER_AES))
953 iveiv_entry.iv[3] |= 0x20;
954 iveiv_entry.iv[3] |= key->keyidx << 6;
955 rt2800_register_multiwrite(rt2x00dev, offset,
956 &iveiv_entry, sizeof(iveiv_entry));
957
958 offset = MAC_WCID_ENTRY(key->hw_key_idx);
959
960 memset(&wcid_entry, 0, sizeof(wcid_entry));
961 if (crypto->cmd == SET_KEY)
10026f77 962 memcpy(wcid_entry.mac, crypto->address, ETH_ALEN);
f4450616
BZ		 963 rt2800_register_multiwrite(rt2x00dev, offset,
964 &wcid_entry, sizeof(wcid_entry));
965}
966
967int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
968 struct rt2x00lib_crypto *crypto,
969 struct ieee80211_key_conf *key)
970{
971 struct hw_key_entry key_entry;
972 struct rt2x00_field32 field;
973 u32 offset;
974 u32 reg;
975
976 if (crypto->cmd == SET_KEY) {
977 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
978
979 memcpy(key_entry.key, crypto->key,
980 sizeof(key_entry.key));
981 memcpy(key_entry.tx_mic, crypto->tx_mic,
982 sizeof(key_entry.tx_mic));
983 memcpy(key_entry.rx_mic, crypto->rx_mic,
984 sizeof(key_entry.rx_mic));
985
986 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
987 rt2800_register_multiwrite(rt2x00dev, offset,
988 &key_entry, sizeof(key_entry));
989 }
990
991 /*
992 * The cipher types are stored over multiple registers
993 * starting with SHARED_KEY_MODE_BASE each word will have
994 * 32 bits and contains the cipher types for 2 bssidx each.
995 * Using the correct defines correctly will cause overhead,
996 * so just calculate the correct offset.
997 */
998 field.bit_offset = 4 * (key->hw_key_idx % 8);
999 field.bit_mask = 0x7 << field.bit_offset;
1000
1001 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1002
1003 rt2800_register_read(rt2x00dev, offset, &reg);
1004 rt2x00_set_field32(&reg, field,
1005 (crypto->cmd == SET_KEY) * crypto->cipher);
1006 rt2800_register_write(rt2x00dev, offset, reg);
1007
1008 /*
1009 * Update WCID information
1010 */
1011 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1012
1013 return 0;
1014}
1015EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1016
1ed3811c
HS		 1017static inline int rt2800_find_pairwise_keyslot(struct rt2x00_dev *rt2x00dev)
1018{
1019 int idx;
1020 u32 offset, reg;
1021
1022 /*
1023 * Search for the first free pairwise key entry and return the
1024 * corresponding index.
1025 *
1026 * Make sure the WCID starts _after_ the last possible shared key
1027 * entry (>32).
1028 *
1029 * Since parts of the pairwise key table might be shared with
1030 * the beacon frame buffers 6 & 7 we should only write into the
1031 * first 222 entries.
1032 */
1033 for (idx = 33; idx <= 222; idx++) {
1034 offset = MAC_WCID_ATTR_ENTRY(idx);
1035 rt2800_register_read(rt2x00dev, offset, &reg);
1036 if (!reg)
1037 return idx;
1038 }
1039 return -1;
1040}
1041
f4450616
BZ		 1042int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1043 struct rt2x00lib_crypto *crypto,
1044 struct ieee80211_key_conf *key)
1045{
1046 struct hw_key_entry key_entry;
1047 u32 offset;
1ed3811c 1048 int idx;
f4450616
BZ		 1049
1050 if (crypto->cmd == SET_KEY) {
1ed3811c
HS		 1051 idx = rt2800_find_pairwise_keyslot(rt2x00dev);
1052 if (idx < 0)
f4450616 1053 return -ENOSPC;
1ed3811c 1054 key->hw_key_idx = idx;
f4450616
BZ		 1055
1056 memcpy(key_entry.key, crypto->key,
1057 sizeof(key_entry.key));
1058 memcpy(key_entry.tx_mic, crypto->tx_mic,
1059 sizeof(key_entry.tx_mic));
1060 memcpy(key_entry.rx_mic, crypto->rx_mic,
1061 sizeof(key_entry.rx_mic));
1062
1063 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1064 rt2800_register_multiwrite(rt2x00dev, offset,
1065 &key_entry, sizeof(key_entry));
1066 }
1067
1068 /*
1069 * Update WCID information
1070 */
1071 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1072
1073 return 0;
1074}
1075EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1076
1077void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1078 const unsigned int filter_flags)
1079{
1080 u32 reg;
1081
1082 /*
1083 * Start configuration steps.
1084 * Note that the version error will always be dropped
1085 * and broadcast frames will always be accepted since
1086 * there is no filter for it at this time.
1087 */
1088 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1089 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1090 !(filter_flags & FIF_FCSFAIL));
1091 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1092 !(filter_flags & FIF_PLCPFAIL));
1093 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1094 !(filter_flags & FIF_PROMISC_IN_BSS));
1095 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1096 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1097 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1098 !(filter_flags & FIF_ALLMULTI));
1099 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1100 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1101 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1102 !(filter_flags & FIF_CONTROL));
1103 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1104 !(filter_flags & FIF_CONTROL));
1105 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1106 !(filter_flags & FIF_CONTROL));
1107 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1108 !(filter_flags & FIF_CONTROL));
1109 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1110 !(filter_flags & FIF_CONTROL));
1111 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1112 !(filter_flags & FIF_PSPOLL));
1113 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
1114 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
1115 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1116 !(filter_flags & FIF_CONTROL));
1117 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1118}
1119EXPORT_SYMBOL_GPL(rt2800_config_filter);
1120
1121void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1122 struct rt2x00intf_conf *conf, const unsigned int flags)
1123{
f4450616 1124 u32 reg;
fa8b4b22 1125 bool update_bssid = false;
f4450616
BZ		 1126
1127 if (flags & CONFIG_UPDATE_TYPE) {
f4450616
BZ		 1128 /*
1129 * Enable synchronisation.
1130 */
1131 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
f4450616 1132 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
f4450616 1133 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
15a533c4
HS		 1134
1135 if (conf->sync == TSF_SYNC_AP_NONE) {
1136 /*
1137 * Tune beacon queue transmit parameters for AP mode
1138 */
1139 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1140 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1141 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1142 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1143 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1144 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1145 } else {
1146 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1147 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1148 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1149 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1150 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1151 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1152 }
f4450616
BZ		 1153 }
1154
1155 if (flags & CONFIG_UPDATE_MAC) {
fa8b4b22
HS		 1156 if (flags & CONFIG_UPDATE_TYPE &&
1157 conf->sync == TSF_SYNC_AP_NONE) {
1158 /*
1159 * The BSSID register has to be set to our own mac
1160 * address in AP mode.
1161 */
1162 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1163 update_bssid = true;
1164 }
1165
c600c826
ID		 1166 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1167 reg = le32_to_cpu(conf->mac[1]);
1168 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1169 conf->mac[1] = cpu_to_le32(reg);
1170 }
f4450616
BZ		 1171
1172 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1173 conf->mac, sizeof(conf->mac));
1174 }
1175
fa8b4b22 1176 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
c600c826
ID		 1177 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1178 reg = le32_to_cpu(conf->bssid[1]);
1179 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1180 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1181 conf->bssid[1] = cpu_to_le32(reg);
1182 }
f4450616
BZ		 1183
1184 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1185 conf->bssid, sizeof(conf->bssid));
1186 }
1187}
1188EXPORT_SYMBOL_GPL(rt2800_config_intf);
1189
87c1915d
HS		 1190static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1191 struct rt2x00lib_erp *erp)
1192{
1193 bool any_sta_nongf = !!(erp->ht_opmode &
1194 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1195 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1196 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1197 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1198 u32 reg;
1199
1200 /* default protection rate for HT20: OFDM 24M */
1201 mm20_rate = gf20_rate = 0x4004;
1202
1203 /* default protection rate for HT40: duplicate OFDM 24M */
1204 mm40_rate = gf40_rate = 0x4084;
1205
1206 switch (protection) {
1207 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1208 /*
1209 * All STAs in this BSS are HT20/40 but there might be
1210 * STAs not supporting greenfield mode.
1211 * => Disable protection for HT transmissions.
1212 */
1213 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1214
1215 break;
1216 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1217 /*
1218 * All STAs in this BSS are HT20 or HT20/40 but there
1219 * might be STAs not supporting greenfield mode.
1220 * => Protect all HT40 transmissions.
1221 */
1222 mm20_mode = gf20_mode = 0;
1223 mm40_mode = gf40_mode = 2;
1224
1225 break;
1226 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1227 /*
1228 * Nonmember protection:
1229 * According to 802.11n we _should_ protect all
1230 * HT transmissions (but we don't have to).
1231 *
1232 * But if cts_protection is enabled we _shall_ protect
1233 * all HT transmissions using a CCK rate.
1234 *
1235 * And if any station is non GF we _shall_ protect
1236 * GF transmissions.
1237 *
1238 * We decide to protect everything
1239 * -> fall through to mixed mode.
1240 */
1241 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1242 /*
1243 * Legacy STAs are present
1244 * => Protect all HT transmissions.
1245 */
1246 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1247
1248 /*
1249 * If erp protection is needed we have to protect HT
1250 * transmissions with CCK 11M long preamble.
1251 */
1252 if (erp->cts_protection) {
1253 /* don't duplicate RTS/CTS in CCK mode */
1254 mm20_rate = mm40_rate = 0x0003;
1255 gf20_rate = gf40_rate = 0x0003;
1256 }
1257 break;
6403eab1 1258 }
87c1915d
HS		 1259
1260 /* check for STAs not supporting greenfield mode */
1261 if (any_sta_nongf)
1262 gf20_mode = gf40_mode = 2;
1263
1264 /* Update HT protection config */
1265 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1266 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1267 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1268 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1269
1270 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1271 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1272 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1273 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1274
1275 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1276 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1277 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1278 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1279
1280 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1281 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1282 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1283 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1284}
1285
02044643
HS		 1286void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1287 u32 changed)
f4450616
BZ		 1288{
1289 u32 reg;
1290
02044643
HS		 1291 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1292 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1293 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1294 !!erp->short_preamble);
1295 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1296 !!erp->short_preamble);
1297 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1298 }
f4450616 1299
02044643
HS		 1300 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1301 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1302 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1303 erp->cts_protection ? 2 : 0);
1304 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1305 }
f4450616 1306
02044643
HS		 1307 if (changed & BSS_CHANGED_BASIC_RATES) {
1308 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1309 erp->basic_rates);
1310 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1311 }
f4450616 1312
02044643
HS		 1313 if (changed & BSS_CHANGED_ERP_SLOT) {
1314 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1315 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1316 erp->slot_time);
1317 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
f4450616 1318
02044643
HS		 1319 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1320 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1321 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1322 }
f4450616 1323
02044643
HS		 1324 if (changed & BSS_CHANGED_BEACON_INT) {
1325 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1326 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1327 erp->beacon_int * 16);
1328 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1329 }
87c1915d
HS		 1330
1331 if (changed & BSS_CHANGED_HT)
1332 rt2800_config_ht_opmode(rt2x00dev, erp);
f4450616
BZ		 1333}
1334EXPORT_SYMBOL_GPL(rt2800_config_erp);
1335
872834df
GW		 1336static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1337{
1338 u32 reg;
1339 u16 eeprom;
1340 u8 led_ctrl, led_g_mode, led_r_mode;
1341
1342 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1343 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1344 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1345 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1346 } else {
1347 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1348 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1349 }
1350 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1351
1352 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1353 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1354 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1355 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1356 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1357 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1358 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1359 if (led_ctrl == 0 || led_ctrl > 0x40) {
1360 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1361 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1362 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1363 } else {
1364 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1365 (led_g_mode << 2) | led_r_mode, 1);
1366 }
1367 }
1368}
1369
d96aa640
RJH		 1370static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1371 enum antenna ant)
1372{
1373 u32 reg;
1374 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1375 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1376
1377 if (rt2x00_is_pci(rt2x00dev)) {
1378 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1379 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1380 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1381 } else if (rt2x00_is_usb(rt2x00dev))
1382 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1383 eesk_pin, 0);
1384
1385 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
fe59147c 1386 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
d96aa640
RJH		 1387 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, gpio_bit3);
1388 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1389}
1390
f4450616
BZ		 1391void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1392{
1393 u8 r1;
1394 u8 r3;
d96aa640 1395 u16 eeprom;
f4450616
BZ		 1396
1397 rt2800_bbp_read(rt2x00dev, 1, &r1);
1398 rt2800_bbp_read(rt2x00dev, 3, &r3);
1399
872834df
GW		 1400 if (rt2x00_rt(rt2x00dev, RT3572) &&
1401 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1402 rt2800_config_3572bt_ant(rt2x00dev);
1403
f4450616
BZ		 1404 /*
1405 * Configure the TX antenna.
1406 */
d96aa640 1407 switch (ant->tx_chain_num) {
f4450616
BZ		 1408 case 1:
1409 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1410 break;
1411 case 2:
872834df
GW		 1412 if (rt2x00_rt(rt2x00dev, RT3572) &&
1413 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1414 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1415 else
1416 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
f4450616
BZ		 1417 break;
1418 case 3:
e22557f2 1419 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1420 break;
1421 }
1422
1423 /*
1424 * Configure the RX antenna.
1425 */
d96aa640 1426 switch (ant->rx_chain_num) {
f4450616 1427 case 1:
d96aa640
RJH		 1428 if (rt2x00_rt(rt2x00dev, RT3070) ||
1429 rt2x00_rt(rt2x00dev, RT3090) ||
1430 rt2x00_rt(rt2x00dev, RT3390)) {
1431 rt2x00_eeprom_read(rt2x00dev,
1432 EEPROM_NIC_CONF1, &eeprom);
1433 if (rt2x00_get_field16(eeprom,
1434 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1435 rt2800_set_ant_diversity(rt2x00dev,
1436 rt2x00dev->default_ant.rx);
1437 }
f4450616
BZ		 1438 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1439 break;
1440 case 2:
872834df
GW		 1441 if (rt2x00_rt(rt2x00dev, RT3572) &&
1442 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1443 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1444 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1445 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1446 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1447 } else {
1448 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1449 }
f4450616
BZ		 1450 break;
1451 case 3:
1452 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1453 break;
1454 }
1455
1456 rt2800_bbp_write(rt2x00dev, 3, r3);
1457 rt2800_bbp_write(rt2x00dev, 1, r1);
1458}
1459EXPORT_SYMBOL_GPL(rt2800_config_ant);
1460
1461static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1462 struct rt2x00lib_conf *libconf)
1463{
1464 u16 eeprom;
1465 short lna_gain;
1466
1467 if (libconf->rf.channel <= 14) {
1468 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1469 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1470 } else if (libconf->rf.channel <= 64) {
1471 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1472 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1473 } else if (libconf->rf.channel <= 128) {
1474 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1475 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1476 } else {
1477 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1478 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1479 }
1480
1481 rt2x00dev->lna_gain = lna_gain;
1482}
1483
06855ef4
GW		 1484static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1485 struct ieee80211_conf *conf,
1486 struct rf_channel *rf,
1487 struct channel_info *info)
f4450616
BZ		 1488{
1489 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1490
d96aa640 1491 if (rt2x00dev->default_ant.tx_chain_num == 1)
f4450616
BZ		 1492 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1493
d96aa640 1494 if (rt2x00dev->default_ant.rx_chain_num == 1) {
f4450616
BZ		 1495 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1496 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
d96aa640 1497 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
f4450616
BZ		 1498 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1499
1500 if (rf->channel > 14) {
1501 /*
1502 * When TX power is below 0, we should increase it by 7 to
25985edc 1503 * make it a positive value (Minimum value is -7).
f4450616
BZ		 1504 * However this means that values between 0 and 7 have
1505 * double meaning, and we should set a 7DBm boost flag.
1506 */
1507 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
8d1331b3 1508 (info->default_power1 >= 0));
f4450616 1509
8d1331b3
ID		 1510 if (info->default_power1 < 0)
1511 info->default_power1 += 7;
f4450616 1512
8d1331b3 1513 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
f4450616
BZ		 1514
1515 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
8d1331b3 1516 (info->default_power2 >= 0));
f4450616 1517
8d1331b3
ID		 1518 if (info->default_power2 < 0)
1519 info->default_power2 += 7;
f4450616 1520
8d1331b3 1521 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
f4450616 1522 } else {
8d1331b3
ID		 1523 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1524 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
f4450616
BZ		 1525 }
1526
1527 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1528
1529 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1530 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1531 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1532 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1533
1534 udelay(200);
1535
1536 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1537 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1538 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1539 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1540
1541 udelay(200);
1542
1543 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1544 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1545 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1546 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1547}
1548
06855ef4
GW		 1549static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1550 struct ieee80211_conf *conf,
1551 struct rf_channel *rf,
1552 struct channel_info *info)
f4450616
BZ		 1553{
1554 u8 rfcsr;
1555
1556 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
41a26170 1557 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
f4450616
BZ		 1558
1559 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 1560 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 1561 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1562
1563 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
8d1331b3 1564 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
f4450616
BZ		 1565 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1566
5a673964 1567 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
8d1331b3 1568 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
5a673964
HS		 1569 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1570
f4450616
BZ		 1571 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1572 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1573 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1574
1575 rt2800_rfcsr_write(rt2x00dev, 24,
1576 rt2x00dev->calibration[conf_is_ht40(conf)]);
1577
71976907 1578 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 1579 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 1580 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
f4450616
BZ		 1581}
1582
872834df
GW		 1583static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1584 struct ieee80211_conf *conf,
1585 struct rf_channel *rf,
1586 struct channel_info *info)
1587{
1588 u8 rfcsr;
1589 u32 reg;
1590
1591 if (rf->channel <= 14) {
1592 rt2800_bbp_write(rt2x00dev, 25, 0x15);
1593 rt2800_bbp_write(rt2x00dev, 26, 0x85);
1594 } else {
1595 rt2800_bbp_write(rt2x00dev, 25, 0x09);
1596 rt2800_bbp_write(rt2x00dev, 26, 0xff);
1597 }
1598
1599 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1600 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1601
1602 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1603 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1604 if (rf->channel <= 14)
1605 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
1606 else
1607 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
1608 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1609
1610 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
1611 if (rf->channel <= 14)
1612 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
1613 else
1614 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
1615 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
1616
1617 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1618 if (rf->channel <= 14) {
1619 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
1620 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1621 (info->default_power1 & 0x3) |
1622 ((info->default_power1 & 0xC) << 1));
1623 } else {
1624 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
1625 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1626 (info->default_power1 & 0x3) |
1627 ((info->default_power1 & 0xC) << 1));
1628 }
1629 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1630
1631 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1632 if (rf->channel <= 14) {
1633 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
1634 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1635 (info->default_power2 & 0x3) |
1636 ((info->default_power2 & 0xC) << 1));
1637 } else {
1638 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
1639 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1640 (info->default_power2 & 0x3) |
1641 ((info->default_power2 & 0xC) << 1));
1642 }
1643 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1644
1645 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1646 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1647 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1648 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1649 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1650 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1651 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1652 if (rf->channel <= 14) {
1653 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1654 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1655 }
1656 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1657 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1658 } else {
1659 switch (rt2x00dev->default_ant.tx_chain_num) {
1660 case 1:
1661 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1662 case 2:
1663 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1664 break;
1665 }
1666
1667 switch (rt2x00dev->default_ant.rx_chain_num) {
1668 case 1:
1669 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1670 case 2:
1671 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1672 break;
1673 }
1674 }
1675 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1676
1677 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1678 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1679 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1680
1681 rt2800_rfcsr_write(rt2x00dev, 24,
1682 rt2x00dev->calibration[conf_is_ht40(conf)]);
1683 rt2800_rfcsr_write(rt2x00dev, 31,
1684 rt2x00dev->calibration[conf_is_ht40(conf)]);
1685
1686 if (rf->channel <= 14) {
1687 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
1688 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
1689 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1690 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
1691 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1692 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
1693 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1694 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
1695 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
1696 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
1697 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1698 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1699 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
1700 } else {
1701 rt2800_rfcsr_write(rt2x00dev, 7, 0x14);
1702 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1703 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1704 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1705 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
1706 rt2800_rfcsr_write(rt2x00dev, 16, 0x7a);
1707 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1708 if (rf->channel <= 64) {
1709 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
1710 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
1711 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1712 } else if (rf->channel <= 128) {
1713 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
1714 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
1715 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1716 } else {
1717 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
1718 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
1719 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1720 }
1721 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
1722 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
1723 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
1724 }
1725
1726 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1727 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT7, 0);
1728 if (rf->channel <= 14)
1729 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 1);
1730 else
1731 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 0);
1732 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1733
1734 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1735 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1736 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1737}
60687ba7
RST		 1738
1739#define RT5390_POWER_BOUND 0x27
1740#define RT5390_FREQ_OFFSET_BOUND 0x5f
1741
1742static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
adde5882
GJ		 1743 struct ieee80211_conf *conf,
1744 struct rf_channel *rf,
1745 struct channel_info *info)
1746{
1747 u8 rfcsr;
adde5882
GJ		 1748
1749 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
1750 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
1751 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
1752 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
1753 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
1754
1755 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
1756 if (info->default_power1 > RT5390_POWER_BOUND)
1757 rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT5390_POWER_BOUND);
1758 else
1759 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
1760 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
1761
1762 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1763 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1764 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
1765 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1766 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1767 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1768
1769 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1770 if (rt2x00dev->freq_offset > RT5390_FREQ_OFFSET_BOUND)
1771 rt2x00_set_field8(&rfcsr, RFCSR17_CODE,
1772 RT5390_FREQ_OFFSET_BOUND);
1773 else
1774 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
1775 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1776
adde5882
GJ		 1777 if (rf->channel <= 14) {
1778 int idx = rf->channel-1;
1779
fdbc7b0a 1780 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
adde5882
GJ		 1781 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1782 /* r55/r59 value array of channel 1~14 */
1783 static const char r55_bt_rev[] = {0x83, 0x83,
1784 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
1785 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
1786 static const char r59_bt_rev[] = {0x0e, 0x0e,
1787 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
1788 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
1789
1790 rt2800_rfcsr_write(rt2x00dev, 55,
1791 r55_bt_rev[idx]);
1792 rt2800_rfcsr_write(rt2x00dev, 59,
1793 r59_bt_rev[idx]);
1794 } else {
1795 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
1796 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
1797 0x88, 0x88, 0x86, 0x85, 0x84};
1798
1799 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
1800 }
1801 } else {
1802 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1803 static const char r55_nonbt_rev[] = {0x23, 0x23,
1804 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
1805 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
1806 static const char r59_nonbt_rev[] = {0x07, 0x07,
1807 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
1808 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
1809
1810 rt2800_rfcsr_write(rt2x00dev, 55,
1811 r55_nonbt_rev[idx]);
1812 rt2800_rfcsr_write(rt2x00dev, 59,
1813 r59_nonbt_rev[idx]);
1814 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
1815 static const char r59_non_bt[] = {0x8f, 0x8f,
1816 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
1817 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
1818
1819 rt2800_rfcsr_write(rt2x00dev, 59,
1820 r59_non_bt[idx]);
1821 }
1822 }
1823 }
1824
1825 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1826 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
1827 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
1828 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1829
1830 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1831 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1832 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
60687ba7
RST		 1833}
1834
f4450616
BZ		 1835static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1836 struct ieee80211_conf *conf,
1837 struct rf_channel *rf,
1838 struct channel_info *info)
1839{
1840 u32 reg;
1841 unsigned int tx_pin;
1842 u8 bbp;
1843
46323e11 1844 if (rf->channel <= 14) {
8d1331b3
ID		 1845 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
1846 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
46323e11 1847 } else {
8d1331b3
ID		 1848 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
1849 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
46323e11
ID		 1850 }
1851
06855ef4
GW		 1852 if (rt2x00_rf(rt2x00dev, RF2020) ||
1853 rt2x00_rf(rt2x00dev, RF3020) ||
1854 rt2x00_rf(rt2x00dev, RF3021) ||
46323e11 1855 rt2x00_rf(rt2x00dev, RF3022) ||
f93bc9b3 1856 rt2x00_rf(rt2x00dev, RF3320))
06855ef4 1857 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
872834df
GW		 1858 else if (rt2x00_rf(rt2x00dev, RF3052))
1859 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
aca355b9
GW		 1860 else if (rt2x00_rf(rt2x00dev, RF5370) ||
1861 rt2x00_rf(rt2x00dev, RF5390))
adde5882 1862 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
fa6f632f 1863 else
06855ef4 1864 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
f4450616
BZ		 1865
1866 /*
1867 * Change BBP settings
1868 */
1869 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1870 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1871 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1872 rt2800_bbp_write(rt2x00dev, 86, 0);
1873
1874 if (rf->channel <= 14) {
adde5882 1875 if (!rt2x00_rt(rt2x00dev, RT5390)) {
7dab73b3
ID		 1876 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
1877 &rt2x00dev->cap_flags)) {
adde5882
GJ		 1878 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1879 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1880 } else {
1881 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1882 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1883 }
f4450616
BZ		 1884 }
1885 } else {
872834df
GW		 1886 if (rt2x00_rt(rt2x00dev, RT3572))
1887 rt2800_bbp_write(rt2x00dev, 82, 0x94);
1888 else
1889 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
f4450616 1890
7dab73b3 1891 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
f4450616
BZ		 1892 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1893 else
1894 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1895 }
1896
1897 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 1898 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1899 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1900 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1901 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1902
872834df
GW		 1903 if (rt2x00_rt(rt2x00dev, RT3572))
1904 rt2800_rfcsr_write(rt2x00dev, 8, 0);
1905
f4450616
BZ		 1906 tx_pin = 0;
1907
1908 /* Turn on unused PA or LNA when not using 1T or 1R */
d96aa640 1909 if (rt2x00dev->default_ant.tx_chain_num == 2) {
65f31b5e
GW		 1910 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
1911 rf->channel > 14);
1912 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
1913 rf->channel <= 14);
f4450616
BZ		 1914 }
1915
1916 /* Turn on unused PA or LNA when not using 1T or 1R */
d96aa640 1917 if (rt2x00dev->default_ant.rx_chain_num == 2) {
f4450616
BZ		 1918 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1919 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1920 }
1921
1922 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1923 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1924 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1925 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
8f96e91f
GW		 1926 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1927 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
1928 else
1929 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
1930 rf->channel <= 14);
f4450616
BZ		 1931 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1932
1933 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1934
872834df
GW		 1935 if (rt2x00_rt(rt2x00dev, RT3572))
1936 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
1937
f4450616
BZ		 1938 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1939 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1940 rt2800_bbp_write(rt2x00dev, 4, bbp);
1941
1942 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 1943 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1944 rt2800_bbp_write(rt2x00dev, 3, bbp);
1945
8d0c9b65 1946 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 1947 if (conf_is_ht40(conf)) {
1948 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1949 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1950 rt2800_bbp_write(rt2x00dev, 73, 0x16);
1951 } else {
1952 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1953 rt2800_bbp_write(rt2x00dev, 70, 0x08);
1954 rt2800_bbp_write(rt2x00dev, 73, 0x11);
1955 }
1956 }
1957
1958 msleep(1);
977206d7
HS		 1959
1960 /*
1961 * Clear channel statistic counters
1962 */
1963 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
1964 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
1965 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
f4450616
BZ		 1966}
1967
9e33a355
HS		 1968static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
1969{
1970 u8 tssi_bounds[9];
1971 u8 current_tssi;
1972 u16 eeprom;
1973 u8 step;
1974 int i;
1975
1976 /*
1977 * Read TSSI boundaries for temperature compensation from
1978 * the EEPROM.
1979 *
1980 * Array idx 0 1 2 3 4 5 6 7 8
1981 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
1982 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
1983 */
1984 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1985 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
1986 tssi_bounds[0] = rt2x00_get_field16(eeprom,
1987 EEPROM_TSSI_BOUND_BG1_MINUS4);
1988 tssi_bounds[1] = rt2x00_get_field16(eeprom,
1989 EEPROM_TSSI_BOUND_BG1_MINUS3);
1990
1991 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
1992 tssi_bounds[2] = rt2x00_get_field16(eeprom,
1993 EEPROM_TSSI_BOUND_BG2_MINUS2);
1994 tssi_bounds[3] = rt2x00_get_field16(eeprom,
1995 EEPROM_TSSI_BOUND_BG2_MINUS1);
1996
1997 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
1998 tssi_bounds[4] = rt2x00_get_field16(eeprom,
1999 EEPROM_TSSI_BOUND_BG3_REF);
2000 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2001 EEPROM_TSSI_BOUND_BG3_PLUS1);
2002
2003 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
2004 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2005 EEPROM_TSSI_BOUND_BG4_PLUS2);
2006 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2007 EEPROM_TSSI_BOUND_BG4_PLUS3);
2008
2009 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
2010 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2011 EEPROM_TSSI_BOUND_BG5_PLUS4);
2012
2013 step = rt2x00_get_field16(eeprom,
2014 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
2015 } else {
2016 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
2017 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2018 EEPROM_TSSI_BOUND_A1_MINUS4);
2019 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2020 EEPROM_TSSI_BOUND_A1_MINUS3);
2021
2022 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
2023 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2024 EEPROM_TSSI_BOUND_A2_MINUS2);
2025 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2026 EEPROM_TSSI_BOUND_A2_MINUS1);
2027
2028 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
2029 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2030 EEPROM_TSSI_BOUND_A3_REF);
2031 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2032 EEPROM_TSSI_BOUND_A3_PLUS1);
2033
2034 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
2035 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2036 EEPROM_TSSI_BOUND_A4_PLUS2);
2037 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2038 EEPROM_TSSI_BOUND_A4_PLUS3);
2039
2040 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
2041 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2042 EEPROM_TSSI_BOUND_A5_PLUS4);
2043
2044 step = rt2x00_get_field16(eeprom,
2045 EEPROM_TSSI_BOUND_A5_AGC_STEP);
2046 }
2047
2048 /*
2049 * Check if temperature compensation is supported.
2050 */
2051 if (tssi_bounds[4] == 0xff)
2052 return 0;
2053
2054 /*
2055 * Read current TSSI (BBP 49).
2056 */
2057 rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
2058
2059 /*
2060 * Compare TSSI value (BBP49) with the compensation boundaries
2061 * from the EEPROM and increase or decrease tx power.
2062 */
2063 for (i = 0; i <= 3; i++) {
2064 if (current_tssi > tssi_bounds[i])
2065 break;
2066 }
2067
2068 if (i == 4) {
2069 for (i = 8; i >= 5; i--) {
2070 if (current_tssi < tssi_bounds[i])
2071 break;
2072 }
2073 }
2074
2075 return (i - 4) * step;
2076}
2077
e90c54b2
RJH		 2078static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
2079 enum ieee80211_band band)
2080{
2081 u16 eeprom;
2082 u8 comp_en;
2083 u8 comp_type;
75faae8b 2084 int comp_value = 0;
e90c54b2
RJH		 2085
2086 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
2087
75faae8b
HS		 2088 /*
2089 * HT40 compensation not required.
2090 */
2091 if (eeprom == 0xffff ||
2092 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
e90c54b2
RJH		 2093 return 0;
2094
2095 if (band == IEEE80211_BAND_2GHZ) {
2096 comp_en = rt2x00_get_field16(eeprom,
2097 EEPROM_TXPOWER_DELTA_ENABLE_2G);
2098 if (comp_en) {
2099 comp_type = rt2x00_get_field16(eeprom,
2100 EEPROM_TXPOWER_DELTA_TYPE_2G);
2101 comp_value = rt2x00_get_field16(eeprom,
2102 EEPROM_TXPOWER_DELTA_VALUE_2G);
2103 if (!comp_type)
2104 comp_value = -comp_value;
2105 }
2106 } else {
2107 comp_en = rt2x00_get_field16(eeprom,
2108 EEPROM_TXPOWER_DELTA_ENABLE_5G);
2109 if (comp_en) {
2110 comp_type = rt2x00_get_field16(eeprom,
2111 EEPROM_TXPOWER_DELTA_TYPE_5G);
2112 comp_value = rt2x00_get_field16(eeprom,
2113 EEPROM_TXPOWER_DELTA_VALUE_5G);
2114 if (!comp_type)
2115 comp_value = -comp_value;
2116 }
2117 }
2118
2119 return comp_value;
2120}
2121
fa71a160
HS		 2122static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
2123 enum ieee80211_band band, int power_level,
2124 u8 txpower, int delta)
e90c54b2
RJH		 2125{
2126 u32 reg;
2127 u16 eeprom;
2128 u8 criterion;
2129 u8 eirp_txpower;
2130 u8 eirp_txpower_criterion;
2131 u8 reg_limit;
e90c54b2
RJH		 2132
2133 if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b))
2134 return txpower;
2135
7dab73b3 2136 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
e90c54b2
RJH		 2137 /*
2138 * Check if eirp txpower exceed txpower_limit.
2139 * We use OFDM 6M as criterion and its eirp txpower
2140 * is stored at EEPROM_EIRP_MAX_TX_POWER.
2141 * .11b data rate need add additional 4dbm
2142 * when calculating eirp txpower.
2143 */
2144 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
2145 criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS);
2146
2147 rt2x00_eeprom_read(rt2x00dev,
2148 EEPROM_EIRP_MAX_TX_POWER, &eeprom);
2149
2150 if (band == IEEE80211_BAND_2GHZ)
2151 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2152 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2153 else
2154 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2155 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2156
2157 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2af242e1 2158 (is_rate_b ? 4 : 0) + delta;
e90c54b2
RJH		 2159
2160 reg_limit = (eirp_txpower > power_level) ?
2161 (eirp_txpower - power_level) : 0;
2162 } else
2163 reg_limit = 0;
2164
2af242e1 2165 return txpower + delta - reg_limit;
e90c54b2
RJH		 2166}
2167
f4450616 2168static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
9e33a355
HS		 2169 enum ieee80211_band band,
2170 int power_level)
f4450616 2171{
5e846004 2172 u8 txpower;
5e846004 2173 u16 eeprom;
e90c54b2 2174 int i, is_rate_b;
f4450616 2175 u32 reg;
f4450616 2176 u8 r1;
5e846004 2177 u32 offset;
2af242e1
HS		 2178 int delta;
2179
2180 /*
2181 * Calculate HT40 compensation delta
2182 */
2183 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
f4450616 2184
9e33a355
HS		 2185 /*
2186 * calculate temperature compensation delta
2187 */
2188 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
f4450616 2189
5e846004 2190 /*
e90c54b2 2191 * set to normal bbp tx power control mode: +/- 0dBm
5e846004 2192 */
f4450616 2193 rt2800_bbp_read(rt2x00dev, 1, &r1);
e90c54b2 2194 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0);
f4450616 2195 rt2800_bbp_write(rt2x00dev, 1, r1);
5e846004
HS		 2196 offset = TX_PWR_CFG_0;
2197
2198 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
2199 /* just to be safe */
2200 if (offset > TX_PWR_CFG_4)
2201 break;
2202
2203 rt2800_register_read(rt2x00dev, offset, &reg);
2204
2205 /* read the next four txpower values */
2206 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
2207 &eeprom);
2208
e90c54b2
RJH		 2209 is_rate_b = i ? 0 : 1;
2210 /*
2211 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
5e846004 2212 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
e90c54b2
RJH		 2213 * TX_PWR_CFG_4: unknown
2214 */
5e846004
HS		 2215 txpower = rt2x00_get_field16(eeprom,
2216 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 2217 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2218 power_level, txpower, delta);
e90c54b2 2219 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
5e846004 2220
e90c54b2
RJH		 2221 /*
2222 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
5e846004 2223 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
e90c54b2
RJH		 2224 * TX_PWR_CFG_4: unknown
2225 */
5e846004
HS		 2226 txpower = rt2x00_get_field16(eeprom,
2227 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 2228 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2229 power_level, txpower, delta);
e90c54b2 2230 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
5e846004 2231
e90c54b2
RJH		 2232 /*
2233 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
5e846004 2234 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
e90c54b2
RJH		 2235 * TX_PWR_CFG_4: unknown
2236 */
5e846004
HS		 2237 txpower = rt2x00_get_field16(eeprom,
2238 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 2239 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2240 power_level, txpower, delta);
e90c54b2 2241 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
5e846004 2242
e90c54b2
RJH		 2243 /*
2244 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
5e846004 2245 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
e90c54b2
RJH		 2246 * TX_PWR_CFG_4: unknown
2247 */
5e846004
HS		 2248 txpower = rt2x00_get_field16(eeprom,
2249 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 2250 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2251 power_level, txpower, delta);
e90c54b2 2252 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
5e846004
HS		 2253
2254 /* read the next four txpower values */
2255 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
2256 &eeprom);
2257
e90c54b2
RJH		 2258 is_rate_b = 0;
2259 /*
2260 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
5e846004 2261 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 2262 * TX_PWR_CFG_4: unknown
2263 */
5e846004
HS		 2264 txpower = rt2x00_get_field16(eeprom,
2265 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 2266 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2267 power_level, txpower, delta);
e90c54b2 2268 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
5e846004 2269
e90c54b2
RJH		 2270 /*
2271 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
5e846004 2272 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 2273 * TX_PWR_CFG_4: unknown
2274 */
5e846004
HS		 2275 txpower = rt2x00_get_field16(eeprom,
2276 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 2277 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2278 power_level, txpower, delta);
e90c54b2 2279 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
5e846004 2280
e90c54b2
RJH		 2281 /*
2282 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
5e846004 2283 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 2284 * TX_PWR_CFG_4: unknown
2285 */
5e846004
HS		 2286 txpower = rt2x00_get_field16(eeprom,
2287 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 2288 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2289 power_level, txpower, delta);
e90c54b2 2290 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
5e846004 2291
e90c54b2
RJH		 2292 /*
2293 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
5e846004 2294 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 2295 * TX_PWR_CFG_4: unknown
2296 */
5e846004
HS		 2297 txpower = rt2x00_get_field16(eeprom,
2298 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 2299 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2300 power_level, txpower, delta);
e90c54b2 2301 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
5e846004
HS		 2302
2303 rt2800_register_write(rt2x00dev, offset, reg);
2304
2305 /* next TX_PWR_CFG register */
2306 offset += 4;
2307 }
f4450616
BZ		 2308}
2309
9e33a355
HS		 2310void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
2311{
2312 rt2800_config_txpower(rt2x00dev, rt2x00dev->curr_band,
2313 rt2x00dev->tx_power);
2314}
2315EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
2316
f4450616
BZ		 2317static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
2318 struct rt2x00lib_conf *libconf)
2319{
2320 u32 reg;
2321
2322 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2323 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
2324 libconf->conf->short_frame_max_tx_count);
2325 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
2326 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 2327 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2328}
2329
2330static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
2331 struct rt2x00lib_conf *libconf)
2332{
2333 enum dev_state state =
2334 (libconf->conf->flags & IEEE80211_CONF_PS) ?
2335 STATE_SLEEP : STATE_AWAKE;
2336 u32 reg;
2337
2338 if (state == STATE_SLEEP) {
2339 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
2340
2341 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2342 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
2343 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
2344 libconf->conf->listen_interval - 1);
2345 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
2346 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2347
2348 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2349 } else {
f4450616
BZ		 2350 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2351 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
2352 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
2353 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
2354 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 2355
2356 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 2357 }
2358}
2359
2360void rt2800_config(struct rt2x00_dev *rt2x00dev,
2361 struct rt2x00lib_conf *libconf,
2362 const unsigned int flags)
2363{
2364 /* Always recalculate LNA gain before changing configuration */
2365 rt2800_config_lna_gain(rt2x00dev, libconf);
2366
e90c54b2 2367 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
f4450616
BZ		 2368 rt2800_config_channel(rt2x00dev, libconf->conf,
2369 &libconf->rf, &libconf->channel);
9e33a355
HS		 2370 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2371 libconf->conf->power_level);
e90c54b2 2372 }
f4450616 2373 if (flags & IEEE80211_CONF_CHANGE_POWER)
9e33a355
HS		 2374 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2375 libconf->conf->power_level);
f4450616
BZ		 2376 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2377 rt2800_config_retry_limit(rt2x00dev, libconf);
2378 if (flags & IEEE80211_CONF_CHANGE_PS)
2379 rt2800_config_ps(rt2x00dev, libconf);
2380}
2381EXPORT_SYMBOL_GPL(rt2800_config);
2382
2383/*
2384 * Link tuning
2385 */
2386void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2387{
2388 u32 reg;
2389
2390 /*
2391 * Update FCS error count from register.
2392 */
2393 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2394 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
2395}
2396EXPORT_SYMBOL_GPL(rt2800_link_stats);
2397
2398static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
2399{
2400 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
d5385bfc 2401 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 2402 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 2403 rt2x00_rt(rt2x00dev, RT3090) ||
adde5882
GJ		 2404 rt2x00_rt(rt2x00dev, RT3390) ||
2405 rt2x00_rt(rt2x00dev, RT5390))
f4450616
BZ		 2406 return 0x1c + (2 * rt2x00dev->lna_gain);
2407 else
2408 return 0x2e + rt2x00dev->lna_gain;
2409 }
2410
2411 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2412 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
2413 else
2414 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
2415}
2416
2417static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
2418 struct link_qual *qual, u8 vgc_level)
2419{
2420 if (qual->vgc_level != vgc_level) {
2421 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
2422 qual->vgc_level = vgc_level;
2423 qual->vgc_level_reg = vgc_level;
2424 }
2425}
2426
2427void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2428{
2429 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
2430}
2431EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
2432
2433void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
2434 const u32 count)
2435{
8d0c9b65 2436 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616
BZ		 2437 return;
2438
2439 /*
2440 * When RSSI is better then -80 increase VGC level with 0x10
2441 */
2442 rt2800_set_vgc(rt2x00dev, qual,
2443 rt2800_get_default_vgc(rt2x00dev) +
2444 ((qual->rssi > -80) * 0x10));
2445}
2446EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 2447
2448/*
2449 * Initialization functions.
2450 */
b9a07ae9 2451static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 2452{
2453 u32 reg;
d5385bfc 2454 u16 eeprom;
fcf51541 2455 unsigned int i;
e3a896b9 2456 int ret;
fcf51541 2457
a9dce149
GW		 2458 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2459 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2460 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2461 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2462 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2463 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2464 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2465
e3a896b9
GW		 2466 ret = rt2800_drv_init_registers(rt2x00dev);
2467 if (ret)
2468 return ret;
fcf51541
BZ		 2469
2470 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
2471 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
2472 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
2473 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
2474 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
2475 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
2476
2477 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
2478 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
2479 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
2480 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
2481 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
2482 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
2483
2484 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
2485 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2486
2487 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
2488
2489 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
8544df32 2490 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
fcf51541
BZ		 2491 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2492 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
2493 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2494 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2495 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
2496 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2497
a9dce149
GW		 2498 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
2499
2500 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
2501 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
2502 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
2503 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2504
64522957 2505 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2506 rt2x00_rt(rt2x00dev, RT3090) ||
2507 rt2x00_rt(rt2x00dev, RT3390)) {
fcf51541
BZ		 2508 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2509 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 2510 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2511 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2512 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
38c8a566
RJH		 2513 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2514 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 2515 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2516 0x0000002c);
2517 else
2518 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2519 0x0000000f);
2520 } else {
2521 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2522 }
d5385bfc 2523 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 2524 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 2525
2526 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2527 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2528 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
2529 } else {
2530 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2531 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2532 }
c295a81d
HS		 2533 } else if (rt2800_is_305x_soc(rt2x00dev)) {
2534 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2535 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
961636ba 2536 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
872834df
GW		 2537 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
2538 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2539 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
adde5882
GJ		 2540 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2541 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
2542 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2543 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
fcf51541
BZ		 2544 } else {
2545 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
2546 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2547 }
2548
2549 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
2550 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
2551 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
2552 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
2553 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
2554 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
2555 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
2556 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
2557 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
2558 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
2559
2560 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
2561 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 2562 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 2563 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
2564 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
2565
2566 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
2567 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 2568 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 2569 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 2570 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 2571 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
2572 else
2573 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
2574 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
2575 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
2576 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
2577
a9dce149
GW		 2578 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
2579 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
2580 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
2581 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
2582 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
2583 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
2584 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
2585 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
2586 rt2800_register_write(rt2x00dev, LED_CFG, reg);
2587
fcf51541
BZ		 2588 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
2589
a9dce149
GW		 2590 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2591 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
2592 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
2593 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
2594 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
2595 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
2596 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
2597 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2598
fcf51541
BZ		 2599 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
2600 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 2601 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 2602 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
2603 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 2604 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 2605 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
2606 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
2607 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2608
2609 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 2610 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541 2611 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2612 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2613 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2614 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2615 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 2616 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 2617 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 2618 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2619 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 2620 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2621
2622 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 2623 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541 2624 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2625 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2626 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2627 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2628 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 2629 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 2630 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 2631 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2632 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 2633 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2634
2635 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2636 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2637 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2638 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2639 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2640 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2641 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2642 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2643 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2644 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 2645 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2646 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2647
2648 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2649 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
d13a97f0 2650 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2651 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2652 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2653 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2654 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2655 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2656 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2657 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 2658 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2659 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2660
2661 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2662 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2663 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2664 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2665 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2666 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2667 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2668 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2669 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2670 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 2671 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2672 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2673
2674 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2675 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2676 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2677 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2678 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2679 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2680 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2681 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2682 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2683 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 2684 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2685 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2686
cea90e55 2687 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 2688 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
2689
2690 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2691 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2692 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2693 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2694 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2695 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
2696 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
2697 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
2698 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
2699 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
2700 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2701 }
2702
961621ab
HS		 2703 /*
2704 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2705 * although it is reserved.
2706 */
2707 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
2708 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
2709 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
2710 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
2711 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
2712 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
2713 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
2714 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
2715 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
2716 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
2717 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
2718 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
2719
fcf51541
BZ		 2720 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
2721
2722 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2723 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
2724 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
2725 IEEE80211_MAX_RTS_THRESHOLD);
2726 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
2727 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2728
2729 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 2730
a21c2ab4
HS		 2731 /*
2732 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
2733 * time should be set to 16. However, the original Ralink driver uses
2734 * 16 for both and indeed using a value of 10 for CCK SIFS results in
2735 * connection problems with 11g + CTS protection. Hence, use the same
2736 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
2737 */
a9dce149 2738 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 2739 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
2740 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 2741 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
2742 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
2743 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
2744 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2745
fcf51541
BZ		 2746 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
2747
2748 /*
2749 * ASIC will keep garbage value after boot, clear encryption keys.
2750 */
2751 for (i = 0; i < 4; i++)
2752 rt2800_register_write(rt2x00dev,
2753 SHARED_KEY_MODE_ENTRY(i), 0);
2754
2755 for (i = 0; i < 256; i++) {
f4e16e41 2756 static const u32 wcid[2] = { 0xffffffff, 0x00ffffff };
fcf51541
BZ		 2757 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
2758 wcid, sizeof(wcid));
2759
1ed3811c 2760 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 0);
fcf51541
BZ		 2761 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
2762 }
2763
2764 /*
2765 * Clear all beacons
fcf51541 2766 */
69cf36a4
HS		 2767 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
2768 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
2769 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
2770 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
2771 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
2772 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
2773 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
2774 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
fcf51541 2775
cea90e55 2776 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 2777 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2778 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
2779 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
c6fcc0e5
RJH		 2780 } else if (rt2x00_is_pcie(rt2x00dev)) {
2781 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2782 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
2783 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 2784 }
2785
2786 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
2787 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
2788 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
2789 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
2790 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
2791 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
2792 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
2793 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
2794 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
2795 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
2796
2797 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
2798 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
2799 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
2800 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
2801 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
2802 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
2803 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
2804 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
2805 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
2806 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
2807
2808 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
2809 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
2810 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
2811 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
2812 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
2813 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
2814 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
2815 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
2816 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
2817 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
2818
2819 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
2820 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
2821 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
2822 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
2823 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
2824 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
2825
47ee3eb1
HS		 2826 /*
2827 * Do not force the BA window size, we use the TXWI to set it
2828 */
2829 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
2830 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
2831 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
2832 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
2833
fcf51541
BZ		 2834 /*
2835 * We must clear the error counters.
2836 * These registers are cleared on read,
2837 * so we may pass a useless variable to store the value.
2838 */
2839 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2840 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
2841 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
2842 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
2843 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
2844 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
2845
9f926fb5
HS		 2846 /*
2847 * Setup leadtime for pre tbtt interrupt to 6ms
2848 */
2849 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
2850 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
2851 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
2852
977206d7
HS		 2853 /*
2854 * Set up channel statistics timer
2855 */
2856 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
2857 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
2858 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
2859 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
2860 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
2861 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
2862 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
2863
fcf51541
BZ		 2864 return 0;
2865}
fcf51541
BZ		 2866
2867static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
2868{
2869 unsigned int i;
2870 u32 reg;
2871
2872 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2873 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
2874 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
2875 return 0;
2876
2877 udelay(REGISTER_BUSY_DELAY);
2878 }
2879
2880 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
2881 return -EACCES;
2882}
2883
2884static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2885{
2886 unsigned int i;
2887 u8 value;
2888
2889 /*
2890 * BBP was enabled after firmware was loaded,
2891 * but we need to reactivate it now.
2892 */
2893 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2894 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2895 msleep(1);
2896
2897 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2898 rt2800_bbp_read(rt2x00dev, 0, &value);
2899 if ((value != 0xff) && (value != 0x00))
2900 return 0;
2901 udelay(REGISTER_BUSY_DELAY);
2902 }
2903
2904 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
2905 return -EACCES;
2906}
2907
b9a07ae9 2908static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 2909{
2910 unsigned int i;
2911 u16 eeprom;
2912 u8 reg_id;
2913 u8 value;
2914
2915 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
2916 rt2800_wait_bbp_ready(rt2x00dev)))
2917 return -EACCES;
2918
adde5882
GJ		 2919 if (rt2x00_rt(rt2x00dev, RT5390)) {
2920 rt2800_bbp_read(rt2x00dev, 4, &value);
2921 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
2922 rt2800_bbp_write(rt2x00dev, 4, value);
2923 }
60687ba7 2924
adde5882 2925 if (rt2800_is_305x_soc(rt2x00dev) ||
872834df 2926 rt2x00_rt(rt2x00dev, RT3572) ||
adde5882 2927 rt2x00_rt(rt2x00dev, RT5390))
baff8006
HS		 2928 rt2800_bbp_write(rt2x00dev, 31, 0x08);
2929
fcf51541
BZ		 2930 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
2931 rt2800_bbp_write(rt2x00dev, 66, 0x38);
a9dce149 2932
adde5882
GJ		 2933 if (rt2x00_rt(rt2x00dev, RT5390))
2934 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
60687ba7 2935
a9dce149
GW		 2936 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2937 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2938 rt2800_bbp_write(rt2x00dev, 73, 0x12);
adde5882
GJ		 2939 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2940 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2941 rt2800_bbp_write(rt2x00dev, 73, 0x13);
2942 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2943 rt2800_bbp_write(rt2x00dev, 76, 0x28);
2944 rt2800_bbp_write(rt2x00dev, 77, 0x59);
a9dce149
GW		 2945 } else {
2946 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2947 rt2800_bbp_write(rt2x00dev, 73, 0x10);
2948 }
2949
fcf51541 2950 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
8cdd15e0 2951
d5385bfc 2952 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 2953 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 2954 rt2x00_rt(rt2x00dev, RT3090) ||
adde5882 2955 rt2x00_rt(rt2x00dev, RT3390) ||
872834df 2956 rt2x00_rt(rt2x00dev, RT3572) ||
adde5882 2957 rt2x00_rt(rt2x00dev, RT5390)) {
8cdd15e0
GW		 2958 rt2800_bbp_write(rt2x00dev, 79, 0x13);
2959 rt2800_bbp_write(rt2x00dev, 80, 0x05);
2960 rt2800_bbp_write(rt2x00dev, 81, 0x33);
baff8006
HS		 2961 } else if (rt2800_is_305x_soc(rt2x00dev)) {
2962 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
2963 rt2800_bbp_write(rt2x00dev, 80, 0x08);
8cdd15e0
GW		 2964 } else {
2965 rt2800_bbp_write(rt2x00dev, 81, 0x37);
2966 }
2967
fcf51541 2968 rt2800_bbp_write(rt2x00dev, 82, 0x62);
adde5882
GJ		 2969 if (rt2x00_rt(rt2x00dev, RT5390))
2970 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
2971 else
2972 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
a9dce149 2973
5ed8f458 2974 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
a9dce149 2975 rt2800_bbp_write(rt2x00dev, 84, 0x19);
adde5882
GJ		 2976 else if (rt2x00_rt(rt2x00dev, RT5390))
2977 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
a9dce149
GW		 2978 else
2979 rt2800_bbp_write(rt2x00dev, 84, 0x99);
2980
adde5882
GJ		 2981 if (rt2x00_rt(rt2x00dev, RT5390))
2982 rt2800_bbp_write(rt2x00dev, 86, 0x38);
2983 else
2984 rt2800_bbp_write(rt2x00dev, 86, 0x00);
60687ba7 2985
fcf51541 2986 rt2800_bbp_write(rt2x00dev, 91, 0x04);
60687ba7 2987
adde5882
GJ		 2988 if (rt2x00_rt(rt2x00dev, RT5390))
2989 rt2800_bbp_write(rt2x00dev, 92, 0x02);
2990 else
2991 rt2800_bbp_write(rt2x00dev, 92, 0x00);
8cdd15e0 2992
d5385bfc 2993 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 2994 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904 2995 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
baff8006 2996 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
872834df 2997 rt2x00_rt(rt2x00dev, RT3572) ||
adde5882 2998 rt2x00_rt(rt2x00dev, RT5390) ||
baff8006 2999 rt2800_is_305x_soc(rt2x00dev))
8cdd15e0
GW		 3000 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
3001 else
3002 rt2800_bbp_write(rt2x00dev, 103, 0x00);
3003
adde5882
GJ		 3004 if (rt2x00_rt(rt2x00dev, RT5390))
3005 rt2800_bbp_write(rt2x00dev, 104, 0x92);
60687ba7 3006
baff8006
HS		 3007 if (rt2800_is_305x_soc(rt2x00dev))
3008 rt2800_bbp_write(rt2x00dev, 105, 0x01);
adde5882
GJ		 3009 else if (rt2x00_rt(rt2x00dev, RT5390))
3010 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
baff8006
HS		 3011 else
3012 rt2800_bbp_write(rt2x00dev, 105, 0x05);
60687ba7 3013
adde5882
GJ		 3014 if (rt2x00_rt(rt2x00dev, RT5390))
3015 rt2800_bbp_write(rt2x00dev, 106, 0x03);
3016 else
3017 rt2800_bbp_write(rt2x00dev, 106, 0x35);
60687ba7 3018
adde5882
GJ		 3019 if (rt2x00_rt(rt2x00dev, RT5390))
3020 rt2800_bbp_write(rt2x00dev, 128, 0x12);
fcf51541 3021
64522957 3022 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 3023 rt2x00_rt(rt2x00dev, RT3090) ||
adde5882 3024 rt2x00_rt(rt2x00dev, RT3390) ||
872834df 3025 rt2x00_rt(rt2x00dev, RT3572) ||
adde5882 3026 rt2x00_rt(rt2x00dev, RT5390)) {
d5385bfc 3027 rt2800_bbp_read(rt2x00dev, 138, &value);
fcf51541 3028
38c8a566
RJH		 3029 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3030 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
d5385bfc 3031 value |= 0x20;
38c8a566 3032 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
d5385bfc 3033 value &= ~0x02;
fcf51541 3034
d5385bfc 3035 rt2800_bbp_write(rt2x00dev, 138, value);
fcf51541
BZ		 3036 }
3037
adde5882
GJ		 3038 if (rt2x00_rt(rt2x00dev, RT5390)) {
3039 int ant, div_mode;
3040
3041 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3042 div_mode = rt2x00_get_field16(eeprom,
3043 EEPROM_NIC_CONF1_ANT_DIVERSITY);
3044 ant = (div_mode == 3) ? 1 : 0;
3045
3046 /* check if this is a Bluetooth combo card */
fdbc7b0a 3047 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
adde5882
GJ		 3048 u32 reg;
3049
3050 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
3051 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
3052 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT6, 0);
3053 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 0);
3054 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 0);
3055 if (ant == 0)
3056 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 1);
3057 else if (ant == 1)
3058 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 1);
3059 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
3060 }
3061
3062 rt2800_bbp_read(rt2x00dev, 152, &value);
3063 if (ant == 0)
3064 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
3065 else
3066 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
3067 rt2800_bbp_write(rt2x00dev, 152, value);
3068
3069 /* Init frequency calibration */
3070 rt2800_bbp_write(rt2x00dev, 142, 1);
3071 rt2800_bbp_write(rt2x00dev, 143, 57);
3072 }
fcf51541
BZ		 3073
3074 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
3075 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
3076
3077 if (eeprom != 0xffff && eeprom != 0x0000) {
3078 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
3079 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
3080 rt2800_bbp_write(rt2x00dev, reg_id, value);
3081 }
3082 }
3083
3084 return 0;
3085}
fcf51541
BZ		 3086
3087static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
3088 bool bw40, u8 rfcsr24, u8 filter_target)
3089{
3090 unsigned int i;
3091 u8 bbp;
3092 u8 rfcsr;
3093 u8 passband;
3094 u8 stopband;
3095 u8 overtuned = 0;
3096
3097 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3098
3099 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3100 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
3101 rt2800_bbp_write(rt2x00dev, 4, bbp);
3102
80d184e6
RJH		 3103 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
3104 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
3105 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
3106
fcf51541
BZ		 3107 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3108 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
3109 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3110
3111 /*
3112 * Set power & frequency of passband test tone
3113 */
3114 rt2800_bbp_write(rt2x00dev, 24, 0);
3115
3116 for (i = 0; i < 100; i++) {
3117 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3118 msleep(1);
3119
3120 rt2800_bbp_read(rt2x00dev, 55, &passband);
3121 if (passband)
3122 break;
3123 }
3124
3125 /*
3126 * Set power & frequency of stopband test tone
3127 */
3128 rt2800_bbp_write(rt2x00dev, 24, 0x06);
3129
3130 for (i = 0; i < 100; i++) {
3131 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3132 msleep(1);
3133
3134 rt2800_bbp_read(rt2x00dev, 55, &stopband);
3135
3136 if ((passband - stopband) <= filter_target) {
3137 rfcsr24++;
3138 overtuned += ((passband - stopband) == filter_target);
3139 } else
3140 break;
3141
3142 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3143 }
3144
3145 rfcsr24 -= !!overtuned;
3146
3147 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3148 return rfcsr24;
3149}
3150
b9a07ae9 3151static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 3152{
3153 u8 rfcsr;
3154 u8 bbp;
8cdd15e0
GW		 3155 u32 reg;
3156 u16 eeprom;
fcf51541 3157
d5385bfc 3158 if (!rt2x00_rt(rt2x00dev, RT3070) &&
64522957 3159 !rt2x00_rt(rt2x00dev, RT3071) &&
cc78e904 3160 !rt2x00_rt(rt2x00dev, RT3090) &&
23812383 3161 !rt2x00_rt(rt2x00dev, RT3390) &&
872834df 3162 !rt2x00_rt(rt2x00dev, RT3572) &&
adde5882 3163 !rt2x00_rt(rt2x00dev, RT5390) &&
baff8006 3164 !rt2800_is_305x_soc(rt2x00dev))
fcf51541
BZ		 3165 return 0;
3166
fcf51541
BZ		 3167 /*
3168 * Init RF calibration.
3169 */
adde5882
GJ		 3170 if (rt2x00_rt(rt2x00dev, RT5390)) {
3171 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
3172 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
3173 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3174 msleep(1);
3175 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
3176 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3177 } else {
3178 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3179 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
3180 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3181 msleep(1);
3182 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
3183 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3184 }
fcf51541 3185
d5385bfc 3186 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957
GW		 3187 rt2x00_rt(rt2x00dev, RT3071) ||
3188 rt2x00_rt(rt2x00dev, RT3090)) {
fcf51541
BZ		 3189 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3190 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3191 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
80d184e6 3192 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
fcf51541 3193 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
8cdd15e0 3194 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
fcf51541
BZ		 3195 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3196 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
3197 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3198 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3199 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3200 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3201 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3202 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3203 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3204 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3205 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3206 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
fcf51541 3207 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
cc78e904
GW		 3208 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3209 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
3210 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
3211 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3212 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
fcf51541 3213 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
cc78e904
GW		 3214 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
3215 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
3216 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
3217 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
3218 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
3219 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
fcf51541 3220 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
cc78e904
GW		 3221 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
3222 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
fcf51541 3223 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
cc78e904
GW		 3224 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3225 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
3226 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
3227 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
3228 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
3229 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
3230 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
fcf51541 3231 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
cc78e904 3232 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
fcf51541 3233 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
cc78e904
GW		 3234 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
3235 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3236 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3237 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
3238 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
3239 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
3240 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
872834df
GW		 3241 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3242 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
3243 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
3244 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3245 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
3246 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
3247 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
3248 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
3249 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
3250 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
3251 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
3252 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
3253 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
3254 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
3255 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
3256 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3257 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
3258 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
3259 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
3260 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
3261 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
3262 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
3263 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3264 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
3265 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3266 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
3267 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3268 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3269 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3270 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
3271 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
3272 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
baff8006 3273 } else if (rt2800_is_305x_soc(rt2x00dev)) {
23812383
HS		 3274 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
3275 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
3276 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
3277 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
3278 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3279 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3280 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3281 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
3282 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
3283 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3284 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
3285 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3286 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
3287 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
3288 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3289 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3290 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3291 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3292 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3293 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3294 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3295 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3296 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3297 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
3298 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3299 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3300 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
3301 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
3302 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
3303 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
baff8006
HS		 3304 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3305 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
3306 return 0;
adde5882
GJ		 3307 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
3308 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
3309 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3310 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
3311 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
3312 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3313 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
3314 else
3315 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
3316 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
3317 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3318 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3319 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
3320 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3321 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
3322 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
3323 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
3324 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
3325 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
3326
3327 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
3328 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
3329 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3330 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
3331 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
3332 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3333 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3334 else
3335 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
3336 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
3337 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3338 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3339 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3340
3341 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3342 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3343 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3344 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3345 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3346 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3347 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3348 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3349 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3350 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3351
3352 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3353 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3354 else
3355 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
3356 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3357 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
3358 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
3359 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3360 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3361 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3362 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3363 else
3364 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
3365 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3366 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3367 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3368
3369 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3370 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3371 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3372 else
3373 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
3374 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3375 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
3376 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
3377 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3378 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3379 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
3380
3381 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3382 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3383 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
3384 else
3385 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
3386 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
3387 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
8cdd15e0
GW		 3388 }
3389
3390 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3391 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3392 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3393 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3394 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
64522957
GW		 3395 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3396 rt2x00_rt(rt2x00dev, RT3090)) {
80d184e6
RJH		 3397 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
3398
d5385bfc
GW		 3399 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3400 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3401 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3402
d5385bfc
GW		 3403 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3404 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
64522957
GW		 3405 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3406 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
38c8a566
RJH		 3407 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3408 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 3409 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3410 else
3411 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
3412 }
3413 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
80d184e6
RJH		 3414
3415 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3416 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3417 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
cc78e904
GW		 3418 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3419 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3420 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3421 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
872834df
GW		 3422 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3423 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3424 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3425 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3426
3427 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3428 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3429 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3430 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3431 msleep(1);
3432 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3433 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3434 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
fcf51541
BZ		 3435 }
3436
3437 /*
3438 * Set RX Filter calibration for 20MHz and 40MHz
3439 */
8cdd15e0
GW		 3440 if (rt2x00_rt(rt2x00dev, RT3070)) {
3441 rt2x00dev->calibration[0] =
3442 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
3443 rt2x00dev->calibration[1] =
3444 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
64522957 3445 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 3446 rt2x00_rt(rt2x00dev, RT3090) ||
872834df
GW		 3447 rt2x00_rt(rt2x00dev, RT3390) ||
3448 rt2x00_rt(rt2x00dev, RT3572)) {
d5385bfc
GW		 3449 rt2x00dev->calibration[0] =
3450 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
3451 rt2x00dev->calibration[1] =
3452 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
8cdd15e0 3453 }
fcf51541 3454
adde5882
GJ		 3455 if (!rt2x00_rt(rt2x00dev, RT5390)) {
3456 /*
3457 * Set back to initial state
3458 */
3459 rt2800_bbp_write(rt2x00dev, 24, 0);
fcf51541 3460
adde5882
GJ		 3461 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3462 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
3463 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
fcf51541 3464
adde5882
GJ		 3465 /*
3466 * Set BBP back to BW20
3467 */
3468 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3469 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
3470 rt2800_bbp_write(rt2x00dev, 4, bbp);
3471 }
fcf51541 3472
d5385bfc 3473 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 3474 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 3475 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3476 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
8cdd15e0
GW		 3477 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
3478
3479 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
3480 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
3481 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
3482
adde5882
GJ		 3483 if (!rt2x00_rt(rt2x00dev, RT5390)) {
3484 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
3485 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
3486 if (rt2x00_rt(rt2x00dev, RT3070) ||
3487 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3488 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3489 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
7dab73b3
ID		 3490 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
3491 &rt2x00dev->cap_flags))
adde5882
GJ		 3492 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
3493 }
3494 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
3495 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
3496 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
3497 rt2x00_get_field16(eeprom,
3498 EEPROM_TXMIXER_GAIN_BG_VAL));
3499 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3500 }
8cdd15e0 3501
64522957
GW		 3502 if (rt2x00_rt(rt2x00dev, RT3090)) {
3503 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3504
80d184e6 3505 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
38c8a566
RJH		 3506 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3507 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
64522957 3508 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
38c8a566 3509 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
64522957
GW		 3510 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
3511
3512 rt2800_bbp_write(rt2x00dev, 138, bbp);
3513 }
3514
3515 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 3516 rt2x00_rt(rt2x00dev, RT3090) ||
3517 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 3518 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
3519 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3520 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
3521 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
3522 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3523 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3524 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3525
3526 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
3527 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
3528 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
3529
3530 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
3531 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
3532 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3533
3534 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
3535 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
3536 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3537 }
3538
80d184e6 3539 if (rt2x00_rt(rt2x00dev, RT3070)) {
8cdd15e0 3540 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
80d184e6 3541 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
8cdd15e0
GW		 3542 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
3543 else
3544 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
3545 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
3546 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
3547 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
3548 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
3549 }
3550
adde5882
GJ		 3551 if (rt2x00_rt(rt2x00dev, RT5390)) {
3552 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
3553 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
3554 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
60687ba7 3555
adde5882
GJ		 3556 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
3557 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
3558 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
60687ba7 3559
adde5882
GJ		 3560 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3561 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
3562 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3563 }
60687ba7 3564
fcf51541
BZ		 3565 return 0;
3566}
b9a07ae9
ID		 3567
3568int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
3569{
3570 u32 reg;
3571 u16 word;
3572
3573 /*
3574 * Initialize all registers.
3575 */
3576 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
3577 rt2800_init_registers(rt2x00dev) ||
3578 rt2800_init_bbp(rt2x00dev) ||
3579 rt2800_init_rfcsr(rt2x00dev)))
3580 return -EIO;
3581
3582 /*
3583 * Send signal to firmware during boot time.
3584 */
3585 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
3586
3587 if (rt2x00_is_usb(rt2x00dev) &&
3588 (rt2x00_rt(rt2x00dev, RT3070) ||
3589 rt2x00_rt(rt2x00dev, RT3071) ||
3590 rt2x00_rt(rt2x00dev, RT3572))) {
3591 udelay(200);
3592 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
3593 udelay(10);
3594 }
3595
3596 /*
3597 * Enable RX.
3598 */
3599 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3600 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3601 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3602 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3603
3604 udelay(50);
3605
3606 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3607 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
3608 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
3609 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
3610 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
3611 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3612
3613 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3614 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3615 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
3616 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3617
3618 /*
3619 * Initialize LED control
3620 */
38c8a566
RJH		 3621 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
3622 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
b9a07ae9
ID		 3623 word & 0xff, (word >> 8) & 0xff);
3624
38c8a566
RJH		 3625 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
3626 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
b9a07ae9
ID		 3627 word & 0xff, (word >> 8) & 0xff);
3628
38c8a566
RJH		 3629 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
3630 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
b9a07ae9
ID		 3631 word & 0xff, (word >> 8) & 0xff);
3632
3633 return 0;
3634}
3635EXPORT_SYMBOL_GPL(rt2800_enable_radio);
3636
3637void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
3638{
3639 u32 reg;
3640
3641 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3642 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
b9a07ae9 3643 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
b9a07ae9
ID		 3644 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3645
3646 /* Wait for DMA, ignore error */
3647 rt2800_wait_wpdma_ready(rt2x00dev);
3648
3649 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3650 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
3651 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3652 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
b9a07ae9
ID		 3653}
3654EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2ce33995 3655
30e84034
BZ		 3656int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
3657{
3658 u32 reg;
3659
3660 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
3661
3662 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
3663}
3664EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
3665
3666static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
3667{
3668 u32 reg;
3669
31a4cf1f
GW		 3670 mutex_lock(&rt2x00dev->csr_mutex);
3671
3672 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
30e84034
BZ		 3673 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
3674 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
3675 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
31a4cf1f 3676 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
30e84034
BZ		 3677
3678 /* Wait until the EEPROM has been loaded */
3679 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
3680
3681 /* Apparently the data is read from end to start */
31a4cf1f
GW		 3682 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
3683 (u32 *)&rt2x00dev->eeprom[i]);
3684 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
3685 (u32 *)&rt2x00dev->eeprom[i + 2]);
3686 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
3687 (u32 *)&rt2x00dev->eeprom[i + 4]);
3688 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
3689 (u32 *)&rt2x00dev->eeprom[i + 6]);
3690
3691 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 3692}
3693
3694void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
3695{
3696 unsigned int i;
3697
3698 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
3699 rt2800_efuse_read(rt2x00dev, i);
3700}
3701EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
3702
38bd7b8a
BZ		 3703int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
3704{
3705 u16 word;
3706 u8 *mac;
3707 u8 default_lna_gain;
3708
3709 /*
3710 * Start validation of the data that has been read.
3711 */
3712 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
3713 if (!is_valid_ether_addr(mac)) {
3714 random_ether_addr(mac);
3715 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
3716 }
3717
38c8a566 3718 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
38bd7b8a 3719 if (word == 0xffff) {
38c8a566
RJH		 3720 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3721 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
3722 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
3723 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a 3724 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 3725 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 3726 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 3727 /*
3728 * There is a max of 2 RX streams for RT28x0 series
3729 */
38c8a566
RJH		 3730 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
3731 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3732 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a
BZ		 3733 }
3734
38c8a566 3735 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
38bd7b8a 3736 if (word == 0xffff) {
38c8a566
RJH		 3737 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
3738 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
3739 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
3740 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
3741 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
3742 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
3743 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
3744 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
3745 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
3746 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
3747 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
3748 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
3749 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
3750 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
3751 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
3752 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
38bd7b8a
BZ		 3753 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
3754 }
3755
3756 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
3757 if ((word & 0x00ff) == 0x00ff) {
3758 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
ec2d1791
GW		 3759 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
3760 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
3761 }
3762 if ((word & 0xff00) == 0xff00) {
38bd7b8a
BZ		 3763 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
3764 LED_MODE_TXRX_ACTIVITY);
3765 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
3766 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
38c8a566
RJH		 3767 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
3768 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
3769 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
ec2d1791 3770 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
38bd7b8a
BZ		 3771 }
3772
3773 /*
3774 * During the LNA validation we are going to use
3775 * lna0 as correct value. Note that EEPROM_LNA
3776 * is never validated.
3777 */
3778 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
3779 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
3780
3781 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
3782 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
3783 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
3784 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
3785 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
3786 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
3787
3788 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
3789 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
3790 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
3791 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
3792 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
3793 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
3794 default_lna_gain);
3795 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
3796
3797 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
3798 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
3799 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
3800 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
3801 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
3802 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
3803
3804 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
3805 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
3806 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
3807 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
3808 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
3809 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
3810 default_lna_gain);
3811 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
3812
3813 return 0;
3814}
3815EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
3816
3817int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
3818{
3819 u32 reg;
3820 u16 value;
3821 u16 eeprom;
3822
3823 /*
3824 * Read EEPROM word for configuration.
3825 */
38c8a566 3826 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
38bd7b8a
BZ		 3827
3828 /*
adde5882
GJ		 3829 * Identify RF chipset by EEPROM value
3830 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
3831 * RT53xx: defined in "EEPROM_CHIP_ID" field
38bd7b8a 3832 */
38bd7b8a 3833 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
adde5882
GJ		 3834 if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390)
3835 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
3836 else
3837 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
38bd7b8a 3838
49e721ec
GW		 3839 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
3840 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
3841
3842 if (!rt2x00_rt(rt2x00dev, RT2860) &&
49e721ec 3843 !rt2x00_rt(rt2x00dev, RT2872) &&
49e721ec 3844 !rt2x00_rt(rt2x00dev, RT2883) &&
49e721ec
GW		 3845 !rt2x00_rt(rt2x00dev, RT3070) &&
3846 !rt2x00_rt(rt2x00dev, RT3071) &&
3847 !rt2x00_rt(rt2x00dev, RT3090) &&
3848 !rt2x00_rt(rt2x00dev, RT3390) &&
adde5882
GJ		 3849 !rt2x00_rt(rt2x00dev, RT3572) &&
3850 !rt2x00_rt(rt2x00dev, RT5390)) {
49e721ec
GW		 3851 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
3852 return -ENODEV;
f273fe55 3853 }
714fa663 3854
5122d898
GW		 3855 if (!rt2x00_rf(rt2x00dev, RF2820) &&
3856 !rt2x00_rf(rt2x00dev, RF2850) &&
3857 !rt2x00_rf(rt2x00dev, RF2720) &&
3858 !rt2x00_rf(rt2x00dev, RF2750) &&
3859 !rt2x00_rf(rt2x00dev, RF3020) &&
3860 !rt2x00_rf(rt2x00dev, RF2020) &&
3861 !rt2x00_rf(rt2x00dev, RF3021) &&
6c0fe265 3862 !rt2x00_rf(rt2x00dev, RF3022) &&
f93bc9b3 3863 !rt2x00_rf(rt2x00dev, RF3052) &&
adde5882 3864 !rt2x00_rf(rt2x00dev, RF3320) &&
aca355b9 3865 !rt2x00_rf(rt2x00dev, RF5370) &&
adde5882 3866 !rt2x00_rf(rt2x00dev, RF5390)) {
38bd7b8a
BZ		 3867 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
3868 return -ENODEV;
3869 }
3870
3871 /*
3872 * Identify default antenna configuration.
3873 */
d96aa640 3874 rt2x00dev->default_ant.tx_chain_num =
38c8a566 3875 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
d96aa640 3876 rt2x00dev->default_ant.rx_chain_num =
38c8a566 3877 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
38bd7b8a 3878
d96aa640
RJH		 3879 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3880
3881 if (rt2x00_rt(rt2x00dev, RT3070) ||
3882 rt2x00_rt(rt2x00dev, RT3090) ||
3883 rt2x00_rt(rt2x00dev, RT3390)) {
3884 value = rt2x00_get_field16(eeprom,
3885 EEPROM_NIC_CONF1_ANT_DIVERSITY);
3886 switch (value) {
3887 case 0:
3888 case 1:
3889 case 2:
3890 rt2x00dev->default_ant.tx = ANTENNA_A;
3891 rt2x00dev->default_ant.rx = ANTENNA_A;
3892 break;
3893 case 3:
3894 rt2x00dev->default_ant.tx = ANTENNA_A;
3895 rt2x00dev->default_ant.rx = ANTENNA_B;
3896 break;
3897 }
3898 } else {
3899 rt2x00dev->default_ant.tx = ANTENNA_A;
3900 rt2x00dev->default_ant.rx = ANTENNA_A;
3901 }
3902
38bd7b8a 3903 /*
9328fdac 3904 * Determine external LNA informations.
38bd7b8a 3905 */
38c8a566 3906 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
7dab73b3 3907 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
38c8a566 3908 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
7dab73b3 3909 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
38bd7b8a
BZ		 3910
3911 /*
3912 * Detect if this device has an hardware controlled radio.
3913 */
38c8a566 3914 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
7dab73b3 3915 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
38bd7b8a 3916
fdbc7b0a
GW		 3917 /*
3918 * Detect if this device has Bluetooth co-existence.
3919 */
3920 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
3921 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
3922
9328fdac
GW		 3923 /*
3924 * Read frequency offset and RF programming sequence.
3925 */
3926 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
3927 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
3928
38bd7b8a
BZ		 3929 /*
3930 * Store led settings, for correct led behaviour.
3931 */
3932#ifdef CONFIG_RT2X00_LIB_LEDS
3933 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3934 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
3935 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
3936
9328fdac 3937 rt2x00dev->led_mcu_reg = eeprom;
38bd7b8a
BZ		 3938#endif /* CONFIG_RT2X00_LIB_LEDS */
3939
e90c54b2
RJH		 3940 /*
3941 * Check if support EIRP tx power limit feature.
3942 */
3943 rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
3944
3945 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
3946 EIRP_MAX_TX_POWER_LIMIT)
7dab73b3 3947 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
e90c54b2 3948
38bd7b8a
BZ		 3949 return 0;
3950}
3951EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
3952
4da2933f 3953/*
55f9321a 3954 * RF value list for rt28xx
4da2933f
BZ		 3955 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
3956 */
3957static const struct rf_channel rf_vals[] = {
3958 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
3959 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
3960 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
3961 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
3962 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
3963 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
3964 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
3965 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
3966 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
3967 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
3968 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
3969 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
3970 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
3971 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
3972
3973 /* 802.11 UNI / HyperLan 2 */
3974 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
3975 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
3976 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
3977 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
3978 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
3979 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
3980 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
3981 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
3982 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
3983 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
3984 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
3985 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
3986
3987 /* 802.11 HyperLan 2 */
3988 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
3989 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
3990 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
3991 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
3992 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
3993 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
3994 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
3995 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
3996 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
3997 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
3998 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
3999 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
4000 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
4001 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
4002 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
4003 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
4004
4005 /* 802.11 UNII */
4006 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
4007 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
4008 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
4009 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
4010 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
4011 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
4012 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
4013 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
4014 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
4015 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
4016 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
4017
4018 /* 802.11 Japan */
4019 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
4020 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
4021 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
4022 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
4023 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
4024 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
4025 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
4026};
4027
4028/*
55f9321a
ID		 4029 * RF value list for rt3xxx
4030 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4da2933f 4031 */
55f9321a 4032static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 4033 {1, 241, 2, 2 },
4034 {2, 241, 2, 7 },
4035 {3, 242, 2, 2 },
4036 {4, 242, 2, 7 },
4037 {5, 243, 2, 2 },
4038 {6, 243, 2, 7 },
4039 {7, 244, 2, 2 },
4040 {8, 244, 2, 7 },
4041 {9, 245, 2, 2 },
4042 {10, 245, 2, 7 },
4043 {11, 246, 2, 2 },
4044 {12, 246, 2, 7 },
4045 {13, 247, 2, 2 },
4046 {14, 248, 2, 4 },
55f9321a
ID		 4047
4048 /* 802.11 UNI / HyperLan 2 */
4049 {36, 0x56, 0, 4},
4050 {38, 0x56, 0, 6},
4051 {40, 0x56, 0, 8},
4052 {44, 0x57, 0, 0},
4053 {46, 0x57, 0, 2},
4054 {48, 0x57, 0, 4},
4055 {52, 0x57, 0, 8},
4056 {54, 0x57, 0, 10},
4057 {56, 0x58, 0, 0},
4058 {60, 0x58, 0, 4},
4059 {62, 0x58, 0, 6},
4060 {64, 0x58, 0, 8},
4061
4062 /* 802.11 HyperLan 2 */
4063 {100, 0x5b, 0, 8},
4064 {102, 0x5b, 0, 10},
4065 {104, 0x5c, 0, 0},
4066 {108, 0x5c, 0, 4},
4067 {110, 0x5c, 0, 6},
4068 {112, 0x5c, 0, 8},
4069 {116, 0x5d, 0, 0},
4070 {118, 0x5d, 0, 2},
4071 {120, 0x5d, 0, 4},
4072 {124, 0x5d, 0, 8},
4073 {126, 0x5d, 0, 10},
4074 {128, 0x5e, 0, 0},
4075 {132, 0x5e, 0, 4},
4076 {134, 0x5e, 0, 6},
4077 {136, 0x5e, 0, 8},
4078 {140, 0x5f, 0, 0},
4079
4080 /* 802.11 UNII */
4081 {149, 0x5f, 0, 9},
4082 {151, 0x5f, 0, 11},
4083 {153, 0x60, 0, 1},
4084 {157, 0x60, 0, 5},
4085 {159, 0x60, 0, 7},
4086 {161, 0x60, 0, 9},
4087 {165, 0x61, 0, 1},
4088 {167, 0x61, 0, 3},
4089 {169, 0x61, 0, 5},
4090 {171, 0x61, 0, 7},
4091 {173, 0x61, 0, 9},
4da2933f
BZ		 4092};
4093
4094int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4095{
4da2933f
BZ		 4096 struct hw_mode_spec *spec = &rt2x00dev->spec;
4097 struct channel_info *info;
8d1331b3
ID		 4098 char *default_power1;
4099 char *default_power2;
4da2933f
BZ		 4100 unsigned int i;
4101 u16 eeprom;
4102
93b6bd26
GW		 4103 /*
4104 * Disable powersaving as default on PCI devices.
4105 */
cea90e55 4106 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
93b6bd26
GW		 4107 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
4108
4da2933f
BZ		 4109 /*
4110 * Initialize all hw fields.
4111 */
4112 rt2x00dev->hw->flags =
4da2933f
BZ		 4113 IEEE80211_HW_SIGNAL_DBM |
4114 IEEE80211_HW_SUPPORTS_PS |
1df90809
HS		 4115 IEEE80211_HW_PS_NULLFUNC_STACK |
4116 IEEE80211_HW_AMPDU_AGGREGATION;
5a5b6ed6
HS		 4117 /*
4118 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
4119 * unless we are capable of sending the buffered frames out after the
4120 * DTIM transmission using rt2x00lib_beacondone. This will send out
4121 * multicast and broadcast traffic immediately instead of buffering it
4122 * infinitly and thus dropping it after some time.
4123 */
4124 if (!rt2x00_is_usb(rt2x00dev))
4125 rt2x00dev->hw->flags |=
4126 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
4da2933f 4127
4da2933f
BZ		 4128 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
4129 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
4130 rt2x00_eeprom_addr(rt2x00dev,
4131 EEPROM_MAC_ADDR_0));
4132
3f2bee24
HS		 4133 /*
4134 * As rt2800 has a global fallback table we cannot specify
4135 * more then one tx rate per frame but since the hw will
4136 * try several rates (based on the fallback table) we should
ba3b9e5e 4137 * initialize max_report_rates to the maximum number of rates
3f2bee24
HS		 4138 * we are going to try. Otherwise mac80211 will truncate our
4139 * reported tx rates and the rc algortihm will end up with
4140 * incorrect data.
4141 */
ba3b9e5e
HS		 4142 rt2x00dev->hw->max_rates = 1;
4143 rt2x00dev->hw->max_report_rates = 7;
3f2bee24
HS		 4144 rt2x00dev->hw->max_rate_tries = 1;
4145
38c8a566 4146 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4da2933f
BZ		 4147
4148 /*
4149 * Initialize hw_mode information.
4150 */
4151 spec->supported_bands = SUPPORT_BAND_2GHZ;
4152 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
4153
5122d898 4154 if (rt2x00_rf(rt2x00dev, RF2820) ||
55f9321a 4155 rt2x00_rf(rt2x00dev, RF2720)) {
4da2933f
BZ		 4156 spec->num_channels = 14;
4157 spec->channels = rf_vals;
55f9321a
ID		 4158 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
4159 rt2x00_rf(rt2x00dev, RF2750)) {
4da2933f
BZ		 4160 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4161 spec->num_channels = ARRAY_SIZE(rf_vals);
4162 spec->channels = rf_vals;
5122d898
GW		 4163 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
4164 rt2x00_rf(rt2x00dev, RF2020) ||
4165 rt2x00_rf(rt2x00dev, RF3021) ||
f93bc9b3 4166 rt2x00_rf(rt2x00dev, RF3022) ||
adde5882 4167 rt2x00_rf(rt2x00dev, RF3320) ||
aca355b9 4168 rt2x00_rf(rt2x00dev, RF5370) ||
adde5882 4169 rt2x00_rf(rt2x00dev, RF5390)) {
55f9321a
ID		 4170 spec->num_channels = 14;
4171 spec->channels = rf_vals_3x;
4172 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
4173 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4174 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
4175 spec->channels = rf_vals_3x;
4da2933f
BZ		 4176 }
4177
4178 /*
4179 * Initialize HT information.
4180 */
5122d898 4181 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 4182 spec->ht.ht_supported = true;
4183 else
4184 spec->ht.ht_supported = false;
4185
4da2933f 4186 spec->ht.cap =
06443e46 4187 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 4188 IEEE80211_HT_CAP_GRN_FLD |
4189 IEEE80211_HT_CAP_SGI_20 |
aa674631 4190 IEEE80211_HT_CAP_SGI_40;
22cabaa6 4191
38c8a566 4192 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
22cabaa6
HS		 4193 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
4194
aa674631 4195 spec->ht.cap |=
38c8a566 4196 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
aa674631
ID		 4197 IEEE80211_HT_CAP_RX_STBC_SHIFT;
4198
4da2933f
BZ		 4199 spec->ht.ampdu_factor = 3;
4200 spec->ht.ampdu_density = 4;
4201 spec->ht.mcs.tx_params =
4202 IEEE80211_HT_MCS_TX_DEFINED |
4203 IEEE80211_HT_MCS_TX_RX_DIFF |
38c8a566 4204 ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
4da2933f
BZ		 4205 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
4206
38c8a566 4207 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
4da2933f
BZ		 4208 case 3:
4209 spec->ht.mcs.rx_mask[2] = 0xff;
4210 case 2:
4211 spec->ht.mcs.rx_mask[1] = 0xff;
4212 case 1:
4213 spec->ht.mcs.rx_mask[0] = 0xff;
4214 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
4215 break;
4216 }
4217
4218 /*
4219 * Create channel information array
4220 */
baeb2ffa 4221 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4da2933f
BZ		 4222 if (!info)
4223 return -ENOMEM;
4224
4225 spec->channels_info = info;
4226
8d1331b3
ID		 4227 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
4228 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4da2933f
BZ		 4229
4230 for (i = 0; i < 14; i++) {
e90c54b2
RJH		 4231 info[i].default_power1 = default_power1[i];
4232 info[i].default_power2 = default_power2[i];
4da2933f
BZ		 4233 }
4234
4235 if (spec->num_channels > 14) {
8d1331b3
ID		 4236 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
4237 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4da2933f
BZ		 4238
4239 for (i = 14; i < spec->num_channels; i++) {
e90c54b2
RJH		 4240 info[i].default_power1 = default_power1[i];
4241 info[i].default_power2 = default_power2[i];
4da2933f
BZ		 4242 }
4243 }
4244
4245 return 0;
4246}
4247EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
4248
2ce33995
BZ		 4249/*
4250 * IEEE80211 stack callback functions.
4251 */
e783619e
HS		 4252void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
4253 u16 *iv16)
2ce33995
BZ		 4254{
4255 struct rt2x00_dev *rt2x00dev = hw->priv;
4256 struct mac_iveiv_entry iveiv_entry;
4257 u32 offset;
4258
4259 offset = MAC_IVEIV_ENTRY(hw_key_idx);
4260 rt2800_register_multiread(rt2x00dev, offset,
4261 &iveiv_entry, sizeof(iveiv_entry));
4262
855da5e0
JL		 4263 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
4264 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995 4265}
e783619e 4266EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
2ce33995 4267
e783619e 4268int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2ce33995
BZ		 4269{
4270 struct rt2x00_dev *rt2x00dev = hw->priv;
4271 u32 reg;
4272 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
4273
4274 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4275 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
4276 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4277
4278 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
4279 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
4280 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4281
4282 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
4283 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
4284 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4285
4286 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4287 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
4288 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4289
4290 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4291 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
4292 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4293
4294 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4295 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
4296 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4297
4298 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4299 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
4300 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4301
4302 return 0;
4303}
e783619e 4304EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2ce33995 4305
e783619e
HS		 4306int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
4307 const struct ieee80211_tx_queue_params *params)
2ce33995
BZ		 4308{
4309 struct rt2x00_dev *rt2x00dev = hw->priv;
4310 struct data_queue *queue;
4311 struct rt2x00_field32 field;
4312 int retval;
4313 u32 reg;
4314 u32 offset;
4315
4316 /*
4317 * First pass the configuration through rt2x00lib, that will
4318 * update the queue settings and validate the input. After that
4319 * we are free to update the registers based on the value
4320 * in the queue parameter.
4321 */
4322 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
4323 if (retval)
4324 return retval;
4325
4326 /*
4327 * We only need to perform additional register initialization
4328 * for WMM queues/
4329 */
4330 if (queue_idx >= 4)
4331 return 0;
4332
11f818e0 4333 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2ce33995
BZ		 4334
4335 /* Update WMM TXOP register */
4336 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
4337 field.bit_offset = (queue_idx & 1) * 16;
4338 field.bit_mask = 0xffff << field.bit_offset;
4339
4340 rt2800_register_read(rt2x00dev, offset, &reg);
4341 rt2x00_set_field32(&reg, field, queue->txop);
4342 rt2800_register_write(rt2x00dev, offset, reg);
4343
4344 /* Update WMM registers */
4345 field.bit_offset = queue_idx * 4;
4346 field.bit_mask = 0xf << field.bit_offset;
4347
4348 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
4349 rt2x00_set_field32(&reg, field, queue->aifs);
4350 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
4351
4352 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
4353 rt2x00_set_field32(&reg, field, queue->cw_min);
4354 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
4355
4356 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
4357 rt2x00_set_field32(&reg, field, queue->cw_max);
4358 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
4359
4360 /* Update EDCA registers */
4361 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
4362
4363 rt2800_register_read(rt2x00dev, offset, &reg);
4364 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
4365 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
4366 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
4367 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
4368 rt2800_register_write(rt2x00dev, offset, reg);
4369
4370 return 0;
4371}
e783619e 4372EXPORT_SYMBOL_GPL(rt2800_conf_tx);
2ce33995 4373
e783619e 4374u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2ce33995
BZ		 4375{
4376 struct rt2x00_dev *rt2x00dev = hw->priv;
4377 u64 tsf;
4378 u32 reg;
4379
4380 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
4381 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
4382 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
4383 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
4384
4385 return tsf;
4386}
e783619e 4387EXPORT_SYMBOL_GPL(rt2800_get_tsf);
2ce33995 4388
e783619e
HS		 4389int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4390 enum ieee80211_ampdu_mlme_action action,
0b01f030
JB		 4391 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
4392 u8 buf_size)
1df90809 4393{
1df90809
HS		 4394 int ret = 0;
4395
4396 switch (action) {
4397 case IEEE80211_AMPDU_RX_START:
4398 case IEEE80211_AMPDU_RX_STOP:
58ed826e
HS		 4399 /*
4400 * The hw itself takes care of setting up BlockAck mechanisms.
4401 * So, we only have to allow mac80211 to nagotiate a BlockAck
4402 * agreement. Once that is done, the hw will BlockAck incoming
4403 * AMPDUs without further setup.
4404 */
1df90809
HS		 4405 break;
4406 case IEEE80211_AMPDU_TX_START:
4407 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4408 break;
4409 case IEEE80211_AMPDU_TX_STOP:
4410 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4411 break;
4412 case IEEE80211_AMPDU_TX_OPERATIONAL:
4413 break;
4414 default:
4e9e58c6 4415 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
1df90809
HS		 4416 }
4417
4418 return ret;
4419}
e783619e 4420EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
a5ea2f02 4421
977206d7
HS		 4422int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
4423 struct survey_info *survey)
4424{
4425 struct rt2x00_dev *rt2x00dev = hw->priv;
4426 struct ieee80211_conf *conf = &hw->conf;
4427 u32 idle, busy, busy_ext;
4428
4429 if (idx != 0)
4430 return -ENOENT;
4431
4432 survey->channel = conf->channel;
4433
4434 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
4435 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
4436 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
4437
4438 if (idle || busy) {
4439 survey->filled = SURVEY_INFO_CHANNEL_TIME |
4440 SURVEY_INFO_CHANNEL_TIME_BUSY |
4441 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
4442
4443 survey->channel_time = (idle + busy) / 1000;
4444 survey->channel_time_busy = busy / 1000;
4445 survey->channel_time_ext_busy = busy_ext / 1000;
4446 }
4447
4448 return 0;
4449
4450}
4451EXPORT_SYMBOL_GPL(rt2800_get_survey);
4452
a5ea2f02
ID		 4453MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
4454MODULE_VERSION(DRV_VERSION);
4455MODULE_DESCRIPTION("Ralink RT2800 library");
4456MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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