projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ath9k: make ath9k_hw_keysetmac static
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
CommitLineData
89297425 1/*
a5ea2f02 2 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 3 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 4 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 5
9c9a0d14 6 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 7 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
8 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
9 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
10 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
11 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
12 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 13 <http://rt2x00.serialmonkey.com>
14
15 This program is free software; you can redistribute it and/or modify
16 it under the terms of the GNU General Public License as published by
17 the Free Software Foundation; either version 2 of the License, or
18 (at your option) any later version.
19
20 This program is distributed in the hope that it will be useful,
21 but WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 GNU General Public License for more details.
24
25 You should have received a copy of the GNU General Public License
26 along with this program; if not, write to the
27 Free Software Foundation, Inc.,
28 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31/*
32 Module: rt2800lib
33 Abstract: rt2800 generic device routines.
34 */
35
36#include <linux/kernel.h>
37#include <linux/module.h>
5a0e3ad6 38#include <linux/slab.h>
89297425
BZ		 39
40#include "rt2x00.h"
41#include "rt2800lib.h"
42#include "rt2800.h"
43
89297425
BZ		 44/*
45 * Register access.
46 * All access to the CSR registers will go through the methods
47 * rt2800_register_read and rt2800_register_write.
48 * BBP and RF register require indirect register access,
49 * and use the CSR registers BBPCSR and RFCSR to achieve this.
50 * These indirect registers work with busy bits,
51 * and we will try maximal REGISTER_BUSY_COUNT times to access
52 * the register while taking a REGISTER_BUSY_DELAY us delay
53 * between each attampt. When the busy bit is still set at that time,
54 * the access attempt is considered to have failed,
55 * and we will print an error.
56 * The _lock versions must be used if you already hold the csr_mutex
57 */
58#define WAIT_FOR_BBP(__dev, __reg) \
59 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
60#define WAIT_FOR_RFCSR(__dev, __reg) \
61 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RF(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
64#define WAIT_FOR_MCU(__dev, __reg) \
65 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
66 H2M_MAILBOX_CSR_OWNER, (__reg))
67
baff8006
HS		 68static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
69{
70 /* check for rt2872 on SoC */
71 if (!rt2x00_is_soc(rt2x00dev) ||
72 !rt2x00_rt(rt2x00dev, RT2872))
73 return false;
74
75 /* we know for sure that these rf chipsets are used on rt305x boards */
76 if (rt2x00_rf(rt2x00dev, RF3020) ||
77 rt2x00_rf(rt2x00dev, RF3021) ||
78 rt2x00_rf(rt2x00dev, RF3022))
79 return true;
80
81 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
82 return false;
83}
84
fcf51541
BZ		 85static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
86 const unsigned int word, const u8 value)
89297425
BZ		 87{
88 u32 reg;
89
90 mutex_lock(&rt2x00dev->csr_mutex);
91
92 /*
93 * Wait until the BBP becomes available, afterwards we
94 * can safely write the new data into the register.
95 */
96 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
97 reg = 0;
98 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
99 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
cea90e55 102 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
89297425
BZ		 103 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
104
105 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
106 }
107
108 mutex_unlock(&rt2x00dev->csr_mutex);
109}
89297425 110
fcf51541
BZ		 111static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
112 const unsigned int word, u8 *value)
89297425
BZ		 113{
114 u32 reg;
115
116 mutex_lock(&rt2x00dev->csr_mutex);
117
118 /*
119 * Wait until the BBP becomes available, afterwards we
120 * can safely write the read request into the register.
121 * After the data has been written, we wait until hardware
122 * returns the correct value, if at any time the register
123 * doesn't become available in time, reg will be 0xffffffff
124 * which means we return 0xff to the caller.
125 */
126 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
127 reg = 0;
128 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
cea90e55 131 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
89297425
BZ		 132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142}
89297425 143
fcf51541
BZ		 144static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
89297425
BZ		 146{
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166}
89297425 167
fcf51541
BZ		 168static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
89297425
BZ		 170{
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197}
89297425 198
fcf51541
BZ		 199static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
89297425
BZ		 201{
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222}
89297425
BZ		 223
224void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
225 const u8 command, const u8 token,
226 const u8 arg0, const u8 arg1)
227{
228 u32 reg;
229
ee303e54 230 /*
cea90e55 231 * SOC devices don't support MCU requests.
ee303e54 232 */
cea90e55 233 if (rt2x00_is_soc(rt2x00dev))
ee303e54 234 return;
89297425
BZ		 235
236 mutex_lock(&rt2x00dev->csr_mutex);
237
238 /*
239 * Wait until the MCU becomes available, afterwards we
240 * can safely write the new data into the register.
241 */
242 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
243 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
244 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
245 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
246 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
247 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
248
249 reg = 0;
250 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
251 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
252 }
253
254 mutex_unlock(&rt2x00dev->csr_mutex);
255}
256EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 257
67a4c1e2
GW		 258int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
259{
260 unsigned int i;
261 u32 reg;
262
263 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
264 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
265 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
266 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
267 return 0;
268
269 msleep(1);
270 }
271
272 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
273 return -EACCES;
274}
275EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
276
0b8004aa 277void rt2800_write_txwi(__le32 *txwi, struct txentry_desc *txdesc)
59679b91 278{
59679b91
GW		 279 u32 word;
280
281 /*
282 * Initialize TX Info descriptor
283 */
284 rt2x00_desc_read(txwi, 0, &word);
285 rt2x00_set_field32(&word, TXWI_W0_FRAG,
286 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
287 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
288 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
289 rt2x00_set_field32(&word, TXWI_W0_TS,
290 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
291 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
292 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
293 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
294 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop);
295 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
296 rt2x00_set_field32(&word, TXWI_W0_BW,
297 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
298 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
299 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
300 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
301 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
302 rt2x00_desc_write(txwi, 0, word);
303
304 rt2x00_desc_read(txwi, 1, &word);
305 rt2x00_set_field32(&word, TXWI_W1_ACK,
306 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
307 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
308 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
309 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
310 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
311 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
312 txdesc->key_idx : 0xff);
313 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
314 txdesc->length);
315 rt2x00_set_field32(&word, TXWI_W1_PACKETID, txdesc->queue + 1);
316 rt2x00_desc_write(txwi, 1, word);
317
318 /*
319 * Always write 0 to IV/EIV fields, hardware will insert the IV
320 * from the IVEIV register when TXD_W3_WIV is set to 0.
321 * When TXD_W3_WIV is set to 1 it will use the IV data
322 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
323 * crypto entry in the registers should be used to encrypt the frame.
324 */
325 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
326 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
327}
328EXPORT_SYMBOL_GPL(rt2800_write_txwi);
329
2de64dd2
GW		 330void rt2800_process_rxwi(struct sk_buff *skb, struct rxdone_entry_desc *rxdesc)
331{
332 __le32 *rxwi = (__le32 *) skb->data;
333 u32 word;
334
335 rt2x00_desc_read(rxwi, 0, &word);
336
337 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
338 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
339
340 rt2x00_desc_read(rxwi, 1, &word);
341
342 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
343 rxdesc->flags |= RX_FLAG_SHORT_GI;
344
345 if (rt2x00_get_field32(word, RXWI_W1_BW))
346 rxdesc->flags |= RX_FLAG_40MHZ;
347
348 /*
349 * Detect RX rate, always use MCS as signal type.
350 */
351 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
352 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
353 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
354
355 /*
356 * Mask of 0x8 bit to remove the short preamble flag.
357 */
358 if (rxdesc->rate_mode == RATE_MODE_CCK)
359 rxdesc->signal &= ~0x8;
360
361 rt2x00_desc_read(rxwi, 2, &word);
362
363 rxdesc->rssi =
364 (rt2x00_get_field32(word, RXWI_W2_RSSI0) +
365 rt2x00_get_field32(word, RXWI_W2_RSSI1)) / 2;
366
367 /*
368 * Remove RXWI descriptor from start of buffer.
369 */
370 skb_pull(skb, RXWI_DESC_SIZE);
371}
372EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
373
f0194b2d
GW		 374void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
375{
376 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
377 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
378 unsigned int beacon_base;
379 u32 reg;
380
381 /*
382 * Disable beaconing while we are reloading the beacon data,
383 * otherwise we might be sending out invalid data.
384 */
385 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
386 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
387 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
388
389 /*
390 * Add space for the TXWI in front of the skb.
391 */
392 skb_push(entry->skb, TXWI_DESC_SIZE);
393 memset(entry->skb, 0, TXWI_DESC_SIZE);
394
395 /*
396 * Register descriptor details in skb frame descriptor.
397 */
398 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
399 skbdesc->desc = entry->skb->data;
400 skbdesc->desc_len = TXWI_DESC_SIZE;
401
402 /*
403 * Add the TXWI for the beacon to the skb.
404 */
405 rt2800_write_txwi((__le32 *)entry->skb->data, txdesc);
406
407 /*
408 * Dump beacon to userspace through debugfs.
409 */
410 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
411
412 /*
413 * Write entire beacon with TXWI to register.
414 */
415 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
416 rt2800_register_multiwrite(rt2x00dev, beacon_base,
417 entry->skb->data, entry->skb->len);
418
419 /*
420 * Enable beaconing again.
421 */
422 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
423 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
424 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
425 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
426
427 /*
428 * Clean up beacon skb.
429 */
430 dev_kfree_skb_any(entry->skb);
431 entry->skb = NULL;
432}
433EXPORT_SYMBOL(rt2800_write_beacon);
434
f4450616
BZ		 435#ifdef CONFIG_RT2X00_LIB_DEBUGFS
436const struct rt2x00debug rt2800_rt2x00debug = {
437 .owner = THIS_MODULE,
438 .csr = {
439 .read = rt2800_register_read,
440 .write = rt2800_register_write,
441 .flags = RT2X00DEBUGFS_OFFSET,
442 .word_base = CSR_REG_BASE,
443 .word_size = sizeof(u32),
444 .word_count = CSR_REG_SIZE / sizeof(u32),
445 },
446 .eeprom = {
447 .read = rt2x00_eeprom_read,
448 .write = rt2x00_eeprom_write,
449 .word_base = EEPROM_BASE,
450 .word_size = sizeof(u16),
451 .word_count = EEPROM_SIZE / sizeof(u16),
452 },
453 .bbp = {
454 .read = rt2800_bbp_read,
455 .write = rt2800_bbp_write,
456 .word_base = BBP_BASE,
457 .word_size = sizeof(u8),
458 .word_count = BBP_SIZE / sizeof(u8),
459 },
460 .rf = {
461 .read = rt2x00_rf_read,
462 .write = rt2800_rf_write,
463 .word_base = RF_BASE,
464 .word_size = sizeof(u32),
465 .word_count = RF_SIZE / sizeof(u32),
466 },
467};
468EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
469#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
470
471int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
472{
473 u32 reg;
474
475 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
476 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
477}
478EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
479
480#ifdef CONFIG_RT2X00_LIB_LEDS
481static void rt2800_brightness_set(struct led_classdev *led_cdev,
482 enum led_brightness brightness)
483{
484 struct rt2x00_led *led =
485 container_of(led_cdev, struct rt2x00_led, led_dev);
486 unsigned int enabled = brightness != LED_OFF;
487 unsigned int bg_mode =
488 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
489 unsigned int polarity =
490 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
491 EEPROM_FREQ_LED_POLARITY);
492 unsigned int ledmode =
493 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
494 EEPROM_FREQ_LED_MODE);
495
496 if (led->type == LED_TYPE_RADIO) {
497 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
498 enabled ? 0x20 : 0);
499 } else if (led->type == LED_TYPE_ASSOC) {
500 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
501 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
502 } else if (led->type == LED_TYPE_QUALITY) {
503 /*
504 * The brightness is divided into 6 levels (0 - 5),
505 * The specs tell us the following levels:
506 * 0, 1 ,3, 7, 15, 31
507 * to determine the level in a simple way we can simply
508 * work with bitshifting:
509 * (1 << level) - 1
510 */
511 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
512 (1 << brightness / (LED_FULL / 6)) - 1,
513 polarity);
514 }
515}
516
517static int rt2800_blink_set(struct led_classdev *led_cdev,
518 unsigned long *delay_on, unsigned long *delay_off)
519{
520 struct rt2x00_led *led =
521 container_of(led_cdev, struct rt2x00_led, led_dev);
522 u32 reg;
523
524 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
525 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
526 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
f4450616
BZ		 527 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
528
529 return 0;
530}
531
b3579d6a 532static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 533 struct rt2x00_led *led, enum led_type type)
534{
535 led->rt2x00dev = rt2x00dev;
536 led->type = type;
537 led->led_dev.brightness_set = rt2800_brightness_set;
538 led->led_dev.blink_set = rt2800_blink_set;
539 led->flags = LED_INITIALIZED;
540}
f4450616
BZ		 541#endif /* CONFIG_RT2X00_LIB_LEDS */
542
543/*
544 * Configuration handlers.
545 */
546static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
547 struct rt2x00lib_crypto *crypto,
548 struct ieee80211_key_conf *key)
549{
550 struct mac_wcid_entry wcid_entry;
551 struct mac_iveiv_entry iveiv_entry;
552 u32 offset;
553 u32 reg;
554
555 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
556
e4a0ab34
ID		 557 if (crypto->cmd == SET_KEY) {
558 rt2800_register_read(rt2x00dev, offset, &reg);
559 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
560 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
561 /*
562 * Both the cipher as the BSS Idx numbers are split in a main
563 * value of 3 bits, and a extended field for adding one additional
564 * bit to the value.
565 */
566 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
567 (crypto->cipher & 0x7));
568 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
569 (crypto->cipher & 0x8) >> 3);
570 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
571 (crypto->bssidx & 0x7));
572 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
573 (crypto->bssidx & 0x8) >> 3);
574 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
575 rt2800_register_write(rt2x00dev, offset, reg);
576 } else {
577 rt2800_register_write(rt2x00dev, offset, 0);
578 }
f4450616
BZ		 579
580 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
581
582 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
583 if ((crypto->cipher == CIPHER_TKIP) ||
584 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
585 (crypto->cipher == CIPHER_AES))
586 iveiv_entry.iv[3] |= 0x20;
587 iveiv_entry.iv[3] |= key->keyidx << 6;
588 rt2800_register_multiwrite(rt2x00dev, offset,
589 &iveiv_entry, sizeof(iveiv_entry));
590
591 offset = MAC_WCID_ENTRY(key->hw_key_idx);
592
593 memset(&wcid_entry, 0, sizeof(wcid_entry));
594 if (crypto->cmd == SET_KEY)
595 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
596 rt2800_register_multiwrite(rt2x00dev, offset,
597 &wcid_entry, sizeof(wcid_entry));
598}
599
600int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
601 struct rt2x00lib_crypto *crypto,
602 struct ieee80211_key_conf *key)
603{
604 struct hw_key_entry key_entry;
605 struct rt2x00_field32 field;
606 u32 offset;
607 u32 reg;
608
609 if (crypto->cmd == SET_KEY) {
610 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
611
612 memcpy(key_entry.key, crypto->key,
613 sizeof(key_entry.key));
614 memcpy(key_entry.tx_mic, crypto->tx_mic,
615 sizeof(key_entry.tx_mic));
616 memcpy(key_entry.rx_mic, crypto->rx_mic,
617 sizeof(key_entry.rx_mic));
618
619 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
620 rt2800_register_multiwrite(rt2x00dev, offset,
621 &key_entry, sizeof(key_entry));
622 }
623
624 /*
625 * The cipher types are stored over multiple registers
626 * starting with SHARED_KEY_MODE_BASE each word will have
627 * 32 bits and contains the cipher types for 2 bssidx each.
628 * Using the correct defines correctly will cause overhead,
629 * so just calculate the correct offset.
630 */
631 field.bit_offset = 4 * (key->hw_key_idx % 8);
632 field.bit_mask = 0x7 << field.bit_offset;
633
634 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
635
636 rt2800_register_read(rt2x00dev, offset, &reg);
637 rt2x00_set_field32(&reg, field,
638 (crypto->cmd == SET_KEY) * crypto->cipher);
639 rt2800_register_write(rt2x00dev, offset, reg);
640
641 /*
642 * Update WCID information
643 */
644 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
645
646 return 0;
647}
648EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
649
650int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
651 struct rt2x00lib_crypto *crypto,
652 struct ieee80211_key_conf *key)
653{
654 struct hw_key_entry key_entry;
655 u32 offset;
656
657 if (crypto->cmd == SET_KEY) {
658 /*
659 * 1 pairwise key is possible per AID, this means that the AID
660 * equals our hw_key_idx. Make sure the WCID starts _after_ the
661 * last possible shared key entry.
662 */
663 if (crypto->aid > (256 - 32))
664 return -ENOSPC;
665
666 key->hw_key_idx = 32 + crypto->aid;
667
668 memcpy(key_entry.key, crypto->key,
669 sizeof(key_entry.key));
670 memcpy(key_entry.tx_mic, crypto->tx_mic,
671 sizeof(key_entry.tx_mic));
672 memcpy(key_entry.rx_mic, crypto->rx_mic,
673 sizeof(key_entry.rx_mic));
674
675 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
676 rt2800_register_multiwrite(rt2x00dev, offset,
677 &key_entry, sizeof(key_entry));
678 }
679
680 /*
681 * Update WCID information
682 */
683 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
684
685 return 0;
686}
687EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
688
689void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
690 const unsigned int filter_flags)
691{
692 u32 reg;
693
694 /*
695 * Start configuration steps.
696 * Note that the version error will always be dropped
697 * and broadcast frames will always be accepted since
698 * there is no filter for it at this time.
699 */
700 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
701 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
702 !(filter_flags & FIF_FCSFAIL));
703 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
704 !(filter_flags & FIF_PLCPFAIL));
705 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
706 !(filter_flags & FIF_PROMISC_IN_BSS));
707 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
708 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
709 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
710 !(filter_flags & FIF_ALLMULTI));
711 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
712 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
713 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
714 !(filter_flags & FIF_CONTROL));
715 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
716 !(filter_flags & FIF_CONTROL));
717 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
718 !(filter_flags & FIF_CONTROL));
719 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
720 !(filter_flags & FIF_CONTROL));
721 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
722 !(filter_flags & FIF_CONTROL));
723 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
724 !(filter_flags & FIF_PSPOLL));
725 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
726 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
727 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
728 !(filter_flags & FIF_CONTROL));
729 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
730}
731EXPORT_SYMBOL_GPL(rt2800_config_filter);
732
733void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
734 struct rt2x00intf_conf *conf, const unsigned int flags)
735{
736 unsigned int beacon_base;
737 u32 reg;
738
739 if (flags & CONFIG_UPDATE_TYPE) {
740 /*
741 * Clear current synchronisation setup.
742 * For the Beacon base registers we only need to clear
743 * the first byte since that byte contains the VALID and OWNER
744 * bits which (when set to 0) will invalidate the entire beacon.
745 */
746 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
747 rt2800_register_write(rt2x00dev, beacon_base, 0);
748
749 /*
750 * Enable synchronisation.
751 */
752 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
753 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
754 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
6a62e5ef
JB		 755 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
756 (conf->sync == TSF_SYNC_BEACON));
f4450616
BZ		 757 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
758 }
759
760 if (flags & CONFIG_UPDATE_MAC) {
761 reg = le32_to_cpu(conf->mac[1]);
762 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
763 conf->mac[1] = cpu_to_le32(reg);
764
765 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
766 conf->mac, sizeof(conf->mac));
767 }
768
769 if (flags & CONFIG_UPDATE_BSSID) {
770 reg = le32_to_cpu(conf->bssid[1]);
771 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
772 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
773 conf->bssid[1] = cpu_to_le32(reg);
774
775 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
776 conf->bssid, sizeof(conf->bssid));
777 }
778}
779EXPORT_SYMBOL_GPL(rt2800_config_intf);
780
781void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
782{
783 u32 reg;
784
f4450616
BZ		 785 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
786 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
787 !!erp->short_preamble);
788 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
789 !!erp->short_preamble);
790 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
791
792 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
793 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
794 erp->cts_protection ? 2 : 0);
795 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
796
797 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
798 erp->basic_rates);
799 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
800
801 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
802 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
f4450616
BZ		 803 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
804
805 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
f4450616 806 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
f4450616
BZ		 807 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
808
809 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
810 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
811 erp->beacon_int * 16);
812 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
813}
814EXPORT_SYMBOL_GPL(rt2800_config_erp);
815
816void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
817{
818 u8 r1;
819 u8 r3;
820
821 rt2800_bbp_read(rt2x00dev, 1, &r1);
822 rt2800_bbp_read(rt2x00dev, 3, &r3);
823
824 /*
825 * Configure the TX antenna.
826 */
827 switch ((int)ant->tx) {
828 case 1:
829 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
cea90e55 830 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
f4450616
BZ		 831 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
832 break;
833 case 2:
834 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
835 break;
836 case 3:
837 /* Do nothing */
838 break;
839 }
840
841 /*
842 * Configure the RX antenna.
843 */
844 switch ((int)ant->rx) {
845 case 1:
846 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
847 break;
848 case 2:
849 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
850 break;
851 case 3:
852 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
853 break;
854 }
855
856 rt2800_bbp_write(rt2x00dev, 3, r3);
857 rt2800_bbp_write(rt2x00dev, 1, r1);
858}
859EXPORT_SYMBOL_GPL(rt2800_config_ant);
860
861static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
862 struct rt2x00lib_conf *libconf)
863{
864 u16 eeprom;
865 short lna_gain;
866
867 if (libconf->rf.channel <= 14) {
868 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
869 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
870 } else if (libconf->rf.channel <= 64) {
871 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
872 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
873 } else if (libconf->rf.channel <= 128) {
874 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
875 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
876 } else {
877 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
878 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
879 }
880
881 rt2x00dev->lna_gain = lna_gain;
882}
883
06855ef4
GW		 884static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
885 struct ieee80211_conf *conf,
886 struct rf_channel *rf,
887 struct channel_info *info)
f4450616
BZ		 888{
889 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
890
891 if (rt2x00dev->default_ant.tx == 1)
892 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
893
894 if (rt2x00dev->default_ant.rx == 1) {
895 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
896 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
897 } else if (rt2x00dev->default_ant.rx == 2)
898 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
899
900 if (rf->channel > 14) {
901 /*
902 * When TX power is below 0, we should increase it by 7 to
903 * make it a positive value (Minumum value is -7).
904 * However this means that values between 0 and 7 have
905 * double meaning, and we should set a 7DBm boost flag.
906 */
907 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
908 (info->tx_power1 >= 0));
909
910 if (info->tx_power1 < 0)
911 info->tx_power1 += 7;
912
913 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
914 TXPOWER_A_TO_DEV(info->tx_power1));
915
916 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
917 (info->tx_power2 >= 0));
918
919 if (info->tx_power2 < 0)
920 info->tx_power2 += 7;
921
922 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
923 TXPOWER_A_TO_DEV(info->tx_power2));
924 } else {
925 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
926 TXPOWER_G_TO_DEV(info->tx_power1));
927 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
928 TXPOWER_G_TO_DEV(info->tx_power2));
929 }
930
931 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
932
933 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
934 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
935 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
936 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
937
938 udelay(200);
939
940 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
941 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
942 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
943 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
944
945 udelay(200);
946
947 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
948 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
949 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
950 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
951}
952
06855ef4
GW		 953static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
954 struct ieee80211_conf *conf,
955 struct rf_channel *rf,
956 struct channel_info *info)
f4450616
BZ		 957{
958 u8 rfcsr;
959
960 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
41a26170 961 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
f4450616
BZ		 962
963 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 964 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 965 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
966
967 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
968 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
969 TXPOWER_G_TO_DEV(info->tx_power1));
970 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
971
5a673964
HS		 972 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
973 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
974 TXPOWER_G_TO_DEV(info->tx_power2));
975 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
976
f4450616
BZ		 977 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
978 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
979 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
980
981 rt2800_rfcsr_write(rt2x00dev, 24,
982 rt2x00dev->calibration[conf_is_ht40(conf)]);
983
71976907 984 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 985 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 986 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
f4450616
BZ		 987}
988
989static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
990 struct ieee80211_conf *conf,
991 struct rf_channel *rf,
992 struct channel_info *info)
993{
994 u32 reg;
995 unsigned int tx_pin;
996 u8 bbp;
997
06855ef4
GW		 998 if (rt2x00_rf(rt2x00dev, RF2020) ||
999 rt2x00_rf(rt2x00dev, RF3020) ||
1000 rt2x00_rf(rt2x00dev, RF3021) ||
1001 rt2x00_rf(rt2x00dev, RF3022))
1002 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
fa6f632f 1003 else
06855ef4 1004 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
f4450616
BZ		 1005
1006 /*
1007 * Change BBP settings
1008 */
1009 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1010 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1011 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1012 rt2800_bbp_write(rt2x00dev, 86, 0);
1013
1014 if (rf->channel <= 14) {
1015 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1016 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1017 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1018 } else {
1019 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1020 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1021 }
1022 } else {
1023 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1024
1025 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1026 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1027 else
1028 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1029 }
1030
1031 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 1032 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1033 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1034 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1035 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1036
1037 tx_pin = 0;
1038
1039 /* Turn on unused PA or LNA when not using 1T or 1R */
1040 if (rt2x00dev->default_ant.tx != 1) {
1041 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1042 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1043 }
1044
1045 /* Turn on unused PA or LNA when not using 1T or 1R */
1046 if (rt2x00dev->default_ant.rx != 1) {
1047 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1048 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1049 }
1050
1051 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1052 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1053 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1054 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1055 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1056 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1057
1058 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1059
1060 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1061 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1062 rt2800_bbp_write(rt2x00dev, 4, bbp);
1063
1064 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 1065 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1066 rt2800_bbp_write(rt2x00dev, 3, bbp);
1067
8d0c9b65 1068 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 1069 if (conf_is_ht40(conf)) {
1070 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1071 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1072 rt2800_bbp_write(rt2x00dev, 73, 0x16);
1073 } else {
1074 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1075 rt2800_bbp_write(rt2x00dev, 70, 0x08);
1076 rt2800_bbp_write(rt2x00dev, 73, 0x11);
1077 }
1078 }
1079
1080 msleep(1);
1081}
1082
1083static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
1084 const int txpower)
1085{
1086 u32 reg;
1087 u32 value = TXPOWER_G_TO_DEV(txpower);
1088 u8 r1;
1089
1090 rt2800_bbp_read(rt2x00dev, 1, &r1);
a3f84ca4 1091 rt2x00_set_field8(&r1, BBP1_TX_POWER, 0);
f4450616
BZ		 1092 rt2800_bbp_write(rt2x00dev, 1, r1);
1093
1094 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
1095 rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
1096 rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
1097 rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
1098 rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
1099 rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
1100 rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
1101 rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
1102 rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
1103 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
1104
1105 rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
1106 rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
1107 rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
1108 rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
1109 rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
1110 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
1111 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
1112 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
1113 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
1114 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
1115
1116 rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
1117 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
1118 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
1119 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
1120 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
1121 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
1122 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
1123 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
1124 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
1125 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
1126
1127 rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
1128 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
1129 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
1130 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
1131 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
1132 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
1133 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
1134 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
1135 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
1136 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
1137
1138 rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
1139 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
1140 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
1141 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
1142 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
1143 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
1144}
1145
1146static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1147 struct rt2x00lib_conf *libconf)
1148{
1149 u32 reg;
1150
1151 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1152 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1153 libconf->conf->short_frame_max_tx_count);
1154 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1155 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 1156 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1157}
1158
1159static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
1160 struct rt2x00lib_conf *libconf)
1161{
1162 enum dev_state state =
1163 (libconf->conf->flags & IEEE80211_CONF_PS) ?
1164 STATE_SLEEP : STATE_AWAKE;
1165 u32 reg;
1166
1167 if (state == STATE_SLEEP) {
1168 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1169
1170 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1171 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1172 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1173 libconf->conf->listen_interval - 1);
1174 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1175 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1176
1177 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1178 } else {
f4450616
BZ		 1179 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1180 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1181 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1182 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1183 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 1184
1185 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 1186 }
1187}
1188
1189void rt2800_config(struct rt2x00_dev *rt2x00dev,
1190 struct rt2x00lib_conf *libconf,
1191 const unsigned int flags)
1192{
1193 /* Always recalculate LNA gain before changing configuration */
1194 rt2800_config_lna_gain(rt2x00dev, libconf);
1195
1196 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1197 rt2800_config_channel(rt2x00dev, libconf->conf,
1198 &libconf->rf, &libconf->channel);
1199 if (flags & IEEE80211_CONF_CHANGE_POWER)
1200 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1201 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1202 rt2800_config_retry_limit(rt2x00dev, libconf);
1203 if (flags & IEEE80211_CONF_CHANGE_PS)
1204 rt2800_config_ps(rt2x00dev, libconf);
1205}
1206EXPORT_SYMBOL_GPL(rt2800_config);
1207
1208/*
1209 * Link tuning
1210 */
1211void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1212{
1213 u32 reg;
1214
1215 /*
1216 * Update FCS error count from register.
1217 */
1218 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1219 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1220}
1221EXPORT_SYMBOL_GPL(rt2800_link_stats);
1222
1223static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1224{
1225 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
d5385bfc 1226 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 1227 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1228 rt2x00_rt(rt2x00dev, RT3090) ||
1229 rt2x00_rt(rt2x00dev, RT3390))
f4450616
BZ		 1230 return 0x1c + (2 * rt2x00dev->lna_gain);
1231 else
1232 return 0x2e + rt2x00dev->lna_gain;
1233 }
1234
1235 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1236 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1237 else
1238 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1239}
1240
1241static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1242 struct link_qual *qual, u8 vgc_level)
1243{
1244 if (qual->vgc_level != vgc_level) {
1245 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1246 qual->vgc_level = vgc_level;
1247 qual->vgc_level_reg = vgc_level;
1248 }
1249}
1250
1251void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1252{
1253 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1254}
1255EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1256
1257void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1258 const u32 count)
1259{
8d0c9b65 1260 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616
BZ		 1261 return;
1262
1263 /*
1264 * When RSSI is better then -80 increase VGC level with 0x10
1265 */
1266 rt2800_set_vgc(rt2x00dev, qual,
1267 rt2800_get_default_vgc(rt2x00dev) +
1268 ((qual->rssi > -80) * 0x10));
1269}
1270EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 1271
1272/*
1273 * Initialization functions.
1274 */
1275int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1276{
1277 u32 reg;
d5385bfc 1278 u16 eeprom;
fcf51541 1279 unsigned int i;
e3a896b9 1280 int ret;
fcf51541 1281
a9dce149
GW		 1282 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1283 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1284 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1285 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1286 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1287 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1288 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1289
e3a896b9
GW		 1290 ret = rt2800_drv_init_registers(rt2x00dev);
1291 if (ret)
1292 return ret;
fcf51541
BZ		 1293
1294 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1295 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1296 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1297 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1298 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1299 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1300
1301 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1302 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1303 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1304 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1305 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1306 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1307
1308 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1309 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1310
1311 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1312
1313 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1314 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1315 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1316 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1317 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1318 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1319 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1320 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1321
a9dce149
GW		 1322 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
1323
1324 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1325 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
1326 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1327 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1328
64522957 1329 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1330 rt2x00_rt(rt2x00dev, RT3090) ||
1331 rt2x00_rt(rt2x00dev, RT3390)) {
fcf51541
BZ		 1332 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1333 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 1334 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 1335 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1336 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
d5385bfc
GW		 1337 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1338 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1339 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1340 0x0000002c);
1341 else
1342 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1343 0x0000000f);
1344 } else {
1345 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1346 }
d5385bfc 1347 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 1348 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 1349
1350 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1351 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1352 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
1353 } else {
1354 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1355 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1356 }
c295a81d
HS		 1357 } else if (rt2800_is_305x_soc(rt2x00dev)) {
1358 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1359 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1360 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
fcf51541
BZ		 1361 } else {
1362 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1363 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1364 }
1365
1366 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1367 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1368 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1369 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1370 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1371 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1372 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1373 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1374 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1375 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1376
1377 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1378 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 1379 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 1380 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1381 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1382
1383 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1384 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 1385 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 1386 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 1387 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 1388 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1389 else
1390 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1391 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1392 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1393 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1394
a9dce149
GW		 1395 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1396 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
1397 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
1398 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
1399 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
1400 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
1401 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
1402 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
1403 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1404
fcf51541
BZ		 1405 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1406
a9dce149
GW		 1407 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1408 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
1409 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
1410 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1411 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1412 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1413 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1414 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1415
fcf51541
BZ		 1416 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1417 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 1418 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 1419 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1420 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 1421 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 1422 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1423 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1424 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1425
1426 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 1427 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541
BZ		 1428 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1429 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1430 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1431 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1432 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 1433 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 1434 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 1435 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1436 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 1437 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1438
1439 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 1440 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541
BZ		 1441 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1442 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1443 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1444 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1445 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 1446 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 1447 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 1448 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1449 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 1450 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1451
1452 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1453 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1454 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1455 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1456 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1457 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1458 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1459 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1460 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1461 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 1462 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1463 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1464
1465 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1466 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
a9dce149
GW		 1467 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL,
1468 !rt2x00_is_usb(rt2x00dev));
fcf51541
BZ		 1469 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1470 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1471 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1472 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1473 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1474 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1475 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 1476 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1477 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1478
1479 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1480 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1481 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1482 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1483 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1484 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1485 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1486 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1487 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1488 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 1489 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1490 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1491
1492 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1493 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1494 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1495 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1496 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1497 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1498 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1499 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1500 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1501 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 1502 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1503 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1504
cea90e55 1505 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 1506 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1507
1508 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1509 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1510 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1511 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1512 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1513 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1514 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1515 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1516 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1517 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1518 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1519 }
1520
1521 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1522 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1523
1524 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1525 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1526 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1527 IEEE80211_MAX_RTS_THRESHOLD);
1528 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1529 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1530
1531 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 1532
a21c2ab4
HS		 1533 /*
1534 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
1535 * time should be set to 16. However, the original Ralink driver uses
1536 * 16 for both and indeed using a value of 10 for CCK SIFS results in
1537 * connection problems with 11g + CTS protection. Hence, use the same
1538 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
1539 */
a9dce149 1540 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 1541 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
1542 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 1543 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
1544 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
1545 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
1546 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1547
fcf51541
BZ		 1548 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1549
1550 /*
1551 * ASIC will keep garbage value after boot, clear encryption keys.
1552 */
1553 for (i = 0; i < 4; i++)
1554 rt2800_register_write(rt2x00dev,
1555 SHARED_KEY_MODE_ENTRY(i), 0);
1556
1557 for (i = 0; i < 256; i++) {
1558 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1559 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1560 wcid, sizeof(wcid));
1561
1562 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1563 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1564 }
1565
1566 /*
1567 * Clear all beacons
1568 * For the Beacon base registers we only need to clear
1569 * the first byte since that byte contains the VALID and OWNER
1570 * bits which (when set to 0) will invalidate the entire beacon.
1571 */
1572 rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1573 rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1574 rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1575 rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1576 rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1577 rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1578 rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1579 rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1580
cea90e55 1581 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 1582 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
1583 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
1584 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 1585 }
1586
1587 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1588 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1589 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1590 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1591 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1592 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1593 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1594 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1595 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1596 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1597
1598 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1599 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1600 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1601 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1602 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1603 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1604 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1605 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1606 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1607 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1608
1609 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1610 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1611 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1612 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1613 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1614 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1615 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1616 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1617 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1618 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1619
1620 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1621 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1622 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1623 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1624 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1625 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1626
1627 /*
1628 * We must clear the error counters.
1629 * These registers are cleared on read,
1630 * so we may pass a useless variable to store the value.
1631 */
1632 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1633 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1634 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1635 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1636 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1637 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1638
1639 return 0;
1640}
1641EXPORT_SYMBOL_GPL(rt2800_init_registers);
1642
1643static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1644{
1645 unsigned int i;
1646 u32 reg;
1647
1648 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1649 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1650 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1651 return 0;
1652
1653 udelay(REGISTER_BUSY_DELAY);
1654 }
1655
1656 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1657 return -EACCES;
1658}
1659
1660static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1661{
1662 unsigned int i;
1663 u8 value;
1664
1665 /*
1666 * BBP was enabled after firmware was loaded,
1667 * but we need to reactivate it now.
1668 */
1669 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1670 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1671 msleep(1);
1672
1673 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1674 rt2800_bbp_read(rt2x00dev, 0, &value);
1675 if ((value != 0xff) && (value != 0x00))
1676 return 0;
1677 udelay(REGISTER_BUSY_DELAY);
1678 }
1679
1680 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1681 return -EACCES;
1682}
1683
1684int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1685{
1686 unsigned int i;
1687 u16 eeprom;
1688 u8 reg_id;
1689 u8 value;
1690
1691 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
1692 rt2800_wait_bbp_ready(rt2x00dev)))
1693 return -EACCES;
1694
baff8006
HS		 1695 if (rt2800_is_305x_soc(rt2x00dev))
1696 rt2800_bbp_write(rt2x00dev, 31, 0x08);
1697
fcf51541
BZ		 1698 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1699 rt2800_bbp_write(rt2x00dev, 66, 0x38);
a9dce149
GW		 1700
1701 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1702 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1703 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1704 } else {
1705 rt2800_bbp_write(rt2x00dev, 69, 0x12);
1706 rt2800_bbp_write(rt2x00dev, 73, 0x10);
1707 }
1708
fcf51541 1709 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
8cdd15e0 1710
d5385bfc 1711 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 1712 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1713 rt2x00_rt(rt2x00dev, RT3090) ||
1714 rt2x00_rt(rt2x00dev, RT3390)) {
8cdd15e0
GW		 1715 rt2800_bbp_write(rt2x00dev, 79, 0x13);
1716 rt2800_bbp_write(rt2x00dev, 80, 0x05);
1717 rt2800_bbp_write(rt2x00dev, 81, 0x33);
baff8006
HS		 1718 } else if (rt2800_is_305x_soc(rt2x00dev)) {
1719 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
1720 rt2800_bbp_write(rt2x00dev, 80, 0x08);
8cdd15e0
GW		 1721 } else {
1722 rt2800_bbp_write(rt2x00dev, 81, 0x37);
1723 }
1724
fcf51541
BZ		 1725 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1726 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
a9dce149 1727
5ed8f458 1728 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
a9dce149
GW		 1729 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1730 else
1731 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1732
fcf51541
BZ		 1733 rt2800_bbp_write(rt2x00dev, 86, 0x00);
1734 rt2800_bbp_write(rt2x00dev, 91, 0x04);
1735 rt2800_bbp_write(rt2x00dev, 92, 0x00);
8cdd15e0 1736
d5385bfc 1737 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 1738 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904 1739 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
baff8006
HS		 1740 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
1741 rt2800_is_305x_soc(rt2x00dev))
8cdd15e0
GW		 1742 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1743 else
1744 rt2800_bbp_write(rt2x00dev, 103, 0x00);
1745
baff8006
HS		 1746 if (rt2800_is_305x_soc(rt2x00dev))
1747 rt2800_bbp_write(rt2x00dev, 105, 0x01);
1748 else
1749 rt2800_bbp_write(rt2x00dev, 105, 0x05);
a9dce149 1750 rt2800_bbp_write(rt2x00dev, 106, 0x35);
fcf51541 1751
64522957 1752 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1753 rt2x00_rt(rt2x00dev, RT3090) ||
1754 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc 1755 rt2800_bbp_read(rt2x00dev, 138, &value);
fcf51541 1756
d5385bfc
GW		 1757 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1758 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
1759 value |= 0x20;
1760 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
1761 value &= ~0x02;
fcf51541 1762
d5385bfc 1763 rt2800_bbp_write(rt2x00dev, 138, value);
fcf51541
BZ		 1764 }
1765
fcf51541
BZ		 1766
1767 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1768 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1769
1770 if (eeprom != 0xffff && eeprom != 0x0000) {
1771 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1772 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1773 rt2800_bbp_write(rt2x00dev, reg_id, value);
1774 }
1775 }
1776
1777 return 0;
1778}
1779EXPORT_SYMBOL_GPL(rt2800_init_bbp);
1780
1781static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1782 bool bw40, u8 rfcsr24, u8 filter_target)
1783{
1784 unsigned int i;
1785 u8 bbp;
1786 u8 rfcsr;
1787 u8 passband;
1788 u8 stopband;
1789 u8 overtuned = 0;
1790
1791 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1792
1793 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1794 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1795 rt2800_bbp_write(rt2x00dev, 4, bbp);
1796
1797 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1798 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1799 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1800
1801 /*
1802 * Set power & frequency of passband test tone
1803 */
1804 rt2800_bbp_write(rt2x00dev, 24, 0);
1805
1806 for (i = 0; i < 100; i++) {
1807 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1808 msleep(1);
1809
1810 rt2800_bbp_read(rt2x00dev, 55, &passband);
1811 if (passband)
1812 break;
1813 }
1814
1815 /*
1816 * Set power & frequency of stopband test tone
1817 */
1818 rt2800_bbp_write(rt2x00dev, 24, 0x06);
1819
1820 for (i = 0; i < 100; i++) {
1821 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1822 msleep(1);
1823
1824 rt2800_bbp_read(rt2x00dev, 55, &stopband);
1825
1826 if ((passband - stopband) <= filter_target) {
1827 rfcsr24++;
1828 overtuned += ((passband - stopband) == filter_target);
1829 } else
1830 break;
1831
1832 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1833 }
1834
1835 rfcsr24 -= !!overtuned;
1836
1837 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1838 return rfcsr24;
1839}
1840
1841int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1842{
1843 u8 rfcsr;
1844 u8 bbp;
8cdd15e0
GW		 1845 u32 reg;
1846 u16 eeprom;
fcf51541 1847
d5385bfc 1848 if (!rt2x00_rt(rt2x00dev, RT3070) &&
64522957 1849 !rt2x00_rt(rt2x00dev, RT3071) &&
cc78e904 1850 !rt2x00_rt(rt2x00dev, RT3090) &&
23812383 1851 !rt2x00_rt(rt2x00dev, RT3390) &&
baff8006 1852 !rt2800_is_305x_soc(rt2x00dev))
fcf51541
BZ		 1853 return 0;
1854
fcf51541
BZ		 1855 /*
1856 * Init RF calibration.
1857 */
1858 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1859 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1860 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1861 msleep(1);
1862 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1863 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1864
d5385bfc 1865 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957
GW		 1866 rt2x00_rt(rt2x00dev, RT3071) ||
1867 rt2x00_rt(rt2x00dev, RT3090)) {
fcf51541
BZ		 1868 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1869 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1870 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1871 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
1872 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
8cdd15e0 1873 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
fcf51541
BZ		 1874 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1875 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
1876 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1877 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1878 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1879 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1880 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1881 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1882 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1883 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1884 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
1885 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
fcf51541 1886 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
cc78e904
GW		 1887 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
1888 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
1889 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
1890 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
1891 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
fcf51541 1892 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
cc78e904
GW		 1893 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
1894 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
1895 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
1896 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
1897 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1898 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
fcf51541 1899 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
cc78e904
GW		 1900 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
1901 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
fcf51541 1902 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
cc78e904
GW		 1903 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1904 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
1905 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
1906 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
1907 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
1908 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
1909 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
fcf51541 1910 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
cc78e904 1911 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
fcf51541 1912 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
cc78e904
GW		 1913 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1914 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1915 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1916 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
1917 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
1918 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
1919 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
baff8006 1920 } else if (rt2800_is_305x_soc(rt2x00dev)) {
23812383
HS		 1921 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
1922 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
1923 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
1924 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
1925 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1926 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1927 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1928 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
1929 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
1930 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1931 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
1932 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1933 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
1934 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
1935 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1936 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1937 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1938 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1939 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1940 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1941 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1942 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1943 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1944 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
1945 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
1946 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1947 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
1948 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
1949 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
1950 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
baff8006
HS		 1951 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
1952 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
1953 return 0;
8cdd15e0
GW		 1954 }
1955
1956 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1957 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
1958 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
1959 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
1960 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
64522957
GW		 1961 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
1962 rt2x00_rt(rt2x00dev, RT3090)) {
d5385bfc
GW		 1963 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1964 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
1965 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1966
1967 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
1968
1969 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
1970 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
64522957
GW		 1971 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1972 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
d5385bfc
GW		 1973 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1974 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1975 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
1976 else
1977 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
1978 }
1979 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
cc78e904
GW		 1980 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
1981 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1982 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
1983 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
fcf51541
BZ		 1984 }
1985
1986 /*
1987 * Set RX Filter calibration for 20MHz and 40MHz
1988 */
8cdd15e0
GW		 1989 if (rt2x00_rt(rt2x00dev, RT3070)) {
1990 rt2x00dev->calibration[0] =
1991 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1992 rt2x00dev->calibration[1] =
1993 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
64522957 1994 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1995 rt2x00_rt(rt2x00dev, RT3090) ||
1996 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 1997 rt2x00dev->calibration[0] =
1998 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
1999 rt2x00dev->calibration[1] =
2000 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
8cdd15e0 2001 }
fcf51541
BZ		 2002
2003 /*
2004 * Set back to initial state
2005 */
2006 rt2800_bbp_write(rt2x00dev, 24, 0);
2007
2008 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2009 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
2010 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2011
2012 /*
2013 * set BBP back to BW20
2014 */
2015 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2016 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
2017 rt2800_bbp_write(rt2x00dev, 4, bbp);
2018
d5385bfc 2019 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 2020 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2021 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2022 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
8cdd15e0
GW		 2023 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
2024
2025 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
2026 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
2027 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
2028
2029 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2030 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
64522957 2031 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2032 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2033 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
8440c292 2034 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
d5385bfc
GW		 2035 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
2036 }
8cdd15e0
GW		 2037 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
2038 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
2039 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
2040 rt2x00_get_field16(eeprom,
2041 EEPROM_TXMIXER_GAIN_BG_VAL));
2042 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2043
64522957
GW		 2044 if (rt2x00_rt(rt2x00dev, RT3090)) {
2045 rt2800_bbp_read(rt2x00dev, 138, &bbp);
2046
2047 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2048 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
2049 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
2050 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
2051 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
2052
2053 rt2800_bbp_write(rt2x00dev, 138, bbp);
2054 }
2055
2056 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2057 rt2x00_rt(rt2x00dev, RT3090) ||
2058 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 2059 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2060 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2061 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2062 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2063 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2064 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2065 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2066
2067 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
2068 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
2069 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
2070
2071 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
2072 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
2073 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
2074
2075 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
2076 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
2077 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
2078 }
2079
2080 if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) {
8cdd15e0 2081 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
d5385bfc
GW		 2082 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2083 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
8cdd15e0
GW		 2084 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
2085 else
2086 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
2087 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
2088 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
2089 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
2090 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
2091 }
2092
fcf51541
BZ		 2093 return 0;
2094}
2095EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
2ce33995 2096
30e84034
BZ		 2097int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
2098{
2099 u32 reg;
2100
2101 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
2102
2103 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
2104}
2105EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
2106
2107static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
2108{
2109 u32 reg;
2110
31a4cf1f
GW		 2111 mutex_lock(&rt2x00dev->csr_mutex);
2112
2113 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
30e84034
BZ		 2114 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
2115 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
2116 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
31a4cf1f 2117 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
30e84034
BZ		 2118
2119 /* Wait until the EEPROM has been loaded */
2120 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
2121
2122 /* Apparently the data is read from end to start */
31a4cf1f
GW		 2123 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
2124 (u32 *)&rt2x00dev->eeprom[i]);
2125 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
2126 (u32 *)&rt2x00dev->eeprom[i + 2]);
2127 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
2128 (u32 *)&rt2x00dev->eeprom[i + 4]);
2129 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
2130 (u32 *)&rt2x00dev->eeprom[i + 6]);
2131
2132 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 2133}
2134
2135void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
2136{
2137 unsigned int i;
2138
2139 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
2140 rt2800_efuse_read(rt2x00dev, i);
2141}
2142EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
2143
38bd7b8a
BZ		 2144int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2145{
2146 u16 word;
2147 u8 *mac;
2148 u8 default_lna_gain;
2149
2150 /*
2151 * Start validation of the data that has been read.
2152 */
2153 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2154 if (!is_valid_ether_addr(mac)) {
2155 random_ether_addr(mac);
2156 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2157 }
2158
2159 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2160 if (word == 0xffff) {
2161 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2162 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2163 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2164 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2165 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 2166 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 2167 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 2168 /*
2169 * There is a max of 2 RX streams for RT28x0 series
2170 */
2171 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2172 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2173 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2174 }
2175
2176 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2177 if (word == 0xffff) {
2178 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2179 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2180 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2181 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2182 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2183 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2184 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2185 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2186 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2187 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2188 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2189 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2190 }
2191
2192 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2193 if ((word & 0x00ff) == 0x00ff) {
2194 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2195 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2196 LED_MODE_TXRX_ACTIVITY);
2197 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2198 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2199 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2200 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2201 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2202 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2203 }
2204
2205 /*
2206 * During the LNA validation we are going to use
2207 * lna0 as correct value. Note that EEPROM_LNA
2208 * is never validated.
2209 */
2210 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2211 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2212
2213 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2214 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2215 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2216 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2217 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2218 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2219
2220 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2221 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2222 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2223 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2224 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2225 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2226 default_lna_gain);
2227 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2228
2229 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2230 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2231 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2232 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2233 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2234 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2235
2236 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2237 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2238 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2239 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2240 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2241 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2242 default_lna_gain);
2243 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2244
2245 return 0;
2246}
2247EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
2248
2249int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
2250{
2251 u32 reg;
2252 u16 value;
2253 u16 eeprom;
2254
2255 /*
2256 * Read EEPROM word for configuration.
2257 */
2258 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2259
2260 /*
2261 * Identify RF chipset.
2262 */
2263 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2264 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2265
49e721ec
GW		 2266 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2267 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2268
2269 if (!rt2x00_rt(rt2x00dev, RT2860) &&
49e721ec 2270 !rt2x00_rt(rt2x00dev, RT2872) &&
49e721ec 2271 !rt2x00_rt(rt2x00dev, RT2883) &&
49e721ec
GW		 2272 !rt2x00_rt(rt2x00dev, RT3070) &&
2273 !rt2x00_rt(rt2x00dev, RT3071) &&
2274 !rt2x00_rt(rt2x00dev, RT3090) &&
2275 !rt2x00_rt(rt2x00dev, RT3390) &&
2276 !rt2x00_rt(rt2x00dev, RT3572)) {
2277 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2278 return -ENODEV;
f273fe55 2279 }
714fa663 2280
5122d898
GW		 2281 if (!rt2x00_rf(rt2x00dev, RF2820) &&
2282 !rt2x00_rf(rt2x00dev, RF2850) &&
2283 !rt2x00_rf(rt2x00dev, RF2720) &&
2284 !rt2x00_rf(rt2x00dev, RF2750) &&
2285 !rt2x00_rf(rt2x00dev, RF3020) &&
2286 !rt2x00_rf(rt2x00dev, RF2020) &&
2287 !rt2x00_rf(rt2x00dev, RF3021) &&
6c0fe265
GW		 2288 !rt2x00_rf(rt2x00dev, RF3022) &&
2289 !rt2x00_rf(rt2x00dev, RF3052)) {
38bd7b8a
BZ		 2290 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2291 return -ENODEV;
2292 }
2293
2294 /*
2295 * Identify default antenna configuration.
2296 */
2297 rt2x00dev->default_ant.tx =
2298 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2299 rt2x00dev->default_ant.rx =
2300 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2301
2302 /*
2303 * Read frequency offset and RF programming sequence.
2304 */
2305 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2306 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2307
2308 /*
2309 * Read external LNA informations.
2310 */
2311 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2312
2313 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2314 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2315 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2316 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2317
2318 /*
2319 * Detect if this device has an hardware controlled radio.
2320 */
2321 if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2322 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2323
2324 /*
2325 * Store led settings, for correct led behaviour.
2326 */
2327#ifdef CONFIG_RT2X00_LIB_LEDS
2328 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2329 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2330 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2331
2332 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2333#endif /* CONFIG_RT2X00_LIB_LEDS */
2334
2335 return 0;
2336}
2337EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
2338
4da2933f 2339/*
55f9321a 2340 * RF value list for rt28xx
4da2933f
BZ		 2341 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2342 */
2343static const struct rf_channel rf_vals[] = {
2344 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2345 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2346 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2347 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2348 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2349 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2350 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2351 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2352 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2353 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2354 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2355 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2356 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2357 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2358
2359 /* 802.11 UNI / HyperLan 2 */
2360 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2361 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2362 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2363 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2364 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2365 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2366 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2367 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2368 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2369 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2370 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2371 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2372
2373 /* 802.11 HyperLan 2 */
2374 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2375 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2376 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2377 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2378 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2379 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2380 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2381 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2382 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2383 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2384 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2385 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2386 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2387 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2388 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2389 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2390
2391 /* 802.11 UNII */
2392 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2393 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2394 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2395 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2396 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2397 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2398 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2399 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2400 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2401 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2402 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2403
2404 /* 802.11 Japan */
2405 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2406 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2407 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2408 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2409 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2410 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2411 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2412};
2413
2414/*
55f9321a
ID		 2415 * RF value list for rt3xxx
2416 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4da2933f 2417 */
55f9321a 2418static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 2419 {1, 241, 2, 2 },
2420 {2, 241, 2, 7 },
2421 {3, 242, 2, 2 },
2422 {4, 242, 2, 7 },
2423 {5, 243, 2, 2 },
2424 {6, 243, 2, 7 },
2425 {7, 244, 2, 2 },
2426 {8, 244, 2, 7 },
2427 {9, 245, 2, 2 },
2428 {10, 245, 2, 7 },
2429 {11, 246, 2, 2 },
2430 {12, 246, 2, 7 },
2431 {13, 247, 2, 2 },
2432 {14, 248, 2, 4 },
55f9321a
ID		 2433
2434 /* 802.11 UNI / HyperLan 2 */
2435 {36, 0x56, 0, 4},
2436 {38, 0x56, 0, 6},
2437 {40, 0x56, 0, 8},
2438 {44, 0x57, 0, 0},
2439 {46, 0x57, 0, 2},
2440 {48, 0x57, 0, 4},
2441 {52, 0x57, 0, 8},
2442 {54, 0x57, 0, 10},
2443 {56, 0x58, 0, 0},
2444 {60, 0x58, 0, 4},
2445 {62, 0x58, 0, 6},
2446 {64, 0x58, 0, 8},
2447
2448 /* 802.11 HyperLan 2 */
2449 {100, 0x5b, 0, 8},
2450 {102, 0x5b, 0, 10},
2451 {104, 0x5c, 0, 0},
2452 {108, 0x5c, 0, 4},
2453 {110, 0x5c, 0, 6},
2454 {112, 0x5c, 0, 8},
2455 {116, 0x5d, 0, 0},
2456 {118, 0x5d, 0, 2},
2457 {120, 0x5d, 0, 4},
2458 {124, 0x5d, 0, 8},
2459 {126, 0x5d, 0, 10},
2460 {128, 0x5e, 0, 0},
2461 {132, 0x5e, 0, 4},
2462 {134, 0x5e, 0, 6},
2463 {136, 0x5e, 0, 8},
2464 {140, 0x5f, 0, 0},
2465
2466 /* 802.11 UNII */
2467 {149, 0x5f, 0, 9},
2468 {151, 0x5f, 0, 11},
2469 {153, 0x60, 0, 1},
2470 {157, 0x60, 0, 5},
2471 {159, 0x60, 0, 7},
2472 {161, 0x60, 0, 9},
2473 {165, 0x61, 0, 1},
2474 {167, 0x61, 0, 3},
2475 {169, 0x61, 0, 5},
2476 {171, 0x61, 0, 7},
2477 {173, 0x61, 0, 9},
4da2933f
BZ		 2478};
2479
2480int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2481{
4da2933f
BZ		 2482 struct hw_mode_spec *spec = &rt2x00dev->spec;
2483 struct channel_info *info;
2484 char *tx_power1;
2485 char *tx_power2;
2486 unsigned int i;
2487 u16 eeprom;
2488
93b6bd26
GW		 2489 /*
2490 * Disable powersaving as default on PCI devices.
2491 */
cea90e55 2492 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
93b6bd26
GW		 2493 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2494
4da2933f
BZ		 2495 /*
2496 * Initialize all hw fields.
2497 */
2498 rt2x00dev->hw->flags =
2499 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2500 IEEE80211_HW_SIGNAL_DBM |
2501 IEEE80211_HW_SUPPORTS_PS |
2502 IEEE80211_HW_PS_NULLFUNC_STACK;
2503
4da2933f
BZ		 2504 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2505 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2506 rt2x00_eeprom_addr(rt2x00dev,
2507 EEPROM_MAC_ADDR_0));
2508
3f2bee24
HS		 2509 /*
2510 * As rt2800 has a global fallback table we cannot specify
2511 * more then one tx rate per frame but since the hw will
2512 * try several rates (based on the fallback table) we should
2513 * still initialize max_rates to the maximum number of rates
2514 * we are going to try. Otherwise mac80211 will truncate our
2515 * reported tx rates and the rc algortihm will end up with
2516 * incorrect data.
2517 */
2518 rt2x00dev->hw->max_rates = 7;
2519 rt2x00dev->hw->max_rate_tries = 1;
2520
4da2933f
BZ		 2521 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2522
2523 /*
2524 * Initialize hw_mode information.
2525 */
2526 spec->supported_bands = SUPPORT_BAND_2GHZ;
2527 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2528
5122d898 2529 if (rt2x00_rf(rt2x00dev, RF2820) ||
55f9321a 2530 rt2x00_rf(rt2x00dev, RF2720)) {
4da2933f
BZ		 2531 spec->num_channels = 14;
2532 spec->channels = rf_vals;
55f9321a
ID		 2533 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
2534 rt2x00_rf(rt2x00dev, RF2750)) {
4da2933f
BZ		 2535 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2536 spec->num_channels = ARRAY_SIZE(rf_vals);
2537 spec->channels = rf_vals;
5122d898
GW		 2538 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
2539 rt2x00_rf(rt2x00dev, RF2020) ||
2540 rt2x00_rf(rt2x00dev, RF3021) ||
2541 rt2x00_rf(rt2x00dev, RF3022)) {
55f9321a
ID		 2542 spec->num_channels = 14;
2543 spec->channels = rf_vals_3x;
2544 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
2545 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2546 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
2547 spec->channels = rf_vals_3x;
4da2933f
BZ		 2548 }
2549
2550 /*
2551 * Initialize HT information.
2552 */
5122d898 2553 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 2554 spec->ht.ht_supported = true;
2555 else
2556 spec->ht.ht_supported = false;
2557
4da2933f 2558 spec->ht.cap =
06443e46 2559 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 2560 IEEE80211_HT_CAP_GRN_FLD |
2561 IEEE80211_HT_CAP_SGI_20 |
2562 IEEE80211_HT_CAP_SGI_40 |
9a418af5 2563 IEEE80211_HT_CAP_RX_STBC;
22cabaa6
HS		 2564
2565 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) >= 2)
2566 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
2567
4da2933f
BZ		 2568 spec->ht.ampdu_factor = 3;
2569 spec->ht.ampdu_density = 4;
2570 spec->ht.mcs.tx_params =
2571 IEEE80211_HT_MCS_TX_DEFINED |
2572 IEEE80211_HT_MCS_TX_RX_DIFF |
2573 ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2574 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2575
2576 switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2577 case 3:
2578 spec->ht.mcs.rx_mask[2] = 0xff;
2579 case 2:
2580 spec->ht.mcs.rx_mask[1] = 0xff;
2581 case 1:
2582 spec->ht.mcs.rx_mask[0] = 0xff;
2583 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2584 break;
2585 }
2586
2587 /*
2588 * Create channel information array
2589 */
2590 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2591 if (!info)
2592 return -ENOMEM;
2593
2594 spec->channels_info = info;
2595
2596 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2597 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2598
2599 for (i = 0; i < 14; i++) {
2600 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2601 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2602 }
2603
2604 if (spec->num_channels > 14) {
2605 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2606 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2607
2608 for (i = 14; i < spec->num_channels; i++) {
2609 info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2610 info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2611 }
2612 }
2613
2614 return 0;
2615}
2616EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
2617
2ce33995
BZ		 2618/*
2619 * IEEE80211 stack callback functions.
2620 */
2621static void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2622 u32 *iv32, u16 *iv16)
2623{
2624 struct rt2x00_dev *rt2x00dev = hw->priv;
2625 struct mac_iveiv_entry iveiv_entry;
2626 u32 offset;
2627
2628 offset = MAC_IVEIV_ENTRY(hw_key_idx);
2629 rt2800_register_multiread(rt2x00dev, offset,
2630 &iveiv_entry, sizeof(iveiv_entry));
2631
855da5e0
JL		 2632 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
2633 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995
BZ		 2634}
2635
2636static int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2637{
2638 struct rt2x00_dev *rt2x00dev = hw->priv;
2639 u32 reg;
2640 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2641
2642 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2643 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2644 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2645
2646 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2647 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2648 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2649
2650 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2651 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2652 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2653
2654 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2655 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2656 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2657
2658 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2659 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2660 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2661
2662 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2663 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2664 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2665
2666 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2667 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2668 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2669
2670 return 0;
2671}
2672
2673static int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2674 const struct ieee80211_tx_queue_params *params)
2675{
2676 struct rt2x00_dev *rt2x00dev = hw->priv;
2677 struct data_queue *queue;
2678 struct rt2x00_field32 field;
2679 int retval;
2680 u32 reg;
2681 u32 offset;
2682
2683 /*
2684 * First pass the configuration through rt2x00lib, that will
2685 * update the queue settings and validate the input. After that
2686 * we are free to update the registers based on the value
2687 * in the queue parameter.
2688 */
2689 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2690 if (retval)
2691 return retval;
2692
2693 /*
2694 * We only need to perform additional register initialization
2695 * for WMM queues/
2696 */
2697 if (queue_idx >= 4)
2698 return 0;
2699
2700 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2701
2702 /* Update WMM TXOP register */
2703 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2704 field.bit_offset = (queue_idx & 1) * 16;
2705 field.bit_mask = 0xffff << field.bit_offset;
2706
2707 rt2800_register_read(rt2x00dev, offset, &reg);
2708 rt2x00_set_field32(&reg, field, queue->txop);
2709 rt2800_register_write(rt2x00dev, offset, reg);
2710
2711 /* Update WMM registers */
2712 field.bit_offset = queue_idx * 4;
2713 field.bit_mask = 0xf << field.bit_offset;
2714
2715 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2716 rt2x00_set_field32(&reg, field, queue->aifs);
2717 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2718
2719 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2720 rt2x00_set_field32(&reg, field, queue->cw_min);
2721 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2722
2723 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2724 rt2x00_set_field32(&reg, field, queue->cw_max);
2725 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2726
2727 /* Update EDCA registers */
2728 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2729
2730 rt2800_register_read(rt2x00dev, offset, &reg);
2731 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2732 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2733 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2734 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2735 rt2800_register_write(rt2x00dev, offset, reg);
2736
2737 return 0;
2738}
2739
2740static u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2741{
2742 struct rt2x00_dev *rt2x00dev = hw->priv;
2743 u64 tsf;
2744 u32 reg;
2745
2746 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2747 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2748 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2749 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2750
2751 return tsf;
2752}
2753
2754const struct ieee80211_ops rt2800_mac80211_ops = {
2755 .tx = rt2x00mac_tx,
2756 .start = rt2x00mac_start,
2757 .stop = rt2x00mac_stop,
2758 .add_interface = rt2x00mac_add_interface,
2759 .remove_interface = rt2x00mac_remove_interface,
2760 .config = rt2x00mac_config,
2761 .configure_filter = rt2x00mac_configure_filter,
2762 .set_tim = rt2x00mac_set_tim,
2763 .set_key = rt2x00mac_set_key,
2764 .get_stats = rt2x00mac_get_stats,
2765 .get_tkip_seq = rt2800_get_tkip_seq,
2766 .set_rts_threshold = rt2800_set_rts_threshold,
2767 .bss_info_changed = rt2x00mac_bss_info_changed,
2768 .conf_tx = rt2800_conf_tx,
2ce33995
BZ		 2769 .get_tsf = rt2800_get_tsf,
2770 .rfkill_poll = rt2x00mac_rfkill_poll,
2771};
2772EXPORT_SYMBOL_GPL(rt2800_mac80211_ops);
a5ea2f02
ID		 2773
2774MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
2775MODULE_VERSION(DRV_VERSION);
2776MODULE_DESCRIPTION("Ralink RT2800 library");
2777MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.266318 seconds and 5 git commands to generate.