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rt2x00: Use proper type for rxwi_w2 in rt2800_agc_to_rssi
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
CommitLineData
89297425 1/*
96481b20 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
a5ea2f02 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 6
9c9a0d14 7 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32/*
33 Module: rt2800lib
34 Abstract: rt2800 generic device routines.
35 */
36
f31c9a8c 37#include <linux/crc-ccitt.h>
89297425
BZ		 38#include <linux/kernel.h>
39#include <linux/module.h>
5a0e3ad6 40#include <linux/slab.h>
89297425
BZ		 41
42#include "rt2x00.h"
43#include "rt2800lib.h"
44#include "rt2800.h"
45
89297425
BZ		 46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60#define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64#define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66#define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
baff8006
HS		 70static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71{
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
75 return false;
76
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
81 return true;
82
83 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
84 return false;
85}
86
fcf51541
BZ		 87static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
89297425
BZ		 89{
90 u32 reg;
91
92 mutex_lock(&rt2x00dev->csr_mutex);
93
94 /*
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
97 */
98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
efc7d36f 104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 105
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107 }
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110}
89297425 111
fcf51541
BZ		 112static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
89297425
BZ		 114{
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
126 */
127 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 reg = 0;
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
efc7d36f 132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142}
89297425 143
fcf51541
BZ		 144static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
89297425
BZ		 146{
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166}
89297425 167
fcf51541
BZ		 168static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
89297425
BZ		 170{
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197}
89297425 198
fcf51541
BZ		 199static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
89297425
BZ		 201{
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222}
89297425
BZ		 223
224void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
225 const u8 command, const u8 token,
226 const u8 arg0, const u8 arg1)
227{
228 u32 reg;
229
ee303e54 230 /*
cea90e55 231 * SOC devices don't support MCU requests.
ee303e54 232 */
cea90e55 233 if (rt2x00_is_soc(rt2x00dev))
ee303e54 234 return;
89297425
BZ		 235
236 mutex_lock(&rt2x00dev->csr_mutex);
237
238 /*
239 * Wait until the MCU becomes available, afterwards we
240 * can safely write the new data into the register.
241 */
242 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
243 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
244 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
245 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
246 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
247 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
248
249 reg = 0;
250 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
251 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
252 }
253
254 mutex_unlock(&rt2x00dev->csr_mutex);
255}
256EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 257
5ffddc49
ID		 258int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
259{
260 unsigned int i = 0;
261 u32 reg;
262
263 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
264 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
265 if (reg && reg != ~0)
266 return 0;
267 msleep(1);
268 }
269
270 ERROR(rt2x00dev, "Unstable hardware.\n");
271 return -EBUSY;
272}
273EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
274
67a4c1e2
GW		 275int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
276{
277 unsigned int i;
278 u32 reg;
279
280 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
281 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
282 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
283 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
284 return 0;
285
286 msleep(1);
287 }
288
289 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
290 return -EACCES;
291}
292EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
293
f31c9a8c
ID		 294static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
295{
296 u16 fw_crc;
297 u16 crc;
298
299 /*
300 * The last 2 bytes in the firmware array are the crc checksum itself,
301 * this means that we should never pass those 2 bytes to the crc
302 * algorithm.
303 */
304 fw_crc = (data[len - 2] << 8 | data[len - 1]);
305
306 /*
307 * Use the crc ccitt algorithm.
308 * This will return the same value as the legacy driver which
309 * used bit ordering reversion on the both the firmware bytes
310 * before input input as well as on the final output.
311 * Obviously using crc ccitt directly is much more efficient.
312 */
313 crc = crc_ccitt(~0, data, len - 2);
314
315 /*
316 * There is a small difference between the crc-itu-t + bitrev and
317 * the crc-ccitt crc calculation. In the latter method the 2 bytes
318 * will be swapped, use swab16 to convert the crc to the correct
319 * value.
320 */
321 crc = swab16(crc);
322
323 return fw_crc == crc;
324}
325
326int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
327 const u8 *data, const size_t len)
328{
329 size_t offset = 0;
330 size_t fw_len;
331 bool multiple;
332
333 /*
334 * PCI(e) & SOC devices require firmware with a length
335 * of 8kb. USB devices require firmware files with a length
336 * of 4kb. Certain USB chipsets however require different firmware,
337 * which Ralink only provides attached to the original firmware
338 * file. Thus for USB devices, firmware files have a length
339 * which is a multiple of 4kb.
340 */
341 if (rt2x00_is_usb(rt2x00dev)) {
342 fw_len = 4096;
343 multiple = true;
344 } else {
345 fw_len = 8192;
346 multiple = true;
347 }
348
349 /*
350 * Validate the firmware length
351 */
352 if (len != fw_len && (!multiple || (len % fw_len) != 0))
353 return FW_BAD_LENGTH;
354
355 /*
356 * Check if the chipset requires one of the upper parts
357 * of the firmware.
358 */
359 if (rt2x00_is_usb(rt2x00dev) &&
360 !rt2x00_rt(rt2x00dev, RT2860) &&
361 !rt2x00_rt(rt2x00dev, RT2872) &&
362 !rt2x00_rt(rt2x00dev, RT3070) &&
363 ((len / fw_len) == 1))
364 return FW_BAD_VERSION;
365
366 /*
367 * 8kb firmware files must be checked as if it were
368 * 2 separate firmware files.
369 */
370 while (offset < len) {
371 if (!rt2800_check_firmware_crc(data + offset, fw_len))
372 return FW_BAD_CRC;
373
374 offset += fw_len;
375 }
376
377 return FW_OK;
378}
379EXPORT_SYMBOL_GPL(rt2800_check_firmware);
380
381int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
382 const u8 *data, const size_t len)
383{
384 unsigned int i;
385 u32 reg;
386
b9eca242
ID		 387 /*
388 * If driver doesn't wake up firmware here,
389 * rt2800_load_firmware will hang forever when interface is up again.
390 */
391 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
392
f31c9a8c
ID		 393 /*
394 * Wait for stable hardware.
395 */
5ffddc49 396 if (rt2800_wait_csr_ready(rt2x00dev))
f31c9a8c 397 return -EBUSY;
f31c9a8c
ID		 398
399 if (rt2x00_is_pci(rt2x00dev))
400 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
401
402 /*
403 * Disable DMA, will be reenabled later when enabling
404 * the radio.
405 */
406 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
407 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
408 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
409 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
410 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
411 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
412 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
413
414 /*
415 * Write firmware to the device.
416 */
417 rt2800_drv_write_firmware(rt2x00dev, data, len);
418
419 /*
420 * Wait for device to stabilize.
421 */
422 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
423 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
424 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
425 break;
426 msleep(1);
427 }
428
429 if (i == REGISTER_BUSY_COUNT) {
430 ERROR(rt2x00dev, "PBF system register not ready.\n");
431 return -EBUSY;
432 }
433
434 /*
435 * Initialize firmware.
436 */
437 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
438 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
439 msleep(1);
440
441 return 0;
442}
443EXPORT_SYMBOL_GPL(rt2800_load_firmware);
444
0c5879bc
ID		 445void rt2800_write_tx_data(struct queue_entry *entry,
446 struct txentry_desc *txdesc)
59679b91 447{
0c5879bc 448 __le32 *txwi = rt2800_drv_get_txwi(entry);
59679b91
GW		 449 u32 word;
450
451 /*
452 * Initialize TX Info descriptor
453 */
454 rt2x00_desc_read(txwi, 0, &word);
455 rt2x00_set_field32(&word, TXWI_W0_FRAG,
456 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
84804cdc
ID		 457 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
458 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
59679b91
GW		 459 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
460 rt2x00_set_field32(&word, TXWI_W0_TS,
461 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
462 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
463 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
464 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
465 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop);
466 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
467 rt2x00_set_field32(&word, TXWI_W0_BW,
468 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
469 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
470 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
471 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
472 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
473 rt2x00_desc_write(txwi, 0, word);
474
475 rt2x00_desc_read(txwi, 1, &word);
476 rt2x00_set_field32(&word, TXWI_W1_ACK,
477 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
478 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
479 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
480 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
481 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
482 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
483 txdesc->key_idx : 0xff);
484 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
485 txdesc->length);
bc8a979e
ID		 486 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, txdesc->qid);
487 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
59679b91
GW		 488 rt2x00_desc_write(txwi, 1, word);
489
490 /*
491 * Always write 0 to IV/EIV fields, hardware will insert the IV
492 * from the IVEIV register when TXD_W3_WIV is set to 0.
493 * When TXD_W3_WIV is set to 1 it will use the IV data
494 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
495 * crypto entry in the registers should be used to encrypt the frame.
496 */
497 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
498 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
499}
0c5879bc 500EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
59679b91 501
ff6133be 502static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
2de64dd2 503{
74861922
ID		 504 int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
505 int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
506 int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
507 u16 eeprom;
508 u8 offset0;
509 u8 offset1;
510 u8 offset2;
511
e5ef5bad 512 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
74861922
ID		 513 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
514 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
515 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
516 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
517 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
518 } else {
519 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
520 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
521 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
522 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
523 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
524 }
525
526 /*
527 * Convert the value from the descriptor into the RSSI value
528 * If the value in the descriptor is 0, it is considered invalid
529 * and the default (extremely low) rssi value is assumed
530 */
531 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
532 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
533 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
534
535 /*
536 * mac80211 only accepts a single RSSI value. Calculating the
537 * average doesn't deliver a fair answer either since -60:-60 would
538 * be considered equally good as -50:-70 while the second is the one
539 * which gives less energy...
540 */
541 rssi0 = max(rssi0, rssi1);
542 return max(rssi0, rssi2);
543}
544
545void rt2800_process_rxwi(struct queue_entry *entry,
546 struct rxdone_entry_desc *rxdesc)
547{
548 __le32 *rxwi = (__le32 *) entry->skb->data;
2de64dd2
GW		 549 u32 word;
550
551 rt2x00_desc_read(rxwi, 0, &word);
552
553 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
554 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
555
556 rt2x00_desc_read(rxwi, 1, &word);
557
558 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
559 rxdesc->flags |= RX_FLAG_SHORT_GI;
560
561 if (rt2x00_get_field32(word, RXWI_W1_BW))
562 rxdesc->flags |= RX_FLAG_40MHZ;
563
564 /*
565 * Detect RX rate, always use MCS as signal type.
566 */
567 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
568 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
569 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
570
571 /*
572 * Mask of 0x8 bit to remove the short preamble flag.
573 */
574 if (rxdesc->rate_mode == RATE_MODE_CCK)
575 rxdesc->signal &= ~0x8;
576
577 rt2x00_desc_read(rxwi, 2, &word);
578
74861922
ID		 579 /*
580 * Convert descriptor AGC value to RSSI value.
581 */
582 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
2de64dd2
GW		 583
584 /*
585 * Remove RXWI descriptor from start of buffer.
586 */
74861922 587 skb_pull(entry->skb, RXWI_DESC_SIZE);
2de64dd2
GW		 588}
589EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
590
3613884d
ID		 591static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)
592{
593 __le32 *txwi;
594 u32 word;
595 int wcid, ack, pid;
596 int tx_wcid, tx_ack, tx_pid;
597
598 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
599 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
600 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
601
602 /*
603 * This frames has returned with an IO error,
604 * so the status report is not intended for this
605 * frame.
606 */
607 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) {
608 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
609 return false;
610 }
611
612 /*
613 * Validate if this TX status report is intended for
614 * this entry by comparing the WCID/ACK/PID fields.
615 */
616 txwi = rt2800_drv_get_txwi(entry);
617
618 rt2x00_desc_read(txwi, 1, &word);
619 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
620 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK);
621 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID);
622
623 if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid)) {
624 WARNING(entry->queue->rt2x00dev,
625 "TX status report missed for queue %d entry %d\n",
626 entry->queue->qid, entry->entry_idx);
627 rt2x00lib_txdone_noinfo(entry, TXDONE_UNKNOWN);
628 return false;
629 }
630
631 return true;
632}
633
14433331
HS		 634void rt2800_txdone_entry(struct queue_entry *entry, u32 status)
635{
636 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b34793ee 637 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
14433331
HS		 638 struct txdone_entry_desc txdesc;
639 u32 word;
640 u16 mcs, real_mcs;
b34793ee 641 int aggr, ampdu;
14433331
HS		 642 __le32 *txwi;
643
644 /*
645 * Obtain the status about this packet.
646 */
647 txdesc.flags = 0;
648 txwi = rt2800_drv_get_txwi(entry);
649 rt2x00_desc_read(txwi, 0, &word);
b34793ee 650
14433331 651 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
b34793ee
HS		 652 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
653
14433331 654 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
b34793ee
HS		 655 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
656
657 /*
658 * If a frame was meant to be sent as a single non-aggregated MPDU
659 * but ended up in an aggregate the used tx rate doesn't correlate
660 * with the one specified in the TXWI as the whole aggregate is sent
661 * with the same rate.
662 *
663 * For example: two frames are sent to rt2x00, the first one sets
664 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
665 * and requests MCS15. If the hw aggregates both frames into one
666 * AMDPU the tx status for both frames will contain MCS7 although
667 * the frame was sent successfully.
668 *
669 * Hence, replace the requested rate with the real tx rate to not
670 * confuse the rate control algortihm by providing clearly wrong
671 * data.
672 */
673 if (aggr == 1 && ampdu == 0 && real_mcs != mcs) {
674 skbdesc->tx_rate_idx = real_mcs;
675 mcs = real_mcs;
676 }
14433331
HS		 677
678 /*
679 * Ralink has a retry mechanism using a global fallback
680 * table. We setup this fallback table to try the immediate
681 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
682 * always contains the MCS used for the last transmission, be
683 * it successful or not.
684 */
685 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
686 /*
687 * Transmission succeeded. The number of retries is
688 * mcs - real_mcs
689 */
690 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
691 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
692 } else {
693 /*
694 * Transmission failed. The number of retries is
695 * always 7 in this case (for a total number of 8
696 * frames sent).
697 */
698 __set_bit(TXDONE_FAILURE, &txdesc.flags);
699 txdesc.retry = rt2x00dev->long_retry;
700 }
701
702 /*
703 * the frame was retried at least once
704 * -> hw used fallback rates
705 */
706 if (txdesc.retry)
707 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
708
709 rt2x00lib_txdone(entry, &txdesc);
710}
711EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
712
96481b20
ID		 713void rt2800_txdone(struct rt2x00_dev *rt2x00dev)
714{
715 struct data_queue *queue;
716 struct queue_entry *entry;
96481b20 717 u32 reg;
3613884d 718 u8 pid;
96481b20
ID		 719 int i;
720
721 /*
722 * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
723 * at most X times and also stop processing once the TX_STA_FIFO_VALID
724 * flag is not set anymore.
725 *
726 * The legacy drivers use X=TX_RING_SIZE but state in a comment
727 * that the TX_STA_FIFO stack has a size of 16. We stick to our
728 * tx ring size for now.
729 */
730 for (i = 0; i < TX_ENTRIES; i++) {
731 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
732 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
733 break;
734
96481b20
ID		 735 /*
736 * Skip this entry when it contains an invalid
737 * queue identication number.
738 */
bc8a979e 739 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE);
3613884d 740 if (pid >= QID_RX)
96481b20
ID		 741 continue;
742
3613884d 743 queue = rt2x00queue_get_queue(rt2x00dev, pid);
96481b20
ID		 744 if (unlikely(!queue))
745 continue;
746
747 /*
748 * Inside each queue, we process each entry in a chronological
749 * order. We first check that the queue is not empty.
750 */
751 entry = NULL;
752 while (!rt2x00queue_empty(queue)) {
753 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
3613884d 754 if (rt2800_txdone_entry_check(entry, reg))
96481b20 755 break;
96481b20
ID		 756 }
757
758 if (!entry || rt2x00queue_empty(queue))
759 break;
760
14433331 761 rt2800_txdone_entry(entry, reg);
96481b20
ID		 762 }
763}
764EXPORT_SYMBOL_GPL(rt2800_txdone);
765
f0194b2d
GW		 766void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
767{
768 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
769 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
770 unsigned int beacon_base;
771 u32 reg;
772
773 /*
774 * Disable beaconing while we are reloading the beacon data,
775 * otherwise we might be sending out invalid data.
776 */
777 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
778 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
779 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
780
781 /*
782 * Add space for the TXWI in front of the skb.
783 */
784 skb_push(entry->skb, TXWI_DESC_SIZE);
785 memset(entry->skb, 0, TXWI_DESC_SIZE);
786
787 /*
788 * Register descriptor details in skb frame descriptor.
789 */
790 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
791 skbdesc->desc = entry->skb->data;
792 skbdesc->desc_len = TXWI_DESC_SIZE;
793
794 /*
795 * Add the TXWI for the beacon to the skb.
796 */
0c5879bc 797 rt2800_write_tx_data(entry, txdesc);
f0194b2d
GW		 798
799 /*
800 * Dump beacon to userspace through debugfs.
801 */
802 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
803
804 /*
805 * Write entire beacon with TXWI to register.
806 */
807 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
808 rt2800_register_multiwrite(rt2x00dev, beacon_base,
809 entry->skb->data, entry->skb->len);
810
811 /*
812 * Enable beaconing again.
813 */
814 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
815 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
816 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
817 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
818
819 /*
820 * Clean up beacon skb.
821 */
822 dev_kfree_skb_any(entry->skb);
823 entry->skb = NULL;
824}
50e888ea 825EXPORT_SYMBOL_GPL(rt2800_write_beacon);
f0194b2d 826
fdb87251
HS		 827static void inline rt2800_clear_beacon(struct rt2x00_dev *rt2x00dev,
828 unsigned int beacon_base)
829{
830 int i;
831
832 /*
833 * For the Beacon base registers we only need to clear
834 * the whole TXWI which (when set to 0) will invalidate
835 * the entire beacon.
836 */
837 for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
838 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
839}
840
f4450616
BZ		 841#ifdef CONFIG_RT2X00_LIB_DEBUGFS
842const struct rt2x00debug rt2800_rt2x00debug = {
843 .owner = THIS_MODULE,
844 .csr = {
845 .read = rt2800_register_read,
846 .write = rt2800_register_write,
847 .flags = RT2X00DEBUGFS_OFFSET,
848 .word_base = CSR_REG_BASE,
849 .word_size = sizeof(u32),
850 .word_count = CSR_REG_SIZE / sizeof(u32),
851 },
852 .eeprom = {
853 .read = rt2x00_eeprom_read,
854 .write = rt2x00_eeprom_write,
855 .word_base = EEPROM_BASE,
856 .word_size = sizeof(u16),
857 .word_count = EEPROM_SIZE / sizeof(u16),
858 },
859 .bbp = {
860 .read = rt2800_bbp_read,
861 .write = rt2800_bbp_write,
862 .word_base = BBP_BASE,
863 .word_size = sizeof(u8),
864 .word_count = BBP_SIZE / sizeof(u8),
865 },
866 .rf = {
867 .read = rt2x00_rf_read,
868 .write = rt2800_rf_write,
869 .word_base = RF_BASE,
870 .word_size = sizeof(u32),
871 .word_count = RF_SIZE / sizeof(u32),
872 },
873};
874EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
875#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
876
877int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
878{
879 u32 reg;
880
881 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
882 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
883}
884EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
885
886#ifdef CONFIG_RT2X00_LIB_LEDS
887static void rt2800_brightness_set(struct led_classdev *led_cdev,
888 enum led_brightness brightness)
889{
890 struct rt2x00_led *led =
891 container_of(led_cdev, struct rt2x00_led, led_dev);
892 unsigned int enabled = brightness != LED_OFF;
893 unsigned int bg_mode =
894 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
895 unsigned int polarity =
896 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
897 EEPROM_FREQ_LED_POLARITY);
898 unsigned int ledmode =
899 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
900 EEPROM_FREQ_LED_MODE);
901
902 if (led->type == LED_TYPE_RADIO) {
903 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
904 enabled ? 0x20 : 0);
905 } else if (led->type == LED_TYPE_ASSOC) {
906 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
907 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
908 } else if (led->type == LED_TYPE_QUALITY) {
909 /*
910 * The brightness is divided into 6 levels (0 - 5),
911 * The specs tell us the following levels:
912 * 0, 1 ,3, 7, 15, 31
913 * to determine the level in a simple way we can simply
914 * work with bitshifting:
915 * (1 << level) - 1
916 */
917 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
918 (1 << brightness / (LED_FULL / 6)) - 1,
919 polarity);
920 }
921}
922
923static int rt2800_blink_set(struct led_classdev *led_cdev,
924 unsigned long *delay_on, unsigned long *delay_off)
925{
926 struct rt2x00_led *led =
927 container_of(led_cdev, struct rt2x00_led, led_dev);
928 u32 reg;
929
930 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
931 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
932 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
f4450616
BZ		 933 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
934
935 return 0;
936}
937
b3579d6a 938static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 939 struct rt2x00_led *led, enum led_type type)
940{
941 led->rt2x00dev = rt2x00dev;
942 led->type = type;
943 led->led_dev.brightness_set = rt2800_brightness_set;
944 led->led_dev.blink_set = rt2800_blink_set;
945 led->flags = LED_INITIALIZED;
946}
f4450616
BZ		 947#endif /* CONFIG_RT2X00_LIB_LEDS */
948
949/*
950 * Configuration handlers.
951 */
952static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
953 struct rt2x00lib_crypto *crypto,
954 struct ieee80211_key_conf *key)
955{
956 struct mac_wcid_entry wcid_entry;
957 struct mac_iveiv_entry iveiv_entry;
958 u32 offset;
959 u32 reg;
960
961 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
962
e4a0ab34
ID		 963 if (crypto->cmd == SET_KEY) {
964 rt2800_register_read(rt2x00dev, offset, &reg);
965 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
966 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
967 /*
968 * Both the cipher as the BSS Idx numbers are split in a main
969 * value of 3 bits, and a extended field for adding one additional
970 * bit to the value.
971 */
972 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
973 (crypto->cipher & 0x7));
974 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
975 (crypto->cipher & 0x8) >> 3);
976 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
977 (crypto->bssidx & 0x7));
978 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
979 (crypto->bssidx & 0x8) >> 3);
980 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
981 rt2800_register_write(rt2x00dev, offset, reg);
982 } else {
983 rt2800_register_write(rt2x00dev, offset, 0);
984 }
f4450616
BZ		 985
986 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
987
988 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
989 if ((crypto->cipher == CIPHER_TKIP) ||
990 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
991 (crypto->cipher == CIPHER_AES))
992 iveiv_entry.iv[3] |= 0x20;
993 iveiv_entry.iv[3] |= key->keyidx << 6;
994 rt2800_register_multiwrite(rt2x00dev, offset,
995 &iveiv_entry, sizeof(iveiv_entry));
996
997 offset = MAC_WCID_ENTRY(key->hw_key_idx);
998
999 memset(&wcid_entry, 0, sizeof(wcid_entry));
1000 if (crypto->cmd == SET_KEY)
1001 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
1002 rt2800_register_multiwrite(rt2x00dev, offset,
1003 &wcid_entry, sizeof(wcid_entry));
1004}
1005
1006int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1007 struct rt2x00lib_crypto *crypto,
1008 struct ieee80211_key_conf *key)
1009{
1010 struct hw_key_entry key_entry;
1011 struct rt2x00_field32 field;
1012 u32 offset;
1013 u32 reg;
1014
1015 if (crypto->cmd == SET_KEY) {
1016 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1017
1018 memcpy(key_entry.key, crypto->key,
1019 sizeof(key_entry.key));
1020 memcpy(key_entry.tx_mic, crypto->tx_mic,
1021 sizeof(key_entry.tx_mic));
1022 memcpy(key_entry.rx_mic, crypto->rx_mic,
1023 sizeof(key_entry.rx_mic));
1024
1025 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1026 rt2800_register_multiwrite(rt2x00dev, offset,
1027 &key_entry, sizeof(key_entry));
1028 }
1029
1030 /*
1031 * The cipher types are stored over multiple registers
1032 * starting with SHARED_KEY_MODE_BASE each word will have
1033 * 32 bits and contains the cipher types for 2 bssidx each.
1034 * Using the correct defines correctly will cause overhead,
1035 * so just calculate the correct offset.
1036 */
1037 field.bit_offset = 4 * (key->hw_key_idx % 8);
1038 field.bit_mask = 0x7 << field.bit_offset;
1039
1040 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1041
1042 rt2800_register_read(rt2x00dev, offset, &reg);
1043 rt2x00_set_field32(&reg, field,
1044 (crypto->cmd == SET_KEY) * crypto->cipher);
1045 rt2800_register_write(rt2x00dev, offset, reg);
1046
1047 /*
1048 * Update WCID information
1049 */
1050 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1051
1052 return 0;
1053}
1054EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1055
1056int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1057 struct rt2x00lib_crypto *crypto,
1058 struct ieee80211_key_conf *key)
1059{
1060 struct hw_key_entry key_entry;
1061 u32 offset;
1062
1063 if (crypto->cmd == SET_KEY) {
1064 /*
1065 * 1 pairwise key is possible per AID, this means that the AID
1066 * equals our hw_key_idx. Make sure the WCID starts _after_ the
1067 * last possible shared key entry.
2a0cfeb8
HS		 1068 *
1069 * Since parts of the pairwise key table might be shared with
1070 * the beacon frame buffers 6 & 7 we should only write into the
1071 * first 222 entries.
f4450616 1072 */
2a0cfeb8 1073 if (crypto->aid > (222 - 32))
f4450616
BZ		 1074 return -ENOSPC;
1075
1076 key->hw_key_idx = 32 + crypto->aid;
1077
1078 memcpy(key_entry.key, crypto->key,
1079 sizeof(key_entry.key));
1080 memcpy(key_entry.tx_mic, crypto->tx_mic,
1081 sizeof(key_entry.tx_mic));
1082 memcpy(key_entry.rx_mic, crypto->rx_mic,
1083 sizeof(key_entry.rx_mic));
1084
1085 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1086 rt2800_register_multiwrite(rt2x00dev, offset,
1087 &key_entry, sizeof(key_entry));
1088 }
1089
1090 /*
1091 * Update WCID information
1092 */
1093 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1094
1095 return 0;
1096}
1097EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1098
1099void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1100 const unsigned int filter_flags)
1101{
1102 u32 reg;
1103
1104 /*
1105 * Start configuration steps.
1106 * Note that the version error will always be dropped
1107 * and broadcast frames will always be accepted since
1108 * there is no filter for it at this time.
1109 */
1110 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1111 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1112 !(filter_flags & FIF_FCSFAIL));
1113 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1114 !(filter_flags & FIF_PLCPFAIL));
1115 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1116 !(filter_flags & FIF_PROMISC_IN_BSS));
1117 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1118 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1119 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1120 !(filter_flags & FIF_ALLMULTI));
1121 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1122 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1123 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1124 !(filter_flags & FIF_CONTROL));
1125 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1126 !(filter_flags & FIF_CONTROL));
1127 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1128 !(filter_flags & FIF_CONTROL));
1129 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1130 !(filter_flags & FIF_CONTROL));
1131 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1132 !(filter_flags & FIF_CONTROL));
1133 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1134 !(filter_flags & FIF_PSPOLL));
1135 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
1136 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
1137 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1138 !(filter_flags & FIF_CONTROL));
1139 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1140}
1141EXPORT_SYMBOL_GPL(rt2800_config_filter);
1142
1143void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1144 struct rt2x00intf_conf *conf, const unsigned int flags)
1145{
f4450616
BZ		 1146 u32 reg;
1147
1148 if (flags & CONFIG_UPDATE_TYPE) {
1149 /*
1150 * Clear current synchronisation setup.
f4450616 1151 */
fdb87251
HS		 1152 rt2800_clear_beacon(rt2x00dev,
1153 HW_BEACON_OFFSET(intf->beacon->entry_idx));
f4450616
BZ		 1154 /*
1155 * Enable synchronisation.
1156 */
1157 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1158 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
1159 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
6a62e5ef 1160 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
ab8966dd
HS		 1161 (conf->sync == TSF_SYNC_ADHOC ||
1162 conf->sync == TSF_SYNC_AP_NONE));
f4450616 1163 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
9f926fb5
HS		 1164
1165 /*
1166 * Enable pre tbtt interrupt for beaconing modes
1167 */
1168 rt2800_register_read(rt2x00dev, INT_TIMER_EN, &reg);
1169 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER,
ab8966dd 1170 (conf->sync == TSF_SYNC_AP_NONE));
9f926fb5
HS		 1171 rt2800_register_write(rt2x00dev, INT_TIMER_EN, reg);
1172
f4450616
BZ		 1173 }
1174
1175 if (flags & CONFIG_UPDATE_MAC) {
c600c826
ID		 1176 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1177 reg = le32_to_cpu(conf->mac[1]);
1178 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1179 conf->mac[1] = cpu_to_le32(reg);
1180 }
f4450616
BZ		 1181
1182 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1183 conf->mac, sizeof(conf->mac));
1184 }
1185
1186 if (flags & CONFIG_UPDATE_BSSID) {
c600c826
ID		 1187 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1188 reg = le32_to_cpu(conf->bssid[1]);
1189 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1190 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1191 conf->bssid[1] = cpu_to_le32(reg);
1192 }
f4450616
BZ		 1193
1194 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1195 conf->bssid, sizeof(conf->bssid));
1196 }
1197}
1198EXPORT_SYMBOL_GPL(rt2800_config_intf);
1199
87c1915d
HS		 1200static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1201 struct rt2x00lib_erp *erp)
1202{
1203 bool any_sta_nongf = !!(erp->ht_opmode &
1204 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1205 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1206 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1207 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1208 u32 reg;
1209
1210 /* default protection rate for HT20: OFDM 24M */
1211 mm20_rate = gf20_rate = 0x4004;
1212
1213 /* default protection rate for HT40: duplicate OFDM 24M */
1214 mm40_rate = gf40_rate = 0x4084;
1215
1216 switch (protection) {
1217 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1218 /*
1219 * All STAs in this BSS are HT20/40 but there might be
1220 * STAs not supporting greenfield mode.
1221 * => Disable protection for HT transmissions.
1222 */
1223 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1224
1225 break;
1226 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1227 /*
1228 * All STAs in this BSS are HT20 or HT20/40 but there
1229 * might be STAs not supporting greenfield mode.
1230 * => Protect all HT40 transmissions.
1231 */
1232 mm20_mode = gf20_mode = 0;
1233 mm40_mode = gf40_mode = 2;
1234
1235 break;
1236 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1237 /*
1238 * Nonmember protection:
1239 * According to 802.11n we _should_ protect all
1240 * HT transmissions (but we don't have to).
1241 *
1242 * But if cts_protection is enabled we _shall_ protect
1243 * all HT transmissions using a CCK rate.
1244 *
1245 * And if any station is non GF we _shall_ protect
1246 * GF transmissions.
1247 *
1248 * We decide to protect everything
1249 * -> fall through to mixed mode.
1250 */
1251 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1252 /*
1253 * Legacy STAs are present
1254 * => Protect all HT transmissions.
1255 */
1256 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1257
1258 /*
1259 * If erp protection is needed we have to protect HT
1260 * transmissions with CCK 11M long preamble.
1261 */
1262 if (erp->cts_protection) {
1263 /* don't duplicate RTS/CTS in CCK mode */
1264 mm20_rate = mm40_rate = 0x0003;
1265 gf20_rate = gf40_rate = 0x0003;
1266 }
1267 break;
1268 };
1269
1270 /* check for STAs not supporting greenfield mode */
1271 if (any_sta_nongf)
1272 gf20_mode = gf40_mode = 2;
1273
1274 /* Update HT protection config */
1275 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1276 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1277 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1278 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1279
1280 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1281 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1282 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1283 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1284
1285 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1286 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1287 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1288 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1289
1290 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1291 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1292 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1293 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1294}
1295
02044643
HS		 1296void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1297 u32 changed)
f4450616
BZ		 1298{
1299 u32 reg;
1300
02044643
HS		 1301 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1302 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1303 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1304 !!erp->short_preamble);
1305 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1306 !!erp->short_preamble);
1307 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1308 }
f4450616 1309
02044643
HS		 1310 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1311 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1312 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1313 erp->cts_protection ? 2 : 0);
1314 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1315 }
f4450616 1316
02044643
HS		 1317 if (changed & BSS_CHANGED_BASIC_RATES) {
1318 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1319 erp->basic_rates);
1320 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1321 }
f4450616 1322
02044643
HS		 1323 if (changed & BSS_CHANGED_ERP_SLOT) {
1324 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1325 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1326 erp->slot_time);
1327 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
f4450616 1328
02044643
HS		 1329 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1330 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1331 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1332 }
f4450616 1333
02044643
HS		 1334 if (changed & BSS_CHANGED_BEACON_INT) {
1335 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1336 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1337 erp->beacon_int * 16);
1338 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1339 }
87c1915d
HS		 1340
1341 if (changed & BSS_CHANGED_HT)
1342 rt2800_config_ht_opmode(rt2x00dev, erp);
f4450616
BZ		 1343}
1344EXPORT_SYMBOL_GPL(rt2800_config_erp);
1345
1346void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1347{
1348 u8 r1;
1349 u8 r3;
1350
1351 rt2800_bbp_read(rt2x00dev, 1, &r1);
1352 rt2800_bbp_read(rt2x00dev, 3, &r3);
1353
1354 /*
1355 * Configure the TX antenna.
1356 */
1357 switch ((int)ant->tx) {
1358 case 1:
1359 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1360 break;
1361 case 2:
1362 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1363 break;
1364 case 3:
e22557f2 1365 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1366 break;
1367 }
1368
1369 /*
1370 * Configure the RX antenna.
1371 */
1372 switch ((int)ant->rx) {
1373 case 1:
1374 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1375 break;
1376 case 2:
1377 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1378 break;
1379 case 3:
1380 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1381 break;
1382 }
1383
1384 rt2800_bbp_write(rt2x00dev, 3, r3);
1385 rt2800_bbp_write(rt2x00dev, 1, r1);
1386}
1387EXPORT_SYMBOL_GPL(rt2800_config_ant);
1388
1389static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1390 struct rt2x00lib_conf *libconf)
1391{
1392 u16 eeprom;
1393 short lna_gain;
1394
1395 if (libconf->rf.channel <= 14) {
1396 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1397 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1398 } else if (libconf->rf.channel <= 64) {
1399 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1400 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1401 } else if (libconf->rf.channel <= 128) {
1402 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1403 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1404 } else {
1405 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1406 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1407 }
1408
1409 rt2x00dev->lna_gain = lna_gain;
1410}
1411
06855ef4
GW		 1412static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1413 struct ieee80211_conf *conf,
1414 struct rf_channel *rf,
1415 struct channel_info *info)
f4450616
BZ		 1416{
1417 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1418
1419 if (rt2x00dev->default_ant.tx == 1)
1420 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1421
1422 if (rt2x00dev->default_ant.rx == 1) {
1423 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1424 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1425 } else if (rt2x00dev->default_ant.rx == 2)
1426 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1427
1428 if (rf->channel > 14) {
1429 /*
1430 * When TX power is below 0, we should increase it by 7 to
1431 * make it a positive value (Minumum value is -7).
1432 * However this means that values between 0 and 7 have
1433 * double meaning, and we should set a 7DBm boost flag.
1434 */
1435 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
8d1331b3 1436 (info->default_power1 >= 0));
f4450616 1437
8d1331b3
ID		 1438 if (info->default_power1 < 0)
1439 info->default_power1 += 7;
f4450616 1440
8d1331b3 1441 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
f4450616
BZ		 1442
1443 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
8d1331b3 1444 (info->default_power2 >= 0));
f4450616 1445
8d1331b3
ID		 1446 if (info->default_power2 < 0)
1447 info->default_power2 += 7;
f4450616 1448
8d1331b3 1449 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
f4450616 1450 } else {
8d1331b3
ID		 1451 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1452 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
f4450616
BZ		 1453 }
1454
1455 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1456
1457 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1458 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1459 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1460 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1461
1462 udelay(200);
1463
1464 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1465 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1466 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1467 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1468
1469 udelay(200);
1470
1471 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1472 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1473 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1474 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1475}
1476
06855ef4
GW		 1477static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1478 struct ieee80211_conf *conf,
1479 struct rf_channel *rf,
1480 struct channel_info *info)
f4450616
BZ		 1481{
1482 u8 rfcsr;
1483
1484 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
41a26170 1485 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
f4450616
BZ		 1486
1487 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 1488 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 1489 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1490
1491 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
8d1331b3 1492 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
f4450616
BZ		 1493 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1494
5a673964 1495 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
8d1331b3 1496 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
5a673964
HS		 1497 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1498
f4450616
BZ		 1499 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1500 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1501 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1502
1503 rt2800_rfcsr_write(rt2x00dev, 24,
1504 rt2x00dev->calibration[conf_is_ht40(conf)]);
1505
71976907 1506 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 1507 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 1508 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
f4450616
BZ		 1509}
1510
1511static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1512 struct ieee80211_conf *conf,
1513 struct rf_channel *rf,
1514 struct channel_info *info)
1515{
1516 u32 reg;
1517 unsigned int tx_pin;
1518 u8 bbp;
1519
46323e11 1520 if (rf->channel <= 14) {
8d1331b3
ID		 1521 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
1522 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
46323e11 1523 } else {
8d1331b3
ID		 1524 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
1525 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
46323e11
ID		 1526 }
1527
06855ef4
GW		 1528 if (rt2x00_rf(rt2x00dev, RF2020) ||
1529 rt2x00_rf(rt2x00dev, RF3020) ||
1530 rt2x00_rf(rt2x00dev, RF3021) ||
46323e11
ID		 1531 rt2x00_rf(rt2x00dev, RF3022) ||
1532 rt2x00_rf(rt2x00dev, RF3052))
06855ef4 1533 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
fa6f632f 1534 else
06855ef4 1535 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
f4450616
BZ		 1536
1537 /*
1538 * Change BBP settings
1539 */
1540 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1541 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1542 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1543 rt2800_bbp_write(rt2x00dev, 86, 0);
1544
1545 if (rf->channel <= 14) {
1546 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1547 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1548 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1549 } else {
1550 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1551 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1552 }
1553 } else {
1554 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1555
1556 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1557 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1558 else
1559 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1560 }
1561
1562 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 1563 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1564 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1565 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1566 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1567
1568 tx_pin = 0;
1569
1570 /* Turn on unused PA or LNA when not using 1T or 1R */
1571 if (rt2x00dev->default_ant.tx != 1) {
1572 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1573 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1574 }
1575
1576 /* Turn on unused PA or LNA when not using 1T or 1R */
1577 if (rt2x00dev->default_ant.rx != 1) {
1578 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1579 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1580 }
1581
1582 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1583 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1584 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1585 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1586 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1587 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1588
1589 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1590
1591 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1592 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1593 rt2800_bbp_write(rt2x00dev, 4, bbp);
1594
1595 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 1596 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1597 rt2800_bbp_write(rt2x00dev, 3, bbp);
1598
8d0c9b65 1599 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 1600 if (conf_is_ht40(conf)) {
1601 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1602 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1603 rt2800_bbp_write(rt2x00dev, 73, 0x16);
1604 } else {
1605 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1606 rt2800_bbp_write(rt2x00dev, 70, 0x08);
1607 rt2800_bbp_write(rt2x00dev, 73, 0x11);
1608 }
1609 }
1610
1611 msleep(1);
1612}
1613
1614static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
5e846004 1615 const int max_txpower)
f4450616 1616{
5e846004
HS		 1617 u8 txpower;
1618 u8 max_value = (u8)max_txpower;
1619 u16 eeprom;
1620 int i;
f4450616 1621 u32 reg;
f4450616 1622 u8 r1;
5e846004 1623 u32 offset;
f4450616 1624
5e846004
HS		 1625 /*
1626 * set to normal tx power mode: +/- 0dBm
1627 */
f4450616 1628 rt2800_bbp_read(rt2x00dev, 1, &r1);
a3f84ca4 1629 rt2x00_set_field8(&r1, BBP1_TX_POWER, 0);
f4450616
BZ		 1630 rt2800_bbp_write(rt2x00dev, 1, r1);
1631
5e846004
HS		 1632 /*
1633 * The eeprom contains the tx power values for each rate. These
1634 * values map to 100% tx power. Each 16bit word contains four tx
1635 * power values and the order is the same as used in the TX_PWR_CFG
1636 * registers.
1637 */
1638 offset = TX_PWR_CFG_0;
1639
1640 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
1641 /* just to be safe */
1642 if (offset > TX_PWR_CFG_4)
1643 break;
1644
1645 rt2800_register_read(rt2x00dev, offset, &reg);
1646
1647 /* read the next four txpower values */
1648 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
1649 &eeprom);
1650
1651 /* TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
1652 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
1653 * TX_PWR_CFG_4: unknown */
1654 txpower = rt2x00_get_field16(eeprom,
1655 EEPROM_TXPOWER_BYRATE_RATE0);
1656 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0,
1657 min(txpower, max_value));
1658
1659 /* TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
1660 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
1661 * TX_PWR_CFG_4: unknown */
1662 txpower = rt2x00_get_field16(eeprom,
1663 EEPROM_TXPOWER_BYRATE_RATE1);
1664 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1,
1665 min(txpower, max_value));
1666
1667 /* TX_PWR_CFG_0: 55MBS, TX_PWR_CFG_1: 48MBS,
1668 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
1669 * TX_PWR_CFG_4: unknown */
1670 txpower = rt2x00_get_field16(eeprom,
1671 EEPROM_TXPOWER_BYRATE_RATE2);
1672 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2,
1673 min(txpower, max_value));
1674
1675 /* TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
1676 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
1677 * TX_PWR_CFG_4: unknown */
1678 txpower = rt2x00_get_field16(eeprom,
1679 EEPROM_TXPOWER_BYRATE_RATE3);
1680 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3,
1681 min(txpower, max_value));
1682
1683 /* read the next four txpower values */
1684 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
1685 &eeprom);
1686
1687 /* TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
1688 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
1689 * TX_PWR_CFG_4: unknown */
1690 txpower = rt2x00_get_field16(eeprom,
1691 EEPROM_TXPOWER_BYRATE_RATE0);
1692 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4,
1693 min(txpower, max_value));
1694
1695 /* TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
1696 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
1697 * TX_PWR_CFG_4: unknown */
1698 txpower = rt2x00_get_field16(eeprom,
1699 EEPROM_TXPOWER_BYRATE_RATE1);
1700 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5,
1701 min(txpower, max_value));
1702
1703 /* TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
1704 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
1705 * TX_PWR_CFG_4: unknown */
1706 txpower = rt2x00_get_field16(eeprom,
1707 EEPROM_TXPOWER_BYRATE_RATE2);
1708 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6,
1709 min(txpower, max_value));
1710
1711 /* TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
1712 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
1713 * TX_PWR_CFG_4: unknown */
1714 txpower = rt2x00_get_field16(eeprom,
1715 EEPROM_TXPOWER_BYRATE_RATE3);
1716 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7,
1717 min(txpower, max_value));
1718
1719 rt2800_register_write(rt2x00dev, offset, reg);
1720
1721 /* next TX_PWR_CFG register */
1722 offset += 4;
1723 }
f4450616
BZ		 1724}
1725
1726static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1727 struct rt2x00lib_conf *libconf)
1728{
1729 u32 reg;
1730
1731 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1732 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1733 libconf->conf->short_frame_max_tx_count);
1734 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1735 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 1736 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1737}
1738
1739static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
1740 struct rt2x00lib_conf *libconf)
1741{
1742 enum dev_state state =
1743 (libconf->conf->flags & IEEE80211_CONF_PS) ?
1744 STATE_SLEEP : STATE_AWAKE;
1745 u32 reg;
1746
1747 if (state == STATE_SLEEP) {
1748 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1749
1750 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1751 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1752 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1753 libconf->conf->listen_interval - 1);
1754 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1755 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1756
1757 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1758 } else {
f4450616
BZ		 1759 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1760 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1761 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1762 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1763 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 1764
1765 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 1766 }
1767}
1768
1769void rt2800_config(struct rt2x00_dev *rt2x00dev,
1770 struct rt2x00lib_conf *libconf,
1771 const unsigned int flags)
1772{
1773 /* Always recalculate LNA gain before changing configuration */
1774 rt2800_config_lna_gain(rt2x00dev, libconf);
1775
1776 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1777 rt2800_config_channel(rt2x00dev, libconf->conf,
1778 &libconf->rf, &libconf->channel);
1779 if (flags & IEEE80211_CONF_CHANGE_POWER)
1780 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1781 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1782 rt2800_config_retry_limit(rt2x00dev, libconf);
1783 if (flags & IEEE80211_CONF_CHANGE_PS)
1784 rt2800_config_ps(rt2x00dev, libconf);
1785}
1786EXPORT_SYMBOL_GPL(rt2800_config);
1787
1788/*
1789 * Link tuning
1790 */
1791void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1792{
1793 u32 reg;
1794
1795 /*
1796 * Update FCS error count from register.
1797 */
1798 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1799 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1800}
1801EXPORT_SYMBOL_GPL(rt2800_link_stats);
1802
1803static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1804{
1805 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
d5385bfc 1806 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 1807 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1808 rt2x00_rt(rt2x00dev, RT3090) ||
1809 rt2x00_rt(rt2x00dev, RT3390))
f4450616
BZ		 1810 return 0x1c + (2 * rt2x00dev->lna_gain);
1811 else
1812 return 0x2e + rt2x00dev->lna_gain;
1813 }
1814
1815 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1816 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1817 else
1818 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1819}
1820
1821static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1822 struct link_qual *qual, u8 vgc_level)
1823{
1824 if (qual->vgc_level != vgc_level) {
1825 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1826 qual->vgc_level = vgc_level;
1827 qual->vgc_level_reg = vgc_level;
1828 }
1829}
1830
1831void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1832{
1833 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1834}
1835EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1836
1837void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1838 const u32 count)
1839{
8d0c9b65 1840 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616
BZ		 1841 return;
1842
1843 /*
1844 * When RSSI is better then -80 increase VGC level with 0x10
1845 */
1846 rt2800_set_vgc(rt2x00dev, qual,
1847 rt2800_get_default_vgc(rt2x00dev) +
1848 ((qual->rssi > -80) * 0x10));
1849}
1850EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 1851
1852/*
1853 * Initialization functions.
1854 */
b9a07ae9 1855static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 1856{
1857 u32 reg;
d5385bfc 1858 u16 eeprom;
fcf51541 1859 unsigned int i;
e3a896b9 1860 int ret;
fcf51541 1861
a9dce149
GW		 1862 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1863 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1864 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1865 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1866 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1867 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1868 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1869
e3a896b9
GW		 1870 ret = rt2800_drv_init_registers(rt2x00dev);
1871 if (ret)
1872 return ret;
fcf51541
BZ		 1873
1874 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1875 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1876 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1877 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1878 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1879 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1880
1881 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1882 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1883 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1884 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1885 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1886 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1887
1888 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1889 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1890
1891 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1892
1893 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
8544df32 1894 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
fcf51541
BZ		 1895 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1896 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1897 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1898 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1899 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1900 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1901
a9dce149
GW		 1902 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
1903
1904 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1905 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
1906 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1907 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1908
64522957 1909 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1910 rt2x00_rt(rt2x00dev, RT3090) ||
1911 rt2x00_rt(rt2x00dev, RT3390)) {
fcf51541
BZ		 1912 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1913 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 1914 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 1915 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1916 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
d5385bfc
GW		 1917 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1918 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1919 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1920 0x0000002c);
1921 else
1922 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1923 0x0000000f);
1924 } else {
1925 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1926 }
d5385bfc 1927 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 1928 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 1929
1930 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1931 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1932 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
1933 } else {
1934 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1935 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1936 }
c295a81d
HS		 1937 } else if (rt2800_is_305x_soc(rt2x00dev)) {
1938 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1939 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1940 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
fcf51541
BZ		 1941 } else {
1942 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1943 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1944 }
1945
1946 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1947 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1948 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1949 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1950 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1951 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1952 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1953 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1954 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1955 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1956
1957 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1958 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 1959 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 1960 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1961 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1962
1963 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1964 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 1965 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 1966 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 1967 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 1968 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1969 else
1970 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1971 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1972 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1973 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1974
a9dce149
GW		 1975 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1976 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
1977 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
1978 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
1979 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
1980 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
1981 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
1982 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
1983 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1984
fcf51541
BZ		 1985 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1986
a9dce149
GW		 1987 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1988 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
1989 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
1990 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1991 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1992 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1993 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1994 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1995
fcf51541
BZ		 1996 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1997 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 1998 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 1999 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
2000 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 2001 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 2002 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
2003 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
2004 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2005
2006 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 2007 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541
BZ		 2008 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
2009 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
2010 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2011 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2012 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 2013 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 2014 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 2015 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2016 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 2017 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2018
2019 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 2020 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541
BZ		 2021 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
2022 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
2023 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2024 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2025 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 2026 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 2027 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 2028 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2029 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 2030 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2031
2032 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2033 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2034 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
2035 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
2036 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2037 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2038 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2039 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2040 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2041 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 2042 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2043 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2044
2045 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2046 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
d13a97f0 2047 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
fcf51541
BZ		 2048 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
2049 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2050 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2051 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2052 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2053 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2054 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 2055 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2056 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2057
2058 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2059 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2060 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
2061 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
2062 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2063 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2064 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2065 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2066 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2067 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 2068 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2069 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2070
2071 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2072 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2073 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
2074 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
2075 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2076 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2077 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2078 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2079 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2080 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 2081 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2082 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2083
cea90e55 2084 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 2085 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
2086
2087 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2088 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2089 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2090 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2091 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2092 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
2093 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
2094 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
2095 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
2096 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
2097 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2098 }
2099
2100 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
2101 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
2102
2103 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2104 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
2105 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
2106 IEEE80211_MAX_RTS_THRESHOLD);
2107 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
2108 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2109
2110 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 2111
a21c2ab4
HS		 2112 /*
2113 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
2114 * time should be set to 16. However, the original Ralink driver uses
2115 * 16 for both and indeed using a value of 10 for CCK SIFS results in
2116 * connection problems with 11g + CTS protection. Hence, use the same
2117 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
2118 */
a9dce149 2119 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 2120 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
2121 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 2122 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
2123 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
2124 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
2125 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2126
fcf51541
BZ		 2127 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
2128
2129 /*
2130 * ASIC will keep garbage value after boot, clear encryption keys.
2131 */
2132 for (i = 0; i < 4; i++)
2133 rt2800_register_write(rt2x00dev,
2134 SHARED_KEY_MODE_ENTRY(i), 0);
2135
2136 for (i = 0; i < 256; i++) {
2137 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
2138 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
2139 wcid, sizeof(wcid));
2140
2141 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
2142 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
2143 }
2144
2145 /*
2146 * Clear all beacons
fcf51541 2147 */
fdb87251
HS		 2148 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE0);
2149 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE1);
2150 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE2);
2151 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE3);
2152 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE4);
2153 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE5);
2154 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE6);
2155 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE7);
fcf51541 2156
cea90e55 2157 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 2158 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2159 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
2160 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 2161 }
2162
2163 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
2164 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
2165 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
2166 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
2167 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
2168 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
2169 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
2170 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
2171 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
2172 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
2173
2174 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
2175 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
2176 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
2177 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
2178 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
2179 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
2180 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
2181 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
2182 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
2183 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
2184
2185 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
2186 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
2187 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
2188 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
2189 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
2190 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
2191 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
2192 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
2193 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
2194 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
2195
2196 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
2197 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
2198 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
2199 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
2200 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
2201 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
2202
47ee3eb1
HS		 2203 /*
2204 * Do not force the BA window size, we use the TXWI to set it
2205 */
2206 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
2207 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
2208 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
2209 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
2210
fcf51541
BZ		 2211 /*
2212 * We must clear the error counters.
2213 * These registers are cleared on read,
2214 * so we may pass a useless variable to store the value.
2215 */
2216 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2217 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
2218 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
2219 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
2220 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
2221 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
2222
9f926fb5
HS		 2223 /*
2224 * Setup leadtime for pre tbtt interrupt to 6ms
2225 */
2226 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
2227 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
2228 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
2229
fcf51541
BZ		 2230 return 0;
2231}
fcf51541
BZ		 2232
2233static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
2234{
2235 unsigned int i;
2236 u32 reg;
2237
2238 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2239 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
2240 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
2241 return 0;
2242
2243 udelay(REGISTER_BUSY_DELAY);
2244 }
2245
2246 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
2247 return -EACCES;
2248}
2249
2250static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2251{
2252 unsigned int i;
2253 u8 value;
2254
2255 /*
2256 * BBP was enabled after firmware was loaded,
2257 * but we need to reactivate it now.
2258 */
2259 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2260 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2261 msleep(1);
2262
2263 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2264 rt2800_bbp_read(rt2x00dev, 0, &value);
2265 if ((value != 0xff) && (value != 0x00))
2266 return 0;
2267 udelay(REGISTER_BUSY_DELAY);
2268 }
2269
2270 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
2271 return -EACCES;
2272}
2273
b9a07ae9 2274static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 2275{
2276 unsigned int i;
2277 u16 eeprom;
2278 u8 reg_id;
2279 u8 value;
2280
2281 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
2282 rt2800_wait_bbp_ready(rt2x00dev)))
2283 return -EACCES;
2284
baff8006
HS		 2285 if (rt2800_is_305x_soc(rt2x00dev))
2286 rt2800_bbp_write(rt2x00dev, 31, 0x08);
2287
fcf51541
BZ		 2288 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
2289 rt2800_bbp_write(rt2x00dev, 66, 0x38);
a9dce149
GW		 2290
2291 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2292 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2293 rt2800_bbp_write(rt2x00dev, 73, 0x12);
2294 } else {
2295 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2296 rt2800_bbp_write(rt2x00dev, 73, 0x10);
2297 }
2298
fcf51541 2299 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
8cdd15e0 2300
d5385bfc 2301 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 2302 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2303 rt2x00_rt(rt2x00dev, RT3090) ||
2304 rt2x00_rt(rt2x00dev, RT3390)) {
8cdd15e0
GW		 2305 rt2800_bbp_write(rt2x00dev, 79, 0x13);
2306 rt2800_bbp_write(rt2x00dev, 80, 0x05);
2307 rt2800_bbp_write(rt2x00dev, 81, 0x33);
baff8006
HS		 2308 } else if (rt2800_is_305x_soc(rt2x00dev)) {
2309 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
2310 rt2800_bbp_write(rt2x00dev, 80, 0x08);
8cdd15e0
GW		 2311 } else {
2312 rt2800_bbp_write(rt2x00dev, 81, 0x37);
2313 }
2314
fcf51541
BZ		 2315 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2316 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
a9dce149 2317
5ed8f458 2318 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
a9dce149
GW		 2319 rt2800_bbp_write(rt2x00dev, 84, 0x19);
2320 else
2321 rt2800_bbp_write(rt2x00dev, 84, 0x99);
2322
fcf51541
BZ		 2323 rt2800_bbp_write(rt2x00dev, 86, 0x00);
2324 rt2800_bbp_write(rt2x00dev, 91, 0x04);
2325 rt2800_bbp_write(rt2x00dev, 92, 0x00);
8cdd15e0 2326
d5385bfc 2327 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 2328 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904 2329 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
baff8006
HS		 2330 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
2331 rt2800_is_305x_soc(rt2x00dev))
8cdd15e0
GW		 2332 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
2333 else
2334 rt2800_bbp_write(rt2x00dev, 103, 0x00);
2335
baff8006
HS		 2336 if (rt2800_is_305x_soc(rt2x00dev))
2337 rt2800_bbp_write(rt2x00dev, 105, 0x01);
2338 else
2339 rt2800_bbp_write(rt2x00dev, 105, 0x05);
a9dce149 2340 rt2800_bbp_write(rt2x00dev, 106, 0x35);
fcf51541 2341
64522957 2342 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2343 rt2x00_rt(rt2x00dev, RT3090) ||
2344 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc 2345 rt2800_bbp_read(rt2x00dev, 138, &value);
fcf51541 2346
d5385bfc
GW		 2347 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2348 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
2349 value |= 0x20;
2350 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
2351 value &= ~0x02;
fcf51541 2352
d5385bfc 2353 rt2800_bbp_write(rt2x00dev, 138, value);
fcf51541
BZ		 2354 }
2355
fcf51541
BZ		 2356
2357 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
2358 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
2359
2360 if (eeprom != 0xffff && eeprom != 0x0000) {
2361 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
2362 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
2363 rt2800_bbp_write(rt2x00dev, reg_id, value);
2364 }
2365 }
2366
2367 return 0;
2368}
fcf51541
BZ		 2369
2370static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
2371 bool bw40, u8 rfcsr24, u8 filter_target)
2372{
2373 unsigned int i;
2374 u8 bbp;
2375 u8 rfcsr;
2376 u8 passband;
2377 u8 stopband;
2378 u8 overtuned = 0;
2379
2380 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2381
2382 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2383 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
2384 rt2800_bbp_write(rt2x00dev, 4, bbp);
2385
2386 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2387 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
2388 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2389
2390 /*
2391 * Set power & frequency of passband test tone
2392 */
2393 rt2800_bbp_write(rt2x00dev, 24, 0);
2394
2395 for (i = 0; i < 100; i++) {
2396 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2397 msleep(1);
2398
2399 rt2800_bbp_read(rt2x00dev, 55, &passband);
2400 if (passband)
2401 break;
2402 }
2403
2404 /*
2405 * Set power & frequency of stopband test tone
2406 */
2407 rt2800_bbp_write(rt2x00dev, 24, 0x06);
2408
2409 for (i = 0; i < 100; i++) {
2410 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2411 msleep(1);
2412
2413 rt2800_bbp_read(rt2x00dev, 55, &stopband);
2414
2415 if ((passband - stopband) <= filter_target) {
2416 rfcsr24++;
2417 overtuned += ((passband - stopband) == filter_target);
2418 } else
2419 break;
2420
2421 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2422 }
2423
2424 rfcsr24 -= !!overtuned;
2425
2426 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2427 return rfcsr24;
2428}
2429
b9a07ae9 2430static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 2431{
2432 u8 rfcsr;
2433 u8 bbp;
8cdd15e0
GW		 2434 u32 reg;
2435 u16 eeprom;
fcf51541 2436
d5385bfc 2437 if (!rt2x00_rt(rt2x00dev, RT3070) &&
64522957 2438 !rt2x00_rt(rt2x00dev, RT3071) &&
cc78e904 2439 !rt2x00_rt(rt2x00dev, RT3090) &&
23812383 2440 !rt2x00_rt(rt2x00dev, RT3390) &&
baff8006 2441 !rt2800_is_305x_soc(rt2x00dev))
fcf51541
BZ		 2442 return 0;
2443
fcf51541
BZ		 2444 /*
2445 * Init RF calibration.
2446 */
2447 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2448 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2449 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2450 msleep(1);
2451 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2452 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2453
d5385bfc 2454 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957
GW		 2455 rt2x00_rt(rt2x00dev, RT3071) ||
2456 rt2x00_rt(rt2x00dev, RT3090)) {
fcf51541
BZ		 2457 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2458 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2459 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2460 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
2461 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
8cdd15e0 2462 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
fcf51541
BZ		 2463 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2464 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
2465 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2466 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2467 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2468 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2469 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2470 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2471 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2472 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2473 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
2474 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
fcf51541 2475 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
cc78e904
GW		 2476 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2477 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
2478 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
2479 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
2480 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
fcf51541 2481 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
cc78e904
GW		 2482 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
2483 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
2484 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
2485 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
2486 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2487 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
fcf51541 2488 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
cc78e904
GW		 2489 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
2490 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
fcf51541 2491 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
cc78e904
GW		 2492 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2493 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
2494 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
2495 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
2496 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
2497 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
2498 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
fcf51541 2499 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
cc78e904 2500 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
fcf51541 2501 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
cc78e904
GW		 2502 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2503 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2504 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2505 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
2506 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
2507 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
2508 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
baff8006 2509 } else if (rt2800_is_305x_soc(rt2x00dev)) {
23812383
HS		 2510 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
2511 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
2512 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
2513 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
2514 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2515 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2516 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2517 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
2518 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
2519 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2520 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
2521 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2522 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
2523 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
2524 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2525 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2526 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2527 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2528 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2529 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2530 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2531 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2532 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2533 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
2534 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2535 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2536 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
2537 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
2538 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
2539 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
baff8006
HS		 2540 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
2541 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
2542 return 0;
8cdd15e0
GW		 2543 }
2544
2545 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2546 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2547 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
2548 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2549 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
64522957
GW		 2550 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2551 rt2x00_rt(rt2x00dev, RT3090)) {
d5385bfc
GW		 2552 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2553 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
2554 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2555
2556 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
2557
2558 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2559 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
64522957
GW		 2560 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2561 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
d5385bfc
GW		 2562 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2563 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
2564 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2565 else
2566 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
2567 }
2568 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
cc78e904
GW		 2569 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2570 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
2571 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
2572 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
fcf51541
BZ		 2573 }
2574
2575 /*
2576 * Set RX Filter calibration for 20MHz and 40MHz
2577 */
8cdd15e0
GW		 2578 if (rt2x00_rt(rt2x00dev, RT3070)) {
2579 rt2x00dev->calibration[0] =
2580 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
2581 rt2x00dev->calibration[1] =
2582 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
64522957 2583 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2584 rt2x00_rt(rt2x00dev, RT3090) ||
2585 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 2586 rt2x00dev->calibration[0] =
2587 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
2588 rt2x00dev->calibration[1] =
2589 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
8cdd15e0 2590 }
fcf51541
BZ		 2591
2592 /*
2593 * Set back to initial state
2594 */
2595 rt2800_bbp_write(rt2x00dev, 24, 0);
2596
2597 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2598 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
2599 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2600
2601 /*
2602 * set BBP back to BW20
2603 */
2604 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2605 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
2606 rt2800_bbp_write(rt2x00dev, 4, bbp);
2607
d5385bfc 2608 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 2609 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2610 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2611 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
8cdd15e0
GW		 2612 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
2613
2614 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
2615 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
2616 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
2617
2618 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2619 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
64522957 2620 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2621 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2622 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
8440c292 2623 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
d5385bfc
GW		 2624 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
2625 }
8cdd15e0
GW		 2626 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
2627 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
2628 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
2629 rt2x00_get_field16(eeprom,
2630 EEPROM_TXMIXER_GAIN_BG_VAL));
2631 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2632
64522957
GW		 2633 if (rt2x00_rt(rt2x00dev, RT3090)) {
2634 rt2800_bbp_read(rt2x00dev, 138, &bbp);
2635
2636 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2637 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
2638 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
2639 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
2640 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
2641
2642 rt2800_bbp_write(rt2x00dev, 138, bbp);
2643 }
2644
2645 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2646 rt2x00_rt(rt2x00dev, RT3090) ||
2647 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 2648 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2649 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2650 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2651 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2652 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2653 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2654 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2655
2656 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
2657 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
2658 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
2659
2660 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
2661 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
2662 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
2663
2664 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
2665 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
2666 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
2667 }
2668
2669 if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) {
8cdd15e0 2670 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
d5385bfc
GW		 2671 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2672 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
8cdd15e0
GW		 2673 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
2674 else
2675 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
2676 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
2677 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
2678 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
2679 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
2680 }
2681
fcf51541
BZ		 2682 return 0;
2683}
b9a07ae9
ID		 2684
2685int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
2686{
2687 u32 reg;
2688 u16 word;
2689
2690 /*
2691 * Initialize all registers.
2692 */
2693 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
2694 rt2800_init_registers(rt2x00dev) ||
2695 rt2800_init_bbp(rt2x00dev) ||
2696 rt2800_init_rfcsr(rt2x00dev)))
2697 return -EIO;
2698
2699 /*
2700 * Send signal to firmware during boot time.
2701 */
2702 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
2703
2704 if (rt2x00_is_usb(rt2x00dev) &&
2705 (rt2x00_rt(rt2x00dev, RT3070) ||
2706 rt2x00_rt(rt2x00dev, RT3071) ||
2707 rt2x00_rt(rt2x00dev, RT3572))) {
2708 udelay(200);
2709 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
2710 udelay(10);
2711 }
2712
2713 /*
2714 * Enable RX.
2715 */
2716 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2717 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2718 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2719 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2720
2721 udelay(50);
2722
2723 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2724 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
2725 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
2726 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
2727 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2728 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2729
2730 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2731 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2732 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
2733 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2734
2735 /*
2736 * Initialize LED control
2737 */
2738 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
2739 rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
2740 word & 0xff, (word >> 8) & 0xff);
2741
2742 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
2743 rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
2744 word & 0xff, (word >> 8) & 0xff);
2745
2746 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
2747 rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
2748 word & 0xff, (word >> 8) & 0xff);
2749
2750 return 0;
2751}
2752EXPORT_SYMBOL_GPL(rt2800_enable_radio);
2753
2754void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
2755{
2756 u32 reg;
2757
2758 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2759 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2760 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2761 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2762 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2763 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2764 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2765
2766 /* Wait for DMA, ignore error */
2767 rt2800_wait_wpdma_ready(rt2x00dev);
2768
2769 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2770 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
2771 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2772 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2773
2774 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
2775 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
2776}
2777EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2ce33995 2778
30e84034
BZ		 2779int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
2780{
2781 u32 reg;
2782
2783 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
2784
2785 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
2786}
2787EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
2788
2789static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
2790{
2791 u32 reg;
2792
31a4cf1f
GW		 2793 mutex_lock(&rt2x00dev->csr_mutex);
2794
2795 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
30e84034
BZ		 2796 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
2797 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
2798 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
31a4cf1f 2799 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
30e84034
BZ		 2800
2801 /* Wait until the EEPROM has been loaded */
2802 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
2803
2804 /* Apparently the data is read from end to start */
31a4cf1f
GW		 2805 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
2806 (u32 *)&rt2x00dev->eeprom[i]);
2807 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
2808 (u32 *)&rt2x00dev->eeprom[i + 2]);
2809 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
2810 (u32 *)&rt2x00dev->eeprom[i + 4]);
2811 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
2812 (u32 *)&rt2x00dev->eeprom[i + 6]);
2813
2814 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 2815}
2816
2817void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
2818{
2819 unsigned int i;
2820
2821 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
2822 rt2800_efuse_read(rt2x00dev, i);
2823}
2824EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
2825
38bd7b8a
BZ		 2826int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2827{
2828 u16 word;
2829 u8 *mac;
2830 u8 default_lna_gain;
2831
2832 /*
2833 * Start validation of the data that has been read.
2834 */
2835 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2836 if (!is_valid_ether_addr(mac)) {
2837 random_ether_addr(mac);
2838 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2839 }
2840
2841 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2842 if (word == 0xffff) {
2843 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2844 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2845 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2846 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2847 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 2848 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 2849 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 2850 /*
2851 * There is a max of 2 RX streams for RT28x0 series
2852 */
2853 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2854 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2855 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2856 }
2857
2858 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2859 if (word == 0xffff) {
2860 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2861 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2862 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2863 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2864 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2865 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2866 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2867 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2868 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2869 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
ec2d1791
GW		 2870 rt2x00_set_field16(&word, EEPROM_NIC_ANT_DIVERSITY, 0);
2871 rt2x00_set_field16(&word, EEPROM_NIC_DAC_TEST, 0);
38bd7b8a
BZ		 2872 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2873 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2874 }
2875
2876 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2877 if ((word & 0x00ff) == 0x00ff) {
2878 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
ec2d1791
GW		 2879 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2880 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2881 }
2882 if ((word & 0xff00) == 0xff00) {
38bd7b8a
BZ		 2883 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2884 LED_MODE_TXRX_ACTIVITY);
2885 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2886 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2887 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2888 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2889 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
ec2d1791 2890 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
38bd7b8a
BZ		 2891 }
2892
2893 /*
2894 * During the LNA validation we are going to use
2895 * lna0 as correct value. Note that EEPROM_LNA
2896 * is never validated.
2897 */
2898 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2899 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2900
2901 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2902 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2903 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2904 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2905 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2906 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2907
2908 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2909 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2910 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2911 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2912 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2913 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2914 default_lna_gain);
2915 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2916
2917 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2918 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2919 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2920 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2921 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2922 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2923
2924 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2925 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2926 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2927 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2928 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2929 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2930 default_lna_gain);
2931 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2932
8d1331b3
ID		 2933 rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &word);
2934 if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_24GHZ) == 0xff)
2935 rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_24GHZ, MAX_G_TXPOWER);
2936 if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_5GHZ) == 0xff)
2937 rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_5GHZ, MAX_A_TXPOWER);
2938 rt2x00_eeprom_write(rt2x00dev, EEPROM_MAX_TX_POWER, word);
2939
38bd7b8a
BZ		 2940 return 0;
2941}
2942EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
2943
2944int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
2945{
2946 u32 reg;
2947 u16 value;
2948 u16 eeprom;
2949
2950 /*
2951 * Read EEPROM word for configuration.
2952 */
2953 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2954
2955 /*
2956 * Identify RF chipset.
2957 */
2958 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2959 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2960
49e721ec
GW		 2961 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2962 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2963
2964 if (!rt2x00_rt(rt2x00dev, RT2860) &&
49e721ec 2965 !rt2x00_rt(rt2x00dev, RT2872) &&
49e721ec 2966 !rt2x00_rt(rt2x00dev, RT2883) &&
49e721ec
GW		 2967 !rt2x00_rt(rt2x00dev, RT3070) &&
2968 !rt2x00_rt(rt2x00dev, RT3071) &&
2969 !rt2x00_rt(rt2x00dev, RT3090) &&
2970 !rt2x00_rt(rt2x00dev, RT3390) &&
2971 !rt2x00_rt(rt2x00dev, RT3572)) {
2972 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2973 return -ENODEV;
f273fe55 2974 }
714fa663 2975
5122d898
GW		 2976 if (!rt2x00_rf(rt2x00dev, RF2820) &&
2977 !rt2x00_rf(rt2x00dev, RF2850) &&
2978 !rt2x00_rf(rt2x00dev, RF2720) &&
2979 !rt2x00_rf(rt2x00dev, RF2750) &&
2980 !rt2x00_rf(rt2x00dev, RF3020) &&
2981 !rt2x00_rf(rt2x00dev, RF2020) &&
2982 !rt2x00_rf(rt2x00dev, RF3021) &&
6c0fe265
GW		 2983 !rt2x00_rf(rt2x00dev, RF3022) &&
2984 !rt2x00_rf(rt2x00dev, RF3052)) {
38bd7b8a
BZ		 2985 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2986 return -ENODEV;
2987 }
2988
2989 /*
2990 * Identify default antenna configuration.
2991 */
2992 rt2x00dev->default_ant.tx =
2993 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2994 rt2x00dev->default_ant.rx =
2995 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2996
2997 /*
2998 * Read frequency offset and RF programming sequence.
2999 */
3000 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
3001 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
3002
3003 /*
3004 * Read external LNA informations.
3005 */
3006 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
3007
3008 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
3009 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
3010 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
3011 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
3012
3013 /*
3014 * Detect if this device has an hardware controlled radio.
3015 */
3016 if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
3017 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
3018
3019 /*
3020 * Store led settings, for correct led behaviour.
3021 */
3022#ifdef CONFIG_RT2X00_LIB_LEDS
3023 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3024 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
3025 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
3026
3027 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
3028#endif /* CONFIG_RT2X00_LIB_LEDS */
3029
3030 return 0;
3031}
3032EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
3033
4da2933f 3034/*
55f9321a 3035 * RF value list for rt28xx
4da2933f
BZ		 3036 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
3037 */
3038static const struct rf_channel rf_vals[] = {
3039 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
3040 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
3041 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
3042 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
3043 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
3044 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
3045 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
3046 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
3047 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
3048 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
3049 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
3050 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
3051 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
3052 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
3053
3054 /* 802.11 UNI / HyperLan 2 */
3055 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
3056 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
3057 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
3058 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
3059 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
3060 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
3061 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
3062 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
3063 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
3064 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
3065 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
3066 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
3067
3068 /* 802.11 HyperLan 2 */
3069 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
3070 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
3071 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
3072 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
3073 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
3074 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
3075 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
3076 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
3077 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
3078 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
3079 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
3080 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
3081 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
3082 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
3083 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
3084 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
3085
3086 /* 802.11 UNII */
3087 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
3088 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
3089 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
3090 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
3091 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
3092 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
3093 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
3094 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
3095 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
3096 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
3097 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
3098
3099 /* 802.11 Japan */
3100 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
3101 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
3102 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
3103 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
3104 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
3105 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
3106 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
3107};
3108
3109/*
55f9321a
ID		 3110 * RF value list for rt3xxx
3111 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4da2933f 3112 */
55f9321a 3113static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 3114 {1, 241, 2, 2 },
3115 {2, 241, 2, 7 },
3116 {3, 242, 2, 2 },
3117 {4, 242, 2, 7 },
3118 {5, 243, 2, 2 },
3119 {6, 243, 2, 7 },
3120 {7, 244, 2, 2 },
3121 {8, 244, 2, 7 },
3122 {9, 245, 2, 2 },
3123 {10, 245, 2, 7 },
3124 {11, 246, 2, 2 },
3125 {12, 246, 2, 7 },
3126 {13, 247, 2, 2 },
3127 {14, 248, 2, 4 },
55f9321a
ID		 3128
3129 /* 802.11 UNI / HyperLan 2 */
3130 {36, 0x56, 0, 4},
3131 {38, 0x56, 0, 6},
3132 {40, 0x56, 0, 8},
3133 {44, 0x57, 0, 0},
3134 {46, 0x57, 0, 2},
3135 {48, 0x57, 0, 4},
3136 {52, 0x57, 0, 8},
3137 {54, 0x57, 0, 10},
3138 {56, 0x58, 0, 0},
3139 {60, 0x58, 0, 4},
3140 {62, 0x58, 0, 6},
3141 {64, 0x58, 0, 8},
3142
3143 /* 802.11 HyperLan 2 */
3144 {100, 0x5b, 0, 8},
3145 {102, 0x5b, 0, 10},
3146 {104, 0x5c, 0, 0},
3147 {108, 0x5c, 0, 4},
3148 {110, 0x5c, 0, 6},
3149 {112, 0x5c, 0, 8},
3150 {116, 0x5d, 0, 0},
3151 {118, 0x5d, 0, 2},
3152 {120, 0x5d, 0, 4},
3153 {124, 0x5d, 0, 8},
3154 {126, 0x5d, 0, 10},
3155 {128, 0x5e, 0, 0},
3156 {132, 0x5e, 0, 4},
3157 {134, 0x5e, 0, 6},
3158 {136, 0x5e, 0, 8},
3159 {140, 0x5f, 0, 0},
3160
3161 /* 802.11 UNII */
3162 {149, 0x5f, 0, 9},
3163 {151, 0x5f, 0, 11},
3164 {153, 0x60, 0, 1},
3165 {157, 0x60, 0, 5},
3166 {159, 0x60, 0, 7},
3167 {161, 0x60, 0, 9},
3168 {165, 0x61, 0, 1},
3169 {167, 0x61, 0, 3},
3170 {169, 0x61, 0, 5},
3171 {171, 0x61, 0, 7},
3172 {173, 0x61, 0, 9},
4da2933f
BZ		 3173};
3174
3175int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
3176{
4da2933f
BZ		 3177 struct hw_mode_spec *spec = &rt2x00dev->spec;
3178 struct channel_info *info;
8d1331b3
ID		 3179 char *default_power1;
3180 char *default_power2;
4da2933f 3181 unsigned int i;
8d1331b3 3182 unsigned short max_power;
4da2933f
BZ		 3183 u16 eeprom;
3184
93b6bd26
GW		 3185 /*
3186 * Disable powersaving as default on PCI devices.
3187 */
cea90e55 3188 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
93b6bd26
GW		 3189 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3190
4da2933f
BZ		 3191 /*
3192 * Initialize all hw fields.
3193 */
3194 rt2x00dev->hw->flags =
4da2933f
BZ		 3195 IEEE80211_HW_SIGNAL_DBM |
3196 IEEE80211_HW_SUPPORTS_PS |
1df90809
HS		 3197 IEEE80211_HW_PS_NULLFUNC_STACK |
3198 IEEE80211_HW_AMPDU_AGGREGATION;
5a5b6ed6
HS		 3199 /*
3200 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
3201 * unless we are capable of sending the buffered frames out after the
3202 * DTIM transmission using rt2x00lib_beacondone. This will send out
3203 * multicast and broadcast traffic immediately instead of buffering it
3204 * infinitly and thus dropping it after some time.
3205 */
3206 if (!rt2x00_is_usb(rt2x00dev))
3207 rt2x00dev->hw->flags |=
3208 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
4da2933f 3209
4da2933f
BZ		 3210 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
3211 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3212 rt2x00_eeprom_addr(rt2x00dev,
3213 EEPROM_MAC_ADDR_0));
3214
3f2bee24
HS		 3215 /*
3216 * As rt2800 has a global fallback table we cannot specify
3217 * more then one tx rate per frame but since the hw will
3218 * try several rates (based on the fallback table) we should
ba3b9e5e 3219 * initialize max_report_rates to the maximum number of rates
3f2bee24
HS		 3220 * we are going to try. Otherwise mac80211 will truncate our
3221 * reported tx rates and the rc algortihm will end up with
3222 * incorrect data.
3223 */
ba3b9e5e
HS		 3224 rt2x00dev->hw->max_rates = 1;
3225 rt2x00dev->hw->max_report_rates = 7;
3f2bee24
HS		 3226 rt2x00dev->hw->max_rate_tries = 1;
3227
4da2933f
BZ		 3228 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
3229
3230 /*
3231 * Initialize hw_mode information.
3232 */
3233 spec->supported_bands = SUPPORT_BAND_2GHZ;
3234 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
3235
5122d898 3236 if (rt2x00_rf(rt2x00dev, RF2820) ||
55f9321a 3237 rt2x00_rf(rt2x00dev, RF2720)) {
4da2933f
BZ		 3238 spec->num_channels = 14;
3239 spec->channels = rf_vals;
55f9321a
ID		 3240 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
3241 rt2x00_rf(rt2x00dev, RF2750)) {
4da2933f
BZ		 3242 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3243 spec->num_channels = ARRAY_SIZE(rf_vals);
3244 spec->channels = rf_vals;
5122d898
GW		 3245 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
3246 rt2x00_rf(rt2x00dev, RF2020) ||
3247 rt2x00_rf(rt2x00dev, RF3021) ||
3248 rt2x00_rf(rt2x00dev, RF3022)) {
55f9321a
ID		 3249 spec->num_channels = 14;
3250 spec->channels = rf_vals_3x;
3251 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
3252 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3253 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
3254 spec->channels = rf_vals_3x;
4da2933f
BZ		 3255 }
3256
3257 /*
3258 * Initialize HT information.
3259 */
5122d898 3260 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 3261 spec->ht.ht_supported = true;
3262 else
3263 spec->ht.ht_supported = false;
3264
4da2933f 3265 spec->ht.cap =
06443e46 3266 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 3267 IEEE80211_HT_CAP_GRN_FLD |
3268 IEEE80211_HT_CAP_SGI_20 |
aa674631 3269 IEEE80211_HT_CAP_SGI_40;
22cabaa6
HS		 3270
3271 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) >= 2)
3272 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
3273
aa674631
ID		 3274 spec->ht.cap |=
3275 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) <<
3276 IEEE80211_HT_CAP_RX_STBC_SHIFT;
3277
4da2933f
BZ		 3278 spec->ht.ampdu_factor = 3;
3279 spec->ht.ampdu_density = 4;
3280 spec->ht.mcs.tx_params =
3281 IEEE80211_HT_MCS_TX_DEFINED |
3282 IEEE80211_HT_MCS_TX_RX_DIFF |
3283 ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
3284 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
3285
3286 switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
3287 case 3:
3288 spec->ht.mcs.rx_mask[2] = 0xff;
3289 case 2:
3290 spec->ht.mcs.rx_mask[1] = 0xff;
3291 case 1:
3292 spec->ht.mcs.rx_mask[0] = 0xff;
3293 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
3294 break;
3295 }
3296
3297 /*
3298 * Create channel information array
3299 */
3300 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
3301 if (!info)
3302 return -ENOMEM;
3303
3304 spec->channels_info = info;
3305
8d1331b3
ID		 3306 rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &eeprom);
3307 max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_24GHZ);
3308 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
3309 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4da2933f
BZ		 3310
3311 for (i = 0; i < 14; i++) {
8d1331b3
ID		 3312 info[i].max_power = max_power;
3313 info[i].default_power1 = TXPOWER_G_FROM_DEV(default_power1[i]);
3314 info[i].default_power2 = TXPOWER_G_FROM_DEV(default_power2[i]);
4da2933f
BZ		 3315 }
3316
3317 if (spec->num_channels > 14) {
8d1331b3
ID		 3318 max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_5GHZ);
3319 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
3320 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4da2933f
BZ		 3321
3322 for (i = 14; i < spec->num_channels; i++) {
8d1331b3
ID		 3323 info[i].max_power = max_power;
3324 info[i].default_power1 = TXPOWER_A_FROM_DEV(default_power1[i]);
3325 info[i].default_power2 = TXPOWER_A_FROM_DEV(default_power2[i]);
4da2933f
BZ		 3326 }
3327 }
3328
3329 return 0;
3330}
3331EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
3332
2ce33995
BZ		 3333/*
3334 * IEEE80211 stack callback functions.
3335 */
e783619e
HS		 3336void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
3337 u16 *iv16)
2ce33995
BZ		 3338{
3339 struct rt2x00_dev *rt2x00dev = hw->priv;
3340 struct mac_iveiv_entry iveiv_entry;
3341 u32 offset;
3342
3343 offset = MAC_IVEIV_ENTRY(hw_key_idx);
3344 rt2800_register_multiread(rt2x00dev, offset,
3345 &iveiv_entry, sizeof(iveiv_entry));
3346
855da5e0
JL		 3347 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
3348 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995 3349}
e783619e 3350EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
2ce33995 3351
e783619e 3352int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2ce33995
BZ		 3353{
3354 struct rt2x00_dev *rt2x00dev = hw->priv;
3355 u32 reg;
3356 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
3357
3358 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3359 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
3360 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3361
3362 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3363 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
3364 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3365
3366 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3367 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
3368 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3369
3370 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3371 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
3372 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3373
3374 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3375 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
3376 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3377
3378 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3379 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
3380 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3381
3382 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3383 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
3384 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3385
3386 return 0;
3387}
e783619e 3388EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2ce33995 3389
e783619e
HS		 3390int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
3391 const struct ieee80211_tx_queue_params *params)
2ce33995
BZ		 3392{
3393 struct rt2x00_dev *rt2x00dev = hw->priv;
3394 struct data_queue *queue;
3395 struct rt2x00_field32 field;
3396 int retval;
3397 u32 reg;
3398 u32 offset;
3399
3400 /*
3401 * First pass the configuration through rt2x00lib, that will
3402 * update the queue settings and validate the input. After that
3403 * we are free to update the registers based on the value
3404 * in the queue parameter.
3405 */
3406 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
3407 if (retval)
3408 return retval;
3409
3410 /*
3411 * We only need to perform additional register initialization
3412 * for WMM queues/
3413 */
3414 if (queue_idx >= 4)
3415 return 0;
3416
3417 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
3418
3419 /* Update WMM TXOP register */
3420 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
3421 field.bit_offset = (queue_idx & 1) * 16;
3422 field.bit_mask = 0xffff << field.bit_offset;
3423
3424 rt2800_register_read(rt2x00dev, offset, &reg);
3425 rt2x00_set_field32(&reg, field, queue->txop);
3426 rt2800_register_write(rt2x00dev, offset, reg);
3427
3428 /* Update WMM registers */
3429 field.bit_offset = queue_idx * 4;
3430 field.bit_mask = 0xf << field.bit_offset;
3431
3432 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
3433 rt2x00_set_field32(&reg, field, queue->aifs);
3434 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
3435
3436 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
3437 rt2x00_set_field32(&reg, field, queue->cw_min);
3438 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
3439
3440 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
3441 rt2x00_set_field32(&reg, field, queue->cw_max);
3442 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
3443
3444 /* Update EDCA registers */
3445 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
3446
3447 rt2800_register_read(rt2x00dev, offset, &reg);
3448 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
3449 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
3450 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
3451 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
3452 rt2800_register_write(rt2x00dev, offset, reg);
3453
3454 return 0;
3455}
e783619e 3456EXPORT_SYMBOL_GPL(rt2800_conf_tx);
2ce33995 3457
e783619e 3458u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2ce33995
BZ		 3459{
3460 struct rt2x00_dev *rt2x00dev = hw->priv;
3461 u64 tsf;
3462 u32 reg;
3463
3464 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
3465 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
3466 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
3467 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
3468
3469 return tsf;
3470}
e783619e 3471EXPORT_SYMBOL_GPL(rt2800_get_tsf);
2ce33995 3472
e783619e
HS		 3473int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3474 enum ieee80211_ampdu_mlme_action action,
3475 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
1df90809 3476{
1df90809
HS		 3477 int ret = 0;
3478
3479 switch (action) {
3480 case IEEE80211_AMPDU_RX_START:
3481 case IEEE80211_AMPDU_RX_STOP:
58ed826e
HS		 3482 /*
3483 * The hw itself takes care of setting up BlockAck mechanisms.
3484 * So, we only have to allow mac80211 to nagotiate a BlockAck
3485 * agreement. Once that is done, the hw will BlockAck incoming
3486 * AMPDUs without further setup.
3487 */
1df90809
HS		 3488 break;
3489 case IEEE80211_AMPDU_TX_START:
3490 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3491 break;
3492 case IEEE80211_AMPDU_TX_STOP:
3493 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3494 break;
3495 case IEEE80211_AMPDU_TX_OPERATIONAL:
3496 break;
3497 default:
4e9e58c6 3498 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
1df90809
HS		 3499 }
3500
3501 return ret;
3502}
e783619e 3503EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
a5ea2f02
ID		 3504
3505MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
3506MODULE_VERSION(DRV_VERSION);
3507MODULE_DESCRIPTION("Ralink RT2800 library");
3508MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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