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mwifiex: add custom IE framework
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2800pci.c
CommitLineData
a9b3a9f7 1/*
96481b20 2 Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14
GW		 3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
a9b3a9f7
ID		 10 <http://rt2x00.serialmonkey.com>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 */
27
28/*
29 Module: rt2800pci
30 Abstract: rt2800pci device specific routines.
31 Supported chipsets: RT2800E & RT2800ED.
32 */
33
a9b3a9f7
ID		 34#include <linux/delay.h>
35#include <linux/etherdevice.h>
36#include <linux/init.h>
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/pci.h>
40#include <linux/platform_device.h>
41#include <linux/eeprom_93cx6.h>
42
43#include "rt2x00.h"
44#include "rt2x00pci.h"
45#include "rt2x00soc.h"
7ef5cc92 46#include "rt2800lib.h"
b54f78a8 47#include "rt2800.h"
a9b3a9f7
ID		 48#include "rt2800pci.h"
49
a9b3a9f7
ID		 50/*
51 * Allow hardware encryption to be disabled.
52 */
eb939922 53static bool modparam_nohwcrypt = false;
a9b3a9f7
ID		 54module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
55MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
56
a9b3a9f7
ID		 57static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
58{
59 unsigned int i;
60 u32 reg;
61
f18d4463
LC		 62 /*
63 * SOC devices don't support MCU requests.
64 */
65 if (rt2x00_is_soc(rt2x00dev))
66 return;
67
a9b3a9f7 68 for (i = 0; i < 200; i++) {
9a819996 69 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
a9b3a9f7
ID		 70
71 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
72 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
73 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
74 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
75 break;
76
77 udelay(REGISTER_BUSY_DELAY);
78 }
79
80 if (i == 200)
81 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
82
9a819996
HS		 83 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
84 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
a9b3a9f7
ID		 85}
86
72c7296e 87#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
a9b3a9f7
ID		 88static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
89{
ef8397cf 90 void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
a9b3a9f7
ID		 91
92 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
ef8397cf
GW		 93
94 iounmap(base_addr);
a9b3a9f7
ID		 95}
96#else
97static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
98{
99}
72c7296e 100#endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
a9b3a9f7 101
72c7296e 102#ifdef CONFIG_PCI
a9b3a9f7
ID		 103static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
104{
105 struct rt2x00_dev *rt2x00dev = eeprom->data;
106 u32 reg;
107
9a819996 108 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 109
110 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
111 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
112 eeprom->reg_data_clock =
113 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
114 eeprom->reg_chip_select =
115 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
116}
117
118static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
119{
120 struct rt2x00_dev *rt2x00dev = eeprom->data;
121 u32 reg = 0;
122
123 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
124 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
125 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
126 !!eeprom->reg_data_clock);
127 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
128 !!eeprom->reg_chip_select);
129
9a819996 130 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
a9b3a9f7
ID		 131}
132
133static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
134{
135 struct eeprom_93cx6 eeprom;
136 u32 reg;
137
9a819996 138 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 139
140 eeprom.data = rt2x00dev;
141 eeprom.register_read = rt2800pci_eepromregister_read;
142 eeprom.register_write = rt2800pci_eepromregister_write;
20f8b139
GW		 143 switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
144 {
145 case 0:
146 eeprom.width = PCI_EEPROM_WIDTH_93C46;
147 break;
148 case 1:
149 eeprom.width = PCI_EEPROM_WIDTH_93C66;
150 break;
151 default:
152 eeprom.width = PCI_EEPROM_WIDTH_93C86;
153 break;
154 }
a9b3a9f7
ID		 155 eeprom.reg_data_in = 0;
156 eeprom.reg_data_out = 0;
157 eeprom.reg_data_clock = 0;
158 eeprom.reg_chip_select = 0;
159
160 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
161 EEPROM_SIZE / sizeof(u16));
162}
163
a6598682
GW		 164static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
165{
30e84034 166 return rt2800_efuse_detect(rt2x00dev);
a9b3a9f7
ID		 167}
168
30e84034 169static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 170{
30e84034 171 rt2800_read_eeprom_efuse(rt2x00dev);
a9b3a9f7
ID		 172}
173#else
174static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
175{
176}
177
a6598682
GW		 178static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
179{
180 return 0;
181}
182
a9b3a9f7
ID		 183static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
184{
185}
72c7296e 186#endif /* CONFIG_PCI */
a9b3a9f7 187
5450b7e2
ID		 188/*
189 * Queue handlers.
190 */
191static void rt2800pci_start_queue(struct data_queue *queue)
192{
193 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
194 u32 reg;
195
196 switch (queue->qid) {
197 case QID_RX:
9a819996 198 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5450b7e2 199 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
9a819996 200 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5450b7e2
ID		 201 break;
202 case QID_BEACON:
9a819996 203 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
5450b7e2
ID		 204 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
205 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
206 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
9a819996 207 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
69cf36a4 208
9a819996 209 rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, &reg);
69cf36a4 210 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 1);
9a819996 211 rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
5450b7e2
ID		 212 break;
213 default:
214 break;
6403eab1 215 }
5450b7e2
ID		 216}
217
218static void rt2800pci_kick_queue(struct data_queue *queue)
219{
220 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
221 struct queue_entry *entry;
222
223 switch (queue->qid) {
f615e9a3
ID		 224 case QID_AC_VO:
225 case QID_AC_VI:
5450b7e2
ID		 226 case QID_AC_BE:
227 case QID_AC_BK:
5450b7e2 228 entry = rt2x00queue_get_entry(queue, Q_INDEX);
9a819996
HS		 229 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(queue->qid),
230 entry->entry_idx);
5450b7e2
ID		 231 break;
232 case QID_MGMT:
233 entry = rt2x00queue_get_entry(queue, Q_INDEX);
9a819996
HS		 234 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(5),
235 entry->entry_idx);
5450b7e2
ID		 236 break;
237 default:
238 break;
239 }
240}
241
242static void rt2800pci_stop_queue(struct data_queue *queue)
243{
244 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
245 u32 reg;
246
247 switch (queue->qid) {
248 case QID_RX:
9a819996 249 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5450b7e2 250 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
9a819996 251 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5450b7e2
ID		 252 break;
253 case QID_BEACON:
9a819996 254 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
5450b7e2
ID		 255 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
256 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
257 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
9a819996 258 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
69cf36a4 259
9a819996 260 rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, &reg);
69cf36a4 261 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 0);
9a819996 262 rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
a9d61e9e
HS		 263
264 /*
abc11994
HS		 265 * Wait for current invocation to finish. The tasklet
266 * won't be scheduled anymore afterwards since we disabled
267 * the TBTT and PRE TBTT timer.
a9d61e9e 268 */
abc11994
HS		 269 tasklet_kill(&rt2x00dev->tbtt_tasklet);
270 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
271
5450b7e2
ID		 272 break;
273 default:
274 break;
275 }
276}
277
a9b3a9f7
ID		 278/*
279 * Firmware functions
280 */
281static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
282{
283 return FIRMWARE_RT2860;
284}
285
f31c9a8c 286static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
a9b3a9f7
ID		 287 const u8 *data, const size_t len)
288{
a9b3a9f7
ID		 289 u32 reg;
290
a9b3a9f7
ID		 291 /*
292 * enable Host program ram write selection
293 */
294 reg = 0;
295 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
9a819996 296 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
a9b3a9f7
ID		 297
298 /*
299 * Write firmware to device.
300 */
d4c838ef
ID		 301 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
302 data, len);
a9b3a9f7 303
9a819996
HS		 304 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
305 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
a9b3a9f7 306
9a819996
HS		 307 rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
308 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
a9b3a9f7
ID		 309
310 return 0;
311}
312
313/*
314 * Initialization functions.
315 */
316static bool rt2800pci_get_entry_state(struct queue_entry *entry)
317{
318 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
319 u32 word;
320
321 if (entry->queue->qid == QID_RX) {
322 rt2x00_desc_read(entry_priv->desc, 1, &word);
323
324 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
325 } else {
326 rt2x00_desc_read(entry_priv->desc, 1, &word);
327
328 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
329 }
330}
331
332static void rt2800pci_clear_entry(struct queue_entry *entry)
333{
334 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
335 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95192339 336 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
a9b3a9f7
ID		 337 u32 word;
338
339 if (entry->queue->qid == QID_RX) {
340 rt2x00_desc_read(entry_priv->desc, 0, &word);
341 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
342 rt2x00_desc_write(entry_priv->desc, 0, word);
343
344 rt2x00_desc_read(entry_priv->desc, 1, &word);
345 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
346 rt2x00_desc_write(entry_priv->desc, 1, word);
95192339
HS		 347
348 /*
349 * Set RX IDX in register to inform hardware that we have
350 * handled this entry and it is available for reuse again.
351 */
9a819996 352 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
95192339 353 entry->entry_idx);
a9b3a9f7
ID		 354 } else {
355 rt2x00_desc_read(entry_priv->desc, 1, &word);
356 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
357 rt2x00_desc_write(entry_priv->desc, 1, word);
358 }
359}
360
361static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
362{
363 struct queue_entry_priv_pci *entry_priv;
a9b3a9f7 364
a9b3a9f7
ID		 365 /*
366 * Initialize registers.
367 */
368 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
9a819996
HS		 369 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
370 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0,
371 rt2x00dev->tx[0].limit);
372 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
373 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX0, 0);
a9b3a9f7
ID		 374
375 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
9a819996
HS		 376 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
377 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1,
378 rt2x00dev->tx[1].limit);
379 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
380 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX1, 0);
a9b3a9f7
ID		 381
382 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
9a819996
HS		 383 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
384 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2,
385 rt2x00dev->tx[2].limit);
386 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
387 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX2, 0);
a9b3a9f7
ID		 388
389 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
9a819996
HS		 390 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
391 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3,
392 rt2x00dev->tx[3].limit);
393 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
394 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX3, 0);
a9b3a9f7 395
3a4b43fd
JK		 396 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR4, 0);
397 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT4, 0);
398 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX4, 0);
399 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX4, 0);
400
401 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR5, 0);
402 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT5, 0);
403 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX5, 0);
404 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX5, 0);
405
a9b3a9f7 406 entry_priv = rt2x00dev->rx->entries[0].priv_data;
9a819996
HS		 407 rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
408 rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT,
409 rt2x00dev->rx[0].limit);
410 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
411 rt2x00dev->rx[0].limit - 1);
412 rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0);
a9b3a9f7 413
f7b395e9 414 rt2800_disable_wpdma(rt2x00dev);
a9b3a9f7 415
9a819996 416 rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
a9b3a9f7
ID		 417
418 return 0;
419}
420
a9b3a9f7
ID		 421/*
422 * Device state switch handlers.
423 */
a9b3a9f7
ID		 424static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
425 enum dev_state state)
426{
a9b3a9f7 427 u32 reg;
a9d61e9e 428 unsigned long flags;
a9b3a9f7
ID		 429
430 /*
431 * When interrupts are being enabled, the interrupt registers
432 * should clear the register to assure a clean state.
433 */
434 if (state == STATE_RADIO_IRQ_ON) {
9a819996
HS		 435 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
436 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
a9d61e9e 437 }
a9b3a9f7 438
a9d61e9e 439 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
dfd00c4c
SG		 440 reg = 0;
441 if (state == STATE_RADIO_IRQ_ON) {
442 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, 1);
443 rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, 1);
444 rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, 1);
445 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, 1);
446 rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, 1);
447 }
9a819996 448 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
a9d61e9e
HS		 449 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
450
451 if (state == STATE_RADIO_IRQ_OFF) {
452 /*
abc11994 453 * Wait for possibly running tasklets to finish.
a9d61e9e 454 */
abc11994
HS		 455 tasklet_kill(&rt2x00dev->txstatus_tasklet);
456 tasklet_kill(&rt2x00dev->rxdone_tasklet);
457 tasklet_kill(&rt2x00dev->autowake_tasklet);
458 tasklet_kill(&rt2x00dev->tbtt_tasklet);
459 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
a9d61e9e 460 }
a9b3a9f7
ID		 461}
462
e3a896b9
GW		 463static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
464{
465 u32 reg;
466
467 /*
468 * Reset DMA indexes
469 */
9a819996 470 rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
e3a896b9
GW		 471 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
472 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
473 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
474 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
475 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
476 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
477 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
9a819996 478 rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
e3a896b9 479
9a819996
HS		 480 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
481 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
e3a896b9 482
872834df
GW		 483 if (rt2x00_is_pcie(rt2x00dev) &&
484 (rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884
JL		 485 rt2x00_rt(rt2x00dev, RT5390) ||
486 rt2x00_rt(rt2x00dev, RT5392))) {
9a819996 487 rt2x00pci_register_read(rt2x00dev, AUX_CTRL, &reg);
adde5882
GJ		 488 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
489 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
9a819996 490 rt2x00pci_register_write(rt2x00dev, AUX_CTRL, reg);
adde5882 491 }
60687ba7 492
9a819996 493 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
e3a896b9 494
2a48e8ae 495 reg = 0;
e3a896b9
GW		 496 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
497 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
9a819996 498 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
e3a896b9 499
9a819996 500 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
e3a896b9
GW		 501
502 return 0;
503}
504
a9b3a9f7
ID		 505static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
506{
e8b461c3
JK		 507 int retval;
508
52b8243b
JK		 509 /* Wait for DMA, ignore error until we initialize queues. */
510 rt2800_wait_wpdma_ready(rt2x00dev);
511
512 if (unlikely(rt2800pci_init_queues(rt2x00dev)))
a9b3a9f7
ID		 513 return -EIO;
514
e8b461c3
JK		 515 retval = rt2800_enable_radio(rt2x00dev);
516 if (retval)
517 return retval;
518
519 /* After resume MCU_BOOT_SIGNAL will trash these. */
520 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
521 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
522
523 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_RADIO_OFF, 0xff, 0x02);
524 rt2800pci_mcu_status(rt2x00dev, TOKEN_RADIO_OFF);
525
526 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP, 0, 0);
527 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
528
529 return retval;
a9b3a9f7
ID		 530}
531
532static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
533{
7f6e144f
RJH		 534 if (rt2x00_is_soc(rt2x00dev)) {
535 rt2800_disable_radio(rt2x00dev);
9a819996
HS		 536 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
537 rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
7f6e144f 538 }
a9b3a9f7
ID		 539}
540
541static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
542 enum dev_state state)
543{
a9b3a9f7 544 if (state == STATE_AWAKE) {
09a3311c
JK		 545 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP,
546 0, 0x02);
547 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
7f6e144f 548 } else if (state == STATE_SLEEP) {
9a819996
HS		 549 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
550 0xffffffff);
551 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID,
552 0xffffffff);
09a3311c
JK		 553 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_SLEEP,
554 0xff, 0x01);
a9b3a9f7
ID		 555 }
556
557 return 0;
558}
559
560static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
561 enum dev_state state)
562{
563 int retval = 0;
564
565 switch (state) {
566 case STATE_RADIO_ON:
a9b3a9f7
ID		 567 retval = rt2800pci_enable_radio(rt2x00dev);
568 break;
569 case STATE_RADIO_OFF:
570 /*
571 * After the radio has been disabled, the device should
572 * be put to sleep for powersaving.
573 */
574 rt2800pci_disable_radio(rt2x00dev);
575 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
576 break;
a9b3a9f7
ID		 577 case STATE_RADIO_IRQ_ON:
578 case STATE_RADIO_IRQ_OFF:
579 rt2800pci_toggle_irq(rt2x00dev, state);
580 break;
581 case STATE_DEEP_SLEEP:
582 case STATE_SLEEP:
583 case STATE_STANDBY:
584 case STATE_AWAKE:
585 retval = rt2800pci_set_state(rt2x00dev, state);
586 break;
587 default:
588 retval = -ENOTSUPP;
589 break;
590 }
591
592 if (unlikely(retval))
593 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
594 state, retval);
595
596 return retval;
597}
598
599/*
600 * TX descriptor initialization
601 */
0c5879bc 602static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)
a9b3a9f7 603{
0c5879bc 604 return (__le32 *) entry->skb->data;
745b1ae3
HS		 605}
606
93331458 607static void rt2800pci_write_tx_desc(struct queue_entry *entry,
745b1ae3
HS		 608 struct txentry_desc *txdesc)
609{
93331458
ID		 610 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
611 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
85b7a8b3 612 __le32 *txd = entry_priv->desc;
745b1ae3
HS		 613 u32 word;
614
a9b3a9f7
ID		 615 /*
616 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
617 * must contains a TXWI structure + 802.11 header + padding + 802.11
618 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
619 * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
620 * data. It means that LAST_SEC0 is always 0.
621 */
622
623 /*
624 * Initialize TX descriptor
625 */
3de3d966 626 word = 0;
a9b3a9f7
ID		 627 rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
628 rt2x00_desc_write(txd, 0, word);
629
3de3d966 630 word = 0;
93331458 631 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);
a9b3a9f7
ID		 632 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
633 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
634 rt2x00_set_field32(&word, TXD_W1_BURST,
635 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
85b7a8b3 636 rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
a9b3a9f7
ID		 637 rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
638 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
639 rt2x00_desc_write(txd, 1, word);
640
3de3d966 641 word = 0;
a9b3a9f7 642 rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
85b7a8b3 643 skbdesc->skb_dma + TXWI_DESC_SIZE);
a9b3a9f7
ID		 644 rt2x00_desc_write(txd, 2, word);
645
3de3d966 646 word = 0;
a9b3a9f7
ID		 647 rt2x00_set_field32(&word, TXD_W3_WIV,
648 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
649 rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
650 rt2x00_desc_write(txd, 3, word);
85b7a8b3
GW		 651
652 /*
653 * Register descriptor details in skb frame descriptor.
654 */
655 skbdesc->desc = txd;
656 skbdesc->desc_len = TXD_DESC_SIZE;
a9b3a9f7
ID		 657}
658
a9b3a9f7
ID		 659/*
660 * RX control handlers
661 */
662static void rt2800pci_fill_rxdone(struct queue_entry *entry,
663 struct rxdone_entry_desc *rxdesc)
664{
a9b3a9f7
ID		 665 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
666 __le32 *rxd = entry_priv->desc;
2de64dd2
GW		 667 u32 word;
668
669 rt2x00_desc_read(rxd, 3, &word);
670
671 if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
a9b3a9f7
ID		 672 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
673
78b8f3b0
GW		 674 /*
675 * Unfortunately we don't know the cipher type used during
676 * decryption. This prevents us from correct providing
677 * correct statistics through debugfs.
678 */
2de64dd2 679 rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
a9b3a9f7 680
2de64dd2 681 if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
a9b3a9f7
ID		 682 /*
683 * Hardware has stripped IV/EIV data from 802.11 frame during
684 * decryption. Unfortunately the descriptor doesn't contain
685 * any fields with the EIV/IV data either, so they can't
686 * be restored by rt2x00lib.
687 */
688 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
689
a45f369d
GW		 690 /*
691 * The hardware has already checked the Michael Mic and has
692 * stripped it from the frame. Signal this to mac80211.
693 */
694 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
695
a9b3a9f7
ID		 696 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
697 rxdesc->flags |= RX_FLAG_DECRYPTED;
698 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
699 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
700 }
701
2de64dd2 702 if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
a9b3a9f7
ID		 703 rxdesc->dev_flags |= RXDONE_MY_BSS;
704
2de64dd2 705 if (rt2x00_get_field32(word, RXD_W3_L2PAD))
a9b3a9f7 706 rxdesc->dev_flags |= RXDONE_L2PAD;
a9b3a9f7 707
a9b3a9f7 708 /*
2de64dd2 709 * Process the RXWI structure that is at the start of the buffer.
a9b3a9f7 710 */
74861922 711 rt2800_process_rxwi(entry, rxdesc);
a9b3a9f7
ID		 712}
713
714/*
715 * Interrupt functions.
716 */
4d66edc8
GW		 717static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
718{
719 struct ieee80211_conf conf = { .flags = 0 };
720 struct rt2x00lib_conf libconf = { .conf = &conf };
721
722 rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
723}
724
2e7798b7 725static bool rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
96c3da7d
HS		 726{
727 struct data_queue *queue;
728 struct queue_entry *entry;
729 u32 status;
730 u8 qid;
2e7798b7 731 int max_tx_done = 16;
96c3da7d 732
c4d63244 733 while (kfifo_get(&rt2x00dev->txstatus_fifo, &status)) {
12eec2cc 734 qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
87443e87 735 if (unlikely(qid >= QID_RX)) {
96c3da7d
HS		 736 /*
737 * Unknown queue, this shouldn't happen. Just drop
738 * this tx status.
739 */
740 WARNING(rt2x00dev, "Got TX status report with "
094a1d92 741 "unexpected pid %u, dropping\n", qid);
96c3da7d
HS		 742 break;
743 }
744
11f818e0 745 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
96c3da7d
HS		 746 if (unlikely(queue == NULL)) {
747 /*
748 * The queue is NULL, this shouldn't happen. Stop
749 * processing here and drop the tx status
750 */
751 WARNING(rt2x00dev, "Got TX status for an unavailable "
094a1d92 752 "queue %u, dropping\n", qid);
96c3da7d
HS		 753 break;
754 }
755
87443e87 756 if (unlikely(rt2x00queue_empty(queue))) {
96c3da7d
HS		 757 /*
758 * The queue is empty. Stop processing here
759 * and drop the tx status.
760 */
761 WARNING(rt2x00dev, "Got TX status for an empty "
094a1d92 762 "queue %u, dropping\n", qid);
96c3da7d
HS		 763 break;
764 }
765
766 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
31937c42 767 rt2800_txdone_entry(entry, status, rt2800pci_get_txwi(entry));
2e7798b7
HS		 768
769 if (--max_tx_done == 0)
770 break;
96c3da7d 771 }
2e7798b7
HS		 772
773 return !max_tx_done;
96c3da7d
HS		 774}
775
7a5a681a
HS		 776static inline void rt2800pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
777 struct rt2x00_field32 irq_field)
a9b3a9f7 778{
a9d61e9e 779 u32 reg;
a9b3a9f7
ID		 780
781 /*
a9d61e9e
HS		 782 * Enable a single interrupt. The interrupt mask register
783 * access needs locking.
9f926fb5 784 */
0aa13b2e 785 spin_lock_irq(&rt2x00dev->irqmask_lock);
9a819996 786 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
a9d61e9e 787 rt2x00_set_field32(&reg, irq_field, 1);
9a819996 788 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
0aa13b2e 789 spin_unlock_irq(&rt2x00dev->irqmask_lock);
a9d61e9e 790}
9f926fb5 791
a9d61e9e
HS		 792static void rt2800pci_txstatus_tasklet(unsigned long data)
793{
2e7798b7
HS		 794 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
795 if (rt2800pci_txdone(rt2x00dev))
796 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
9f926fb5
HS		 797
798 /*
a9d61e9e
HS		 799 * No need to enable the tx status interrupt here as we always
800 * leave it enabled to minimize the possibility of a tx status
801 * register overflow. See comment in interrupt handler.
a9b3a9f7 802 */
a9d61e9e 803}
a9b3a9f7 804
a9d61e9e
HS		 805static void rt2800pci_pretbtt_tasklet(unsigned long data)
806{
807 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
808 rt2x00lib_pretbtt(rt2x00dev);
abc11994
HS		 809 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
810 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_PRE_TBTT);
a9d61e9e 811}
4d66edc8 812
a9d61e9e
HS		 813static void rt2800pci_tbtt_tasklet(unsigned long data)
814{
815 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
290d6089
HS		 816 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
817 u32 reg;
818
a9d61e9e 819 rt2x00lib_beacondone(rt2x00dev);
290d6089
HS		 820
821 if (rt2x00dev->intf_ap_count) {
822 /*
823 * The rt2800pci hardware tbtt timer is off by 1us per tbtt
824 * causing beacon skew and as a result causing problems with
825 * some powersaving clients over time. Shorten the beacon
826 * interval every 64 beacons by 64us to mitigate this effect.
827 */
828 if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 2)) {
829 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
830 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
831 (rt2x00dev->beacon_int * 16) - 1);
832 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
833 } else if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 1)) {
834 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
835 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
836 (rt2x00dev->beacon_int * 16));
837 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
838 }
839 drv_data->tbtt_tick++;
840 drv_data->tbtt_tick %= BCN_TBTT_OFFSET;
841 }
842
abc11994
HS		 843 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
844 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TBTT);
a9d61e9e 845}
78e256c9 846
a9d61e9e
HS		 847static void rt2800pci_rxdone_tasklet(unsigned long data)
848{
849 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
16638937
HS		 850 if (rt2x00pci_rxdone(rt2x00dev))
851 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
abc11994 852 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
16638937 853 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RX_DONE);
a9d61e9e
HS		 854}
855
856static void rt2800pci_autowake_tasklet(unsigned long data)
857{
858 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
859 rt2800pci_wakeup(rt2x00dev);
abc11994
HS		 860 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
861 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_AUTO_WAKEUP);
a9b3a9f7
ID		 862}
863
96c3da7d
HS		 864static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
865{
866 u32 status;
867 int i;
868
869 /*
870 * The TX_FIFO_STATUS interrupt needs special care. We should
871 * read TX_STA_FIFO but we should do it immediately as otherwise
872 * the register can overflow and we would lose status reports.
873 *
874 * Hence, read the TX_STA_FIFO register and copy all tx status
875 * reports into a kernel FIFO which is handled in the txstatus
876 * tasklet. We use a tasklet to process the tx status reports
877 * because we can schedule the tasklet multiple times (when the
878 * interrupt fires again during tx status processing).
879 *
880 * Furthermore we don't disable the TX_FIFO_STATUS
881 * interrupt here but leave it enabled so that the TX_STA_FIFO
3736fe58 882 * can also be read while the tx status tasklet gets executed.
96c3da7d
HS		 883 *
884 * Since we have only one producer and one consumer we don't
885 * need to lock the kfifo.
886 */
efd2f271 887 for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
9a819996 888 rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &status);
96c3da7d
HS		 889
890 if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
891 break;
892
c4d63244 893 if (!kfifo_put(&rt2x00dev->txstatus_fifo, &status)) {
96c3da7d
HS		 894 WARNING(rt2x00dev, "TX status FIFO overrun,"
895 "drop tx status report.\n");
896 break;
897 }
898 }
899
900 /* Schedule the tasklet for processing the tx status. */
901 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
902}
903
78e256c9
HS		 904static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
905{
906 struct rt2x00_dev *rt2x00dev = dev_instance;
a9d61e9e 907 u32 reg, mask;
78e256c9
HS		 908
909 /* Read status and ACK all interrupts */
9a819996
HS		 910 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
911 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
78e256c9
HS		 912
913 if (!reg)
914 return IRQ_NONE;
915
916 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
917 return IRQ_HANDLED;
918
a9d61e9e
HS		 919 /*
920 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
921 * for interrupts and interrupt masks we can just use the value of
922 * INT_SOURCE_CSR to create the interrupt mask.
923 */
924 mask = ~reg;
78e256c9 925
a9d61e9e
HS		 926 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) {
927 rt2800pci_txstatus_interrupt(rt2x00dev);
96c3da7d 928 /*
a9d61e9e 929 * Never disable the TX_FIFO_STATUS interrupt.
96c3da7d 930 */
a9d61e9e
HS		 931 rt2x00_set_field32(&mask, INT_MASK_CSR_TX_FIFO_STATUS, 1);
932 }
96c3da7d 933
a9d61e9e
HS		 934 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
935 tasklet_hi_schedule(&rt2x00dev->pretbtt_tasklet);
78e256c9 936
a9d61e9e
HS		 937 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
938 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
96c3da7d 939
a9d61e9e
HS		 940 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
941 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
78e256c9 942
a9d61e9e
HS		 943 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
944 tasklet_schedule(&rt2x00dev->autowake_tasklet);
945
946 /*
947 * Disable all interrupts for which a tasklet was scheduled right now,
948 * the tasklet will reenable the appropriate interrupts.
949 */
0aa13b2e 950 spin_lock(&rt2x00dev->irqmask_lock);
9a819996 951 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
a9d61e9e 952 reg &= mask;
9a819996 953 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
0aa13b2e 954 spin_unlock(&rt2x00dev->irqmask_lock);
a9d61e9e
HS		 955
956 return IRQ_HANDLED;
78e256c9
HS		 957}
958
a9b3a9f7
ID		 959/*
960 * Device probe functions.
961 */
7ab71325
BZ		 962static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
963{
964 /*
965 * Read EEPROM into buffer
966 */
cea90e55 967 if (rt2x00_is_soc(rt2x00dev))
7ab71325 968 rt2800pci_read_eeprom_soc(rt2x00dev);
cea90e55
GW		 969 else if (rt2800pci_efuse_detect(rt2x00dev))
970 rt2800pci_read_eeprom_efuse(rt2x00dev);
971 else
972 rt2800pci_read_eeprom_pci(rt2x00dev);
7ab71325
BZ		 973
974 return rt2800_validate_eeprom(rt2x00dev);
975}
976
a9b3a9f7
ID		 977static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
978{
979 int retval;
980
981 /*
982 * Allocate eeprom data.
983 */
984 retval = rt2800pci_validate_eeprom(rt2x00dev);
985 if (retval)
986 return retval;
987
38bd7b8a 988 retval = rt2800_init_eeprom(rt2x00dev);
a9b3a9f7
ID		 989 if (retval)
990 return retval;
991
992 /*
993 * Initialize hw specifications.
994 */
4da2933f 995 retval = rt2800_probe_hw_mode(rt2x00dev);
a9b3a9f7
ID		 996 if (retval)
997 return retval;
998
999 /*
1000 * This device has multiple filters for control frames
1001 * and has a separate filter for PS Poll frames.
1002 */
7dab73b3
ID		 1003 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
1004 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
a9b3a9f7 1005
9f926fb5
HS		 1006 /*
1007 * This device has a pre tbtt interrupt and thus fetches
1008 * a new beacon directly prior to transmission.
1009 */
7dab73b3 1010 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
9f926fb5 1011
a9b3a9f7
ID		 1012 /*
1013 * This device requires firmware.
1014 */
cea90e55 1015 if (!rt2x00_is_soc(rt2x00dev))
7dab73b3
ID		 1016 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
1017 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
1018 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
1019 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
1020 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
a9b3a9f7 1021 if (!modparam_nohwcrypt)
7dab73b3
ID		 1022 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
1023 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
1024 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
a9b3a9f7
ID		 1025
1026 /*
1027 * Set the rssi offset.
1028 */
1029 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1030
1031 return 0;
1032}
1033
e783619e
HS		 1034static const struct ieee80211_ops rt2800pci_mac80211_ops = {
1035 .tx = rt2x00mac_tx,
1036 .start = rt2x00mac_start,
1037 .stop = rt2x00mac_stop,
1038 .add_interface = rt2x00mac_add_interface,
1039 .remove_interface = rt2x00mac_remove_interface,
1040 .config = rt2x00mac_config,
1041 .configure_filter = rt2x00mac_configure_filter,
e783619e
HS		 1042 .set_key = rt2x00mac_set_key,
1043 .sw_scan_start = rt2x00mac_sw_scan_start,
1044 .sw_scan_complete = rt2x00mac_sw_scan_complete,
1045 .get_stats = rt2x00mac_get_stats,
1046 .get_tkip_seq = rt2800_get_tkip_seq,
1047 .set_rts_threshold = rt2800_set_rts_threshold,
a2b1328a
HS		 1048 .sta_add = rt2x00mac_sta_add,
1049 .sta_remove = rt2x00mac_sta_remove,
e783619e
HS		 1050 .bss_info_changed = rt2x00mac_bss_info_changed,
1051 .conf_tx = rt2800_conf_tx,
1052 .get_tsf = rt2800_get_tsf,
1053 .rfkill_poll = rt2x00mac_rfkill_poll,
1054 .ampdu_action = rt2800_ampdu_action,
f44df18c 1055 .flush = rt2x00mac_flush,
977206d7 1056 .get_survey = rt2800_get_survey,
e7dee444 1057 .get_ringparam = rt2x00mac_get_ringparam,
5f0dd296 1058 .tx_frames_pending = rt2x00mac_tx_frames_pending,
e783619e
HS		 1059};
1060
e796643e
ID		 1061static const struct rt2800_ops rt2800pci_rt2800_ops = {
1062 .register_read = rt2x00pci_register_read,
1063 .register_read_lock = rt2x00pci_register_read, /* same for PCI */
1064 .register_write = rt2x00pci_register_write,
1065 .register_write_lock = rt2x00pci_register_write, /* same for PCI */
1066 .register_multiread = rt2x00pci_register_multiread,
1067 .register_multiwrite = rt2x00pci_register_multiwrite,
1068 .regbusy_read = rt2x00pci_regbusy_read,
1069 .drv_write_firmware = rt2800pci_write_firmware,
1070 .drv_init_registers = rt2800pci_init_registers,
0c5879bc 1071 .drv_get_txwi = rt2800pci_get_txwi,
e796643e
ID		 1072};
1073
a9b3a9f7
ID		 1074static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1075 .irq_handler = rt2800pci_interrupt,
a9d61e9e
HS		 1076 .txstatus_tasklet = rt2800pci_txstatus_tasklet,
1077 .pretbtt_tasklet = rt2800pci_pretbtt_tasklet,
1078 .tbtt_tasklet = rt2800pci_tbtt_tasklet,
1079 .rxdone_tasklet = rt2800pci_rxdone_tasklet,
1080 .autowake_tasklet = rt2800pci_autowake_tasklet,
a9b3a9f7
ID		 1081 .probe_hw = rt2800pci_probe_hw,
1082 .get_firmware_name = rt2800pci_get_firmware_name,
f31c9a8c
ID		 1083 .check_firmware = rt2800_check_firmware,
1084 .load_firmware = rt2800_load_firmware,
a9b3a9f7
ID		 1085 .initialize = rt2x00pci_initialize,
1086 .uninitialize = rt2x00pci_uninitialize,
1087 .get_entry_state = rt2800pci_get_entry_state,
1088 .clear_entry = rt2800pci_clear_entry,
1089 .set_device_state = rt2800pci_set_device_state,
f4450616
BZ		 1090 .rfkill_poll = rt2800_rfkill_poll,
1091 .link_stats = rt2800_link_stats,
1092 .reset_tuner = rt2800_reset_tuner,
1093 .link_tuner = rt2800_link_tuner,
9e33a355 1094 .gain_calibration = rt2800_gain_calibration,
2e9c43dd 1095 .vco_calibration = rt2800_vco_calibration,
dbba306f
ID		 1096 .start_queue = rt2800pci_start_queue,
1097 .kick_queue = rt2800pci_kick_queue,
1098 .stop_queue = rt2800pci_stop_queue,
152a5992 1099 .flush_queue = rt2x00pci_flush_queue,
a9b3a9f7 1100 .write_tx_desc = rt2800pci_write_tx_desc,
0c5879bc 1101 .write_tx_data = rt2800_write_tx_data,
f0194b2d 1102 .write_beacon = rt2800_write_beacon,
69cf36a4 1103 .clear_beacon = rt2800_clear_beacon,
a9b3a9f7 1104 .fill_rxdone = rt2800pci_fill_rxdone,
f4450616
BZ		 1105 .config_shared_key = rt2800_config_shared_key,
1106 .config_pairwise_key = rt2800_config_pairwise_key,
1107 .config_filter = rt2800_config_filter,
1108 .config_intf = rt2800_config_intf,
1109 .config_erp = rt2800_config_erp,
1110 .config_ant = rt2800_config_ant,
1111 .config = rt2800_config,
a2b1328a
HS		 1112 .sta_add = rt2800_sta_add,
1113 .sta_remove = rt2800_sta_remove,
a9b3a9f7
ID		 1114};
1115
1116static const struct data_queue_desc rt2800pci_queue_rx = {
efd2f271 1117 .entry_num = 128,
a9b3a9f7
ID		 1118 .data_size = AGGREGATION_SIZE,
1119 .desc_size = RXD_DESC_SIZE,
1120 .priv_size = sizeof(struct queue_entry_priv_pci),
1121};
1122
1123static const struct data_queue_desc rt2800pci_queue_tx = {
efd2f271 1124 .entry_num = 64,
a9b3a9f7
ID		 1125 .data_size = AGGREGATION_SIZE,
1126 .desc_size = TXD_DESC_SIZE,
1127 .priv_size = sizeof(struct queue_entry_priv_pci),
1128};
1129
1130static const struct data_queue_desc rt2800pci_queue_bcn = {
efd2f271 1131 .entry_num = 8,
a9b3a9f7
ID		 1132 .data_size = 0, /* No DMA required for beacons */
1133 .desc_size = TXWI_DESC_SIZE,
1134 .priv_size = sizeof(struct queue_entry_priv_pci),
1135};
1136
1137static const struct rt2x00_ops rt2800pci_ops = {
04d0362e 1138 .name = KBUILD_MODNAME,
3a1c0128 1139 .drv_data_size = sizeof(struct rt2800_drv_data),
04d0362e
GW		 1140 .max_sta_intf = 1,
1141 .max_ap_intf = 8,
1142 .eeprom_size = EEPROM_SIZE,
1143 .rf_size = RF_SIZE,
1144 .tx_queues = NUM_TX_QUEUES,
e6218cc4 1145 .extra_tx_headroom = TXWI_DESC_SIZE,
04d0362e
GW		 1146 .rx = &rt2800pci_queue_rx,
1147 .tx = &rt2800pci_queue_tx,
1148 .bcn = &rt2800pci_queue_bcn,
1149 .lib = &rt2800pci_rt2x00_ops,
e796643e 1150 .drv = &rt2800pci_rt2800_ops,
e783619e 1151 .hw = &rt2800pci_mac80211_ops,
a9b3a9f7 1152#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 1153 .debugfs = &rt2800_rt2x00debug,
a9b3a9f7
ID		 1154#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1155};
1156
1157/*
1158 * RT2800pci module information.
1159 */
72c7296e 1160#ifdef CONFIG_PCI
a3aa1884 1161static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
e01ae27f
GW		 1162 { PCI_DEVICE(0x1814, 0x0601) },
1163 { PCI_DEVICE(0x1814, 0x0681) },
1164 { PCI_DEVICE(0x1814, 0x0701) },
1165 { PCI_DEVICE(0x1814, 0x0781) },
1166 { PCI_DEVICE(0x1814, 0x3090) },
1167 { PCI_DEVICE(0x1814, 0x3091) },
1168 { PCI_DEVICE(0x1814, 0x3092) },
1169 { PCI_DEVICE(0x1432, 0x7708) },
1170 { PCI_DEVICE(0x1432, 0x7727) },
1171 { PCI_DEVICE(0x1432, 0x7728) },
1172 { PCI_DEVICE(0x1432, 0x7738) },
1173 { PCI_DEVICE(0x1432, 0x7748) },
1174 { PCI_DEVICE(0x1432, 0x7758) },
1175 { PCI_DEVICE(0x1432, 0x7768) },
1176 { PCI_DEVICE(0x1462, 0x891a) },
1177 { PCI_DEVICE(0x1a3b, 0x1059) },
f93bc9b3 1178#ifdef CONFIG_RT2800PCI_RT33XX
e01ae27f 1179 { PCI_DEVICE(0x1814, 0x3390) },
f93bc9b3 1180#endif
de1ebdce 1181#ifdef CONFIG_RT2800PCI_RT35XX
e01ae27f
GW		 1182 { PCI_DEVICE(0x1432, 0x7711) },
1183 { PCI_DEVICE(0x1432, 0x7722) },
1184 { PCI_DEVICE(0x1814, 0x3060) },
1185 { PCI_DEVICE(0x1814, 0x3062) },
1186 { PCI_DEVICE(0x1814, 0x3562) },
1187 { PCI_DEVICE(0x1814, 0x3592) },
1188 { PCI_DEVICE(0x1814, 0x3593) },
60687ba7
RST		 1189#endif
1190#ifdef CONFIG_RT2800PCI_RT53XX
f57d7b6c 1191 { PCI_DEVICE(0x1814, 0x5362) },
e01ae27f 1192 { PCI_DEVICE(0x1814, 0x5390) },
f57d7b6c 1193 { PCI_DEVICE(0x1814, 0x5392) },
5126d97e 1194 { PCI_DEVICE(0x1814, 0x539a) },
71e0b38c 1195 { PCI_DEVICE(0x1814, 0x539f) },
de1ebdce 1196#endif
a9b3a9f7
ID		 1197 { 0, }
1198};
72c7296e 1199#endif /* CONFIG_PCI */
a9b3a9f7
ID		 1200
1201MODULE_AUTHOR(DRV_PROJECT);
1202MODULE_VERSION(DRV_VERSION);
1203MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1204MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
72c7296e 1205#ifdef CONFIG_PCI
a9b3a9f7
ID		 1206MODULE_FIRMWARE(FIRMWARE_RT2860);
1207MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
72c7296e 1208#endif /* CONFIG_PCI */
a9b3a9f7
ID		 1209MODULE_LICENSE("GPL");
1210
72c7296e 1211#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
714fa663
GW		 1212static int rt2800soc_probe(struct platform_device *pdev)
1213{
6e93d719 1214 return rt2x00soc_probe(pdev, &rt2800pci_ops);
714fa663 1215}
a9b3a9f7
ID		 1216
1217static struct platform_driver rt2800soc_driver = {
1218 .driver = {
1219 .name = "rt2800_wmac",
1220 .owner = THIS_MODULE,
1221 .mod_name = KBUILD_MODNAME,
1222 },
714fa663 1223 .probe = rt2800soc_probe,
a9b3a9f7
ID		 1224 .remove = __devexit_p(rt2x00soc_remove),
1225 .suspend = rt2x00soc_suspend,
1226 .resume = rt2x00soc_resume,
1227};
72c7296e 1228#endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
a9b3a9f7 1229
72c7296e 1230#ifdef CONFIG_PCI
e01ae27f
GW		 1231static int rt2800pci_probe(struct pci_dev *pci_dev,
1232 const struct pci_device_id *id)
1233{
1234 return rt2x00pci_probe(pci_dev, &rt2800pci_ops);
1235}
1236
a9b3a9f7
ID		 1237static struct pci_driver rt2800pci_driver = {
1238 .name = KBUILD_MODNAME,
1239 .id_table = rt2800pci_device_table,
e01ae27f 1240 .probe = rt2800pci_probe,
a9b3a9f7
ID		 1241 .remove = __devexit_p(rt2x00pci_remove),
1242 .suspend = rt2x00pci_suspend,
1243 .resume = rt2x00pci_resume,
1244};
72c7296e 1245#endif /* CONFIG_PCI */
a9b3a9f7
ID		 1246
1247static int __init rt2800pci_init(void)
1248{
1249 int ret = 0;
1250
72c7296e 1251#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
a9b3a9f7
ID		 1252 ret = platform_driver_register(&rt2800soc_driver);
1253 if (ret)
1254 return ret;
1255#endif
72c7296e 1256#ifdef CONFIG_PCI
a9b3a9f7
ID		 1257 ret = pci_register_driver(&rt2800pci_driver);
1258 if (ret) {
72c7296e 1259#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
a9b3a9f7
ID		 1260 platform_driver_unregister(&rt2800soc_driver);
1261#endif
1262 return ret;
1263 }
1264#endif
1265
1266 return ret;
1267}
1268
1269static void __exit rt2800pci_exit(void)
1270{
72c7296e 1271#ifdef CONFIG_PCI
a9b3a9f7
ID		 1272 pci_unregister_driver(&rt2800pci_driver);
1273#endif
72c7296e 1274#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
a9b3a9f7
ID		 1275 platform_driver_unregister(&rt2800soc_driver);
1276#endif
1277}
1278
1279module_init(rt2800pci_init);
1280module_exit(rt2800pci_exit);
Linux kernel - Deliverables
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