[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2800pci.c

/*
	Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
	Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
	Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
	Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
	Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
	Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
	Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
	Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
	<http://rt2x00.serialmonkey.com>

	This program is free software; you can redistribute it and/or modify
	it under the terms of the GNU General Public License as published by
	the Free Software Foundation; either version 2 of the License, or
	(at your option) any later version.

	This program is distributed in the hope that it will be useful,
	but WITHOUT ANY WARRANTY; without even the implied warranty of
	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	GNU General Public License for more details.

	You should have received a copy of the GNU General Public License
	along with this program; if not, write to the
	Free Software Foundation, Inc.,
	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 */

/*
	Module: rt2800pci
	Abstract: rt2800pci device specific routines.
	Supported chipsets: RT2800E & RT2800ED.
 */

#include <linux/delay.h>
#include <linux/etherdevice.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/eeprom_93cx6.h>

#include "rt2x00.h"
#include "rt2x00mmio.h"
#include "rt2x00pci.h"
#include "rt2800lib.h"
#include "rt2800mmio.h"
#include "rt2800.h"
#include "rt2800pci.h"

/*
 * Allow hardware encryption to be disabled.
 */
static bool modparam_nohwcrypt = false;
module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");

static bool rt2800pci_hwcrypt_disabled(struct rt2x00_dev *rt2x00dev)
{
	return modparam_nohwcrypt;
}

static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
{
	unsigned int i;
	u32 reg;

	/*
	 * SOC devices don't support MCU requests.
	 */
	if (rt2x00_is_soc(rt2x00dev))
		return;

	for (i = 0; i < 200; i++) {
		rt2x00mmio_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);

		if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
		    (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
		    (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
		    (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
			break;

		udelay(REGISTER_BUSY_DELAY);
	}

	if (i == 200)
		rt2x00_err(rt2x00dev, "MCU request failed, no response from hardware\n");

	rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
	rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
}

static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
{
	struct rt2x00_dev *rt2x00dev = eeprom->data;
	u32 reg;

	rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, &reg);

	eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
	eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
	eeprom->reg_data_clock =
	    !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
	eeprom->reg_chip_select =
	    !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
}

static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
{
	struct rt2x00_dev *rt2x00dev = eeprom->data;
	u32 reg = 0;

	rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
	rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
	rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
			   !!eeprom->reg_data_clock);
	rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
			   !!eeprom->reg_chip_select);

	rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg);
}

static int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
{
	struct eeprom_93cx6 eeprom;
	u32 reg;

	rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, &reg);

	eeprom.data = rt2x00dev;
	eeprom.register_read = rt2800pci_eepromregister_read;
	eeprom.register_write = rt2800pci_eepromregister_write;
	switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
	{
	case 0:
		eeprom.width = PCI_EEPROM_WIDTH_93C46;
		break;
	case 1:
		eeprom.width = PCI_EEPROM_WIDTH_93C66;
		break;
	default:
		eeprom.width = PCI_EEPROM_WIDTH_93C86;
		break;
	}
	eeprom.reg_data_in = 0;
	eeprom.reg_data_out = 0;
	eeprom.reg_data_clock = 0;
	eeprom.reg_chip_select = 0;

	eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
			       EEPROM_SIZE / sizeof(u16));

	return 0;
}

static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
{
	return rt2800_efuse_detect(rt2x00dev);
}

static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
{
	return rt2800_read_eeprom_efuse(rt2x00dev);
}

/*
 * Firmware functions
 */
static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
{
	/*
	 * Chip rt3290 use specific 4KB firmware named rt3290.bin.
	 */
	if (rt2x00_rt(rt2x00dev, RT3290))
		return FIRMWARE_RT3290;
	else
		return FIRMWARE_RT2860;
}

static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
				    const u8 *data, const size_t len)
{
	u32 reg;

	/*
	 * enable Host program ram write selection
	 */
	reg = 0;
	rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
	rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, reg);

	/*
	 * Write firmware to device.
	 */
	rt2x00mmio_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
				       data, len);

	rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
	rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);

	rt2x00mmio_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
	rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);

	return 0;
}

/*
 * Device state switch handlers.
 */
static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
{
	int retval;

	retval = rt2800mmio_enable_radio(rt2x00dev);
	if (retval)
		return retval;

	/* After resume MCU_BOOT_SIGNAL will trash these. */
	rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
	rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);

	rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_RADIO_OFF, 0xff, 0x02);
	rt2800pci_mcu_status(rt2x00dev, TOKEN_RADIO_OFF);

	rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP, 0, 0);
	rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);

	return retval;
}

static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
			       enum dev_state state)
{
	if (state == STATE_AWAKE) {
		rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP,
				   0, 0x02);
		rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
	} else if (state == STATE_SLEEP) {
		rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
					  0xffffffff);
		rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID,
					  0xffffffff);
		rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_SLEEP,
				   0xff, 0x01);
	}

	return 0;
}

static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
				      enum dev_state state)
{
	int retval = 0;

	switch (state) {
	case STATE_RADIO_ON:
		retval = rt2800pci_enable_radio(rt2x00dev);
		break;
	case STATE_RADIO_OFF:
		/*
		 * After the radio has been disabled, the device should
		 * be put to sleep for powersaving.
		 */
		rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
		break;
	case STATE_RADIO_IRQ_ON:
	case STATE_RADIO_IRQ_OFF:
		rt2800mmio_toggle_irq(rt2x00dev, state);
		break;
	case STATE_DEEP_SLEEP:
	case STATE_SLEEP:
	case STATE_STANDBY:
	case STATE_AWAKE:
		retval = rt2800pci_set_state(rt2x00dev, state);
		break;
	default:
		retval = -ENOTSUPP;
		break;
	}

	if (unlikely(retval))
		rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
			   state, retval);

	return retval;
}

/*
 * Device probe functions.
 */
static int rt2800pci_read_eeprom(struct rt2x00_dev *rt2x00dev)
{
	int retval;

	if (rt2800pci_efuse_detect(rt2x00dev))
		retval = rt2800pci_read_eeprom_efuse(rt2x00dev);
	else
		retval = rt2800pci_read_eeprom_pci(rt2x00dev);

	return retval;
}

static const struct ieee80211_ops rt2800pci_mac80211_ops = {
	.tx			= rt2x00mac_tx,
	.start			= rt2x00mac_start,
	.stop			= rt2x00mac_stop,
	.add_interface		= rt2x00mac_add_interface,
	.remove_interface	= rt2x00mac_remove_interface,
	.config			= rt2x00mac_config,
	.configure_filter	= rt2x00mac_configure_filter,
	.set_key		= rt2x00mac_set_key,
	.sw_scan_start		= rt2x00mac_sw_scan_start,
	.sw_scan_complete	= rt2x00mac_sw_scan_complete,
	.get_stats		= rt2x00mac_get_stats,
	.get_tkip_seq		= rt2800_get_tkip_seq,
	.set_rts_threshold	= rt2800_set_rts_threshold,
	.sta_add		= rt2x00mac_sta_add,
	.sta_remove		= rt2x00mac_sta_remove,
	.bss_info_changed	= rt2x00mac_bss_info_changed,
	.conf_tx		= rt2800_conf_tx,
	.get_tsf		= rt2800_get_tsf,
	.rfkill_poll		= rt2x00mac_rfkill_poll,
	.ampdu_action		= rt2800_ampdu_action,
	.flush			= rt2x00mac_flush,
	.get_survey		= rt2800_get_survey,
	.get_ringparam		= rt2x00mac_get_ringparam,
	.tx_frames_pending	= rt2x00mac_tx_frames_pending,
};

static const struct rt2800_ops rt2800pci_rt2800_ops = {
	.register_read		= rt2x00mmio_register_read,
	.register_read_lock	= rt2x00mmio_register_read, /* same for PCI */
	.register_write		= rt2x00mmio_register_write,
	.register_write_lock	= rt2x00mmio_register_write, /* same for PCI */
	.register_multiread	= rt2x00mmio_register_multiread,
	.register_multiwrite	= rt2x00mmio_register_multiwrite,
	.regbusy_read		= rt2x00mmio_regbusy_read,
	.read_eeprom		= rt2800pci_read_eeprom,
	.hwcrypt_disabled	= rt2800pci_hwcrypt_disabled,
	.drv_write_firmware	= rt2800pci_write_firmware,
	.drv_init_registers	= rt2800mmio_init_registers,
	.drv_get_txwi		= rt2800mmio_get_txwi,
};

static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
	.irq_handler		= rt2800mmio_interrupt,
	.txstatus_tasklet	= rt2800mmio_txstatus_tasklet,
	.pretbtt_tasklet	= rt2800mmio_pretbtt_tasklet,
	.tbtt_tasklet		= rt2800mmio_tbtt_tasklet,
	.rxdone_tasklet		= rt2800mmio_rxdone_tasklet,
	.autowake_tasklet	= rt2800mmio_autowake_tasklet,
	.probe_hw		= rt2800_probe_hw,
	.get_firmware_name	= rt2800pci_get_firmware_name,
	.check_firmware		= rt2800_check_firmware,
	.load_firmware		= rt2800_load_firmware,
	.initialize		= rt2x00mmio_initialize,
	.uninitialize		= rt2x00mmio_uninitialize,
	.get_entry_state	= rt2800mmio_get_entry_state,
	.clear_entry		= rt2800mmio_clear_entry,
	.set_device_state	= rt2800pci_set_device_state,
	.rfkill_poll		= rt2800_rfkill_poll,
	.link_stats		= rt2800_link_stats,
	.reset_tuner		= rt2800_reset_tuner,
	.link_tuner		= rt2800_link_tuner,
	.gain_calibration	= rt2800_gain_calibration,
	.vco_calibration	= rt2800_vco_calibration,
	.start_queue		= rt2800mmio_start_queue,
	.kick_queue		= rt2800mmio_kick_queue,
	.stop_queue		= rt2800mmio_stop_queue,
	.flush_queue		= rt2x00mmio_flush_queue,
	.write_tx_desc		= rt2800mmio_write_tx_desc,
	.write_tx_data		= rt2800_write_tx_data,
	.write_beacon		= rt2800_write_beacon,
	.clear_beacon		= rt2800_clear_beacon,
	.fill_rxdone		= rt2800mmio_fill_rxdone,
	.config_shared_key	= rt2800_config_shared_key,
	.config_pairwise_key	= rt2800_config_pairwise_key,
	.config_filter		= rt2800_config_filter,
	.config_intf		= rt2800_config_intf,
	.config_erp		= rt2800_config_erp,
	.config_ant		= rt2800_config_ant,
	.config			= rt2800_config,
	.sta_add		= rt2800_sta_add,
	.sta_remove		= rt2800_sta_remove,
};

static const struct rt2x00_ops rt2800pci_ops = {
	.name			= KBUILD_MODNAME,
	.drv_data_size		= sizeof(struct rt2800_drv_data),
	.max_ap_intf		= 8,
	.eeprom_size		= EEPROM_SIZE,
	.rf_size		= RF_SIZE,
	.tx_queues		= NUM_TX_QUEUES,
	.queue_init		= rt2800mmio_queue_init,
	.lib			= &rt2800pci_rt2x00_ops,
	.drv			= &rt2800pci_rt2800_ops,
	.hw			= &rt2800pci_mac80211_ops,
#ifdef CONFIG_RT2X00_LIB_DEBUGFS
	.debugfs		= &rt2800_rt2x00debug,
#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
};

/*
 * RT2800pci module information.
 */
static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
	{ PCI_DEVICE(0x1814, 0x0601) },
	{ PCI_DEVICE(0x1814, 0x0681) },
	{ PCI_DEVICE(0x1814, 0x0701) },
	{ PCI_DEVICE(0x1814, 0x0781) },
	{ PCI_DEVICE(0x1814, 0x3090) },
	{ PCI_DEVICE(0x1814, 0x3091) },
	{ PCI_DEVICE(0x1814, 0x3092) },
	{ PCI_DEVICE(0x1432, 0x7708) },
	{ PCI_DEVICE(0x1432, 0x7727) },
	{ PCI_DEVICE(0x1432, 0x7728) },
	{ PCI_DEVICE(0x1432, 0x7738) },
	{ PCI_DEVICE(0x1432, 0x7748) },
	{ PCI_DEVICE(0x1432, 0x7758) },
	{ PCI_DEVICE(0x1432, 0x7768) },
	{ PCI_DEVICE(0x1462, 0x891a) },
	{ PCI_DEVICE(0x1a3b, 0x1059) },
#ifdef CONFIG_RT2800PCI_RT3290
	{ PCI_DEVICE(0x1814, 0x3290) },
#endif
#ifdef CONFIG_RT2800PCI_RT33XX
	{ PCI_DEVICE(0x1814, 0x3390) },
#endif
#ifdef CONFIG_RT2800PCI_RT35XX
	{ PCI_DEVICE(0x1432, 0x7711) },
	{ PCI_DEVICE(0x1432, 0x7722) },
	{ PCI_DEVICE(0x1814, 0x3060) },
	{ PCI_DEVICE(0x1814, 0x3062) },
	{ PCI_DEVICE(0x1814, 0x3562) },
	{ PCI_DEVICE(0x1814, 0x3592) },
	{ PCI_DEVICE(0x1814, 0x3593) },
	{ PCI_DEVICE(0x1814, 0x359f) },
#endif
#ifdef CONFIG_RT2800PCI_RT53XX
	{ PCI_DEVICE(0x1814, 0x5360) },
	{ PCI_DEVICE(0x1814, 0x5362) },
	{ PCI_DEVICE(0x1814, 0x5390) },
	{ PCI_DEVICE(0x1814, 0x5392) },
	{ PCI_DEVICE(0x1814, 0x539a) },
	{ PCI_DEVICE(0x1814, 0x539b) },
	{ PCI_DEVICE(0x1814, 0x539f) },
#endif
	{ 0, }
};

MODULE_AUTHOR(DRV_PROJECT);
MODULE_VERSION(DRV_VERSION);
MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
MODULE_FIRMWARE(FIRMWARE_RT2860);
MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
MODULE_LICENSE("GPL");

static int rt2800pci_probe(struct pci_dev *pci_dev,
			   const struct pci_device_id *id)
{
	return rt2x00pci_probe(pci_dev, &rt2800pci_ops);
}

static struct pci_driver rt2800pci_driver = {
	.name		= KBUILD_MODNAME,
	.id_table	= rt2800pci_device_table,
	.probe		= rt2800pci_probe,
	.remove		= rt2x00pci_remove,
	.suspend	= rt2x00pci_suspend,
	.resume		= rt2x00pci_resume,
};

module_pci_driver(rt2800pci_driver);
Commit	Line	Data
a9b3a9f7	1	/*
96481b20	2	Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 GW	3	Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
	4	Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
	5	Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
	6	Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
	7	Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
	8	Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
	9	Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
a9b3a9f7 ID	10	<http://rt2x00.serialmonkey.com>
	11
	12	This program is free software; you can redistribute it and/or modify
	13	it under the terms of the GNU General Public License as published by
	14	the Free Software Foundation; either version 2 of the License, or
	15	(at your option) any later version.
	16
	17	This program is distributed in the hope that it will be useful,
	18	but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	GNU General Public License for more details.
	21
	22	You should have received a copy of the GNU General Public License
	23	along with this program; if not, write to the
	24	Free Software Foundation, Inc.,
	25	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	26	*/
	27
	28	/*
	29	Module: rt2800pci
	30	Abstract: rt2800pci device specific routines.
	31	Supported chipsets: RT2800E & RT2800ED.
	32	*/
	33
a9b3a9f7 ID	34	#include <linux/delay.h>
	35	#include <linux/etherdevice.h>
	36	#include <linux/init.h>
	37	#include <linux/kernel.h>
	38	#include <linux/module.h>
	39	#include <linux/pci.h>
a9b3a9f7 ID	40	#include <linux/eeprom_93cx6.h>
	41
	42	#include "rt2x00.h"
69a2bac8	43	#include "rt2x00mmio.h"
a9b3a9f7	44	#include "rt2x00pci.h"
7ef5cc92	45	#include "rt2800lib.h"
0bc202b3	46	#include "rt2800mmio.h"
b54f78a8	47	#include "rt2800.h"
a9b3a9f7 ID	48	#include "rt2800pci.h"
a9b3a9f7 ID	49
a9b3a9f7 ID	50	/*
	51	* Allow hardware encryption to be disabled.
	52	*/
eb939922	53	static bool modparam_nohwcrypt = false;
a9b3a9f7 ID	54	module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
	55	MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
	56
ad417a53 GW	57	static bool rt2800pci_hwcrypt_disabled(struct rt2x00_dev *rt2x00dev)
	58	{
	59	return modparam_nohwcrypt;
	60	}
	61
a9b3a9f7 ID	62	static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
	63	{
	64	unsigned int i;
	65	u32 reg;
	66
f18d4463 LC	67	/*
	68	* SOC devices don't support MCU requests.
	69	*/
	70	if (rt2x00_is_soc(rt2x00dev))
	71	return;
	72
a9b3a9f7	73	for (i = 0; i < 200; i++) {
b9570b66	74	rt2x00mmio_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
a9b3a9f7 ID	75
	76	if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) \|\|
	77	(rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) \|\|
	78	(rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) \|\|
	79	(rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
	80	break;
	81
	82	udelay(REGISTER_BUSY_DELAY);
	83	}
	84
	85	if (i == 200)
ec9c4989	86	rt2x00_err(rt2x00dev, "MCU request failed, no response from hardware\n");
a9b3a9f7	87
b9570b66 GJ	88	rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
b9570b66 GJ	89	rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
a9b3a9f7 ID	90	}
a9b3a9f7 ID	91
a9b3a9f7 ID	92	static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
	93	{
	94	struct rt2x00_dev *rt2x00dev = eeprom->data;
	95	u32 reg;
	96
b9570b66	97	rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7 ID	98
	99	eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
	100	eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
	101	eeprom->reg_data_clock =
	102	!!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
	103	eeprom->reg_chip_select =
	104	!!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
	105	}
	106
	107	static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
	108	{
	109	struct rt2x00_dev *rt2x00dev = eeprom->data;
	110	u32 reg = 0;
	111
	112	rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
	113	rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
	114	rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
	115	!!eeprom->reg_data_clock);
	116	rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
	117	!!eeprom->reg_chip_select);
	118
b9570b66	119	rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg);
a9b3a9f7 ID	120	}
a9b3a9f7 ID	121
a02308e9	122	static int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 ID	123	{
	124	struct eeprom_93cx6 eeprom;
	125	u32 reg;
	126
b9570b66	127	rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7 ID	128
	129	eeprom.data = rt2x00dev;
	130	eeprom.register_read = rt2800pci_eepromregister_read;
	131	eeprom.register_write = rt2800pci_eepromregister_write;
20f8b139 GW	132	switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
	133	{
	134	case 0:
	135	eeprom.width = PCI_EEPROM_WIDTH_93C46;
	136	break;
	137	case 1:
	138	eeprom.width = PCI_EEPROM_WIDTH_93C66;
	139	break;
	140	default:
	141	eeprom.width = PCI_EEPROM_WIDTH_93C86;
	142	break;
	143	}
a9b3a9f7 ID	144	eeprom.reg_data_in = 0;
	145	eeprom.reg_data_out = 0;
	146	eeprom.reg_data_clock = 0;
	147	eeprom.reg_chip_select = 0;
	148
	149	eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
	150	EEPROM_SIZE / sizeof(u16));
a02308e9 GJ	151
a02308e9 GJ	152	return 0;
a9b3a9f7 ID	153	}
a9b3a9f7 ID	154
a6598682 GW	155	static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
a6598682 GW	156	{
30e84034	157	return rt2800_efuse_detect(rt2x00dev);
a9b3a9f7 ID	158	}
a9b3a9f7 ID	159
a02308e9	160	static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
a9b3a9f7	161	{
a02308e9	162	return rt2800_read_eeprom_efuse(rt2x00dev);
a9b3a9f7	163	}
a9b3a9f7	164
a9b3a9f7 ID	165	/*
	166	* Firmware functions
	167	*/
	168	static char rt2800pci_get_firmware_name(struct rt2x00_dev rt2x00dev)
	169	{
a89534ed WH	170	/*
	171	* Chip rt3290 use specific 4KB firmware named rt3290.bin.
	172	*/
	173	if (rt2x00_rt(rt2x00dev, RT3290))
	174	return FIRMWARE_RT3290;
	175	else
	176	return FIRMWARE_RT2860;
a9b3a9f7 ID	177	}
a9b3a9f7 ID	178
f31c9a8c	179	static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
a9b3a9f7 ID	180	const u8 *data, const size_t len)
a9b3a9f7 ID	181	{
a9b3a9f7 ID	182	u32 reg;
a9b3a9f7 ID	183
a9b3a9f7 ID	184	/*
	185	* enable Host program ram write selection
	186	*/
	187	reg = 0;
	188	rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
b9570b66	189	rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
a9b3a9f7 ID	190
	191	/*
	192	* Write firmware to device.
	193	*/
b9570b66 GJ	194	rt2x00mmio_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
b9570b66 GJ	195	data, len);
a9b3a9f7	196
b9570b66 GJ	197	rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
b9570b66 GJ	198	rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
a9b3a9f7	199
b9570b66 GJ	200	rt2x00mmio_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
b9570b66 GJ	201	rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
a9b3a9f7 ID	202
	203	return 0;
	204	}
	205
a9b3a9f7 ID	206	/*
	207	* Device state switch handlers.
	208	*/
1e7d3035 GJ	209	static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
	210	{
	211	int retval;
	212
	213	retval = rt2800mmio_enable_radio(rt2x00dev);
e8b461c3 JK	214	if (retval)
	215	return retval;
	216
	217	/* After resume MCU_BOOT_SIGNAL will trash these. */
b9570b66 GJ	218	rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
b9570b66 GJ	219	rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
e8b461c3 JK	220
	221	rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_RADIO_OFF, 0xff, 0x02);
	222	rt2800pci_mcu_status(rt2x00dev, TOKEN_RADIO_OFF);
	223
	224	rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP, 0, 0);
	225	rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
	226
	227	return retval;
a9b3a9f7 ID	228	}
a9b3a9f7 ID	229
a9b3a9f7 ID	230	static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
	231	enum dev_state state)
	232	{
a9b3a9f7	233	if (state == STATE_AWAKE) {
09a3311c JK	234	rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP,
	235	0, 0x02);
	236	rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
7f6e144f	237	} else if (state == STATE_SLEEP) {
b9570b66 GJ	238	rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
	239	0xffffffff);
	240	rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID,
	241	0xffffffff);
09a3311c JK	242	rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_SLEEP,
09a3311c JK	243	0xff, 0x01);
a9b3a9f7 ID	244	}
	245
	246	return 0;
	247	}
	248
	249	static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
	250	enum dev_state state)
	251	{
	252	int retval = 0;
	253
	254	switch (state) {
	255	case STATE_RADIO_ON:
a9b3a9f7 ID	256	retval = rt2800pci_enable_radio(rt2x00dev);
	257	break;
	258	case STATE_RADIO_OFF:
	259	/*
	260	* After the radio has been disabled, the device should
	261	* be put to sleep for powersaving.
	262	*/
a9b3a9f7 ID	263	rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
a9b3a9f7 ID	264	break;
a9b3a9f7 ID	265	case STATE_RADIO_IRQ_ON:
a9b3a9f7 ID	266	case STATE_RADIO_IRQ_OFF:
b5cfde3f	267	rt2800mmio_toggle_irq(rt2x00dev, state);
a9b3a9f7 ID	268	break;
	269	case STATE_DEEP_SLEEP:
	270	case STATE_SLEEP:
	271	case STATE_STANDBY:
	272	case STATE_AWAKE:
	273	retval = rt2800pci_set_state(rt2x00dev, state);
	274	break;
	275	default:
	276	retval = -ENOTSUPP;
	277	break;
	278	}
	279
	280	if (unlikely(retval))
ec9c4989 JP	281	rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
ec9c4989 JP	282	state, retval);
a9b3a9f7 ID	283
	284	return retval;
	285	}
	286
a9b3a9f7 ID	287	/*
	288	* Device probe functions.
	289	*/
a02308e9	290	static int rt2800pci_read_eeprom(struct rt2x00_dev *rt2x00dev)
7ab71325	291	{
a02308e9 GJ	292	int retval;
a02308e9 GJ	293
68597ea8	294	if (rt2800pci_efuse_detect(rt2x00dev))
a02308e9	295	retval = rt2800pci_read_eeprom_efuse(rt2x00dev);
cea90e55	296	else
a02308e9 GJ	297	retval = rt2800pci_read_eeprom_pci(rt2x00dev);
	298
	299	return retval;
a9b3a9f7 ID	300	}
a9b3a9f7 ID	301
e783619e HS	302	static const struct ieee80211_ops rt2800pci_mac80211_ops = {
	303	.tx = rt2x00mac_tx,
	304	.start = rt2x00mac_start,
	305	.stop = rt2x00mac_stop,
	306	.add_interface = rt2x00mac_add_interface,
	307	.remove_interface = rt2x00mac_remove_interface,
	308	.config = rt2x00mac_config,
	309	.configure_filter = rt2x00mac_configure_filter,
e783619e HS	310	.set_key = rt2x00mac_set_key,
	311	.sw_scan_start = rt2x00mac_sw_scan_start,
	312	.sw_scan_complete = rt2x00mac_sw_scan_complete,
	313	.get_stats = rt2x00mac_get_stats,
	314	.get_tkip_seq = rt2800_get_tkip_seq,
	315	.set_rts_threshold = rt2800_set_rts_threshold,
a2b1328a HS	316	.sta_add = rt2x00mac_sta_add,
a2b1328a HS	317	.sta_remove = rt2x00mac_sta_remove,
e783619e HS	318	.bss_info_changed = rt2x00mac_bss_info_changed,
	319	.conf_tx = rt2800_conf_tx,
	320	.get_tsf = rt2800_get_tsf,
	321	.rfkill_poll = rt2x00mac_rfkill_poll,
	322	.ampdu_action = rt2800_ampdu_action,
f44df18c	323	.flush = rt2x00mac_flush,
977206d7	324	.get_survey = rt2800_get_survey,
e7dee444	325	.get_ringparam = rt2x00mac_get_ringparam,
5f0dd296	326	.tx_frames_pending = rt2x00mac_tx_frames_pending,
e783619e HS	327	};
e783619e HS	328
e796643e	329	static const struct rt2800_ops rt2800pci_rt2800_ops = {
b9570b66 GJ	330	.register_read = rt2x00mmio_register_read,
	331	.register_read_lock = rt2x00mmio_register_read, /* same for PCI */
	332	.register_write = rt2x00mmio_register_write,
	333	.register_write_lock = rt2x00mmio_register_write, /* same for PCI */
	334	.register_multiread = rt2x00mmio_register_multiread,
	335	.register_multiwrite = rt2x00mmio_register_multiwrite,
	336	.regbusy_read = rt2x00mmio_regbusy_read,
ad417a53 GW	337	.read_eeprom = rt2800pci_read_eeprom,
ad417a53 GW	338	.hwcrypt_disabled = rt2800pci_hwcrypt_disabled,
e796643e	339	.drv_write_firmware = rt2800pci_write_firmware,
7573afdf	340	.drv_init_registers = rt2800mmio_init_registers,
45c67550	341	.drv_get_txwi = rt2800mmio_get_txwi,
e796643e ID	342	};
e796643e ID	343
a9b3a9f7	344	static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
b5cfde3f GJ	345	.irq_handler = rt2800mmio_interrupt,
	346	.txstatus_tasklet = rt2800mmio_txstatus_tasklet,
	347	.pretbtt_tasklet = rt2800mmio_pretbtt_tasklet,
	348	.tbtt_tasklet = rt2800mmio_tbtt_tasklet,
	349	.rxdone_tasklet = rt2800mmio_rxdone_tasklet,
	350	.autowake_tasklet = rt2800mmio_autowake_tasklet,
ad417a53	351	.probe_hw = rt2800_probe_hw,
a9b3a9f7	352	.get_firmware_name = rt2800pci_get_firmware_name,
f31c9a8c ID	353	.check_firmware = rt2800_check_firmware,
f31c9a8c ID	354	.load_firmware = rt2800_load_firmware,
b9570b66 GJ	355	.initialize = rt2x00mmio_initialize,
b9570b66 GJ	356	.uninitialize = rt2x00mmio_uninitialize,
7573afdf GJ	357	.get_entry_state = rt2800mmio_get_entry_state,
7573afdf GJ	358	.clear_entry = rt2800mmio_clear_entry,
a9b3a9f7	359	.set_device_state = rt2800pci_set_device_state,
f4450616 BZ	360	.rfkill_poll = rt2800_rfkill_poll,
	361	.link_stats = rt2800_link_stats,
	362	.reset_tuner = rt2800_reset_tuner,
	363	.link_tuner = rt2800_link_tuner,
9e33a355	364	.gain_calibration = rt2800_gain_calibration,
2e9c43dd	365	.vco_calibration = rt2800_vco_calibration,
51e62469 GJ	366	.start_queue = rt2800mmio_start_queue,
	367	.kick_queue = rt2800mmio_kick_queue,
	368	.stop_queue = rt2800mmio_stop_queue,
b9570b66	369	.flush_queue = rt2x00mmio_flush_queue,
45c67550	370	.write_tx_desc = rt2800mmio_write_tx_desc,
0c5879bc	371	.write_tx_data = rt2800_write_tx_data,
f0194b2d	372	.write_beacon = rt2800_write_beacon,
69cf36a4	373	.clear_beacon = rt2800_clear_beacon,
d10b7547	374	.fill_rxdone = rt2800mmio_fill_rxdone,
f4450616 BZ	375	.config_shared_key = rt2800_config_shared_key,
	376	.config_pairwise_key = rt2800_config_pairwise_key,
	377	.config_filter = rt2800_config_filter,
	378	.config_intf = rt2800_config_intf,
	379	.config_erp = rt2800_config_erp,
	380	.config_ant = rt2800_config_ant,
	381	.config = rt2800_config,
a2b1328a HS	382	.sta_add = rt2800_sta_add,
a2b1328a HS	383	.sta_remove = rt2800_sta_remove,
a9b3a9f7 ID	384	};
a9b3a9f7 ID	385
a9b3a9f7	386	static const struct rt2x00_ops rt2800pci_ops = {
04d0362e	387	.name = KBUILD_MODNAME,
3a1c0128	388	.drv_data_size = sizeof(struct rt2800_drv_data),
04d0362e GW	389	.max_ap_intf = 8,
	390	.eeprom_size = EEPROM_SIZE,
	391	.rf_size = RF_SIZE,
	392	.tx_queues = NUM_TX_QUEUES,
51e62469	393	.queue_init = rt2800mmio_queue_init,
04d0362e	394	.lib = &rt2800pci_rt2x00_ops,
e796643e	395	.drv = &rt2800pci_rt2800_ops,
e783619e	396	.hw = &rt2800pci_mac80211_ops,
a9b3a9f7	397	#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e	398	.debugfs = &rt2800_rt2x00debug,
a9b3a9f7 ID	399	#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
	400	};
	401
	402	/*
	403	* RT2800pci module information.
	404	*/
a3aa1884	405	static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
e01ae27f GW	406	{ PCI_DEVICE(0x1814, 0x0601) },
	407	{ PCI_DEVICE(0x1814, 0x0681) },
	408	{ PCI_DEVICE(0x1814, 0x0701) },
	409	{ PCI_DEVICE(0x1814, 0x0781) },
	410	{ PCI_DEVICE(0x1814, 0x3090) },
	411	{ PCI_DEVICE(0x1814, 0x3091) },
	412	{ PCI_DEVICE(0x1814, 0x3092) },
	413	{ PCI_DEVICE(0x1432, 0x7708) },
	414	{ PCI_DEVICE(0x1432, 0x7727) },
	415	{ PCI_DEVICE(0x1432, 0x7728) },
	416	{ PCI_DEVICE(0x1432, 0x7738) },
	417	{ PCI_DEVICE(0x1432, 0x7748) },
	418	{ PCI_DEVICE(0x1432, 0x7758) },
	419	{ PCI_DEVICE(0x1432, 0x7768) },
	420	{ PCI_DEVICE(0x1462, 0x891a) },
	421	{ PCI_DEVICE(0x1a3b, 0x1059) },
a89534ed WH	422	#ifdef CONFIG_RT2800PCI_RT3290
	423	{ PCI_DEVICE(0x1814, 0x3290) },
	424	#endif
f93bc9b3	425	#ifdef CONFIG_RT2800PCI_RT33XX
e01ae27f	426	{ PCI_DEVICE(0x1814, 0x3390) },
f93bc9b3	427	#endif
de1ebdce	428	#ifdef CONFIG_RT2800PCI_RT35XX
e01ae27f GW	429	{ PCI_DEVICE(0x1432, 0x7711) },
	430	{ PCI_DEVICE(0x1432, 0x7722) },
	431	{ PCI_DEVICE(0x1814, 0x3060) },
	432	{ PCI_DEVICE(0x1814, 0x3062) },
	433	{ PCI_DEVICE(0x1814, 0x3562) },
	434	{ PCI_DEVICE(0x1814, 0x3592) },
	435	{ PCI_DEVICE(0x1814, 0x3593) },
c4806014	436	{ PCI_DEVICE(0x1814, 0x359f) },
60687ba7 RST	437	#endif
60687ba7 RST	438	#ifdef CONFIG_RT2800PCI_RT53XX
ccf91bd6	439	{ PCI_DEVICE(0x1814, 0x5360) },
f57d7b6c	440	{ PCI_DEVICE(0x1814, 0x5362) },
e01ae27f	441	{ PCI_DEVICE(0x1814, 0x5390) },
f57d7b6c	442	{ PCI_DEVICE(0x1814, 0x5392) },
5126d97e	443	{ PCI_DEVICE(0x1814, 0x539a) },
2aed6915	444	{ PCI_DEVICE(0x1814, 0x539b) },
71e0b38c	445	{ PCI_DEVICE(0x1814, 0x539f) },
de1ebdce	446	#endif
a9b3a9f7 ID	447	{ 0, }
	448	};
	449
	450	MODULE_AUTHOR(DRV_PROJECT);
	451	MODULE_VERSION(DRV_VERSION);
	452	MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
	453	MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
a9b3a9f7 ID	454	MODULE_FIRMWARE(FIRMWARE_RT2860);
a9b3a9f7 ID	455	MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
a9b3a9f7 ID	456	MODULE_LICENSE("GPL");
a9b3a9f7 ID	457
e01ae27f GW	458	static int rt2800pci_probe(struct pci_dev *pci_dev,
	459	const struct pci_device_id *id)
	460	{
	461	return rt2x00pci_probe(pci_dev, &rt2800pci_ops);
	462	}
	463
a9b3a9f7 ID	464	static struct pci_driver rt2800pci_driver = {
	465	.name = KBUILD_MODNAME,
	466	.id_table = rt2800pci_device_table,
e01ae27f	467	.probe = rt2800pci_probe,
69202359	468	.remove = rt2x00pci_remove,
a9b3a9f7 ID	469	.suspend = rt2x00pci_suspend,
	470	.resume = rt2x00pci_resume,
	471	};
fe7ef7c6	472
a1b13b9a	473	module_pci_driver(rt2800pci_driver);