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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2800pci.c
CommitLineData
a9b3a9f7 1/*
96481b20 2 Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14
GW		 3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
a9b3a9f7
ID		 10 <http://rt2x00.serialmonkey.com>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 */
27
28/*
29 Module: rt2800pci
30 Abstract: rt2800pci device specific routines.
31 Supported chipsets: RT2800E & RT2800ED.
32 */
33
a9b3a9f7
ID		 34#include <linux/delay.h>
35#include <linux/etherdevice.h>
36#include <linux/init.h>
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/pci.h>
40#include <linux/platform_device.h>
41#include <linux/eeprom_93cx6.h>
42
43#include "rt2x00.h"
69a2bac8 44#include "rt2x00mmio.h"
a9b3a9f7
ID		 45#include "rt2x00pci.h"
46#include "rt2x00soc.h"
7ef5cc92 47#include "rt2800lib.h"
b54f78a8 48#include "rt2800.h"
a9b3a9f7
ID		 49#include "rt2800pci.h"
50
a9b3a9f7
ID		 51/*
52 * Allow hardware encryption to be disabled.
53 */
eb939922 54static bool modparam_nohwcrypt = false;
a9b3a9f7
ID		 55module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
56MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
57
ad417a53
GW		 58static bool rt2800pci_hwcrypt_disabled(struct rt2x00_dev *rt2x00dev)
59{
60 return modparam_nohwcrypt;
61}
62
a9b3a9f7
ID		 63static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
64{
65 unsigned int i;
66 u32 reg;
67
f18d4463
LC		 68 /*
69 * SOC devices don't support MCU requests.
70 */
71 if (rt2x00_is_soc(rt2x00dev))
72 return;
73
a9b3a9f7 74 for (i = 0; i < 200; i++) {
b9570b66 75 rt2x00mmio_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
a9b3a9f7
ID		 76
77 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
78 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
79 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
80 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
81 break;
82
83 udelay(REGISTER_BUSY_DELAY);
84 }
85
86 if (i == 200)
ec9c4989 87 rt2x00_err(rt2x00dev, "MCU request failed, no response from hardware\n");
a9b3a9f7 88
b9570b66
GJ		 89 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
90 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
a9b3a9f7
ID		 91}
92
5818a46a 93#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
a02308e9 94static int rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 95{
ef8397cf 96 void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
a9b3a9f7 97
a02308e9
GJ		 98 if (!base_addr)
99 return -ENOMEM;
100
a9b3a9f7 101 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
ef8397cf
GW		 102
103 iounmap(base_addr);
a02308e9 104 return 0;
a9b3a9f7
ID		 105}
106#else
a02308e9 107static inline int rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 108{
a02308e9 109 return -ENOMEM;
a9b3a9f7 110}
5818a46a 111#endif /* CONFIG_SOC_RT288X || CONFIG_SOC_RT305X */
a9b3a9f7 112
72c7296e 113#ifdef CONFIG_PCI
a9b3a9f7
ID		 114static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
115{
116 struct rt2x00_dev *rt2x00dev = eeprom->data;
117 u32 reg;
118
b9570b66 119 rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 120
121 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
122 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
123 eeprom->reg_data_clock =
124 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
125 eeprom->reg_chip_select =
126 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
127}
128
129static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
130{
131 struct rt2x00_dev *rt2x00dev = eeprom->data;
132 u32 reg = 0;
133
134 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
135 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
136 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
137 !!eeprom->reg_data_clock);
138 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
139 !!eeprom->reg_chip_select);
140
b9570b66 141 rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg);
a9b3a9f7
ID		 142}
143
a02308e9 144static int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
a9b3a9f7
ID		 145{
146 struct eeprom_93cx6 eeprom;
147 u32 reg;
148
b9570b66 149 rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 150
151 eeprom.data = rt2x00dev;
152 eeprom.register_read = rt2800pci_eepromregister_read;
153 eeprom.register_write = rt2800pci_eepromregister_write;
20f8b139
GW		 154 switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
155 {
156 case 0:
157 eeprom.width = PCI_EEPROM_WIDTH_93C46;
158 break;
159 case 1:
160 eeprom.width = PCI_EEPROM_WIDTH_93C66;
161 break;
162 default:
163 eeprom.width = PCI_EEPROM_WIDTH_93C86;
164 break;
165 }
a9b3a9f7
ID		 166 eeprom.reg_data_in = 0;
167 eeprom.reg_data_out = 0;
168 eeprom.reg_data_clock = 0;
169 eeprom.reg_chip_select = 0;
170
171 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
172 EEPROM_SIZE / sizeof(u16));
a02308e9
GJ		 173
174 return 0;
a9b3a9f7
ID		 175}
176
a6598682
GW		 177static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
178{
30e84034 179 return rt2800_efuse_detect(rt2x00dev);
a9b3a9f7
ID		 180}
181
a02308e9 182static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 183{
a02308e9 184 return rt2800_read_eeprom_efuse(rt2x00dev);
a9b3a9f7
ID		 185}
186#else
a02308e9 187static inline int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 188{
a02308e9 189 return -EOPNOTSUPP;
a9b3a9f7
ID		 190}
191
a6598682
GW		 192static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
193{
194 return 0;
195}
196
a02308e9 197static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 198{
a02308e9 199 return -EOPNOTSUPP;
a9b3a9f7 200}
72c7296e 201#endif /* CONFIG_PCI */
a9b3a9f7 202
5450b7e2
ID		 203/*
204 * Queue handlers.
205 */
206static void rt2800pci_start_queue(struct data_queue *queue)
207{
208 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
209 u32 reg;
210
211 switch (queue->qid) {
212 case QID_RX:
b9570b66 213 rt2x00mmio_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5450b7e2 214 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
b9570b66 215 rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5450b7e2
ID		 216 break;
217 case QID_BEACON:
b9570b66 218 rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
5450b7e2
ID		 219 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
220 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
221 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
b9570b66 222 rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
69cf36a4 223
b9570b66 224 rt2x00mmio_register_read(rt2x00dev, INT_TIMER_EN, &reg);
69cf36a4 225 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 1);
b9570b66 226 rt2x00mmio_register_write(rt2x00dev, INT_TIMER_EN, reg);
5450b7e2
ID		 227 break;
228 default:
229 break;
6403eab1 230 }
5450b7e2
ID		 231}
232
233static void rt2800pci_kick_queue(struct data_queue *queue)
234{
235 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
236 struct queue_entry *entry;
237
238 switch (queue->qid) {
f615e9a3
ID		 239 case QID_AC_VO:
240 case QID_AC_VI:
5450b7e2
ID		 241 case QID_AC_BE:
242 case QID_AC_BK:
5450b7e2 243 entry = rt2x00queue_get_entry(queue, Q_INDEX);
b9570b66
GJ		 244 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX(queue->qid),
245 entry->entry_idx);
5450b7e2
ID		 246 break;
247 case QID_MGMT:
248 entry = rt2x00queue_get_entry(queue, Q_INDEX);
b9570b66
GJ		 249 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX(5),
250 entry->entry_idx);
5450b7e2
ID		 251 break;
252 default:
253 break;
254 }
255}
256
257static void rt2800pci_stop_queue(struct data_queue *queue)
258{
259 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
260 u32 reg;
261
262 switch (queue->qid) {
263 case QID_RX:
b9570b66 264 rt2x00mmio_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5450b7e2 265 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
b9570b66 266 rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5450b7e2
ID		 267 break;
268 case QID_BEACON:
b9570b66 269 rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
5450b7e2
ID		 270 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
271 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
272 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
b9570b66 273 rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
69cf36a4 274
b9570b66 275 rt2x00mmio_register_read(rt2x00dev, INT_TIMER_EN, &reg);
69cf36a4 276 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 0);
b9570b66 277 rt2x00mmio_register_write(rt2x00dev, INT_TIMER_EN, reg);
a9d61e9e
HS		 278
279 /*
abc11994
HS		 280 * Wait for current invocation to finish. The tasklet
281 * won't be scheduled anymore afterwards since we disabled
282 * the TBTT and PRE TBTT timer.
a9d61e9e 283 */
abc11994
HS		 284 tasklet_kill(&rt2x00dev->tbtt_tasklet);
285 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
286
5450b7e2
ID		 287 break;
288 default:
289 break;
290 }
291}
292
a9b3a9f7
ID		 293/*
294 * Firmware functions
295 */
296static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
297{
a89534ed
WH		 298 /*
299 * Chip rt3290 use specific 4KB firmware named rt3290.bin.
300 */
301 if (rt2x00_rt(rt2x00dev, RT3290))
302 return FIRMWARE_RT3290;
303 else
304 return FIRMWARE_RT2860;
a9b3a9f7
ID		 305}
306
f31c9a8c 307static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
a9b3a9f7
ID		 308 const u8 *data, const size_t len)
309{
a9b3a9f7
ID		 310 u32 reg;
311
a9b3a9f7
ID		 312 /*
313 * enable Host program ram write selection
314 */
315 reg = 0;
316 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
b9570b66 317 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
a9b3a9f7
ID		 318
319 /*
320 * Write firmware to device.
321 */
b9570b66
GJ		 322 rt2x00mmio_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
323 data, len);
a9b3a9f7 324
b9570b66
GJ		 325 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
326 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
a9b3a9f7 327
b9570b66
GJ		 328 rt2x00mmio_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
329 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
a9b3a9f7
ID		 330
331 return 0;
332}
333
334/*
335 * Initialization functions.
336 */
337static bool rt2800pci_get_entry_state(struct queue_entry *entry)
338{
b9570b66 339 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
a9b3a9f7
ID		 340 u32 word;
341
342 if (entry->queue->qid == QID_RX) {
343 rt2x00_desc_read(entry_priv->desc, 1, &word);
344
345 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
346 } else {
347 rt2x00_desc_read(entry_priv->desc, 1, &word);
348
349 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
350 }
351}
352
353static void rt2800pci_clear_entry(struct queue_entry *entry)
354{
b9570b66 355 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
a9b3a9f7 356 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95192339 357 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
a9b3a9f7
ID		 358 u32 word;
359
360 if (entry->queue->qid == QID_RX) {
361 rt2x00_desc_read(entry_priv->desc, 0, &word);
362 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
363 rt2x00_desc_write(entry_priv->desc, 0, word);
364
365 rt2x00_desc_read(entry_priv->desc, 1, &word);
366 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
367 rt2x00_desc_write(entry_priv->desc, 1, word);
95192339
HS		 368
369 /*
370 * Set RX IDX in register to inform hardware that we have
371 * handled this entry and it is available for reuse again.
372 */
b9570b66
GJ		 373 rt2x00mmio_register_write(rt2x00dev, RX_CRX_IDX,
374 entry->entry_idx);
a9b3a9f7
ID		 375 } else {
376 rt2x00_desc_read(entry_priv->desc, 1, &word);
377 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
378 rt2x00_desc_write(entry_priv->desc, 1, word);
379 }
380}
381
382static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
383{
b9570b66 384 struct queue_entry_priv_mmio *entry_priv;
a9b3a9f7 385
a9b3a9f7
ID		 386 /*
387 * Initialize registers.
388 */
389 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
b9570b66
GJ		 390 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR0,
391 entry_priv->desc_dma);
392 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT0,
393 rt2x00dev->tx[0].limit);
394 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX0, 0);
395 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX0, 0);
a9b3a9f7
ID		 396
397 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
b9570b66
GJ		 398 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR1,
399 entry_priv->desc_dma);
400 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT1,
401 rt2x00dev->tx[1].limit);
402 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX1, 0);
403 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX1, 0);
a9b3a9f7
ID		 404
405 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
b9570b66
GJ		 406 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR2,
407 entry_priv->desc_dma);
408 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT2,
409 rt2x00dev->tx[2].limit);
410 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX2, 0);
411 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX2, 0);
a9b3a9f7
ID		 412
413 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
b9570b66
GJ		 414 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR3,
415 entry_priv->desc_dma);
416 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT3,
417 rt2x00dev->tx[3].limit);
418 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX3, 0);
419 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX3, 0);
420
421 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR4, 0);
422 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT4, 0);
423 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX4, 0);
424 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX4, 0);
425
426 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR5, 0);
427 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT5, 0);
428 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX5, 0);
429 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX5, 0);
3a4b43fd 430
a9b3a9f7 431 entry_priv = rt2x00dev->rx->entries[0].priv_data;
b9570b66
GJ		 432 rt2x00mmio_register_write(rt2x00dev, RX_BASE_PTR,
433 entry_priv->desc_dma);
434 rt2x00mmio_register_write(rt2x00dev, RX_MAX_CNT,
435 rt2x00dev->rx[0].limit);
436 rt2x00mmio_register_write(rt2x00dev, RX_CRX_IDX,
437 rt2x00dev->rx[0].limit - 1);
438 rt2x00mmio_register_write(rt2x00dev, RX_DRX_IDX, 0);
a9b3a9f7 439
f7b395e9 440 rt2800_disable_wpdma(rt2x00dev);
a9b3a9f7 441
b9570b66 442 rt2x00mmio_register_write(rt2x00dev, DELAY_INT_CFG, 0);
a9b3a9f7
ID		 443
444 return 0;
445}
446
a9b3a9f7
ID		 447/*
448 * Device state switch handlers.
449 */
a9b3a9f7
ID		 450static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
451 enum dev_state state)
452{
a9b3a9f7 453 u32 reg;
a9d61e9e 454 unsigned long flags;
a9b3a9f7
ID		 455
456 /*
457 * When interrupts are being enabled, the interrupt registers
458 * should clear the register to assure a clean state.
459 */
460 if (state == STATE_RADIO_IRQ_ON) {
b9570b66
GJ		 461 rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
462 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
a9d61e9e 463 }
a9b3a9f7 464
a9d61e9e 465 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
dfd00c4c
SG		 466 reg = 0;
467 if (state == STATE_RADIO_IRQ_ON) {
468 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, 1);
469 rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, 1);
470 rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, 1);
471 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, 1);
472 rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, 1);
473 }
b9570b66 474 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
a9d61e9e
HS		 475 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
476
477 if (state == STATE_RADIO_IRQ_OFF) {
478 /*
abc11994 479 * Wait for possibly running tasklets to finish.
a9d61e9e 480 */
abc11994
HS		 481 tasklet_kill(&rt2x00dev->txstatus_tasklet);
482 tasklet_kill(&rt2x00dev->rxdone_tasklet);
483 tasklet_kill(&rt2x00dev->autowake_tasklet);
484 tasklet_kill(&rt2x00dev->tbtt_tasklet);
485 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
a9d61e9e 486 }
a9b3a9f7
ID		 487}
488
e3a896b9
GW		 489static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
490{
491 u32 reg;
492
493 /*
494 * Reset DMA indexes
495 */
b9570b66 496 rt2x00mmio_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
e3a896b9
GW		 497 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
498 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
499 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
500 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
501 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
502 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
503 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
b9570b66 504 rt2x00mmio_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
e3a896b9 505
b9570b66
GJ		 506 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
507 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
e3a896b9 508
872834df 509 if (rt2x00_is_pcie(rt2x00dev) &&
41caa760
GJ		 510 (rt2x00_rt(rt2x00dev, RT3090) ||
511 rt2x00_rt(rt2x00dev, RT3390) ||
512 rt2x00_rt(rt2x00dev, RT3572) ||
513 rt2x00_rt(rt2x00dev, RT3593) ||
2ed71884 514 rt2x00_rt(rt2x00dev, RT5390) ||
41caa760
GJ		 515 rt2x00_rt(rt2x00dev, RT5392) ||
516 rt2x00_rt(rt2x00dev, RT5592))) {
b9570b66 517 rt2x00mmio_register_read(rt2x00dev, AUX_CTRL, &reg);
adde5882
GJ		 518 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
519 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
b9570b66 520 rt2x00mmio_register_write(rt2x00dev, AUX_CTRL, reg);
adde5882 521 }
60687ba7 522
b9570b66 523 rt2x00mmio_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
e3a896b9 524
2a48e8ae 525 reg = 0;
e3a896b9
GW		 526 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
527 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
b9570b66 528 rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
e3a896b9 529
b9570b66 530 rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
e3a896b9
GW		 531
532 return 0;
533}
534
a9b3a9f7
ID		 535static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
536{
e8b461c3
JK		 537 int retval;
538
52b8243b
JK		 539 /* Wait for DMA, ignore error until we initialize queues. */
540 rt2800_wait_wpdma_ready(rt2x00dev);
541
542 if (unlikely(rt2800pci_init_queues(rt2x00dev)))
a9b3a9f7
ID		 543 return -EIO;
544
e8b461c3
JK		 545 retval = rt2800_enable_radio(rt2x00dev);
546 if (retval)
547 return retval;
548
549 /* After resume MCU_BOOT_SIGNAL will trash these. */
b9570b66
GJ		 550 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
551 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
e8b461c3
JK		 552
553 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_RADIO_OFF, 0xff, 0x02);
554 rt2800pci_mcu_status(rt2x00dev, TOKEN_RADIO_OFF);
555
556 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP, 0, 0);
557 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
558
559 return retval;
a9b3a9f7
ID		 560}
561
562static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
563{
7f6e144f
RJH		 564 if (rt2x00_is_soc(rt2x00dev)) {
565 rt2800_disable_radio(rt2x00dev);
b9570b66
GJ		 566 rt2x00mmio_register_write(rt2x00dev, PWR_PIN_CFG, 0);
567 rt2x00mmio_register_write(rt2x00dev, TX_PIN_CFG, 0);
7f6e144f 568 }
a9b3a9f7
ID		 569}
570
571static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
572 enum dev_state state)
573{
a9b3a9f7 574 if (state == STATE_AWAKE) {
09a3311c
JK		 575 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP,
576 0, 0x02);
577 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
7f6e144f 578 } else if (state == STATE_SLEEP) {
b9570b66
GJ		 579 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
580 0xffffffff);
581 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID,
582 0xffffffff);
09a3311c
JK		 583 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_SLEEP,
584 0xff, 0x01);
a9b3a9f7
ID		 585 }
586
587 return 0;
588}
589
590static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
591 enum dev_state state)
592{
593 int retval = 0;
594
595 switch (state) {
596 case STATE_RADIO_ON:
a9b3a9f7
ID		 597 retval = rt2800pci_enable_radio(rt2x00dev);
598 break;
599 case STATE_RADIO_OFF:
600 /*
601 * After the radio has been disabled, the device should
602 * be put to sleep for powersaving.
603 */
604 rt2800pci_disable_radio(rt2x00dev);
605 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
606 break;
a9b3a9f7
ID		 607 case STATE_RADIO_IRQ_ON:
608 case STATE_RADIO_IRQ_OFF:
609 rt2800pci_toggle_irq(rt2x00dev, state);
610 break;
611 case STATE_DEEP_SLEEP:
612 case STATE_SLEEP:
613 case STATE_STANDBY:
614 case STATE_AWAKE:
615 retval = rt2800pci_set_state(rt2x00dev, state);
616 break;
617 default:
618 retval = -ENOTSUPP;
619 break;
620 }
621
622 if (unlikely(retval))
ec9c4989
JP		 623 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
624 state, retval);
a9b3a9f7
ID		 625
626 return retval;
627}
628
629/*
630 * TX descriptor initialization
631 */
0c5879bc 632static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)
a9b3a9f7 633{
0c5879bc 634 return (__le32 *) entry->skb->data;
745b1ae3
HS		 635}
636
93331458 637static void rt2800pci_write_tx_desc(struct queue_entry *entry,
745b1ae3
HS		 638 struct txentry_desc *txdesc)
639{
93331458 640 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
b9570b66 641 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
85b7a8b3 642 __le32 *txd = entry_priv->desc;
745b1ae3 643 u32 word;
a53aff5d 644 const unsigned int txwi_size = entry->queue->winfo_size;
745b1ae3 645
a9b3a9f7
ID		 646 /*
647 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
648 * must contains a TXWI structure + 802.11 header + padding + 802.11
649 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
650 * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
651 * data. It means that LAST_SEC0 is always 0.
652 */
653
654 /*
655 * Initialize TX descriptor
656 */
3de3d966 657 word = 0;
a9b3a9f7
ID		 658 rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
659 rt2x00_desc_write(txd, 0, word);
660
3de3d966 661 word = 0;
93331458 662 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);
a9b3a9f7
ID		 663 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
664 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
665 rt2x00_set_field32(&word, TXD_W1_BURST,
666 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
a53aff5d 667 rt2x00_set_field32(&word, TXD_W1_SD_LEN0, txwi_size);
a9b3a9f7
ID		 668 rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
669 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
670 rt2x00_desc_write(txd, 1, word);
671
3de3d966 672 word = 0;
a9b3a9f7 673 rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
a53aff5d 674 skbdesc->skb_dma + txwi_size);
a9b3a9f7
ID		 675 rt2x00_desc_write(txd, 2, word);
676
3de3d966 677 word = 0;
a9b3a9f7
ID		 678 rt2x00_set_field32(&word, TXD_W3_WIV,
679 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
680 rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
681 rt2x00_desc_write(txd, 3, word);
85b7a8b3
GW		 682
683 /*
684 * Register descriptor details in skb frame descriptor.
685 */
686 skbdesc->desc = txd;
687 skbdesc->desc_len = TXD_DESC_SIZE;
a9b3a9f7
ID		 688}
689
a9b3a9f7
ID		 690/*
691 * RX control handlers
692 */
693static void rt2800pci_fill_rxdone(struct queue_entry *entry,
694 struct rxdone_entry_desc *rxdesc)
695{
b9570b66 696 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
a9b3a9f7 697 __le32 *rxd = entry_priv->desc;
2de64dd2
GW		 698 u32 word;
699
700 rt2x00_desc_read(rxd, 3, &word);
701
702 if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
a9b3a9f7
ID		 703 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
704
78b8f3b0
GW		 705 /*
706 * Unfortunately we don't know the cipher type used during
707 * decryption. This prevents us from correct providing
708 * correct statistics through debugfs.
709 */
2de64dd2 710 rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
a9b3a9f7 711
2de64dd2 712 if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
a9b3a9f7
ID		 713 /*
714 * Hardware has stripped IV/EIV data from 802.11 frame during
715 * decryption. Unfortunately the descriptor doesn't contain
716 * any fields with the EIV/IV data either, so they can't
717 * be restored by rt2x00lib.
718 */
719 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
720
a45f369d
GW		 721 /*
722 * The hardware has already checked the Michael Mic and has
723 * stripped it from the frame. Signal this to mac80211.
724 */
725 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
726
a9b3a9f7
ID		 727 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
728 rxdesc->flags |= RX_FLAG_DECRYPTED;
729 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
730 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
731 }
732
2de64dd2 733 if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
a9b3a9f7
ID		 734 rxdesc->dev_flags |= RXDONE_MY_BSS;
735
2de64dd2 736 if (rt2x00_get_field32(word, RXD_W3_L2PAD))
a9b3a9f7 737 rxdesc->dev_flags |= RXDONE_L2PAD;
a9b3a9f7 738
a9b3a9f7 739 /*
2de64dd2 740 * Process the RXWI structure that is at the start of the buffer.
a9b3a9f7 741 */
74861922 742 rt2800_process_rxwi(entry, rxdesc);
a9b3a9f7
ID		 743}
744
745/*
746 * Interrupt functions.
747 */
4d66edc8
GW		 748static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
749{
750 struct ieee80211_conf conf = { .flags = 0 };
751 struct rt2x00lib_conf libconf = { .conf = &conf };
752
753 rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
754}
755
8857d6dc
HS		 756static bool rt2800pci_txdone_entry_check(struct queue_entry *entry, u32 status)
757{
758 __le32 *txwi;
759 u32 word;
760 int wcid, tx_wcid;
761
762 wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID);
763
764 txwi = rt2800_drv_get_txwi(entry);
765 rt2x00_desc_read(txwi, 1, &word);
766 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
767
768 return (tx_wcid == wcid);
769}
770
771static bool rt2800pci_txdone_find_entry(struct queue_entry *entry, void *data)
772{
773 u32 status = *(u32 *)data;
774
775 /*
776 * rt2800pci hardware might reorder frames when exchanging traffic
777 * with multiple BA enabled STAs.
778 *
779 * For example, a tx queue
780 * [ STA1 | STA2 | STA1 | STA2 ]
781 * can result in tx status reports
782 * [ STA1 | STA1 | STA2 | STA2 ]
783 * when the hw decides to aggregate the frames for STA1 into one AMPDU.
784 *
785 * To mitigate this effect, associate the tx status to the first frame
786 * in the tx queue with a matching wcid.
787 */
788 if (rt2800pci_txdone_entry_check(entry, status) &&
789 !test_bit(ENTRY_DATA_STATUS_SET, &entry->flags)) {
790 /*
791 * Got a matching frame, associate the tx status with
792 * the frame
793 */
794 entry->status = status;
795 set_bit(ENTRY_DATA_STATUS_SET, &entry->flags);
796 return true;
797 }
798
799 /* Check the next frame */
800 return false;
801}
802
803static bool rt2800pci_txdone_match_first(struct queue_entry *entry, void *data)
804{
805 u32 status = *(u32 *)data;
806
807 /*
808 * Find the first frame without tx status and assign this status to it
809 * regardless if it matches or not.
810 */
811 if (!test_bit(ENTRY_DATA_STATUS_SET, &entry->flags)) {
812 /*
813 * Got a matching frame, associate the tx status with
814 * the frame
815 */
816 entry->status = status;
817 set_bit(ENTRY_DATA_STATUS_SET, &entry->flags);
818 return true;
819 }
820
821 /* Check the next frame */
822 return false;
823}
824static bool rt2800pci_txdone_release_entries(struct queue_entry *entry,
825 void *data)
826{
827 if (test_bit(ENTRY_DATA_STATUS_SET, &entry->flags)) {
828 rt2800_txdone_entry(entry, entry->status,
829 rt2800pci_get_txwi(entry));
830 return false;
831 }
832
833 /* No more frames to release */
834 return true;
835}
836
2e7798b7 837static bool rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
96c3da7d
HS		 838{
839 struct data_queue *queue;
96c3da7d
HS		 840 u32 status;
841 u8 qid;
2e7798b7 842 int max_tx_done = 16;
96c3da7d 843
c4d63244 844 while (kfifo_get(&rt2x00dev->txstatus_fifo, &status)) {
12eec2cc 845 qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
87443e87 846 if (unlikely(qid >= QID_RX)) {
96c3da7d
HS		 847 /*
848 * Unknown queue, this shouldn't happen. Just drop
849 * this tx status.
850 */
ec9c4989
JP		 851 rt2x00_warn(rt2x00dev, "Got TX status report with unexpected pid %u, dropping\n",
852 qid);
96c3da7d
HS		 853 break;
854 }
855
11f818e0 856 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
96c3da7d
HS		 857 if (unlikely(queue == NULL)) {
858 /*
859 * The queue is NULL, this shouldn't happen. Stop
860 * processing here and drop the tx status
861 */
ec9c4989
JP		 862 rt2x00_warn(rt2x00dev, "Got TX status for an unavailable queue %u, dropping\n",
863 qid);
96c3da7d
HS		 864 break;
865 }
866
87443e87 867 if (unlikely(rt2x00queue_empty(queue))) {
96c3da7d
HS		 868 /*
869 * The queue is empty. Stop processing here
870 * and drop the tx status.
871 */
ec9c4989
JP		 872 rt2x00_warn(rt2x00dev, "Got TX status for an empty queue %u, dropping\n",
873 qid);
96c3da7d
HS		 874 break;
875 }
876
8857d6dc
HS		 877 /*
878 * Let's associate this tx status with the first
879 * matching frame.
880 */
881 if (!rt2x00queue_for_each_entry(queue, Q_INDEX_DONE,
882 Q_INDEX, &status,
883 rt2800pci_txdone_find_entry)) {
884 /*
885 * We cannot match the tx status to any frame, so just
886 * use the first one.
887 */
888 if (!rt2x00queue_for_each_entry(queue, Q_INDEX_DONE,
889 Q_INDEX, &status,
890 rt2800pci_txdone_match_first)) {
ec9c4989
JP		 891 rt2x00_warn(rt2x00dev, "No frame found for TX status on queue %u, dropping\n",
892 qid);
8857d6dc
HS		 893 break;
894 }
895 }
896
897 /*
898 * Release all frames with a valid tx status.
899 */
900 rt2x00queue_for_each_entry(queue, Q_INDEX_DONE,
901 Q_INDEX, NULL,
902 rt2800pci_txdone_release_entries);
2e7798b7
HS		 903
904 if (--max_tx_done == 0)
905 break;
96c3da7d 906 }
2e7798b7
HS		 907
908 return !max_tx_done;
96c3da7d
HS		 909}
910
7a5a681a
HS		 911static inline void rt2800pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
912 struct rt2x00_field32 irq_field)
a9b3a9f7 913{
a9d61e9e 914 u32 reg;
a9b3a9f7
ID		 915
916 /*
a9d61e9e
HS		 917 * Enable a single interrupt. The interrupt mask register
918 * access needs locking.
9f926fb5 919 */
0aa13b2e 920 spin_lock_irq(&rt2x00dev->irqmask_lock);
b9570b66 921 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, &reg);
a9d61e9e 922 rt2x00_set_field32(&reg, irq_field, 1);
b9570b66 923 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
0aa13b2e 924 spin_unlock_irq(&rt2x00dev->irqmask_lock);
a9d61e9e 925}
9f926fb5 926
a9d61e9e
HS		 927static void rt2800pci_txstatus_tasklet(unsigned long data)
928{
2e7798b7
HS		 929 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
930 if (rt2800pci_txdone(rt2x00dev))
931 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
9f926fb5
HS		 932
933 /*
a9d61e9e
HS		 934 * No need to enable the tx status interrupt here as we always
935 * leave it enabled to minimize the possibility of a tx status
936 * register overflow. See comment in interrupt handler.
a9b3a9f7 937 */
a9d61e9e 938}
a9b3a9f7 939
a9d61e9e
HS		 940static void rt2800pci_pretbtt_tasklet(unsigned long data)
941{
942 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
943 rt2x00lib_pretbtt(rt2x00dev);
abc11994
HS		 944 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
945 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_PRE_TBTT);
a9d61e9e 946}
4d66edc8 947
a9d61e9e
HS		 948static void rt2800pci_tbtt_tasklet(unsigned long data)
949{
950 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
290d6089
HS		 951 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
952 u32 reg;
953
a9d61e9e 954 rt2x00lib_beacondone(rt2x00dev);
290d6089
HS		 955
956 if (rt2x00dev->intf_ap_count) {
957 /*
958 * The rt2800pci hardware tbtt timer is off by 1us per tbtt
959 * causing beacon skew and as a result causing problems with
960 * some powersaving clients over time. Shorten the beacon
961 * interval every 64 beacons by 64us to mitigate this effect.
962 */
963 if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 2)) {
b9570b66 964 rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
290d6089
HS		 965 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
966 (rt2x00dev->beacon_int * 16) - 1);
b9570b66 967 rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
290d6089 968 } else if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 1)) {
b9570b66 969 rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
290d6089
HS		 970 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
971 (rt2x00dev->beacon_int * 16));
b9570b66 972 rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
290d6089
HS		 973 }
974 drv_data->tbtt_tick++;
975 drv_data->tbtt_tick %= BCN_TBTT_OFFSET;
976 }
977
abc11994
HS		 978 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
979 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TBTT);
a9d61e9e 980}
78e256c9 981
a9d61e9e
HS		 982static void rt2800pci_rxdone_tasklet(unsigned long data)
983{
984 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
b9570b66 985 if (rt2x00mmio_rxdone(rt2x00dev))
16638937 986 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
abc11994 987 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
16638937 988 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RX_DONE);
a9d61e9e
HS		 989}
990
991static void rt2800pci_autowake_tasklet(unsigned long data)
992{
993 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
994 rt2800pci_wakeup(rt2x00dev);
abc11994
HS		 995 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
996 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_AUTO_WAKEUP);
a9b3a9f7
ID		 997}
998
96c3da7d
HS		 999static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
1000{
1001 u32 status;
1002 int i;
1003
1004 /*
1005 * The TX_FIFO_STATUS interrupt needs special care. We should
1006 * read TX_STA_FIFO but we should do it immediately as otherwise
1007 * the register can overflow and we would lose status reports.
1008 *
1009 * Hence, read the TX_STA_FIFO register and copy all tx status
1010 * reports into a kernel FIFO which is handled in the txstatus
1011 * tasklet. We use a tasklet to process the tx status reports
1012 * because we can schedule the tasklet multiple times (when the
1013 * interrupt fires again during tx status processing).
1014 *
1015 * Furthermore we don't disable the TX_FIFO_STATUS
1016 * interrupt here but leave it enabled so that the TX_STA_FIFO
3736fe58 1017 * can also be read while the tx status tasklet gets executed.
96c3da7d
HS		 1018 *
1019 * Since we have only one producer and one consumer we don't
1020 * need to lock the kfifo.
1021 */
1cfcbe4c 1022 for (i = 0; i < rt2x00dev->tx->limit; i++) {
b9570b66 1023 rt2x00mmio_register_read(rt2x00dev, TX_STA_FIFO, &status);
96c3da7d
HS		 1024
1025 if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
1026 break;
1027
c4d63244 1028 if (!kfifo_put(&rt2x00dev->txstatus_fifo, &status)) {
ec9c4989 1029 rt2x00_warn(rt2x00dev, "TX status FIFO overrun, drop tx status report\n");
96c3da7d
HS		 1030 break;
1031 }
1032 }
1033
1034 /* Schedule the tasklet for processing the tx status. */
1035 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
1036}
1037
78e256c9
HS		 1038static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
1039{
1040 struct rt2x00_dev *rt2x00dev = dev_instance;
a9d61e9e 1041 u32 reg, mask;
78e256c9
HS		 1042
1043 /* Read status and ACK all interrupts */
b9570b66
GJ		 1044 rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1045 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
78e256c9
HS		 1046
1047 if (!reg)
1048 return IRQ_NONE;
1049
1050 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1051 return IRQ_HANDLED;
1052
a9d61e9e
HS		 1053 /*
1054 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
1055 * for interrupts and interrupt masks we can just use the value of
1056 * INT_SOURCE_CSR to create the interrupt mask.
1057 */
1058 mask = ~reg;
78e256c9 1059
a9d61e9e
HS		 1060 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) {
1061 rt2800pci_txstatus_interrupt(rt2x00dev);
96c3da7d 1062 /*
a9d61e9e 1063 * Never disable the TX_FIFO_STATUS interrupt.
96c3da7d 1064 */
a9d61e9e
HS		 1065 rt2x00_set_field32(&mask, INT_MASK_CSR_TX_FIFO_STATUS, 1);
1066 }
96c3da7d 1067
a9d61e9e
HS		 1068 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
1069 tasklet_hi_schedule(&rt2x00dev->pretbtt_tasklet);
78e256c9 1070
a9d61e9e
HS		 1071 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
1072 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
96c3da7d 1073
a9d61e9e
HS		 1074 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
1075 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
78e256c9 1076
a9d61e9e
HS		 1077 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
1078 tasklet_schedule(&rt2x00dev->autowake_tasklet);
1079
1080 /*
1081 * Disable all interrupts for which a tasklet was scheduled right now,
1082 * the tasklet will reenable the appropriate interrupts.
1083 */
0aa13b2e 1084 spin_lock(&rt2x00dev->irqmask_lock);
b9570b66 1085 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, &reg);
a9d61e9e 1086 reg &= mask;
b9570b66 1087 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
0aa13b2e 1088 spin_unlock(&rt2x00dev->irqmask_lock);
a9d61e9e
HS		 1089
1090 return IRQ_HANDLED;
78e256c9
HS		 1091}
1092
a9b3a9f7
ID		 1093/*
1094 * Device probe functions.
1095 */
a02308e9 1096static int rt2800pci_read_eeprom(struct rt2x00_dev *rt2x00dev)
7ab71325 1097{
a02308e9
GJ		 1098 int retval;
1099
cea90e55 1100 if (rt2x00_is_soc(rt2x00dev))
a02308e9 1101 retval = rt2800pci_read_eeprom_soc(rt2x00dev);
cea90e55 1102 else if (rt2800pci_efuse_detect(rt2x00dev))
a02308e9 1103 retval = rt2800pci_read_eeprom_efuse(rt2x00dev);
cea90e55 1104 else
a02308e9
GJ		 1105 retval = rt2800pci_read_eeprom_pci(rt2x00dev);
1106
1107 return retval;
a9b3a9f7
ID		 1108}
1109
e783619e
HS		 1110static const struct ieee80211_ops rt2800pci_mac80211_ops = {
1111 .tx = rt2x00mac_tx,
1112 .start = rt2x00mac_start,
1113 .stop = rt2x00mac_stop,
1114 .add_interface = rt2x00mac_add_interface,
1115 .remove_interface = rt2x00mac_remove_interface,
1116 .config = rt2x00mac_config,
1117 .configure_filter = rt2x00mac_configure_filter,
e783619e
HS		 1118 .set_key = rt2x00mac_set_key,
1119 .sw_scan_start = rt2x00mac_sw_scan_start,
1120 .sw_scan_complete = rt2x00mac_sw_scan_complete,
1121 .get_stats = rt2x00mac_get_stats,
1122 .get_tkip_seq = rt2800_get_tkip_seq,
1123 .set_rts_threshold = rt2800_set_rts_threshold,
a2b1328a
HS		 1124 .sta_add = rt2x00mac_sta_add,
1125 .sta_remove = rt2x00mac_sta_remove,
e783619e
HS		 1126 .bss_info_changed = rt2x00mac_bss_info_changed,
1127 .conf_tx = rt2800_conf_tx,
1128 .get_tsf = rt2800_get_tsf,
1129 .rfkill_poll = rt2x00mac_rfkill_poll,
1130 .ampdu_action = rt2800_ampdu_action,
f44df18c 1131 .flush = rt2x00mac_flush,
977206d7 1132 .get_survey = rt2800_get_survey,
e7dee444 1133 .get_ringparam = rt2x00mac_get_ringparam,
5f0dd296 1134 .tx_frames_pending = rt2x00mac_tx_frames_pending,
e783619e
HS		 1135};
1136
e796643e 1137static const struct rt2800_ops rt2800pci_rt2800_ops = {
b9570b66
GJ		 1138 .register_read = rt2x00mmio_register_read,
1139 .register_read_lock = rt2x00mmio_register_read, /* same for PCI */
1140 .register_write = rt2x00mmio_register_write,
1141 .register_write_lock = rt2x00mmio_register_write, /* same for PCI */
1142 .register_multiread = rt2x00mmio_register_multiread,
1143 .register_multiwrite = rt2x00mmio_register_multiwrite,
1144 .regbusy_read = rt2x00mmio_regbusy_read,
ad417a53
GW		 1145 .read_eeprom = rt2800pci_read_eeprom,
1146 .hwcrypt_disabled = rt2800pci_hwcrypt_disabled,
e796643e
ID		 1147 .drv_write_firmware = rt2800pci_write_firmware,
1148 .drv_init_registers = rt2800pci_init_registers,
0c5879bc 1149 .drv_get_txwi = rt2800pci_get_txwi,
e796643e
ID		 1150};
1151
a9b3a9f7
ID		 1152static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1153 .irq_handler = rt2800pci_interrupt,
a9d61e9e
HS		 1154 .txstatus_tasklet = rt2800pci_txstatus_tasklet,
1155 .pretbtt_tasklet = rt2800pci_pretbtt_tasklet,
1156 .tbtt_tasklet = rt2800pci_tbtt_tasklet,
1157 .rxdone_tasklet = rt2800pci_rxdone_tasklet,
1158 .autowake_tasklet = rt2800pci_autowake_tasklet,
ad417a53 1159 .probe_hw = rt2800_probe_hw,
a9b3a9f7 1160 .get_firmware_name = rt2800pci_get_firmware_name,
f31c9a8c
ID		 1161 .check_firmware = rt2800_check_firmware,
1162 .load_firmware = rt2800_load_firmware,
b9570b66
GJ		 1163 .initialize = rt2x00mmio_initialize,
1164 .uninitialize = rt2x00mmio_uninitialize,
a9b3a9f7
ID		 1165 .get_entry_state = rt2800pci_get_entry_state,
1166 .clear_entry = rt2800pci_clear_entry,
1167 .set_device_state = rt2800pci_set_device_state,
f4450616
BZ		 1168 .rfkill_poll = rt2800_rfkill_poll,
1169 .link_stats = rt2800_link_stats,
1170 .reset_tuner = rt2800_reset_tuner,
1171 .link_tuner = rt2800_link_tuner,
9e33a355 1172 .gain_calibration = rt2800_gain_calibration,
2e9c43dd 1173 .vco_calibration = rt2800_vco_calibration,
dbba306f
ID		 1174 .start_queue = rt2800pci_start_queue,
1175 .kick_queue = rt2800pci_kick_queue,
1176 .stop_queue = rt2800pci_stop_queue,
b9570b66 1177 .flush_queue = rt2x00mmio_flush_queue,
a9b3a9f7 1178 .write_tx_desc = rt2800pci_write_tx_desc,
0c5879bc 1179 .write_tx_data = rt2800_write_tx_data,
f0194b2d 1180 .write_beacon = rt2800_write_beacon,
69cf36a4 1181 .clear_beacon = rt2800_clear_beacon,
a9b3a9f7 1182 .fill_rxdone = rt2800pci_fill_rxdone,
f4450616
BZ		 1183 .config_shared_key = rt2800_config_shared_key,
1184 .config_pairwise_key = rt2800_config_pairwise_key,
1185 .config_filter = rt2800_config_filter,
1186 .config_intf = rt2800_config_intf,
1187 .config_erp = rt2800_config_erp,
1188 .config_ant = rt2800_config_ant,
1189 .config = rt2800_config,
a2b1328a
HS		 1190 .sta_add = rt2800_sta_add,
1191 .sta_remove = rt2800_sta_remove,
a9b3a9f7
ID		 1192};
1193
1896b760
GJ		 1194static void rt2800pci_queue_init(struct data_queue *queue)
1195{
ae1b1c5d
GJ		 1196 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1197 unsigned short txwi_size, rxwi_size;
1198
1199 rt2800_get_txwi_rxwi_size(rt2x00dev, &txwi_size, &rxwi_size);
1200
1896b760
GJ		 1201 switch (queue->qid) {
1202 case QID_RX:
1203 queue->limit = 128;
1204 queue->data_size = AGGREGATION_SIZE;
1205 queue->desc_size = RXD_DESC_SIZE;
ae1b1c5d 1206 queue->winfo_size = rxwi_size;
1896b760
GJ		 1207 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1208 break;
a9b3a9f7 1209
1896b760
GJ		 1210 case QID_AC_VO:
1211 case QID_AC_VI:
1212 case QID_AC_BE:
1213 case QID_AC_BK:
1214 queue->limit = 64;
1215 queue->data_size = AGGREGATION_SIZE;
1216 queue->desc_size = TXD_DESC_SIZE;
ae1b1c5d 1217 queue->winfo_size = txwi_size;
1896b760
GJ		 1218 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1219 break;
a9b3a9f7 1220
1896b760
GJ		 1221 case QID_BEACON:
1222 queue->limit = 8;
1223 queue->data_size = 0; /* No DMA required for beacons */
1224 queue->desc_size = TXD_DESC_SIZE;
ae1b1c5d 1225 queue->winfo_size = txwi_size;
1896b760
GJ		 1226 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1227 break;
1228
1229 case QID_ATIM:
1230 /* fallthrough */
1231 default:
1232 BUG();
1233 break;
1234 }
1235}
a9b3a9f7
ID		 1236
1237static const struct rt2x00_ops rt2800pci_ops = {
04d0362e 1238 .name = KBUILD_MODNAME,
3a1c0128 1239 .drv_data_size = sizeof(struct rt2800_drv_data),
04d0362e
GW		 1240 .max_ap_intf = 8,
1241 .eeprom_size = EEPROM_SIZE,
1242 .rf_size = RF_SIZE,
1243 .tx_queues = NUM_TX_QUEUES,
1896b760 1244 .queue_init = rt2800pci_queue_init,
04d0362e 1245 .lib = &rt2800pci_rt2x00_ops,
e796643e 1246 .drv = &rt2800pci_rt2800_ops,
e783619e 1247 .hw = &rt2800pci_mac80211_ops,
a9b3a9f7 1248#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 1249 .debugfs = &rt2800_rt2x00debug,
a9b3a9f7
ID		 1250#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1251};
1252
1253/*
1254 * RT2800pci module information.
1255 */
72c7296e 1256#ifdef CONFIG_PCI
a3aa1884 1257static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
e01ae27f
GW		 1258 { PCI_DEVICE(0x1814, 0x0601) },
1259 { PCI_DEVICE(0x1814, 0x0681) },
1260 { PCI_DEVICE(0x1814, 0x0701) },
1261 { PCI_DEVICE(0x1814, 0x0781) },
1262 { PCI_DEVICE(0x1814, 0x3090) },
1263 { PCI_DEVICE(0x1814, 0x3091) },
1264 { PCI_DEVICE(0x1814, 0x3092) },
1265 { PCI_DEVICE(0x1432, 0x7708) },
1266 { PCI_DEVICE(0x1432, 0x7727) },
1267 { PCI_DEVICE(0x1432, 0x7728) },
1268 { PCI_DEVICE(0x1432, 0x7738) },
1269 { PCI_DEVICE(0x1432, 0x7748) },
1270 { PCI_DEVICE(0x1432, 0x7758) },
1271 { PCI_DEVICE(0x1432, 0x7768) },
1272 { PCI_DEVICE(0x1462, 0x891a) },
1273 { PCI_DEVICE(0x1a3b, 0x1059) },
a89534ed
WH		 1274#ifdef CONFIG_RT2800PCI_RT3290
1275 { PCI_DEVICE(0x1814, 0x3290) },
1276#endif
f93bc9b3 1277#ifdef CONFIG_RT2800PCI_RT33XX
e01ae27f 1278 { PCI_DEVICE(0x1814, 0x3390) },
f93bc9b3 1279#endif
de1ebdce 1280#ifdef CONFIG_RT2800PCI_RT35XX
e01ae27f
GW		 1281 { PCI_DEVICE(0x1432, 0x7711) },
1282 { PCI_DEVICE(0x1432, 0x7722) },
1283 { PCI_DEVICE(0x1814, 0x3060) },
1284 { PCI_DEVICE(0x1814, 0x3062) },
1285 { PCI_DEVICE(0x1814, 0x3562) },
1286 { PCI_DEVICE(0x1814, 0x3592) },
1287 { PCI_DEVICE(0x1814, 0x3593) },
c4806014 1288 { PCI_DEVICE(0x1814, 0x359f) },
60687ba7
RST		 1289#endif
1290#ifdef CONFIG_RT2800PCI_RT53XX
ccf91bd6 1291 { PCI_DEVICE(0x1814, 0x5360) },
f57d7b6c 1292 { PCI_DEVICE(0x1814, 0x5362) },
e01ae27f 1293 { PCI_DEVICE(0x1814, 0x5390) },
f57d7b6c 1294 { PCI_DEVICE(0x1814, 0x5392) },
5126d97e 1295 { PCI_DEVICE(0x1814, 0x539a) },
2aed6915 1296 { PCI_DEVICE(0x1814, 0x539b) },
71e0b38c 1297 { PCI_DEVICE(0x1814, 0x539f) },
de1ebdce 1298#endif
a9b3a9f7
ID		 1299 { 0, }
1300};
72c7296e 1301#endif /* CONFIG_PCI */
a9b3a9f7
ID		 1302
1303MODULE_AUTHOR(DRV_PROJECT);
1304MODULE_VERSION(DRV_VERSION);
1305MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1306MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
72c7296e 1307#ifdef CONFIG_PCI
a9b3a9f7
ID		 1308MODULE_FIRMWARE(FIRMWARE_RT2860);
1309MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
72c7296e 1310#endif /* CONFIG_PCI */
a9b3a9f7
ID		 1311MODULE_LICENSE("GPL");
1312
5818a46a 1313#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
714fa663
GW		 1314static int rt2800soc_probe(struct platform_device *pdev)
1315{
6e93d719 1316 return rt2x00soc_probe(pdev, &rt2800pci_ops);
714fa663 1317}
a9b3a9f7
ID		 1318
1319static struct platform_driver rt2800soc_driver = {
1320 .driver = {
1321 .name = "rt2800_wmac",
1322 .owner = THIS_MODULE,
1323 .mod_name = KBUILD_MODNAME,
1324 },
714fa663 1325 .probe = rt2800soc_probe,
69202359 1326 .remove = rt2x00soc_remove,
a9b3a9f7
ID		 1327 .suspend = rt2x00soc_suspend,
1328 .resume = rt2x00soc_resume,
1329};
5818a46a 1330#endif /* CONFIG_SOC_RT288X || CONFIG_SOC_RT305X */
a9b3a9f7 1331
72c7296e 1332#ifdef CONFIG_PCI
e01ae27f
GW		 1333static int rt2800pci_probe(struct pci_dev *pci_dev,
1334 const struct pci_device_id *id)
1335{
1336 return rt2x00pci_probe(pci_dev, &rt2800pci_ops);
1337}
1338
a9b3a9f7
ID		 1339static struct pci_driver rt2800pci_driver = {
1340 .name = KBUILD_MODNAME,
1341 .id_table = rt2800pci_device_table,
e01ae27f 1342 .probe = rt2800pci_probe,
69202359 1343 .remove = rt2x00pci_remove,
a9b3a9f7
ID		 1344 .suspend = rt2x00pci_suspend,
1345 .resume = rt2x00pci_resume,
1346};
72c7296e 1347#endif /* CONFIG_PCI */
a9b3a9f7
ID		 1348
1349static int __init rt2800pci_init(void)
1350{
1351 int ret = 0;
1352
5818a46a 1353#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
a9b3a9f7
ID		 1354 ret = platform_driver_register(&rt2800soc_driver);
1355 if (ret)
1356 return ret;
1357#endif
72c7296e 1358#ifdef CONFIG_PCI
a9b3a9f7
ID		 1359 ret = pci_register_driver(&rt2800pci_driver);
1360 if (ret) {
5818a46a 1361#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
a9b3a9f7
ID		 1362 platform_driver_unregister(&rt2800soc_driver);
1363#endif
1364 return ret;
1365 }
1366#endif
1367
1368 return ret;
1369}
1370
1371static void __exit rt2800pci_exit(void)
1372{
72c7296e 1373#ifdef CONFIG_PCI
a9b3a9f7
ID		 1374 pci_unregister_driver(&rt2800pci_driver);
1375#endif
5818a46a 1376#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
a9b3a9f7
ID		 1377 platform_driver_unregister(&rt2800soc_driver);
1378#endif
1379}
1380
1381module_init(rt2800pci_init);
1382module_exit(rt2800pci_exit);
Linux kernel - Deliverables
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