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rt2x00: Whitespace cleanup.
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2800pci.c
CommitLineData
a9b3a9f7 1/*
9c9a0d14
GW		 2 Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
a9b3a9f7
ID		 10 <http://rt2x00.serialmonkey.com>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 */
27
28/*
29 Module: rt2800pci
30 Abstract: rt2800pci device specific routines.
31 Supported chipsets: RT2800E & RT2800ED.
32 */
33
34#include <linux/crc-ccitt.h>
35#include <linux/delay.h>
36#include <linux/etherdevice.h>
37#include <linux/init.h>
38#include <linux/kernel.h>
39#include <linux/module.h>
40#include <linux/pci.h>
41#include <linux/platform_device.h>
42#include <linux/eeprom_93cx6.h>
43
44#include "rt2x00.h"
45#include "rt2x00pci.h"
46#include "rt2x00soc.h"
7ef5cc92 47#include "rt2800lib.h"
b54f78a8 48#include "rt2800.h"
a9b3a9f7
ID		 49#include "rt2800pci.h"
50
51#ifdef CONFIG_RT2800PCI_PCI_MODULE
52#define CONFIG_RT2800PCI_PCI
53#endif
54
55#ifdef CONFIG_RT2800PCI_WISOC_MODULE
56#define CONFIG_RT2800PCI_WISOC
57#endif
58
59/*
60 * Allow hardware encryption to be disabled.
61 */
62static int modparam_nohwcrypt = 1;
63module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
64MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
65
a9b3a9f7
ID		 66static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
67{
68 unsigned int i;
69 u32 reg;
70
71 for (i = 0; i < 200; i++) {
9ca21eb7 72 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
a9b3a9f7
ID		 73
74 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
75 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
76 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
77 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
78 break;
79
80 udelay(REGISTER_BUSY_DELAY);
81 }
82
83 if (i == 200)
84 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
85
9ca21eb7
BZ		 86 rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
87 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
a9b3a9f7
ID		 88}
89
90#ifdef CONFIG_RT2800PCI_WISOC
91static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
92{
93 u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */
94
95 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
96}
97#else
98static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
99{
100}
101#endif /* CONFIG_RT2800PCI_WISOC */
102
103#ifdef CONFIG_RT2800PCI_PCI
104static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
105{
106 struct rt2x00_dev *rt2x00dev = eeprom->data;
107 u32 reg;
108
9ca21eb7 109 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 110
111 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
112 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
113 eeprom->reg_data_clock =
114 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
115 eeprom->reg_chip_select =
116 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
117}
118
119static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
120{
121 struct rt2x00_dev *rt2x00dev = eeprom->data;
122 u32 reg = 0;
123
124 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
125 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
126 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
127 !!eeprom->reg_data_clock);
128 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
129 !!eeprom->reg_chip_select);
130
9ca21eb7 131 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
a9b3a9f7
ID		 132}
133
134static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
135{
136 struct eeprom_93cx6 eeprom;
137 u32 reg;
138
9ca21eb7 139 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 140
141 eeprom.data = rt2x00dev;
142 eeprom.register_read = rt2800pci_eepromregister_read;
143 eeprom.register_write = rt2800pci_eepromregister_write;
144 eeprom.width = !rt2x00_get_field32(reg, E2PROM_CSR_TYPE) ?
145 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
146 eeprom.reg_data_in = 0;
147 eeprom.reg_data_out = 0;
148 eeprom.reg_data_clock = 0;
149 eeprom.reg_chip_select = 0;
150
151 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
152 EEPROM_SIZE / sizeof(u16));
153}
154
a6598682
GW		 155static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
156{
30e84034 157 return rt2800_efuse_detect(rt2x00dev);
a9b3a9f7
ID		 158}
159
30e84034 160static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 161{
30e84034 162 rt2800_read_eeprom_efuse(rt2x00dev);
a9b3a9f7
ID		 163}
164#else
165static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
166{
167}
168
a6598682
GW		 169static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
170{
171 return 0;
172}
173
a9b3a9f7
ID		 174static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
175{
176}
177#endif /* CONFIG_RT2800PCI_PCI */
178
a9b3a9f7
ID		 179/*
180 * Firmware functions
181 */
182static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
183{
184 return FIRMWARE_RT2860;
185}
186
187static int rt2800pci_check_firmware(struct rt2x00_dev *rt2x00dev,
188 const u8 *data, const size_t len)
189{
190 u16 fw_crc;
191 u16 crc;
192
193 /*
194 * Only support 8kb firmware files.
195 */
196 if (len != 8192)
197 return FW_BAD_LENGTH;
198
199 /*
200 * The last 2 bytes in the firmware array are the crc checksum itself,
201 * this means that we should never pass those 2 bytes to the crc
202 * algorithm.
203 */
204 fw_crc = (data[len - 2] << 8 | data[len - 1]);
205
206 /*
207 * Use the crc ccitt algorithm.
208 * This will return the same value as the legacy driver which
209 * used bit ordering reversion on the both the firmware bytes
210 * before input input as well as on the final output.
211 * Obviously using crc ccitt directly is much more efficient.
212 */
213 crc = crc_ccitt(~0, data, len - 2);
214
215 /*
216 * There is a small difference between the crc-itu-t + bitrev and
217 * the crc-ccitt crc calculation. In the latter method the 2 bytes
218 * will be swapped, use swab16 to convert the crc to the correct
219 * value.
220 */
221 crc = swab16(crc);
222
223 return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
224}
225
226static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
227 const u8 *data, const size_t len)
228{
229 unsigned int i;
230 u32 reg;
231
232 /*
233 * Wait for stable hardware.
234 */
235 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9ca21eb7 236 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
a9b3a9f7
ID		 237 if (reg && reg != ~0)
238 break;
239 msleep(1);
240 }
241
242 if (i == REGISTER_BUSY_COUNT) {
243 ERROR(rt2x00dev, "Unstable hardware.\n");
244 return -EBUSY;
245 }
246
9ca21eb7
BZ		 247 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
248 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
a9b3a9f7
ID		 249
250 /*
251 * Disable DMA, will be reenabled later when enabling
252 * the radio.
253 */
9ca21eb7 254 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 255 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
256 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
257 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
258 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
259 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 260 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7
ID		 261
262 /*
263 * enable Host program ram write selection
264 */
265 reg = 0;
266 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
9ca21eb7 267 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
a9b3a9f7
ID		 268
269 /*
270 * Write firmware to device.
271 */
4f2732ce 272 rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
a9b3a9f7
ID		 273 data, len);
274
9ca21eb7
BZ		 275 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
276 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
a9b3a9f7
ID		 277
278 /*
279 * Wait for device to stabilize.
280 */
281 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9ca21eb7 282 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
a9b3a9f7
ID		 283 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
284 break;
285 msleep(1);
286 }
287
288 if (i == REGISTER_BUSY_COUNT) {
289 ERROR(rt2x00dev, "PBF system register not ready.\n");
290 return -EBUSY;
291 }
292
293 /*
294 * Disable interrupts
295 */
296 rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_OFF);
297
298 /*
299 * Initialize BBP R/W access agent
300 */
9ca21eb7
BZ		 301 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
302 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
a9b3a9f7
ID		 303
304 return 0;
305}
306
307/*
308 * Initialization functions.
309 */
310static bool rt2800pci_get_entry_state(struct queue_entry *entry)
311{
312 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
313 u32 word;
314
315 if (entry->queue->qid == QID_RX) {
316 rt2x00_desc_read(entry_priv->desc, 1, &word);
317
318 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
319 } else {
320 rt2x00_desc_read(entry_priv->desc, 1, &word);
321
322 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
323 }
324}
325
326static void rt2800pci_clear_entry(struct queue_entry *entry)
327{
328 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
329 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
330 u32 word;
331
332 if (entry->queue->qid == QID_RX) {
333 rt2x00_desc_read(entry_priv->desc, 0, &word);
334 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
335 rt2x00_desc_write(entry_priv->desc, 0, word);
336
337 rt2x00_desc_read(entry_priv->desc, 1, &word);
338 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
339 rt2x00_desc_write(entry_priv->desc, 1, word);
340 } else {
341 rt2x00_desc_read(entry_priv->desc, 1, &word);
342 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
343 rt2x00_desc_write(entry_priv->desc, 1, word);
344 }
345}
346
347static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
348{
349 struct queue_entry_priv_pci *entry_priv;
350 u32 reg;
351
9ca21eb7 352 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
a9b3a9f7
ID		 353 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
354 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
355 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
356 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
357 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
358 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
359 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
9ca21eb7 360 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
a9b3a9f7 361
9ca21eb7
BZ		 362 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
363 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
a9b3a9f7
ID		 364
365 /*
366 * Initialize registers.
367 */
368 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
9ca21eb7
BZ		 369 rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
370 rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
371 rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
372 rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
a9b3a9f7
ID		 373
374 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
9ca21eb7
BZ		 375 rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
376 rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
377 rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
378 rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
a9b3a9f7
ID		 379
380 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
9ca21eb7
BZ		 381 rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
382 rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
383 rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
384 rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
a9b3a9f7
ID		 385
386 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
9ca21eb7
BZ		 387 rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
388 rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
389 rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
390 rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
a9b3a9f7
ID		 391
392 entry_priv = rt2x00dev->rx->entries[0].priv_data;
9ca21eb7
BZ		 393 rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
394 rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
395 rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
396 rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
a9b3a9f7
ID		 397
398 /*
399 * Enable global DMA configuration
400 */
9ca21eb7 401 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 402 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
403 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
404 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 405 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7 406
9ca21eb7 407 rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
a9b3a9f7
ID		 408
409 return 0;
410}
411
a9b3a9f7
ID		 412/*
413 * Device state switch handlers.
414 */
415static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
416 enum dev_state state)
417{
418 u32 reg;
419
9ca21eb7 420 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
a9b3a9f7
ID		 421 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
422 (state == STATE_RADIO_RX_ON) ||
423 (state == STATE_RADIO_RX_ON_LINK));
9ca21eb7 424 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
a9b3a9f7
ID		 425}
426
427static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
428 enum dev_state state)
429{
430 int mask = (state == STATE_RADIO_IRQ_ON);
431 u32 reg;
432
433 /*
434 * When interrupts are being enabled, the interrupt registers
435 * should clear the register to assure a clean state.
436 */
437 if (state == STATE_RADIO_IRQ_ON) {
9ca21eb7
BZ		 438 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
439 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
a9b3a9f7
ID		 440 }
441
9ca21eb7 442 rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
a9b3a9f7
ID		 443 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
444 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
445 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
446 rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
447 rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
448 rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
449 rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
450 rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
451 rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
452 rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
453 rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, mask);
454 rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
455 rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
456 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
457 rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
458 rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
459 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
460 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
9ca21eb7 461 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
a9b3a9f7
ID		 462}
463
464static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
465{
466 unsigned int i;
467 u32 reg;
468
469 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9ca21eb7 470 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 471 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
472 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
473 return 0;
474
475 msleep(1);
476 }
477
478 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
479 return -EACCES;
480}
481
482static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
483{
484 u32 reg;
485 u16 word;
486
487 /*
488 * Initialize all registers.
489 */
490 if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) ||
491 rt2800pci_init_queues(rt2x00dev) ||
fcf51541 492 rt2800_init_registers(rt2x00dev) ||
a9b3a9f7 493 rt2800pci_wait_wpdma_ready(rt2x00dev) ||
fcf51541
BZ		 494 rt2800_init_bbp(rt2x00dev) ||
495 rt2800_init_rfcsr(rt2x00dev)))
a9b3a9f7
ID		 496 return -EIO;
497
498 /*
499 * Send signal to firmware during boot time.
500 */
3a9e5b0f 501 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
a9b3a9f7
ID		 502
503 /*
504 * Enable RX.
505 */
9ca21eb7 506 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
a9b3a9f7
ID		 507 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
508 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
9ca21eb7 509 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
a9b3a9f7 510
9ca21eb7 511 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 512 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
513 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
514 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
515 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 516 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7 517
9ca21eb7 518 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
a9b3a9f7
ID		 519 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
520 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
9ca21eb7 521 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
a9b3a9f7
ID		 522
523 /*
524 * Initialize LED control
525 */
526 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
3a9e5b0f 527 rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
a9b3a9f7
ID		 528 word & 0xff, (word >> 8) & 0xff);
529
530 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
3a9e5b0f 531 rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
a9b3a9f7
ID		 532 word & 0xff, (word >> 8) & 0xff);
533
534 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
3a9e5b0f 535 rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
a9b3a9f7
ID		 536 word & 0xff, (word >> 8) & 0xff);
537
538 return 0;
539}
540
541static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
542{
543 u32 reg;
544
9ca21eb7 545 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 546 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
547 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
548 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
549 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
550 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 551 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7 552
9ca21eb7
BZ		 553 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
554 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
555 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
a9b3a9f7 556
9ca21eb7 557 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
a9b3a9f7 558
9ca21eb7 559 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
a9b3a9f7
ID		 560 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
561 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
562 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
563 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
564 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
565 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
566 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
9ca21eb7 567 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
a9b3a9f7 568
9ca21eb7
BZ		 569 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
570 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
a9b3a9f7
ID		 571
572 /* Wait for DMA, ignore error */
573 rt2800pci_wait_wpdma_ready(rt2x00dev);
574}
575
576static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
577 enum dev_state state)
578{
579 /*
580 * Always put the device to sleep (even when we intend to wakeup!)
581 * if the device is booting and wasn't asleep it will return
582 * failure when attempting to wakeup.
583 */
3a9e5b0f 584 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
a9b3a9f7
ID		 585
586 if (state == STATE_AWAKE) {
3a9e5b0f 587 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
a9b3a9f7
ID		 588 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
589 }
590
591 return 0;
592}
593
594static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
595 enum dev_state state)
596{
597 int retval = 0;
598
599 switch (state) {
600 case STATE_RADIO_ON:
601 /*
602 * Before the radio can be enabled, the device first has
603 * to be woken up. After that it needs a bit of time
604 * to be fully awake and then the radio can be enabled.
605 */
606 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
607 msleep(1);
608 retval = rt2800pci_enable_radio(rt2x00dev);
609 break;
610 case STATE_RADIO_OFF:
611 /*
612 * After the radio has been disabled, the device should
613 * be put to sleep for powersaving.
614 */
615 rt2800pci_disable_radio(rt2x00dev);
616 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
617 break;
618 case STATE_RADIO_RX_ON:
619 case STATE_RADIO_RX_ON_LINK:
620 case STATE_RADIO_RX_OFF:
621 case STATE_RADIO_RX_OFF_LINK:
622 rt2800pci_toggle_rx(rt2x00dev, state);
623 break;
624 case STATE_RADIO_IRQ_ON:
625 case STATE_RADIO_IRQ_OFF:
626 rt2800pci_toggle_irq(rt2x00dev, state);
627 break;
628 case STATE_DEEP_SLEEP:
629 case STATE_SLEEP:
630 case STATE_STANDBY:
631 case STATE_AWAKE:
632 retval = rt2800pci_set_state(rt2x00dev, state);
633 break;
634 default:
635 retval = -ENOTSUPP;
636 break;
637 }
638
639 if (unlikely(retval))
640 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
641 state, retval);
642
643 return retval;
644}
645
646/*
647 * TX descriptor initialization
648 */
649static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
650 struct sk_buff *skb,
651 struct txentry_desc *txdesc)
652{
653 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
654 __le32 *txd = skbdesc->desc;
655 __le32 *txwi = (__le32 *)(skb->data - rt2x00dev->hw->extra_tx_headroom);
656 u32 word;
657
658 /*
659 * Initialize TX Info descriptor
660 */
661 rt2x00_desc_read(txwi, 0, &word);
662 rt2x00_set_field32(&word, TXWI_W0_FRAG,
663 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
664 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
665 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
666 rt2x00_set_field32(&word, TXWI_W0_TS,
667 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
668 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
669 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
670 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
671 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
672 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
673 rt2x00_set_field32(&word, TXWI_W0_BW,
674 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
675 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
676 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
677 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
678 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
679 rt2x00_desc_write(txwi, 0, word);
680
681 rt2x00_desc_read(txwi, 1, &word);
682 rt2x00_set_field32(&word, TXWI_W1_ACK,
683 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
684 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
685 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
686 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
687 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
688 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
f644fea1 689 txdesc->key_idx : 0xff);
a9b3a9f7
ID		 690 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
691 skb->len - txdesc->l2pad);
692 rt2x00_set_field32(&word, TXWI_W1_PACKETID,
693 skbdesc->entry->queue->qid + 1);
694 rt2x00_desc_write(txwi, 1, word);
695
696 /*
697 * Always write 0 to IV/EIV fields, hardware will insert the IV
77dba493
BZ		 698 * from the IVEIV register when TXD_W3_WIV is set to 0.
699 * When TXD_W3_WIV is set to 1 it will use the IV data
a9b3a9f7
ID		 700 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
701 * crypto entry in the registers should be used to encrypt the frame.
702 */
703 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
704 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
705
706 /*
707 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
708 * must contains a TXWI structure + 802.11 header + padding + 802.11
709 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
710 * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
711 * data. It means that LAST_SEC0 is always 0.
712 */
713
714 /*
715 * Initialize TX descriptor
716 */
717 rt2x00_desc_read(txd, 0, &word);
718 rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
719 rt2x00_desc_write(txd, 0, word);
720
721 rt2x00_desc_read(txd, 1, &word);
722 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
723 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
724 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
725 rt2x00_set_field32(&word, TXD_W1_BURST,
726 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
727 rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
728 rt2x00dev->hw->extra_tx_headroom);
729 rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
730 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
731 rt2x00_desc_write(txd, 1, word);
732
733 rt2x00_desc_read(txd, 2, &word);
734 rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
735 skbdesc->skb_dma + rt2x00dev->hw->extra_tx_headroom);
736 rt2x00_desc_write(txd, 2, word);
737
738 rt2x00_desc_read(txd, 3, &word);
739 rt2x00_set_field32(&word, TXD_W3_WIV,
740 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
741 rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
742 rt2x00_desc_write(txd, 3, word);
743}
744
745/*
746 * TX data initialization
747 */
748static void rt2800pci_write_beacon(struct queue_entry *entry)
749{
750 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
751 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
752 unsigned int beacon_base;
753 u32 reg;
754
755 /*
756 * Disable beaconing while we are reloading the beacon data,
757 * otherwise we might be sending out invalid data.
758 */
9ca21eb7 759 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
a9b3a9f7 760 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
9ca21eb7 761 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
a9b3a9f7
ID		 762
763 /*
764 * Write entire beacon with descriptor to register.
765 */
766 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
4f2732ce 767 rt2800_register_multiwrite(rt2x00dev,
a9b3a9f7
ID		 768 beacon_base,
769 skbdesc->desc, skbdesc->desc_len);
4f2732ce 770 rt2800_register_multiwrite(rt2x00dev,
a9b3a9f7
ID		 771 beacon_base + skbdesc->desc_len,
772 entry->skb->data, entry->skb->len);
773
774 /*
775 * Clean up beacon skb.
776 */
777 dev_kfree_skb_any(entry->skb);
778 entry->skb = NULL;
779}
780
781static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
782 const enum data_queue_qid queue_idx)
783{
784 struct data_queue *queue;
785 unsigned int idx, qidx = 0;
786 u32 reg;
787
788 if (queue_idx == QID_BEACON) {
9ca21eb7 789 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
a9b3a9f7
ID		 790 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
791 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
792 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
793 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
9ca21eb7 794 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
a9b3a9f7
ID		 795 }
796 return;
797 }
798
799 if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
800 return;
801
802 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
803 idx = queue->index[Q_INDEX];
804
805 if (queue_idx == QID_MGMT)
806 qidx = 5;
807 else
808 qidx = queue_idx;
809
9ca21eb7 810 rt2800_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
a9b3a9f7
ID		 811}
812
813static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
814 const enum data_queue_qid qid)
815{
816 u32 reg;
817
818 if (qid == QID_BEACON) {
9ca21eb7 819 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, 0);
a9b3a9f7
ID		 820 return;
821 }
822
9ca21eb7 823 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
a9b3a9f7
ID		 824 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
825 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
826 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
827 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
9ca21eb7 828 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
a9b3a9f7
ID		 829}
830
831/*
832 * RX control handlers
833 */
834static void rt2800pci_fill_rxdone(struct queue_entry *entry,
835 struct rxdone_entry_desc *rxdesc)
836{
837 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
838 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
839 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
840 __le32 *rxd = entry_priv->desc;
841 __le32 *rxwi = (__le32 *)entry->skb->data;
842 u32 rxd3;
843 u32 rxwi0;
844 u32 rxwi1;
845 u32 rxwi2;
846 u32 rxwi3;
847
848 rt2x00_desc_read(rxd, 3, &rxd3);
849 rt2x00_desc_read(rxwi, 0, &rxwi0);
850 rt2x00_desc_read(rxwi, 1, &rxwi1);
851 rt2x00_desc_read(rxwi, 2, &rxwi2);
852 rt2x00_desc_read(rxwi, 3, &rxwi3);
853
854 if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR))
855 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
856
857 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
858 /*
859 * Unfortunately we don't know the cipher type used during
860 * decryption. This prevents us from correct providing
861 * correct statistics through debugfs.
862 */
863 rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
864 rxdesc->cipher_status =
865 rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);
866 }
867
868 if (rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED)) {
869 /*
870 * Hardware has stripped IV/EIV data from 802.11 frame during
871 * decryption. Unfortunately the descriptor doesn't contain
872 * any fields with the EIV/IV data either, so they can't
873 * be restored by rt2x00lib.
874 */
875 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
876
877 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
878 rxdesc->flags |= RX_FLAG_DECRYPTED;
879 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
880 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
881 }
882
883 if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS))
884 rxdesc->dev_flags |= RXDONE_MY_BSS;
885
886 if (rt2x00_get_field32(rxd3, RXD_W3_L2PAD)) {
887 rxdesc->dev_flags |= RXDONE_L2PAD;
888 skbdesc->flags |= SKBDESC_L2_PADDED;
889 }
890
891 if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
892 rxdesc->flags |= RX_FLAG_SHORT_GI;
893
894 if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
895 rxdesc->flags |= RX_FLAG_40MHZ;
896
897 /*
898 * Detect RX rate, always use MCS as signal type.
899 */
900 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
901 rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
902 rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
903
904 /*
905 * Mask of 0x8 bit to remove the short preamble flag.
906 */
907 if (rxdesc->rate_mode == RATE_MODE_CCK)
908 rxdesc->signal &= ~0x8;
909
910 rxdesc->rssi =
911 (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
912 rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
913
914 rxdesc->noise =
915 (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
916 rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
917
918 rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
919
920 /*
921 * Set RX IDX in register to inform hardware that we have handled
922 * this entry and it is available for reuse again.
923 */
9ca21eb7 924 rt2800_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
a9b3a9f7
ID		 925
926 /*
927 * Remove TXWI descriptor from start of buffer.
928 */
929 skb_pull(entry->skb, RXWI_DESC_SIZE);
930 skb_trim(entry->skb, rxdesc->size);
931}
932
933/*
934 * Interrupt functions.
935 */
936static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
937{
938 struct data_queue *queue;
939 struct queue_entry *entry;
940 struct queue_entry *entry_done;
941 struct queue_entry_priv_pci *entry_priv;
942 struct txdone_entry_desc txdesc;
943 u32 word;
944 u32 reg;
945 u32 old_reg;
946 unsigned int type;
947 unsigned int index;
948 u16 mcs, real_mcs;
949
950 /*
951 * During each loop we will compare the freshly read
952 * TX_STA_FIFO register value with the value read from
953 * the previous loop. If the 2 values are equal then
954 * we should stop processing because the chance it
955 * quite big that the device has been unplugged and
956 * we risk going into an endless loop.
957 */
958 old_reg = 0;
959
960 while (1) {
9ca21eb7 961 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
a9b3a9f7
ID		 962 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
963 break;
964
965 if (old_reg == reg)
966 break;
967 old_reg = reg;
968
969 /*
970 * Skip this entry when it contains an invalid
971 * queue identication number.
972 */
973 type = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE) - 1;
974 if (type >= QID_RX)
975 continue;
976
977 queue = rt2x00queue_get_queue(rt2x00dev, type);
978 if (unlikely(!queue))
979 continue;
980
981 /*
982 * Skip this entry when it contains an invalid
983 * index number.
984 */
985 index = rt2x00_get_field32(reg, TX_STA_FIFO_WCID) - 1;
986 if (unlikely(index >= queue->limit))
987 continue;
988
989 entry = &queue->entries[index];
990 entry_priv = entry->priv_data;
991 rt2x00_desc_read((__le32 *)entry->skb->data, 0, &word);
992
993 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
994 while (entry != entry_done) {
995 /*
996 * Catch up.
997 * Just report any entries we missed as failed.
998 */
999 WARNING(rt2x00dev,
1000 "TX status report missed for entry %d\n",
1001 entry_done->entry_idx);
1002
1003 txdesc.flags = 0;
1004 __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
1005 txdesc.retry = 0;
1006
1007 rt2x00lib_txdone(entry_done, &txdesc);
1008 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1009 }
1010
1011 /*
1012 * Obtain the status about this packet.
1013 */
1014 txdesc.flags = 0;
1015 if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS))
1016 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1017 else
1018 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1019
1020 /*
1021 * Ralink has a retry mechanism using a global fallback
1022 * table. We setup this fallback table to try immediate
1023 * lower rate for all rates. In the TX_STA_FIFO,
1024 * the MCS field contains the MCS used for the successfull
1025 * transmission. If the first transmission succeed,
1026 * we have mcs == tx_mcs. On the second transmission,
1027 * we have mcs = tx_mcs - 1. So the number of
1028 * retry is (tx_mcs - mcs).
1029 */
1030 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
1031 real_mcs = rt2x00_get_field32(reg, TX_STA_FIFO_MCS);
1032 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
1033 txdesc.retry = mcs - min(mcs, real_mcs);
1034
1035 rt2x00lib_txdone(entry, &txdesc);
1036 }
1037}
1038
1039static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
1040{
1041 struct rt2x00_dev *rt2x00dev = dev_instance;
1042 u32 reg;
1043
1044 /* Read status and ACK all interrupts */
9ca21eb7
BZ		 1045 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1046 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
a9b3a9f7
ID		 1047
1048 if (!reg)
1049 return IRQ_NONE;
1050
1051 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1052 return IRQ_HANDLED;
1053
1054 /*
1055 * 1 - Rx ring done interrupt.
1056 */
1057 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
1058 rt2x00pci_rxdone(rt2x00dev);
1059
1060 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
1061 rt2800pci_txdone(rt2x00dev);
1062
1063 return IRQ_HANDLED;
1064}
1065
1066/*
1067 * Device probe functions.
1068 */
7ab71325
BZ		 1069static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1070{
1071 /*
1072 * Read EEPROM into buffer
1073 */
1074 switch (rt2x00dev->chip.rt) {
1075 case RT2880:
1076 case RT3052:
1077 rt2800pci_read_eeprom_soc(rt2x00dev);
1078 break;
1079 default:
1080 if (rt2800pci_efuse_detect(rt2x00dev))
1081 rt2800pci_read_eeprom_efuse(rt2x00dev);
1082 else
1083 rt2800pci_read_eeprom_pci(rt2x00dev);
1084 break;
1085 }
1086
1087 return rt2800_validate_eeprom(rt2x00dev);
1088}
1089
b0a1edab
BZ		 1090static const struct rt2800_ops rt2800pci_rt2800_ops = {
1091 .register_read = rt2x00pci_register_read,
31a4cf1f 1092 .register_read_lock = rt2x00pci_register_read, /* same for PCI */
b0a1edab
BZ		 1093 .register_write = rt2x00pci_register_write,
1094 .register_write_lock = rt2x00pci_register_write, /* same for PCI */
1095
1096 .register_multiread = rt2x00pci_register_multiread,
1097 .register_multiwrite = rt2x00pci_register_multiwrite,
1098
1099 .regbusy_read = rt2x00pci_regbusy_read,
1100};
1101
a9b3a9f7
ID		 1102static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1103{
1104 int retval;
1105
b0a1edab
BZ		 1106 rt2x00dev->priv = (void *)&rt2800pci_rt2800_ops;
1107
a9b3a9f7
ID		 1108 /*
1109 * Allocate eeprom data.
1110 */
1111 retval = rt2800pci_validate_eeprom(rt2x00dev);
1112 if (retval)
1113 return retval;
1114
38bd7b8a 1115 retval = rt2800_init_eeprom(rt2x00dev);
a9b3a9f7
ID		 1116 if (retval)
1117 return retval;
1118
1119 /*
1120 * Initialize hw specifications.
1121 */
4da2933f 1122 retval = rt2800_probe_hw_mode(rt2x00dev);
a9b3a9f7
ID		 1123 if (retval)
1124 return retval;
1125
1126 /*
1127 * This device has multiple filters for control frames
1128 * and has a separate filter for PS Poll frames.
1129 */
1130 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
1131 __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
1132
1133 /*
1134 * This device requires firmware.
1135 */
1136 if (!rt2x00_rt(&rt2x00dev->chip, RT2880) &&
1137 !rt2x00_rt(&rt2x00dev->chip, RT3052))
1138 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
1139 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1140 __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
1141 if (!modparam_nohwcrypt)
1142 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
1143
1144 /*
1145 * Set the rssi offset.
1146 */
1147 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1148
1149 return 0;
1150}
1151
a9b3a9f7
ID		 1152static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1153 .irq_handler = rt2800pci_interrupt,
1154 .probe_hw = rt2800pci_probe_hw,
1155 .get_firmware_name = rt2800pci_get_firmware_name,
1156 .check_firmware = rt2800pci_check_firmware,
1157 .load_firmware = rt2800pci_load_firmware,
1158 .initialize = rt2x00pci_initialize,
1159 .uninitialize = rt2x00pci_uninitialize,
1160 .get_entry_state = rt2800pci_get_entry_state,
1161 .clear_entry = rt2800pci_clear_entry,
1162 .set_device_state = rt2800pci_set_device_state,
f4450616
BZ		 1163 .rfkill_poll = rt2800_rfkill_poll,
1164 .link_stats = rt2800_link_stats,
1165 .reset_tuner = rt2800_reset_tuner,
1166 .link_tuner = rt2800_link_tuner,
a9b3a9f7
ID		 1167 .write_tx_desc = rt2800pci_write_tx_desc,
1168 .write_tx_data = rt2x00pci_write_tx_data,
1169 .write_beacon = rt2800pci_write_beacon,
1170 .kick_tx_queue = rt2800pci_kick_tx_queue,
1171 .kill_tx_queue = rt2800pci_kill_tx_queue,
1172 .fill_rxdone = rt2800pci_fill_rxdone,
f4450616
BZ		 1173 .config_shared_key = rt2800_config_shared_key,
1174 .config_pairwise_key = rt2800_config_pairwise_key,
1175 .config_filter = rt2800_config_filter,
1176 .config_intf = rt2800_config_intf,
1177 .config_erp = rt2800_config_erp,
1178 .config_ant = rt2800_config_ant,
1179 .config = rt2800_config,
a9b3a9f7
ID		 1180};
1181
1182static const struct data_queue_desc rt2800pci_queue_rx = {
1183 .entry_num = RX_ENTRIES,
1184 .data_size = AGGREGATION_SIZE,
1185 .desc_size = RXD_DESC_SIZE,
1186 .priv_size = sizeof(struct queue_entry_priv_pci),
1187};
1188
1189static const struct data_queue_desc rt2800pci_queue_tx = {
1190 .entry_num = TX_ENTRIES,
1191 .data_size = AGGREGATION_SIZE,
1192 .desc_size = TXD_DESC_SIZE,
1193 .priv_size = sizeof(struct queue_entry_priv_pci),
1194};
1195
1196static const struct data_queue_desc rt2800pci_queue_bcn = {
1197 .entry_num = 8 * BEACON_ENTRIES,
1198 .data_size = 0, /* No DMA required for beacons */
1199 .desc_size = TXWI_DESC_SIZE,
1200 .priv_size = sizeof(struct queue_entry_priv_pci),
1201};
1202
1203static const struct rt2x00_ops rt2800pci_ops = {
04d0362e
GW		 1204 .name = KBUILD_MODNAME,
1205 .max_sta_intf = 1,
1206 .max_ap_intf = 8,
1207 .eeprom_size = EEPROM_SIZE,
1208 .rf_size = RF_SIZE,
1209 .tx_queues = NUM_TX_QUEUES,
1210 .rx = &rt2800pci_queue_rx,
1211 .tx = &rt2800pci_queue_tx,
1212 .bcn = &rt2800pci_queue_bcn,
1213 .lib = &rt2800pci_rt2x00_ops,
1214 .hw = &rt2800_mac80211_ops,
a9b3a9f7 1215#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 1216 .debugfs = &rt2800_rt2x00debug,
a9b3a9f7
ID		 1217#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1218};
1219
1220/*
1221 * RT2800pci module information.
1222 */
1223static struct pci_device_id rt2800pci_device_table[] = {
1224 { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
1225 { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
1226 { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
1227 { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
1228 { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
1229 { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
1230 { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
1231 { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
1232 { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
1233 { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
1234 { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
1235 { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
1236 { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
1237 { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
1238 { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
1239 { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
1240 { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
1241 { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
1242 { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
1243 { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
1244 { 0, }
1245};
1246
1247MODULE_AUTHOR(DRV_PROJECT);
1248MODULE_VERSION(DRV_VERSION);
1249MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1250MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1251#ifdef CONFIG_RT2800PCI_PCI
1252MODULE_FIRMWARE(FIRMWARE_RT2860);
1253MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1254#endif /* CONFIG_RT2800PCI_PCI */
1255MODULE_LICENSE("GPL");
1256
1257#ifdef CONFIG_RT2800PCI_WISOC
1258#if defined(CONFIG_RALINK_RT288X)
1259__rt2x00soc_probe(RT2880, &rt2800pci_ops);
1260#elif defined(CONFIG_RALINK_RT305X)
1261__rt2x00soc_probe(RT3052, &rt2800pci_ops);
1262#endif
1263
1264static struct platform_driver rt2800soc_driver = {
1265 .driver = {
1266 .name = "rt2800_wmac",
1267 .owner = THIS_MODULE,
1268 .mod_name = KBUILD_MODNAME,
1269 },
1270 .probe = __rt2x00soc_probe,
1271 .remove = __devexit_p(rt2x00soc_remove),
1272 .suspend = rt2x00soc_suspend,
1273 .resume = rt2x00soc_resume,
1274};
1275#endif /* CONFIG_RT2800PCI_WISOC */
1276
1277#ifdef CONFIG_RT2800PCI_PCI
1278static struct pci_driver rt2800pci_driver = {
1279 .name = KBUILD_MODNAME,
1280 .id_table = rt2800pci_device_table,
1281 .probe = rt2x00pci_probe,
1282 .remove = __devexit_p(rt2x00pci_remove),
1283 .suspend = rt2x00pci_suspend,
1284 .resume = rt2x00pci_resume,
1285};
1286#endif /* CONFIG_RT2800PCI_PCI */
1287
1288static int __init rt2800pci_init(void)
1289{
1290 int ret = 0;
1291
1292#ifdef CONFIG_RT2800PCI_WISOC
1293 ret = platform_driver_register(&rt2800soc_driver);
1294 if (ret)
1295 return ret;
1296#endif
1297#ifdef CONFIG_RT2800PCI_PCI
1298 ret = pci_register_driver(&rt2800pci_driver);
1299 if (ret) {
1300#ifdef CONFIG_RT2800PCI_WISOC
1301 platform_driver_unregister(&rt2800soc_driver);
1302#endif
1303 return ret;
1304 }
1305#endif
1306
1307 return ret;
1308}
1309
1310static void __exit rt2800pci_exit(void)
1311{
1312#ifdef CONFIG_RT2800PCI_PCI
1313 pci_unregister_driver(&rt2800pci_driver);
1314#endif
1315#ifdef CONFIG_RT2800PCI_WISOC
1316 platform_driver_unregister(&rt2800soc_driver);
1317#endif
1318}
1319
1320module_init(rt2800pci_init);
1321module_exit(rt2800pci_exit);
Linux kernel - Deliverables
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