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rt2800: Add documentation on MCU requests
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2800pci.c
CommitLineData
a9b3a9f7 1/*
96481b20 2 Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14
GW		 3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
a9b3a9f7
ID		 10 <http://rt2x00.serialmonkey.com>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 */
27
28/*
29 Module: rt2800pci
30 Abstract: rt2800pci device specific routines.
31 Supported chipsets: RT2800E & RT2800ED.
32 */
33
a9b3a9f7
ID		 34#include <linux/delay.h>
35#include <linux/etherdevice.h>
36#include <linux/init.h>
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/pci.h>
40#include <linux/platform_device.h>
41#include <linux/eeprom_93cx6.h>
42
43#include "rt2x00.h"
44#include "rt2x00pci.h"
45#include "rt2x00soc.h"
7ef5cc92 46#include "rt2800lib.h"
b54f78a8 47#include "rt2800.h"
a9b3a9f7
ID		 48#include "rt2800pci.h"
49
a9b3a9f7
ID		 50/*
51 * Allow hardware encryption to be disabled.
52 */
eb939922 53static bool modparam_nohwcrypt = false;
a9b3a9f7
ID		 54module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
55MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
56
a9b3a9f7
ID		 57static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
58{
59 unsigned int i;
60 u32 reg;
61
f18d4463
LC		 62 /*
63 * SOC devices don't support MCU requests.
64 */
65 if (rt2x00_is_soc(rt2x00dev))
66 return;
67
a9b3a9f7 68 for (i = 0; i < 200; i++) {
9a819996 69 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
a9b3a9f7
ID		 70
71 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
72 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
73 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
74 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
75 break;
76
77 udelay(REGISTER_BUSY_DELAY);
78 }
79
80 if (i == 200)
81 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
82
9a819996
HS		 83 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
84 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
a9b3a9f7
ID		 85}
86
72c7296e 87#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
a9b3a9f7
ID		 88static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
89{
ef8397cf 90 void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
a9b3a9f7
ID		 91
92 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
ef8397cf
GW		 93
94 iounmap(base_addr);
a9b3a9f7
ID		 95}
96#else
97static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
98{
99}
72c7296e 100#endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
a9b3a9f7 101
72c7296e 102#ifdef CONFIG_PCI
a9b3a9f7
ID		 103static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
104{
105 struct rt2x00_dev *rt2x00dev = eeprom->data;
106 u32 reg;
107
9a819996 108 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 109
110 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
111 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
112 eeprom->reg_data_clock =
113 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
114 eeprom->reg_chip_select =
115 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
116}
117
118static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
119{
120 struct rt2x00_dev *rt2x00dev = eeprom->data;
121 u32 reg = 0;
122
123 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
124 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
125 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
126 !!eeprom->reg_data_clock);
127 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
128 !!eeprom->reg_chip_select);
129
9a819996 130 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
a9b3a9f7
ID		 131}
132
133static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
134{
135 struct eeprom_93cx6 eeprom;
136 u32 reg;
137
9a819996 138 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 139
140 eeprom.data = rt2x00dev;
141 eeprom.register_read = rt2800pci_eepromregister_read;
142 eeprom.register_write = rt2800pci_eepromregister_write;
20f8b139
GW		 143 switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
144 {
145 case 0:
146 eeprom.width = PCI_EEPROM_WIDTH_93C46;
147 break;
148 case 1:
149 eeprom.width = PCI_EEPROM_WIDTH_93C66;
150 break;
151 default:
152 eeprom.width = PCI_EEPROM_WIDTH_93C86;
153 break;
154 }
a9b3a9f7
ID		 155 eeprom.reg_data_in = 0;
156 eeprom.reg_data_out = 0;
157 eeprom.reg_data_clock = 0;
158 eeprom.reg_chip_select = 0;
159
160 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
161 EEPROM_SIZE / sizeof(u16));
162}
163
a6598682
GW		 164static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
165{
30e84034 166 return rt2800_efuse_detect(rt2x00dev);
a9b3a9f7
ID		 167}
168
30e84034 169static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 170{
30e84034 171 rt2800_read_eeprom_efuse(rt2x00dev);
a9b3a9f7
ID		 172}
173#else
174static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
175{
176}
177
a6598682
GW		 178static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
179{
180 return 0;
181}
182
a9b3a9f7
ID		 183static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
184{
185}
72c7296e 186#endif /* CONFIG_PCI */
a9b3a9f7 187
5450b7e2
ID		 188/*
189 * Queue handlers.
190 */
191static void rt2800pci_start_queue(struct data_queue *queue)
192{
193 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
194 u32 reg;
195
196 switch (queue->qid) {
197 case QID_RX:
9a819996 198 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5450b7e2 199 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
9a819996 200 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5450b7e2
ID		 201 break;
202 case QID_BEACON:
9a819996 203 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
5450b7e2
ID		 204 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
205 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
206 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
9a819996 207 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
69cf36a4 208
9a819996 209 rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, &reg);
69cf36a4 210 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 1);
9a819996 211 rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
5450b7e2
ID		 212 break;
213 default:
214 break;
6403eab1 215 }
5450b7e2
ID		 216}
217
218static void rt2800pci_kick_queue(struct data_queue *queue)
219{
220 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
221 struct queue_entry *entry;
222
223 switch (queue->qid) {
f615e9a3
ID		 224 case QID_AC_VO:
225 case QID_AC_VI:
5450b7e2
ID		 226 case QID_AC_BE:
227 case QID_AC_BK:
5450b7e2 228 entry = rt2x00queue_get_entry(queue, Q_INDEX);
9a819996
HS		 229 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(queue->qid),
230 entry->entry_idx);
5450b7e2
ID		 231 break;
232 case QID_MGMT:
233 entry = rt2x00queue_get_entry(queue, Q_INDEX);
9a819996
HS		 234 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(5),
235 entry->entry_idx);
5450b7e2
ID		 236 break;
237 default:
238 break;
239 }
240}
241
242static void rt2800pci_stop_queue(struct data_queue *queue)
243{
244 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
245 u32 reg;
246
247 switch (queue->qid) {
248 case QID_RX:
9a819996 249 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5450b7e2 250 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
9a819996 251 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5450b7e2
ID		 252 break;
253 case QID_BEACON:
9a819996 254 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
5450b7e2
ID		 255 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
256 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
257 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
9a819996 258 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
69cf36a4 259
9a819996 260 rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, &reg);
69cf36a4 261 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 0);
9a819996 262 rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
a9d61e9e
HS		 263
264 /*
abc11994
HS		 265 * Wait for current invocation to finish. The tasklet
266 * won't be scheduled anymore afterwards since we disabled
267 * the TBTT and PRE TBTT timer.
a9d61e9e 268 */
abc11994
HS		 269 tasklet_kill(&rt2x00dev->tbtt_tasklet);
270 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
271
5450b7e2
ID		 272 break;
273 default:
274 break;
275 }
276}
277
a9b3a9f7
ID		 278/*
279 * Firmware functions
280 */
281static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
282{
283 return FIRMWARE_RT2860;
284}
285
f31c9a8c 286static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
a9b3a9f7
ID		 287 const u8 *data, const size_t len)
288{
a9b3a9f7
ID		 289 u32 reg;
290
a9b3a9f7
ID		 291 /*
292 * enable Host program ram write selection
293 */
294 reg = 0;
295 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
9a819996 296 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
a9b3a9f7
ID		 297
298 /*
299 * Write firmware to device.
300 */
d4c838ef
ID		 301 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
302 data, len);
a9b3a9f7 303
9a819996
HS		 304 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
305 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
a9b3a9f7 306
9a819996
HS		 307 rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
308 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
a9b3a9f7
ID		 309
310 return 0;
311}
312
313/*
314 * Initialization functions.
315 */
316static bool rt2800pci_get_entry_state(struct queue_entry *entry)
317{
318 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
319 u32 word;
320
321 if (entry->queue->qid == QID_RX) {
322 rt2x00_desc_read(entry_priv->desc, 1, &word);
323
324 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
325 } else {
326 rt2x00_desc_read(entry_priv->desc, 1, &word);
327
328 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
329 }
330}
331
332static void rt2800pci_clear_entry(struct queue_entry *entry)
333{
334 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
335 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95192339 336 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
a9b3a9f7
ID		 337 u32 word;
338
339 if (entry->queue->qid == QID_RX) {
340 rt2x00_desc_read(entry_priv->desc, 0, &word);
341 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
342 rt2x00_desc_write(entry_priv->desc, 0, word);
343
344 rt2x00_desc_read(entry_priv->desc, 1, &word);
345 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
346 rt2x00_desc_write(entry_priv->desc, 1, word);
95192339
HS		 347
348 /*
349 * Set RX IDX in register to inform hardware that we have
350 * handled this entry and it is available for reuse again.
351 */
9a819996 352 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
95192339 353 entry->entry_idx);
a9b3a9f7
ID		 354 } else {
355 rt2x00_desc_read(entry_priv->desc, 1, &word);
356 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
357 rt2x00_desc_write(entry_priv->desc, 1, word);
358 }
359}
360
361static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
362{
363 struct queue_entry_priv_pci *entry_priv;
364 u32 reg;
365
a9b3a9f7
ID		 366 /*
367 * Initialize registers.
368 */
369 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
9a819996
HS		 370 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
371 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0,
372 rt2x00dev->tx[0].limit);
373 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
374 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX0, 0);
a9b3a9f7
ID		 375
376 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
9a819996
HS		 377 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
378 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1,
379 rt2x00dev->tx[1].limit);
380 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
381 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX1, 0);
a9b3a9f7
ID		 382
383 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
9a819996
HS		 384 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
385 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2,
386 rt2x00dev->tx[2].limit);
387 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
388 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX2, 0);
a9b3a9f7
ID		 389
390 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
9a819996
HS		 391 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
392 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3,
393 rt2x00dev->tx[3].limit);
394 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
395 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX3, 0);
a9b3a9f7
ID		 396
397 entry_priv = rt2x00dev->rx->entries[0].priv_data;
9a819996
HS		 398 rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
399 rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT,
400 rt2x00dev->rx[0].limit);
401 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
402 rt2x00dev->rx[0].limit - 1);
403 rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0);
a9b3a9f7
ID		 404
405 /*
406 * Enable global DMA configuration
407 */
9a819996 408 rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 409 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
410 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
411 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9a819996 412 rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7 413
9a819996 414 rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
a9b3a9f7
ID		 415
416 return 0;
417}
418
a9b3a9f7
ID		 419/*
420 * Device state switch handlers.
421 */
a9b3a9f7
ID		 422static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
423 enum dev_state state)
424{
a9b3a9f7 425 u32 reg;
a9d61e9e 426 unsigned long flags;
a9b3a9f7
ID		 427
428 /*
429 * When interrupts are being enabled, the interrupt registers
430 * should clear the register to assure a clean state.
431 */
432 if (state == STATE_RADIO_IRQ_ON) {
9a819996
HS		 433 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
434 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
a9d61e9e 435 }
a9b3a9f7 436
a9d61e9e 437 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
dfd00c4c
SG		 438 reg = 0;
439 if (state == STATE_RADIO_IRQ_ON) {
440 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, 1);
441 rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, 1);
442 rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, 1);
443 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, 1);
444 rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, 1);
445 }
9a819996 446 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
a9d61e9e
HS		 447 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
448
449 if (state == STATE_RADIO_IRQ_OFF) {
450 /*
abc11994 451 * Wait for possibly running tasklets to finish.
a9d61e9e 452 */
abc11994
HS		 453 tasklet_kill(&rt2x00dev->txstatus_tasklet);
454 tasklet_kill(&rt2x00dev->rxdone_tasklet);
455 tasklet_kill(&rt2x00dev->autowake_tasklet);
456 tasklet_kill(&rt2x00dev->tbtt_tasklet);
457 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
a9d61e9e 458 }
a9b3a9f7
ID		 459}
460
e3a896b9
GW		 461static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
462{
463 u32 reg;
464
465 /*
466 * Reset DMA indexes
467 */
9a819996 468 rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
e3a896b9
GW		 469 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
470 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
471 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
472 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
473 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
474 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
475 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
9a819996 476 rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
e3a896b9 477
9a819996
HS		 478 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
479 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
e3a896b9 480
872834df
GW		 481 if (rt2x00_is_pcie(rt2x00dev) &&
482 (rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884
JL		 483 rt2x00_rt(rt2x00dev, RT5390) ||
484 rt2x00_rt(rt2x00dev, RT5392))) {
9a819996 485 rt2x00pci_register_read(rt2x00dev, AUX_CTRL, &reg);
adde5882
GJ		 486 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
487 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
9a819996 488 rt2x00pci_register_write(rt2x00dev, AUX_CTRL, reg);
adde5882 489 }
60687ba7 490
9a819996 491 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
e3a896b9 492
2a48e8ae 493 reg = 0;
e3a896b9
GW		 494 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
495 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
9a819996 496 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
e3a896b9 497
9a819996 498 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
e3a896b9
GW		 499
500 return 0;
501}
502
a9b3a9f7
ID		 503static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
504{
67a4c1e2 505 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
b9a07ae9 506 rt2800pci_init_queues(rt2x00dev)))
a9b3a9f7
ID		 507 return -EIO;
508
b9a07ae9 509 return rt2800_enable_radio(rt2x00dev);
a9b3a9f7
ID		 510}
511
512static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
513{
7f6e144f
RJH		 514 if (rt2x00_is_soc(rt2x00dev)) {
515 rt2800_disable_radio(rt2x00dev);
9a819996
HS		 516 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
517 rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
7f6e144f 518 }
a9b3a9f7
ID		 519}
520
521static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
522 enum dev_state state)
523{
a9b3a9f7 524 if (state == STATE_AWAKE) {
09a3311c
JK		 525 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP,
526 0, 0x02);
527 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
7f6e144f 528 } else if (state == STATE_SLEEP) {
9a819996
HS		 529 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
530 0xffffffff);
531 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID,
532 0xffffffff);
09a3311c
JK		 533 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_SLEEP,
534 0xff, 0x01);
a9b3a9f7
ID		 535 }
536
537 return 0;
538}
539
540static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
541 enum dev_state state)
542{
543 int retval = 0;
544
545 switch (state) {
546 case STATE_RADIO_ON:
547 /*
548 * Before the radio can be enabled, the device first has
549 * to be woken up. After that it needs a bit of time
550 * to be fully awake and then the radio can be enabled.
551 */
552 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
553 msleep(1);
554 retval = rt2800pci_enable_radio(rt2x00dev);
555 break;
556 case STATE_RADIO_OFF:
557 /*
558 * After the radio has been disabled, the device should
559 * be put to sleep for powersaving.
560 */
561 rt2800pci_disable_radio(rt2x00dev);
562 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
563 break;
a9b3a9f7
ID		 564 case STATE_RADIO_IRQ_ON:
565 case STATE_RADIO_IRQ_OFF:
566 rt2800pci_toggle_irq(rt2x00dev, state);
567 break;
568 case STATE_DEEP_SLEEP:
569 case STATE_SLEEP:
570 case STATE_STANDBY:
571 case STATE_AWAKE:
572 retval = rt2800pci_set_state(rt2x00dev, state);
573 break;
574 default:
575 retval = -ENOTSUPP;
576 break;
577 }
578
579 if (unlikely(retval))
580 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
581 state, retval);
582
583 return retval;
584}
585
586/*
587 * TX descriptor initialization
588 */
0c5879bc 589static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)
a9b3a9f7 590{
0c5879bc 591 return (__le32 *) entry->skb->data;
745b1ae3
HS		 592}
593
93331458 594static void rt2800pci_write_tx_desc(struct queue_entry *entry,
745b1ae3
HS		 595 struct txentry_desc *txdesc)
596{
93331458
ID		 597 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
598 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
85b7a8b3 599 __le32 *txd = entry_priv->desc;
745b1ae3
HS		 600 u32 word;
601
a9b3a9f7
ID		 602 /*
603 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
604 * must contains a TXWI structure + 802.11 header + padding + 802.11
605 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
606 * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
607 * data. It means that LAST_SEC0 is always 0.
608 */
609
610 /*
611 * Initialize TX descriptor
612 */
3de3d966 613 word = 0;
a9b3a9f7
ID		 614 rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
615 rt2x00_desc_write(txd, 0, word);
616
3de3d966 617 word = 0;
93331458 618 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);
a9b3a9f7
ID		 619 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
620 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
621 rt2x00_set_field32(&word, TXD_W1_BURST,
622 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
85b7a8b3 623 rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
a9b3a9f7
ID		 624 rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
625 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
626 rt2x00_desc_write(txd, 1, word);
627
3de3d966 628 word = 0;
a9b3a9f7 629 rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
85b7a8b3 630 skbdesc->skb_dma + TXWI_DESC_SIZE);
a9b3a9f7
ID		 631 rt2x00_desc_write(txd, 2, word);
632
3de3d966 633 word = 0;
a9b3a9f7
ID		 634 rt2x00_set_field32(&word, TXD_W3_WIV,
635 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
636 rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
637 rt2x00_desc_write(txd, 3, word);
85b7a8b3
GW		 638
639 /*
640 * Register descriptor details in skb frame descriptor.
641 */
642 skbdesc->desc = txd;
643 skbdesc->desc_len = TXD_DESC_SIZE;
a9b3a9f7
ID		 644}
645
a9b3a9f7
ID		 646/*
647 * RX control handlers
648 */
649static void rt2800pci_fill_rxdone(struct queue_entry *entry,
650 struct rxdone_entry_desc *rxdesc)
651{
a9b3a9f7
ID		 652 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
653 __le32 *rxd = entry_priv->desc;
2de64dd2
GW		 654 u32 word;
655
656 rt2x00_desc_read(rxd, 3, &word);
657
658 if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
a9b3a9f7
ID		 659 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
660
78b8f3b0
GW		 661 /*
662 * Unfortunately we don't know the cipher type used during
663 * decryption. This prevents us from correct providing
664 * correct statistics through debugfs.
665 */
2de64dd2 666 rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
a9b3a9f7 667
2de64dd2 668 if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
a9b3a9f7
ID		 669 /*
670 * Hardware has stripped IV/EIV data from 802.11 frame during
671 * decryption. Unfortunately the descriptor doesn't contain
672 * any fields with the EIV/IV data either, so they can't
673 * be restored by rt2x00lib.
674 */
675 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
676
a45f369d
GW		 677 /*
678 * The hardware has already checked the Michael Mic and has
679 * stripped it from the frame. Signal this to mac80211.
680 */
681 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
682
a9b3a9f7
ID		 683 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
684 rxdesc->flags |= RX_FLAG_DECRYPTED;
685 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
686 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
687 }
688
2de64dd2 689 if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
a9b3a9f7
ID		 690 rxdesc->dev_flags |= RXDONE_MY_BSS;
691
2de64dd2 692 if (rt2x00_get_field32(word, RXD_W3_L2PAD))
a9b3a9f7 693 rxdesc->dev_flags |= RXDONE_L2PAD;
a9b3a9f7 694
a9b3a9f7 695 /*
2de64dd2 696 * Process the RXWI structure that is at the start of the buffer.
a9b3a9f7 697 */
74861922 698 rt2800_process_rxwi(entry, rxdesc);
a9b3a9f7
ID		 699}
700
701/*
702 * Interrupt functions.
703 */
4d66edc8
GW		 704static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
705{
706 struct ieee80211_conf conf = { .flags = 0 };
707 struct rt2x00lib_conf libconf = { .conf = &conf };
708
709 rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
710}
711
2e7798b7 712static bool rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
96c3da7d
HS		 713{
714 struct data_queue *queue;
715 struct queue_entry *entry;
716 u32 status;
717 u8 qid;
2e7798b7 718 int max_tx_done = 16;
96c3da7d 719
c4d63244 720 while (kfifo_get(&rt2x00dev->txstatus_fifo, &status)) {
12eec2cc 721 qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
87443e87 722 if (unlikely(qid >= QID_RX)) {
96c3da7d
HS		 723 /*
724 * Unknown queue, this shouldn't happen. Just drop
725 * this tx status.
726 */
727 WARNING(rt2x00dev, "Got TX status report with "
094a1d92 728 "unexpected pid %u, dropping\n", qid);
96c3da7d
HS		 729 break;
730 }
731
11f818e0 732 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
96c3da7d
HS		 733 if (unlikely(queue == NULL)) {
734 /*
735 * The queue is NULL, this shouldn't happen. Stop
736 * processing here and drop the tx status
737 */
738 WARNING(rt2x00dev, "Got TX status for an unavailable "
094a1d92 739 "queue %u, dropping\n", qid);
96c3da7d
HS		 740 break;
741 }
742
87443e87 743 if (unlikely(rt2x00queue_empty(queue))) {
96c3da7d
HS		 744 /*
745 * The queue is empty. Stop processing here
746 * and drop the tx status.
747 */
748 WARNING(rt2x00dev, "Got TX status for an empty "
094a1d92 749 "queue %u, dropping\n", qid);
96c3da7d
HS		 750 break;
751 }
752
753 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
31937c42 754 rt2800_txdone_entry(entry, status, rt2800pci_get_txwi(entry));
2e7798b7
HS		 755
756 if (--max_tx_done == 0)
757 break;
96c3da7d 758 }
2e7798b7
HS		 759
760 return !max_tx_done;
96c3da7d
HS		 761}
762
7a5a681a
HS		 763static inline void rt2800pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
764 struct rt2x00_field32 irq_field)
a9b3a9f7 765{
a9d61e9e 766 u32 reg;
a9b3a9f7
ID		 767
768 /*
a9d61e9e
HS		 769 * Enable a single interrupt. The interrupt mask register
770 * access needs locking.
9f926fb5 771 */
0aa13b2e 772 spin_lock_irq(&rt2x00dev->irqmask_lock);
9a819996 773 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
a9d61e9e 774 rt2x00_set_field32(&reg, irq_field, 1);
9a819996 775 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
0aa13b2e 776 spin_unlock_irq(&rt2x00dev->irqmask_lock);
a9d61e9e 777}
9f926fb5 778
a9d61e9e
HS		 779static void rt2800pci_txstatus_tasklet(unsigned long data)
780{
2e7798b7
HS		 781 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
782 if (rt2800pci_txdone(rt2x00dev))
783 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
9f926fb5
HS		 784
785 /*
a9d61e9e
HS		 786 * No need to enable the tx status interrupt here as we always
787 * leave it enabled to minimize the possibility of a tx status
788 * register overflow. See comment in interrupt handler.
a9b3a9f7 789 */
a9d61e9e 790}
a9b3a9f7 791
a9d61e9e
HS		 792static void rt2800pci_pretbtt_tasklet(unsigned long data)
793{
794 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
795 rt2x00lib_pretbtt(rt2x00dev);
abc11994
HS		 796 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
797 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_PRE_TBTT);
a9d61e9e 798}
4d66edc8 799
a9d61e9e
HS		 800static void rt2800pci_tbtt_tasklet(unsigned long data)
801{
802 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
803 rt2x00lib_beacondone(rt2x00dev);
abc11994
HS		 804 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
805 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TBTT);
a9d61e9e 806}
78e256c9 807
a9d61e9e
HS		 808static void rt2800pci_rxdone_tasklet(unsigned long data)
809{
810 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
16638937
HS		 811 if (rt2x00pci_rxdone(rt2x00dev))
812 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
abc11994 813 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
16638937 814 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RX_DONE);
a9d61e9e
HS		 815}
816
817static void rt2800pci_autowake_tasklet(unsigned long data)
818{
819 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
820 rt2800pci_wakeup(rt2x00dev);
abc11994
HS		 821 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
822 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_AUTO_WAKEUP);
a9b3a9f7
ID		 823}
824
96c3da7d
HS		 825static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
826{
827 u32 status;
828 int i;
829
830 /*
831 * The TX_FIFO_STATUS interrupt needs special care. We should
832 * read TX_STA_FIFO but we should do it immediately as otherwise
833 * the register can overflow and we would lose status reports.
834 *
835 * Hence, read the TX_STA_FIFO register and copy all tx status
836 * reports into a kernel FIFO which is handled in the txstatus
837 * tasklet. We use a tasklet to process the tx status reports
838 * because we can schedule the tasklet multiple times (when the
839 * interrupt fires again during tx status processing).
840 *
841 * Furthermore we don't disable the TX_FIFO_STATUS
842 * interrupt here but leave it enabled so that the TX_STA_FIFO
3736fe58 843 * can also be read while the tx status tasklet gets executed.
96c3da7d
HS		 844 *
845 * Since we have only one producer and one consumer we don't
846 * need to lock the kfifo.
847 */
efd2f271 848 for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
9a819996 849 rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &status);
96c3da7d
HS		 850
851 if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
852 break;
853
c4d63244 854 if (!kfifo_put(&rt2x00dev->txstatus_fifo, &status)) {
96c3da7d
HS		 855 WARNING(rt2x00dev, "TX status FIFO overrun,"
856 "drop tx status report.\n");
857 break;
858 }
859 }
860
861 /* Schedule the tasklet for processing the tx status. */
862 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
863}
864
78e256c9
HS		 865static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
866{
867 struct rt2x00_dev *rt2x00dev = dev_instance;
a9d61e9e 868 u32 reg, mask;
78e256c9
HS		 869
870 /* Read status and ACK all interrupts */
9a819996
HS		 871 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
872 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
78e256c9
HS		 873
874 if (!reg)
875 return IRQ_NONE;
876
877 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
878 return IRQ_HANDLED;
879
a9d61e9e
HS		 880 /*
881 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
882 * for interrupts and interrupt masks we can just use the value of
883 * INT_SOURCE_CSR to create the interrupt mask.
884 */
885 mask = ~reg;
78e256c9 886
a9d61e9e
HS		 887 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) {
888 rt2800pci_txstatus_interrupt(rt2x00dev);
96c3da7d 889 /*
a9d61e9e 890 * Never disable the TX_FIFO_STATUS interrupt.
96c3da7d 891 */
a9d61e9e
HS		 892 rt2x00_set_field32(&mask, INT_MASK_CSR_TX_FIFO_STATUS, 1);
893 }
96c3da7d 894
a9d61e9e
HS		 895 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
896 tasklet_hi_schedule(&rt2x00dev->pretbtt_tasklet);
78e256c9 897
a9d61e9e
HS		 898 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
899 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
96c3da7d 900
a9d61e9e
HS		 901 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
902 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
78e256c9 903
a9d61e9e
HS		 904 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
905 tasklet_schedule(&rt2x00dev->autowake_tasklet);
906
907 /*
908 * Disable all interrupts for which a tasklet was scheduled right now,
909 * the tasklet will reenable the appropriate interrupts.
910 */
0aa13b2e 911 spin_lock(&rt2x00dev->irqmask_lock);
9a819996 912 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
a9d61e9e 913 reg &= mask;
9a819996 914 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
0aa13b2e 915 spin_unlock(&rt2x00dev->irqmask_lock);
a9d61e9e
HS		 916
917 return IRQ_HANDLED;
78e256c9
HS		 918}
919
a9b3a9f7
ID		 920/*
921 * Device probe functions.
922 */
7ab71325
BZ		 923static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
924{
925 /*
926 * Read EEPROM into buffer
927 */
cea90e55 928 if (rt2x00_is_soc(rt2x00dev))
7ab71325 929 rt2800pci_read_eeprom_soc(rt2x00dev);
cea90e55
GW		 930 else if (rt2800pci_efuse_detect(rt2x00dev))
931 rt2800pci_read_eeprom_efuse(rt2x00dev);
932 else
933 rt2800pci_read_eeprom_pci(rt2x00dev);
7ab71325
BZ		 934
935 return rt2800_validate_eeprom(rt2x00dev);
936}
937
a9b3a9f7
ID		 938static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
939{
940 int retval;
941
942 /*
943 * Allocate eeprom data.
944 */
945 retval = rt2800pci_validate_eeprom(rt2x00dev);
946 if (retval)
947 return retval;
948
38bd7b8a 949 retval = rt2800_init_eeprom(rt2x00dev);
a9b3a9f7
ID		 950 if (retval)
951 return retval;
952
953 /*
954 * Initialize hw specifications.
955 */
4da2933f 956 retval = rt2800_probe_hw_mode(rt2x00dev);
a9b3a9f7
ID		 957 if (retval)
958 return retval;
959
960 /*
961 * This device has multiple filters for control frames
962 * and has a separate filter for PS Poll frames.
963 */
7dab73b3
ID		 964 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
965 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
a9b3a9f7 966
9f926fb5
HS		 967 /*
968 * This device has a pre tbtt interrupt and thus fetches
969 * a new beacon directly prior to transmission.
970 */
7dab73b3 971 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
9f926fb5 972
a9b3a9f7
ID		 973 /*
974 * This device requires firmware.
975 */
cea90e55 976 if (!rt2x00_is_soc(rt2x00dev))
7dab73b3
ID		 977 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
978 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
979 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
980 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
981 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
a9b3a9f7 982 if (!modparam_nohwcrypt)
7dab73b3
ID		 983 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
984 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
985 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
a9b3a9f7
ID		 986
987 /*
988 * Set the rssi offset.
989 */
990 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
991
992 return 0;
993}
994
e783619e
HS		 995static const struct ieee80211_ops rt2800pci_mac80211_ops = {
996 .tx = rt2x00mac_tx,
997 .start = rt2x00mac_start,
998 .stop = rt2x00mac_stop,
999 .add_interface = rt2x00mac_add_interface,
1000 .remove_interface = rt2x00mac_remove_interface,
1001 .config = rt2x00mac_config,
1002 .configure_filter = rt2x00mac_configure_filter,
e783619e
HS		 1003 .set_key = rt2x00mac_set_key,
1004 .sw_scan_start = rt2x00mac_sw_scan_start,
1005 .sw_scan_complete = rt2x00mac_sw_scan_complete,
1006 .get_stats = rt2x00mac_get_stats,
1007 .get_tkip_seq = rt2800_get_tkip_seq,
1008 .set_rts_threshold = rt2800_set_rts_threshold,
a2b1328a
HS		 1009 .sta_add = rt2x00mac_sta_add,
1010 .sta_remove = rt2x00mac_sta_remove,
e783619e
HS		 1011 .bss_info_changed = rt2x00mac_bss_info_changed,
1012 .conf_tx = rt2800_conf_tx,
1013 .get_tsf = rt2800_get_tsf,
1014 .rfkill_poll = rt2x00mac_rfkill_poll,
1015 .ampdu_action = rt2800_ampdu_action,
f44df18c 1016 .flush = rt2x00mac_flush,
977206d7 1017 .get_survey = rt2800_get_survey,
e7dee444 1018 .get_ringparam = rt2x00mac_get_ringparam,
5f0dd296 1019 .tx_frames_pending = rt2x00mac_tx_frames_pending,
e783619e
HS		 1020};
1021
e796643e
ID		 1022static const struct rt2800_ops rt2800pci_rt2800_ops = {
1023 .register_read = rt2x00pci_register_read,
1024 .register_read_lock = rt2x00pci_register_read, /* same for PCI */
1025 .register_write = rt2x00pci_register_write,
1026 .register_write_lock = rt2x00pci_register_write, /* same for PCI */
1027 .register_multiread = rt2x00pci_register_multiread,
1028 .register_multiwrite = rt2x00pci_register_multiwrite,
1029 .regbusy_read = rt2x00pci_regbusy_read,
1030 .drv_write_firmware = rt2800pci_write_firmware,
1031 .drv_init_registers = rt2800pci_init_registers,
0c5879bc 1032 .drv_get_txwi = rt2800pci_get_txwi,
e796643e
ID		 1033};
1034
a9b3a9f7
ID		 1035static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1036 .irq_handler = rt2800pci_interrupt,
a9d61e9e
HS		 1037 .txstatus_tasklet = rt2800pci_txstatus_tasklet,
1038 .pretbtt_tasklet = rt2800pci_pretbtt_tasklet,
1039 .tbtt_tasklet = rt2800pci_tbtt_tasklet,
1040 .rxdone_tasklet = rt2800pci_rxdone_tasklet,
1041 .autowake_tasklet = rt2800pci_autowake_tasklet,
a9b3a9f7
ID		 1042 .probe_hw = rt2800pci_probe_hw,
1043 .get_firmware_name = rt2800pci_get_firmware_name,
f31c9a8c
ID		 1044 .check_firmware = rt2800_check_firmware,
1045 .load_firmware = rt2800_load_firmware,
a9b3a9f7
ID		 1046 .initialize = rt2x00pci_initialize,
1047 .uninitialize = rt2x00pci_uninitialize,
1048 .get_entry_state = rt2800pci_get_entry_state,
1049 .clear_entry = rt2800pci_clear_entry,
1050 .set_device_state = rt2800pci_set_device_state,
f4450616
BZ		 1051 .rfkill_poll = rt2800_rfkill_poll,
1052 .link_stats = rt2800_link_stats,
1053 .reset_tuner = rt2800_reset_tuner,
1054 .link_tuner = rt2800_link_tuner,
9e33a355 1055 .gain_calibration = rt2800_gain_calibration,
2e9c43dd 1056 .vco_calibration = rt2800_vco_calibration,
dbba306f
ID		 1057 .start_queue = rt2800pci_start_queue,
1058 .kick_queue = rt2800pci_kick_queue,
1059 .stop_queue = rt2800pci_stop_queue,
152a5992 1060 .flush_queue = rt2x00pci_flush_queue,
a9b3a9f7 1061 .write_tx_desc = rt2800pci_write_tx_desc,
0c5879bc 1062 .write_tx_data = rt2800_write_tx_data,
f0194b2d 1063 .write_beacon = rt2800_write_beacon,
69cf36a4 1064 .clear_beacon = rt2800_clear_beacon,
a9b3a9f7 1065 .fill_rxdone = rt2800pci_fill_rxdone,
f4450616
BZ		 1066 .config_shared_key = rt2800_config_shared_key,
1067 .config_pairwise_key = rt2800_config_pairwise_key,
1068 .config_filter = rt2800_config_filter,
1069 .config_intf = rt2800_config_intf,
1070 .config_erp = rt2800_config_erp,
1071 .config_ant = rt2800_config_ant,
1072 .config = rt2800_config,
a2b1328a
HS		 1073 .sta_add = rt2800_sta_add,
1074 .sta_remove = rt2800_sta_remove,
a9b3a9f7
ID		 1075};
1076
1077static const struct data_queue_desc rt2800pci_queue_rx = {
efd2f271 1078 .entry_num = 128,
a9b3a9f7
ID		 1079 .data_size = AGGREGATION_SIZE,
1080 .desc_size = RXD_DESC_SIZE,
1081 .priv_size = sizeof(struct queue_entry_priv_pci),
1082};
1083
1084static const struct data_queue_desc rt2800pci_queue_tx = {
efd2f271 1085 .entry_num = 64,
a9b3a9f7
ID		 1086 .data_size = AGGREGATION_SIZE,
1087 .desc_size = TXD_DESC_SIZE,
1088 .priv_size = sizeof(struct queue_entry_priv_pci),
1089};
1090
1091static const struct data_queue_desc rt2800pci_queue_bcn = {
efd2f271 1092 .entry_num = 8,
a9b3a9f7
ID		 1093 .data_size = 0, /* No DMA required for beacons */
1094 .desc_size = TXWI_DESC_SIZE,
1095 .priv_size = sizeof(struct queue_entry_priv_pci),
1096};
1097
1098static const struct rt2x00_ops rt2800pci_ops = {
04d0362e 1099 .name = KBUILD_MODNAME,
3a1c0128 1100 .drv_data_size = sizeof(struct rt2800_drv_data),
04d0362e
GW		 1101 .max_sta_intf = 1,
1102 .max_ap_intf = 8,
1103 .eeprom_size = EEPROM_SIZE,
1104 .rf_size = RF_SIZE,
1105 .tx_queues = NUM_TX_QUEUES,
e6218cc4 1106 .extra_tx_headroom = TXWI_DESC_SIZE,
04d0362e
GW		 1107 .rx = &rt2800pci_queue_rx,
1108 .tx = &rt2800pci_queue_tx,
1109 .bcn = &rt2800pci_queue_bcn,
1110 .lib = &rt2800pci_rt2x00_ops,
e796643e 1111 .drv = &rt2800pci_rt2800_ops,
e783619e 1112 .hw = &rt2800pci_mac80211_ops,
a9b3a9f7 1113#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 1114 .debugfs = &rt2800_rt2x00debug,
a9b3a9f7
ID		 1115#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1116};
1117
1118/*
1119 * RT2800pci module information.
1120 */
72c7296e 1121#ifdef CONFIG_PCI
a3aa1884 1122static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
e01ae27f
GW		 1123 { PCI_DEVICE(0x1814, 0x0601) },
1124 { PCI_DEVICE(0x1814, 0x0681) },
1125 { PCI_DEVICE(0x1814, 0x0701) },
1126 { PCI_DEVICE(0x1814, 0x0781) },
1127 { PCI_DEVICE(0x1814, 0x3090) },
1128 { PCI_DEVICE(0x1814, 0x3091) },
1129 { PCI_DEVICE(0x1814, 0x3092) },
1130 { PCI_DEVICE(0x1432, 0x7708) },
1131 { PCI_DEVICE(0x1432, 0x7727) },
1132 { PCI_DEVICE(0x1432, 0x7728) },
1133 { PCI_DEVICE(0x1432, 0x7738) },
1134 { PCI_DEVICE(0x1432, 0x7748) },
1135 { PCI_DEVICE(0x1432, 0x7758) },
1136 { PCI_DEVICE(0x1432, 0x7768) },
1137 { PCI_DEVICE(0x1462, 0x891a) },
1138 { PCI_DEVICE(0x1a3b, 0x1059) },
f93bc9b3 1139#ifdef CONFIG_RT2800PCI_RT33XX
e01ae27f 1140 { PCI_DEVICE(0x1814, 0x3390) },
f93bc9b3 1141#endif
de1ebdce 1142#ifdef CONFIG_RT2800PCI_RT35XX
e01ae27f
GW		 1143 { PCI_DEVICE(0x1432, 0x7711) },
1144 { PCI_DEVICE(0x1432, 0x7722) },
1145 { PCI_DEVICE(0x1814, 0x3060) },
1146 { PCI_DEVICE(0x1814, 0x3062) },
1147 { PCI_DEVICE(0x1814, 0x3562) },
1148 { PCI_DEVICE(0x1814, 0x3592) },
1149 { PCI_DEVICE(0x1814, 0x3593) },
60687ba7
RST		 1150#endif
1151#ifdef CONFIG_RT2800PCI_RT53XX
e01ae27f 1152 { PCI_DEVICE(0x1814, 0x5390) },
5126d97e 1153 { PCI_DEVICE(0x1814, 0x539a) },
71e0b38c 1154 { PCI_DEVICE(0x1814, 0x539f) },
de1ebdce 1155#endif
a9b3a9f7
ID		 1156 { 0, }
1157};
72c7296e 1158#endif /* CONFIG_PCI */
a9b3a9f7
ID		 1159
1160MODULE_AUTHOR(DRV_PROJECT);
1161MODULE_VERSION(DRV_VERSION);
1162MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1163MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
72c7296e 1164#ifdef CONFIG_PCI
a9b3a9f7
ID		 1165MODULE_FIRMWARE(FIRMWARE_RT2860);
1166MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
72c7296e 1167#endif /* CONFIG_PCI */
a9b3a9f7
ID		 1168MODULE_LICENSE("GPL");
1169
72c7296e 1170#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
714fa663
GW		 1171static int rt2800soc_probe(struct platform_device *pdev)
1172{
6e93d719 1173 return rt2x00soc_probe(pdev, &rt2800pci_ops);
714fa663 1174}
a9b3a9f7
ID		 1175
1176static struct platform_driver rt2800soc_driver = {
1177 .driver = {
1178 .name = "rt2800_wmac",
1179 .owner = THIS_MODULE,
1180 .mod_name = KBUILD_MODNAME,
1181 },
714fa663 1182 .probe = rt2800soc_probe,
a9b3a9f7
ID		 1183 .remove = __devexit_p(rt2x00soc_remove),
1184 .suspend = rt2x00soc_suspend,
1185 .resume = rt2x00soc_resume,
1186};
72c7296e 1187#endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
a9b3a9f7 1188
72c7296e 1189#ifdef CONFIG_PCI
e01ae27f
GW		 1190static int rt2800pci_probe(struct pci_dev *pci_dev,
1191 const struct pci_device_id *id)
1192{
1193 return rt2x00pci_probe(pci_dev, &rt2800pci_ops);
1194}
1195
a9b3a9f7
ID		 1196static struct pci_driver rt2800pci_driver = {
1197 .name = KBUILD_MODNAME,
1198 .id_table = rt2800pci_device_table,
e01ae27f 1199 .probe = rt2800pci_probe,
a9b3a9f7
ID		 1200 .remove = __devexit_p(rt2x00pci_remove),
1201 .suspend = rt2x00pci_suspend,
1202 .resume = rt2x00pci_resume,
1203};
72c7296e 1204#endif /* CONFIG_PCI */
a9b3a9f7
ID		 1205
1206static int __init rt2800pci_init(void)
1207{
1208 int ret = 0;
1209
72c7296e 1210#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
a9b3a9f7
ID		 1211 ret = platform_driver_register(&rt2800soc_driver);
1212 if (ret)
1213 return ret;
1214#endif
72c7296e 1215#ifdef CONFIG_PCI
a9b3a9f7
ID		 1216 ret = pci_register_driver(&rt2800pci_driver);
1217 if (ret) {
72c7296e 1218#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
a9b3a9f7
ID		 1219 platform_driver_unregister(&rt2800soc_driver);
1220#endif
1221 return ret;
1222 }
1223#endif
1224
1225 return ret;
1226}
1227
1228static void __exit rt2800pci_exit(void)
1229{
72c7296e 1230#ifdef CONFIG_PCI
a9b3a9f7
ID		 1231 pci_unregister_driver(&rt2800pci_driver);
1232#endif
72c7296e 1233#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
a9b3a9f7
ID		 1234 platform_driver_unregister(&rt2800soc_driver);
1235#endif
1236}
1237
1238module_init(rt2800pci_init);
1239module_exit(rt2800pci_exit);
Linux kernel - Deliverables
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