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rt2x00: rt2800pci: move TX descriptor functions to the rt2800mmio module
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2800pci.c
CommitLineData
a9b3a9f7 1/*
96481b20 2 Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14
GW		 3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
a9b3a9f7
ID		 10 <http://rt2x00.serialmonkey.com>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 */
27
28/*
29 Module: rt2800pci
30 Abstract: rt2800pci device specific routines.
31 Supported chipsets: RT2800E & RT2800ED.
32 */
33
a9b3a9f7
ID		 34#include <linux/delay.h>
35#include <linux/etherdevice.h>
36#include <linux/init.h>
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/pci.h>
40#include <linux/platform_device.h>
41#include <linux/eeprom_93cx6.h>
42
43#include "rt2x00.h"
69a2bac8 44#include "rt2x00mmio.h"
a9b3a9f7
ID		 45#include "rt2x00pci.h"
46#include "rt2x00soc.h"
7ef5cc92 47#include "rt2800lib.h"
0bc202b3 48#include "rt2800mmio.h"
b54f78a8 49#include "rt2800.h"
a9b3a9f7
ID		 50#include "rt2800pci.h"
51
a9b3a9f7
ID		 52/*
53 * Allow hardware encryption to be disabled.
54 */
eb939922 55static bool modparam_nohwcrypt = false;
a9b3a9f7
ID		 56module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
57MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
58
ad417a53
GW		 59static bool rt2800pci_hwcrypt_disabled(struct rt2x00_dev *rt2x00dev)
60{
61 return modparam_nohwcrypt;
62}
63
a9b3a9f7
ID		 64static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
65{
66 unsigned int i;
67 u32 reg;
68
f18d4463
LC		 69 /*
70 * SOC devices don't support MCU requests.
71 */
72 if (rt2x00_is_soc(rt2x00dev))
73 return;
74
a9b3a9f7 75 for (i = 0; i < 200; i++) {
b9570b66 76 rt2x00mmio_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
a9b3a9f7
ID		 77
78 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
79 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
80 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
81 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
82 break;
83
84 udelay(REGISTER_BUSY_DELAY);
85 }
86
87 if (i == 200)
ec9c4989 88 rt2x00_err(rt2x00dev, "MCU request failed, no response from hardware\n");
a9b3a9f7 89
b9570b66
GJ		 90 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
91 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
a9b3a9f7
ID		 92}
93
5818a46a 94#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
a02308e9 95static int rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 96{
ef8397cf 97 void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
a9b3a9f7 98
a02308e9
GJ		 99 if (!base_addr)
100 return -ENOMEM;
101
a9b3a9f7 102 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
ef8397cf
GW		 103
104 iounmap(base_addr);
a02308e9 105 return 0;
a9b3a9f7
ID		 106}
107#else
a02308e9 108static inline int rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 109{
a02308e9 110 return -ENOMEM;
a9b3a9f7 111}
5818a46a 112#endif /* CONFIG_SOC_RT288X || CONFIG_SOC_RT305X */
a9b3a9f7 113
72c7296e 114#ifdef CONFIG_PCI
a9b3a9f7
ID		 115static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
116{
117 struct rt2x00_dev *rt2x00dev = eeprom->data;
118 u32 reg;
119
b9570b66 120 rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 121
122 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
123 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
124 eeprom->reg_data_clock =
125 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
126 eeprom->reg_chip_select =
127 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
128}
129
130static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
131{
132 struct rt2x00_dev *rt2x00dev = eeprom->data;
133 u32 reg = 0;
134
135 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
136 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
137 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
138 !!eeprom->reg_data_clock);
139 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
140 !!eeprom->reg_chip_select);
141
b9570b66 142 rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg);
a9b3a9f7
ID		 143}
144
a02308e9 145static int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
a9b3a9f7
ID		 146{
147 struct eeprom_93cx6 eeprom;
148 u32 reg;
149
b9570b66 150 rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 151
152 eeprom.data = rt2x00dev;
153 eeprom.register_read = rt2800pci_eepromregister_read;
154 eeprom.register_write = rt2800pci_eepromregister_write;
20f8b139
GW		 155 switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
156 {
157 case 0:
158 eeprom.width = PCI_EEPROM_WIDTH_93C46;
159 break;
160 case 1:
161 eeprom.width = PCI_EEPROM_WIDTH_93C66;
162 break;
163 default:
164 eeprom.width = PCI_EEPROM_WIDTH_93C86;
165 break;
166 }
a9b3a9f7
ID		 167 eeprom.reg_data_in = 0;
168 eeprom.reg_data_out = 0;
169 eeprom.reg_data_clock = 0;
170 eeprom.reg_chip_select = 0;
171
172 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
173 EEPROM_SIZE / sizeof(u16));
a02308e9
GJ		 174
175 return 0;
a9b3a9f7
ID		 176}
177
a6598682
GW		 178static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
179{
30e84034 180 return rt2800_efuse_detect(rt2x00dev);
a9b3a9f7
ID		 181}
182
a02308e9 183static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 184{
a02308e9 185 return rt2800_read_eeprom_efuse(rt2x00dev);
a9b3a9f7
ID		 186}
187#else
a02308e9 188static inline int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 189{
a02308e9 190 return -EOPNOTSUPP;
a9b3a9f7
ID		 191}
192
a6598682
GW		 193static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
194{
195 return 0;
196}
197
a02308e9 198static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 199{
a02308e9 200 return -EOPNOTSUPP;
a9b3a9f7 201}
72c7296e 202#endif /* CONFIG_PCI */
a9b3a9f7 203
5450b7e2
ID		 204/*
205 * Queue handlers.
206 */
207static void rt2800pci_start_queue(struct data_queue *queue)
208{
209 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
210 u32 reg;
211
212 switch (queue->qid) {
213 case QID_RX:
b9570b66 214 rt2x00mmio_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5450b7e2 215 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
b9570b66 216 rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5450b7e2
ID		 217 break;
218 case QID_BEACON:
b9570b66 219 rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
5450b7e2
ID		 220 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
221 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
222 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
b9570b66 223 rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
69cf36a4 224
b9570b66 225 rt2x00mmio_register_read(rt2x00dev, INT_TIMER_EN, &reg);
69cf36a4 226 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 1);
b9570b66 227 rt2x00mmio_register_write(rt2x00dev, INT_TIMER_EN, reg);
5450b7e2
ID		 228 break;
229 default:
230 break;
6403eab1 231 }
5450b7e2
ID		 232}
233
234static void rt2800pci_kick_queue(struct data_queue *queue)
235{
236 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
237 struct queue_entry *entry;
238
239 switch (queue->qid) {
f615e9a3
ID		 240 case QID_AC_VO:
241 case QID_AC_VI:
5450b7e2
ID		 242 case QID_AC_BE:
243 case QID_AC_BK:
5450b7e2 244 entry = rt2x00queue_get_entry(queue, Q_INDEX);
b9570b66
GJ		 245 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX(queue->qid),
246 entry->entry_idx);
5450b7e2
ID		 247 break;
248 case QID_MGMT:
249 entry = rt2x00queue_get_entry(queue, Q_INDEX);
b9570b66
GJ		 250 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX(5),
251 entry->entry_idx);
5450b7e2
ID		 252 break;
253 default:
254 break;
255 }
256}
257
258static void rt2800pci_stop_queue(struct data_queue *queue)
259{
260 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
261 u32 reg;
262
263 switch (queue->qid) {
264 case QID_RX:
b9570b66 265 rt2x00mmio_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5450b7e2 266 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
b9570b66 267 rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5450b7e2
ID		 268 break;
269 case QID_BEACON:
b9570b66 270 rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
5450b7e2
ID		 271 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
272 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
273 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
b9570b66 274 rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
69cf36a4 275
b9570b66 276 rt2x00mmio_register_read(rt2x00dev, INT_TIMER_EN, &reg);
69cf36a4 277 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 0);
b9570b66 278 rt2x00mmio_register_write(rt2x00dev, INT_TIMER_EN, reg);
a9d61e9e
HS		 279
280 /*
abc11994
HS		 281 * Wait for current invocation to finish. The tasklet
282 * won't be scheduled anymore afterwards since we disabled
283 * the TBTT and PRE TBTT timer.
a9d61e9e 284 */
abc11994
HS		 285 tasklet_kill(&rt2x00dev->tbtt_tasklet);
286 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
287
5450b7e2
ID		 288 break;
289 default:
290 break;
291 }
292}
293
a9b3a9f7
ID		 294/*
295 * Firmware functions
296 */
297static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
298{
a89534ed
WH		 299 /*
300 * Chip rt3290 use specific 4KB firmware named rt3290.bin.
301 */
302 if (rt2x00_rt(rt2x00dev, RT3290))
303 return FIRMWARE_RT3290;
304 else
305 return FIRMWARE_RT2860;
a9b3a9f7
ID		 306}
307
f31c9a8c 308static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
a9b3a9f7
ID		 309 const u8 *data, const size_t len)
310{
a9b3a9f7
ID		 311 u32 reg;
312
a9b3a9f7
ID		 313 /*
314 * enable Host program ram write selection
315 */
316 reg = 0;
317 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
b9570b66 318 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
a9b3a9f7
ID		 319
320 /*
321 * Write firmware to device.
322 */
b9570b66
GJ		 323 rt2x00mmio_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
324 data, len);
a9b3a9f7 325
b9570b66
GJ		 326 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
327 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
a9b3a9f7 328
b9570b66
GJ		 329 rt2x00mmio_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
330 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
a9b3a9f7
ID		 331
332 return 0;
333}
334
335/*
336 * Initialization functions.
337 */
338static bool rt2800pci_get_entry_state(struct queue_entry *entry)
339{
b9570b66 340 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
a9b3a9f7
ID		 341 u32 word;
342
343 if (entry->queue->qid == QID_RX) {
344 rt2x00_desc_read(entry_priv->desc, 1, &word);
345
346 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
347 } else {
348 rt2x00_desc_read(entry_priv->desc, 1, &word);
349
350 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
351 }
352}
353
354static void rt2800pci_clear_entry(struct queue_entry *entry)
355{
b9570b66 356 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
a9b3a9f7 357 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95192339 358 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
a9b3a9f7
ID		 359 u32 word;
360
361 if (entry->queue->qid == QID_RX) {
362 rt2x00_desc_read(entry_priv->desc, 0, &word);
363 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
364 rt2x00_desc_write(entry_priv->desc, 0, word);
365
366 rt2x00_desc_read(entry_priv->desc, 1, &word);
367 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
368 rt2x00_desc_write(entry_priv->desc, 1, word);
95192339
HS		 369
370 /*
371 * Set RX IDX in register to inform hardware that we have
372 * handled this entry and it is available for reuse again.
373 */
b9570b66
GJ		 374 rt2x00mmio_register_write(rt2x00dev, RX_CRX_IDX,
375 entry->entry_idx);
a9b3a9f7
ID		 376 } else {
377 rt2x00_desc_read(entry_priv->desc, 1, &word);
378 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
379 rt2x00_desc_write(entry_priv->desc, 1, word);
380 }
381}
382
383static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
384{
b9570b66 385 struct queue_entry_priv_mmio *entry_priv;
a9b3a9f7 386
a9b3a9f7
ID		 387 /*
388 * Initialize registers.
389 */
390 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
b9570b66
GJ		 391 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR0,
392 entry_priv->desc_dma);
393 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT0,
394 rt2x00dev->tx[0].limit);
395 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX0, 0);
396 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX0, 0);
a9b3a9f7
ID		 397
398 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
b9570b66
GJ		 399 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR1,
400 entry_priv->desc_dma);
401 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT1,
402 rt2x00dev->tx[1].limit);
403 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX1, 0);
404 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX1, 0);
a9b3a9f7
ID		 405
406 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
b9570b66
GJ		 407 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR2,
408 entry_priv->desc_dma);
409 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT2,
410 rt2x00dev->tx[2].limit);
411 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX2, 0);
412 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX2, 0);
a9b3a9f7
ID		 413
414 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
b9570b66
GJ		 415 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR3,
416 entry_priv->desc_dma);
417 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT3,
418 rt2x00dev->tx[3].limit);
419 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX3, 0);
420 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX3, 0);
421
422 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR4, 0);
423 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT4, 0);
424 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX4, 0);
425 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX4, 0);
426
427 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR5, 0);
428 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT5, 0);
429 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX5, 0);
430 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX5, 0);
3a4b43fd 431
a9b3a9f7 432 entry_priv = rt2x00dev->rx->entries[0].priv_data;
b9570b66
GJ		 433 rt2x00mmio_register_write(rt2x00dev, RX_BASE_PTR,
434 entry_priv->desc_dma);
435 rt2x00mmio_register_write(rt2x00dev, RX_MAX_CNT,
436 rt2x00dev->rx[0].limit);
437 rt2x00mmio_register_write(rt2x00dev, RX_CRX_IDX,
438 rt2x00dev->rx[0].limit - 1);
439 rt2x00mmio_register_write(rt2x00dev, RX_DRX_IDX, 0);
a9b3a9f7 440
f7b395e9 441 rt2800_disable_wpdma(rt2x00dev);
a9b3a9f7 442
b9570b66 443 rt2x00mmio_register_write(rt2x00dev, DELAY_INT_CFG, 0);
a9b3a9f7
ID		 444
445 return 0;
446}
447
a9b3a9f7
ID		 448/*
449 * Device state switch handlers.
450 */
a9b3a9f7
ID		 451static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
452 enum dev_state state)
453{
a9b3a9f7 454 u32 reg;
a9d61e9e 455 unsigned long flags;
a9b3a9f7
ID		 456
457 /*
458 * When interrupts are being enabled, the interrupt registers
459 * should clear the register to assure a clean state.
460 */
461 if (state == STATE_RADIO_IRQ_ON) {
b9570b66
GJ		 462 rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
463 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
a9d61e9e 464 }
a9b3a9f7 465
a9d61e9e 466 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
dfd00c4c
SG		 467 reg = 0;
468 if (state == STATE_RADIO_IRQ_ON) {
469 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, 1);
470 rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, 1);
471 rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, 1);
472 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, 1);
473 rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, 1);
474 }
b9570b66 475 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
a9d61e9e
HS		 476 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
477
478 if (state == STATE_RADIO_IRQ_OFF) {
479 /*
abc11994 480 * Wait for possibly running tasklets to finish.
a9d61e9e 481 */
abc11994
HS		 482 tasklet_kill(&rt2x00dev->txstatus_tasklet);
483 tasklet_kill(&rt2x00dev->rxdone_tasklet);
484 tasklet_kill(&rt2x00dev->autowake_tasklet);
485 tasklet_kill(&rt2x00dev->tbtt_tasklet);
486 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
a9d61e9e 487 }
a9b3a9f7
ID		 488}
489
e3a896b9
GW		 490static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
491{
492 u32 reg;
493
494 /*
495 * Reset DMA indexes
496 */
b9570b66 497 rt2x00mmio_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
e3a896b9
GW		 498 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
499 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
500 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
501 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
502 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
503 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
504 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
b9570b66 505 rt2x00mmio_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
e3a896b9 506
b9570b66
GJ		 507 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
508 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
e3a896b9 509
872834df 510 if (rt2x00_is_pcie(rt2x00dev) &&
41caa760
GJ		 511 (rt2x00_rt(rt2x00dev, RT3090) ||
512 rt2x00_rt(rt2x00dev, RT3390) ||
513 rt2x00_rt(rt2x00dev, RT3572) ||
514 rt2x00_rt(rt2x00dev, RT3593) ||
2ed71884 515 rt2x00_rt(rt2x00dev, RT5390) ||
41caa760
GJ		 516 rt2x00_rt(rt2x00dev, RT5392) ||
517 rt2x00_rt(rt2x00dev, RT5592))) {
b9570b66 518 rt2x00mmio_register_read(rt2x00dev, AUX_CTRL, &reg);
adde5882
GJ		 519 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
520 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
b9570b66 521 rt2x00mmio_register_write(rt2x00dev, AUX_CTRL, reg);
adde5882 522 }
60687ba7 523
b9570b66 524 rt2x00mmio_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
e3a896b9 525
2a48e8ae 526 reg = 0;
e3a896b9
GW		 527 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
528 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
b9570b66 529 rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
e3a896b9 530
b9570b66 531 rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
e3a896b9
GW		 532
533 return 0;
534}
535
a9b3a9f7
ID		 536static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
537{
e8b461c3
JK		 538 int retval;
539
52b8243b
JK		 540 /* Wait for DMA, ignore error until we initialize queues. */
541 rt2800_wait_wpdma_ready(rt2x00dev);
542
543 if (unlikely(rt2800pci_init_queues(rt2x00dev)))
a9b3a9f7
ID		 544 return -EIO;
545
e8b461c3
JK		 546 retval = rt2800_enable_radio(rt2x00dev);
547 if (retval)
548 return retval;
549
550 /* After resume MCU_BOOT_SIGNAL will trash these. */
b9570b66
GJ		 551 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
552 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
e8b461c3
JK		 553
554 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_RADIO_OFF, 0xff, 0x02);
555 rt2800pci_mcu_status(rt2x00dev, TOKEN_RADIO_OFF);
556
557 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP, 0, 0);
558 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
559
560 return retval;
a9b3a9f7
ID		 561}
562
563static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
564{
7f6e144f
RJH		 565 if (rt2x00_is_soc(rt2x00dev)) {
566 rt2800_disable_radio(rt2x00dev);
b9570b66
GJ		 567 rt2x00mmio_register_write(rt2x00dev, PWR_PIN_CFG, 0);
568 rt2x00mmio_register_write(rt2x00dev, TX_PIN_CFG, 0);
7f6e144f 569 }
a9b3a9f7
ID		 570}
571
572static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
573 enum dev_state state)
574{
a9b3a9f7 575 if (state == STATE_AWAKE) {
09a3311c
JK		 576 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP,
577 0, 0x02);
578 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
7f6e144f 579 } else if (state == STATE_SLEEP) {
b9570b66
GJ		 580 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
581 0xffffffff);
582 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID,
583 0xffffffff);
09a3311c
JK		 584 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_SLEEP,
585 0xff, 0x01);
a9b3a9f7
ID		 586 }
587
588 return 0;
589}
590
591static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
592 enum dev_state state)
593{
594 int retval = 0;
595
596 switch (state) {
597 case STATE_RADIO_ON:
a9b3a9f7
ID		 598 retval = rt2800pci_enable_radio(rt2x00dev);
599 break;
600 case STATE_RADIO_OFF:
601 /*
602 * After the radio has been disabled, the device should
603 * be put to sleep for powersaving.
604 */
605 rt2800pci_disable_radio(rt2x00dev);
606 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
607 break;
a9b3a9f7
ID		 608 case STATE_RADIO_IRQ_ON:
609 case STATE_RADIO_IRQ_OFF:
610 rt2800pci_toggle_irq(rt2x00dev, state);
611 break;
612 case STATE_DEEP_SLEEP:
613 case STATE_SLEEP:
614 case STATE_STANDBY:
615 case STATE_AWAKE:
616 retval = rt2800pci_set_state(rt2x00dev, state);
617 break;
618 default:
619 retval = -ENOTSUPP;
620 break;
621 }
622
623 if (unlikely(retval))
ec9c4989
JP		 624 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
625 state, retval);
a9b3a9f7
ID		 626
627 return retval;
628}
629
a9b3a9f7
ID		 630/*
631 * RX control handlers
632 */
633static void rt2800pci_fill_rxdone(struct queue_entry *entry,
634 struct rxdone_entry_desc *rxdesc)
635{
b9570b66 636 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
a9b3a9f7 637 __le32 *rxd = entry_priv->desc;
2de64dd2
GW		 638 u32 word;
639
640 rt2x00_desc_read(rxd, 3, &word);
641
642 if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
a9b3a9f7
ID		 643 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
644
78b8f3b0
GW		 645 /*
646 * Unfortunately we don't know the cipher type used during
647 * decryption. This prevents us from correct providing
648 * correct statistics through debugfs.
649 */
2de64dd2 650 rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
a9b3a9f7 651
2de64dd2 652 if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
a9b3a9f7
ID		 653 /*
654 * Hardware has stripped IV/EIV data from 802.11 frame during
655 * decryption. Unfortunately the descriptor doesn't contain
656 * any fields with the EIV/IV data either, so they can't
657 * be restored by rt2x00lib.
658 */
659 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
660
a45f369d
GW		 661 /*
662 * The hardware has already checked the Michael Mic and has
663 * stripped it from the frame. Signal this to mac80211.
664 */
665 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
666
a9b3a9f7
ID		 667 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
668 rxdesc->flags |= RX_FLAG_DECRYPTED;
669 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
670 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
671 }
672
2de64dd2 673 if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
a9b3a9f7
ID		 674 rxdesc->dev_flags |= RXDONE_MY_BSS;
675
2de64dd2 676 if (rt2x00_get_field32(word, RXD_W3_L2PAD))
a9b3a9f7 677 rxdesc->dev_flags |= RXDONE_L2PAD;
a9b3a9f7 678
a9b3a9f7 679 /*
2de64dd2 680 * Process the RXWI structure that is at the start of the buffer.
a9b3a9f7 681 */
74861922 682 rt2800_process_rxwi(entry, rxdesc);
a9b3a9f7
ID		 683}
684
685/*
686 * Interrupt functions.
687 */
4d66edc8
GW		 688static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
689{
690 struct ieee80211_conf conf = { .flags = 0 };
691 struct rt2x00lib_conf libconf = { .conf = &conf };
692
693 rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
694}
695
8857d6dc
HS		 696static bool rt2800pci_txdone_entry_check(struct queue_entry *entry, u32 status)
697{
698 __le32 *txwi;
699 u32 word;
700 int wcid, tx_wcid;
701
702 wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID);
703
704 txwi = rt2800_drv_get_txwi(entry);
705 rt2x00_desc_read(txwi, 1, &word);
706 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
707
708 return (tx_wcid == wcid);
709}
710
711static bool rt2800pci_txdone_find_entry(struct queue_entry *entry, void *data)
712{
713 u32 status = *(u32 *)data;
714
715 /*
716 * rt2800pci hardware might reorder frames when exchanging traffic
717 * with multiple BA enabled STAs.
718 *
719 * For example, a tx queue
720 * [ STA1 | STA2 | STA1 | STA2 ]
721 * can result in tx status reports
722 * [ STA1 | STA1 | STA2 | STA2 ]
723 * when the hw decides to aggregate the frames for STA1 into one AMPDU.
724 *
725 * To mitigate this effect, associate the tx status to the first frame
726 * in the tx queue with a matching wcid.
727 */
728 if (rt2800pci_txdone_entry_check(entry, status) &&
729 !test_bit(ENTRY_DATA_STATUS_SET, &entry->flags)) {
730 /*
731 * Got a matching frame, associate the tx status with
732 * the frame
733 */
734 entry->status = status;
735 set_bit(ENTRY_DATA_STATUS_SET, &entry->flags);
736 return true;
737 }
738
739 /* Check the next frame */
740 return false;
741}
742
743static bool rt2800pci_txdone_match_first(struct queue_entry *entry, void *data)
744{
745 u32 status = *(u32 *)data;
746
747 /*
748 * Find the first frame without tx status and assign this status to it
749 * regardless if it matches or not.
750 */
751 if (!test_bit(ENTRY_DATA_STATUS_SET, &entry->flags)) {
752 /*
753 * Got a matching frame, associate the tx status with
754 * the frame
755 */
756 entry->status = status;
757 set_bit(ENTRY_DATA_STATUS_SET, &entry->flags);
758 return true;
759 }
760
761 /* Check the next frame */
762 return false;
763}
764static bool rt2800pci_txdone_release_entries(struct queue_entry *entry,
765 void *data)
766{
767 if (test_bit(ENTRY_DATA_STATUS_SET, &entry->flags)) {
768 rt2800_txdone_entry(entry, entry->status,
45c67550 769 rt2800mmio_get_txwi(entry));
8857d6dc
HS		 770 return false;
771 }
772
773 /* No more frames to release */
774 return true;
775}
776
2e7798b7 777static bool rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
96c3da7d
HS		 778{
779 struct data_queue *queue;
96c3da7d
HS		 780 u32 status;
781 u8 qid;
2e7798b7 782 int max_tx_done = 16;
96c3da7d 783
c4d63244 784 while (kfifo_get(&rt2x00dev->txstatus_fifo, &status)) {
12eec2cc 785 qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
87443e87 786 if (unlikely(qid >= QID_RX)) {
96c3da7d
HS		 787 /*
788 * Unknown queue, this shouldn't happen. Just drop
789 * this tx status.
790 */
ec9c4989
JP		 791 rt2x00_warn(rt2x00dev, "Got TX status report with unexpected pid %u, dropping\n",
792 qid);
96c3da7d
HS		 793 break;
794 }
795
11f818e0 796 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
96c3da7d
HS		 797 if (unlikely(queue == NULL)) {
798 /*
799 * The queue is NULL, this shouldn't happen. Stop
800 * processing here and drop the tx status
801 */
ec9c4989
JP		 802 rt2x00_warn(rt2x00dev, "Got TX status for an unavailable queue %u, dropping\n",
803 qid);
96c3da7d
HS		 804 break;
805 }
806
87443e87 807 if (unlikely(rt2x00queue_empty(queue))) {
96c3da7d
HS		 808 /*
809 * The queue is empty. Stop processing here
810 * and drop the tx status.
811 */
ec9c4989
JP		 812 rt2x00_warn(rt2x00dev, "Got TX status for an empty queue %u, dropping\n",
813 qid);
96c3da7d
HS		 814 break;
815 }
816
8857d6dc
HS		 817 /*
818 * Let's associate this tx status with the first
819 * matching frame.
820 */
821 if (!rt2x00queue_for_each_entry(queue, Q_INDEX_DONE,
822 Q_INDEX, &status,
823 rt2800pci_txdone_find_entry)) {
824 /*
825 * We cannot match the tx status to any frame, so just
826 * use the first one.
827 */
828 if (!rt2x00queue_for_each_entry(queue, Q_INDEX_DONE,
829 Q_INDEX, &status,
830 rt2800pci_txdone_match_first)) {
ec9c4989
JP		 831 rt2x00_warn(rt2x00dev, "No frame found for TX status on queue %u, dropping\n",
832 qid);
8857d6dc
HS		 833 break;
834 }
835 }
836
837 /*
838 * Release all frames with a valid tx status.
839 */
840 rt2x00queue_for_each_entry(queue, Q_INDEX_DONE,
841 Q_INDEX, NULL,
842 rt2800pci_txdone_release_entries);
2e7798b7
HS		 843
844 if (--max_tx_done == 0)
845 break;
96c3da7d 846 }
2e7798b7
HS		 847
848 return !max_tx_done;
96c3da7d
HS		 849}
850
7a5a681a
HS		 851static inline void rt2800pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
852 struct rt2x00_field32 irq_field)
a9b3a9f7 853{
a9d61e9e 854 u32 reg;
a9b3a9f7
ID		 855
856 /*
a9d61e9e
HS		 857 * Enable a single interrupt. The interrupt mask register
858 * access needs locking.
9f926fb5 859 */
0aa13b2e 860 spin_lock_irq(&rt2x00dev->irqmask_lock);
b9570b66 861 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, &reg);
a9d61e9e 862 rt2x00_set_field32(&reg, irq_field, 1);
b9570b66 863 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
0aa13b2e 864 spin_unlock_irq(&rt2x00dev->irqmask_lock);
a9d61e9e 865}
9f926fb5 866
a9d61e9e
HS		 867static void rt2800pci_txstatus_tasklet(unsigned long data)
868{
2e7798b7
HS		 869 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
870 if (rt2800pci_txdone(rt2x00dev))
871 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
9f926fb5
HS		 872
873 /*
a9d61e9e
HS		 874 * No need to enable the tx status interrupt here as we always
875 * leave it enabled to minimize the possibility of a tx status
876 * register overflow. See comment in interrupt handler.
a9b3a9f7 877 */
a9d61e9e 878}
a9b3a9f7 879
a9d61e9e
HS		 880static void rt2800pci_pretbtt_tasklet(unsigned long data)
881{
882 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
883 rt2x00lib_pretbtt(rt2x00dev);
abc11994
HS		 884 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
885 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_PRE_TBTT);
a9d61e9e 886}
4d66edc8 887
a9d61e9e
HS		 888static void rt2800pci_tbtt_tasklet(unsigned long data)
889{
890 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
290d6089
HS		 891 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
892 u32 reg;
893
a9d61e9e 894 rt2x00lib_beacondone(rt2x00dev);
290d6089
HS		 895
896 if (rt2x00dev->intf_ap_count) {
897 /*
898 * The rt2800pci hardware tbtt timer is off by 1us per tbtt
899 * causing beacon skew and as a result causing problems with
900 * some powersaving clients over time. Shorten the beacon
901 * interval every 64 beacons by 64us to mitigate this effect.
902 */
903 if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 2)) {
b9570b66 904 rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
290d6089
HS		 905 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
906 (rt2x00dev->beacon_int * 16) - 1);
b9570b66 907 rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
290d6089 908 } else if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 1)) {
b9570b66 909 rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
290d6089
HS		 910 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
911 (rt2x00dev->beacon_int * 16));
b9570b66 912 rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
290d6089
HS		 913 }
914 drv_data->tbtt_tick++;
915 drv_data->tbtt_tick %= BCN_TBTT_OFFSET;
916 }
917
abc11994
HS		 918 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
919 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TBTT);
a9d61e9e 920}
78e256c9 921
a9d61e9e
HS		 922static void rt2800pci_rxdone_tasklet(unsigned long data)
923{
924 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
b9570b66 925 if (rt2x00mmio_rxdone(rt2x00dev))
16638937 926 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
abc11994 927 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
16638937 928 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RX_DONE);
a9d61e9e
HS		 929}
930
931static void rt2800pci_autowake_tasklet(unsigned long data)
932{
933 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
934 rt2800pci_wakeup(rt2x00dev);
abc11994
HS		 935 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
936 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_AUTO_WAKEUP);
a9b3a9f7
ID		 937}
938
96c3da7d
HS		 939static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
940{
941 u32 status;
942 int i;
943
944 /*
945 * The TX_FIFO_STATUS interrupt needs special care. We should
946 * read TX_STA_FIFO but we should do it immediately as otherwise
947 * the register can overflow and we would lose status reports.
948 *
949 * Hence, read the TX_STA_FIFO register and copy all tx status
950 * reports into a kernel FIFO which is handled in the txstatus
951 * tasklet. We use a tasklet to process the tx status reports
952 * because we can schedule the tasklet multiple times (when the
953 * interrupt fires again during tx status processing).
954 *
955 * Furthermore we don't disable the TX_FIFO_STATUS
956 * interrupt here but leave it enabled so that the TX_STA_FIFO
3736fe58 957 * can also be read while the tx status tasklet gets executed.
96c3da7d
HS		 958 *
959 * Since we have only one producer and one consumer we don't
960 * need to lock the kfifo.
961 */
1cfcbe4c 962 for (i = 0; i < rt2x00dev->tx->limit; i++) {
b9570b66 963 rt2x00mmio_register_read(rt2x00dev, TX_STA_FIFO, &status);
96c3da7d
HS		 964
965 if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
966 break;
967
c4d63244 968 if (!kfifo_put(&rt2x00dev->txstatus_fifo, &status)) {
ec9c4989 969 rt2x00_warn(rt2x00dev, "TX status FIFO overrun, drop tx status report\n");
96c3da7d
HS		 970 break;
971 }
972 }
973
974 /* Schedule the tasklet for processing the tx status. */
975 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
976}
977
78e256c9
HS		 978static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
979{
980 struct rt2x00_dev *rt2x00dev = dev_instance;
a9d61e9e 981 u32 reg, mask;
78e256c9
HS		 982
983 /* Read status and ACK all interrupts */
b9570b66
GJ		 984 rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
985 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
78e256c9
HS		 986
987 if (!reg)
988 return IRQ_NONE;
989
990 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
991 return IRQ_HANDLED;
992
a9d61e9e
HS		 993 /*
994 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
995 * for interrupts and interrupt masks we can just use the value of
996 * INT_SOURCE_CSR to create the interrupt mask.
997 */
998 mask = ~reg;
78e256c9 999
a9d61e9e
HS		 1000 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) {
1001 rt2800pci_txstatus_interrupt(rt2x00dev);
96c3da7d 1002 /*
a9d61e9e 1003 * Never disable the TX_FIFO_STATUS interrupt.
96c3da7d 1004 */
a9d61e9e
HS		 1005 rt2x00_set_field32(&mask, INT_MASK_CSR_TX_FIFO_STATUS, 1);
1006 }
96c3da7d 1007
a9d61e9e
HS		 1008 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
1009 tasklet_hi_schedule(&rt2x00dev->pretbtt_tasklet);
78e256c9 1010
a9d61e9e
HS		 1011 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
1012 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
96c3da7d 1013
a9d61e9e
HS		 1014 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
1015 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
78e256c9 1016
a9d61e9e
HS		 1017 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
1018 tasklet_schedule(&rt2x00dev->autowake_tasklet);
1019
1020 /*
1021 * Disable all interrupts for which a tasklet was scheduled right now,
1022 * the tasklet will reenable the appropriate interrupts.
1023 */
0aa13b2e 1024 spin_lock(&rt2x00dev->irqmask_lock);
b9570b66 1025 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, &reg);
a9d61e9e 1026 reg &= mask;
b9570b66 1027 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
0aa13b2e 1028 spin_unlock(&rt2x00dev->irqmask_lock);
a9d61e9e
HS		 1029
1030 return IRQ_HANDLED;
78e256c9
HS		 1031}
1032
a9b3a9f7
ID		 1033/*
1034 * Device probe functions.
1035 */
a02308e9 1036static int rt2800pci_read_eeprom(struct rt2x00_dev *rt2x00dev)
7ab71325 1037{
a02308e9
GJ		 1038 int retval;
1039
cea90e55 1040 if (rt2x00_is_soc(rt2x00dev))
a02308e9 1041 retval = rt2800pci_read_eeprom_soc(rt2x00dev);
cea90e55 1042 else if (rt2800pci_efuse_detect(rt2x00dev))
a02308e9 1043 retval = rt2800pci_read_eeprom_efuse(rt2x00dev);
cea90e55 1044 else
a02308e9
GJ		 1045 retval = rt2800pci_read_eeprom_pci(rt2x00dev);
1046
1047 return retval;
a9b3a9f7
ID		 1048}
1049
e783619e
HS		 1050static const struct ieee80211_ops rt2800pci_mac80211_ops = {
1051 .tx = rt2x00mac_tx,
1052 .start = rt2x00mac_start,
1053 .stop = rt2x00mac_stop,
1054 .add_interface = rt2x00mac_add_interface,
1055 .remove_interface = rt2x00mac_remove_interface,
1056 .config = rt2x00mac_config,
1057 .configure_filter = rt2x00mac_configure_filter,
e783619e
HS		 1058 .set_key = rt2x00mac_set_key,
1059 .sw_scan_start = rt2x00mac_sw_scan_start,
1060 .sw_scan_complete = rt2x00mac_sw_scan_complete,
1061 .get_stats = rt2x00mac_get_stats,
1062 .get_tkip_seq = rt2800_get_tkip_seq,
1063 .set_rts_threshold = rt2800_set_rts_threshold,
a2b1328a
HS		 1064 .sta_add = rt2x00mac_sta_add,
1065 .sta_remove = rt2x00mac_sta_remove,
e783619e
HS		 1066 .bss_info_changed = rt2x00mac_bss_info_changed,
1067 .conf_tx = rt2800_conf_tx,
1068 .get_tsf = rt2800_get_tsf,
1069 .rfkill_poll = rt2x00mac_rfkill_poll,
1070 .ampdu_action = rt2800_ampdu_action,
f44df18c 1071 .flush = rt2x00mac_flush,
977206d7 1072 .get_survey = rt2800_get_survey,
e7dee444 1073 .get_ringparam = rt2x00mac_get_ringparam,
5f0dd296 1074 .tx_frames_pending = rt2x00mac_tx_frames_pending,
e783619e
HS		 1075};
1076
e796643e 1077static const struct rt2800_ops rt2800pci_rt2800_ops = {
b9570b66
GJ		 1078 .register_read = rt2x00mmio_register_read,
1079 .register_read_lock = rt2x00mmio_register_read, /* same for PCI */
1080 .register_write = rt2x00mmio_register_write,
1081 .register_write_lock = rt2x00mmio_register_write, /* same for PCI */
1082 .register_multiread = rt2x00mmio_register_multiread,
1083 .register_multiwrite = rt2x00mmio_register_multiwrite,
1084 .regbusy_read = rt2x00mmio_regbusy_read,
ad417a53
GW		 1085 .read_eeprom = rt2800pci_read_eeprom,
1086 .hwcrypt_disabled = rt2800pci_hwcrypt_disabled,
e796643e
ID		 1087 .drv_write_firmware = rt2800pci_write_firmware,
1088 .drv_init_registers = rt2800pci_init_registers,
45c67550 1089 .drv_get_txwi = rt2800mmio_get_txwi,
e796643e
ID		 1090};
1091
a9b3a9f7
ID		 1092static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1093 .irq_handler = rt2800pci_interrupt,
a9d61e9e
HS		 1094 .txstatus_tasklet = rt2800pci_txstatus_tasklet,
1095 .pretbtt_tasklet = rt2800pci_pretbtt_tasklet,
1096 .tbtt_tasklet = rt2800pci_tbtt_tasklet,
1097 .rxdone_tasklet = rt2800pci_rxdone_tasklet,
1098 .autowake_tasklet = rt2800pci_autowake_tasklet,
ad417a53 1099 .probe_hw = rt2800_probe_hw,
a9b3a9f7 1100 .get_firmware_name = rt2800pci_get_firmware_name,
f31c9a8c
ID		 1101 .check_firmware = rt2800_check_firmware,
1102 .load_firmware = rt2800_load_firmware,
b9570b66
GJ		 1103 .initialize = rt2x00mmio_initialize,
1104 .uninitialize = rt2x00mmio_uninitialize,
a9b3a9f7
ID		 1105 .get_entry_state = rt2800pci_get_entry_state,
1106 .clear_entry = rt2800pci_clear_entry,
1107 .set_device_state = rt2800pci_set_device_state,
f4450616
BZ		 1108 .rfkill_poll = rt2800_rfkill_poll,
1109 .link_stats = rt2800_link_stats,
1110 .reset_tuner = rt2800_reset_tuner,
1111 .link_tuner = rt2800_link_tuner,
9e33a355 1112 .gain_calibration = rt2800_gain_calibration,
2e9c43dd 1113 .vco_calibration = rt2800_vco_calibration,
dbba306f
ID		 1114 .start_queue = rt2800pci_start_queue,
1115 .kick_queue = rt2800pci_kick_queue,
1116 .stop_queue = rt2800pci_stop_queue,
b9570b66 1117 .flush_queue = rt2x00mmio_flush_queue,
45c67550 1118 .write_tx_desc = rt2800mmio_write_tx_desc,
0c5879bc 1119 .write_tx_data = rt2800_write_tx_data,
f0194b2d 1120 .write_beacon = rt2800_write_beacon,
69cf36a4 1121 .clear_beacon = rt2800_clear_beacon,
a9b3a9f7 1122 .fill_rxdone = rt2800pci_fill_rxdone,
f4450616
BZ		 1123 .config_shared_key = rt2800_config_shared_key,
1124 .config_pairwise_key = rt2800_config_pairwise_key,
1125 .config_filter = rt2800_config_filter,
1126 .config_intf = rt2800_config_intf,
1127 .config_erp = rt2800_config_erp,
1128 .config_ant = rt2800_config_ant,
1129 .config = rt2800_config,
a2b1328a
HS		 1130 .sta_add = rt2800_sta_add,
1131 .sta_remove = rt2800_sta_remove,
a9b3a9f7
ID		 1132};
1133
1896b760
GJ		 1134static void rt2800pci_queue_init(struct data_queue *queue)
1135{
ae1b1c5d
GJ		 1136 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1137 unsigned short txwi_size, rxwi_size;
1138
1139 rt2800_get_txwi_rxwi_size(rt2x00dev, &txwi_size, &rxwi_size);
1140
1896b760
GJ		 1141 switch (queue->qid) {
1142 case QID_RX:
1143 queue->limit = 128;
1144 queue->data_size = AGGREGATION_SIZE;
1145 queue->desc_size = RXD_DESC_SIZE;
ae1b1c5d 1146 queue->winfo_size = rxwi_size;
1896b760
GJ		 1147 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1148 break;
a9b3a9f7 1149
1896b760
GJ		 1150 case QID_AC_VO:
1151 case QID_AC_VI:
1152 case QID_AC_BE:
1153 case QID_AC_BK:
1154 queue->limit = 64;
1155 queue->data_size = AGGREGATION_SIZE;
1156 queue->desc_size = TXD_DESC_SIZE;
ae1b1c5d 1157 queue->winfo_size = txwi_size;
1896b760
GJ		 1158 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1159 break;
a9b3a9f7 1160
1896b760
GJ		 1161 case QID_BEACON:
1162 queue->limit = 8;
1163 queue->data_size = 0; /* No DMA required for beacons */
1164 queue->desc_size = TXD_DESC_SIZE;
ae1b1c5d 1165 queue->winfo_size = txwi_size;
1896b760
GJ		 1166 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1167 break;
1168
1169 case QID_ATIM:
1170 /* fallthrough */
1171 default:
1172 BUG();
1173 break;
1174 }
1175}
a9b3a9f7
ID		 1176
1177static const struct rt2x00_ops rt2800pci_ops = {
04d0362e 1178 .name = KBUILD_MODNAME,
3a1c0128 1179 .drv_data_size = sizeof(struct rt2800_drv_data),
04d0362e
GW		 1180 .max_ap_intf = 8,
1181 .eeprom_size = EEPROM_SIZE,
1182 .rf_size = RF_SIZE,
1183 .tx_queues = NUM_TX_QUEUES,
1896b760 1184 .queue_init = rt2800pci_queue_init,
04d0362e 1185 .lib = &rt2800pci_rt2x00_ops,
e796643e 1186 .drv = &rt2800pci_rt2800_ops,
e783619e 1187 .hw = &rt2800pci_mac80211_ops,
a9b3a9f7 1188#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 1189 .debugfs = &rt2800_rt2x00debug,
a9b3a9f7
ID		 1190#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1191};
1192
1193/*
1194 * RT2800pci module information.
1195 */
72c7296e 1196#ifdef CONFIG_PCI
a3aa1884 1197static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
e01ae27f
GW		 1198 { PCI_DEVICE(0x1814, 0x0601) },
1199 { PCI_DEVICE(0x1814, 0x0681) },
1200 { PCI_DEVICE(0x1814, 0x0701) },
1201 { PCI_DEVICE(0x1814, 0x0781) },
1202 { PCI_DEVICE(0x1814, 0x3090) },
1203 { PCI_DEVICE(0x1814, 0x3091) },
1204 { PCI_DEVICE(0x1814, 0x3092) },
1205 { PCI_DEVICE(0x1432, 0x7708) },
1206 { PCI_DEVICE(0x1432, 0x7727) },
1207 { PCI_DEVICE(0x1432, 0x7728) },
1208 { PCI_DEVICE(0x1432, 0x7738) },
1209 { PCI_DEVICE(0x1432, 0x7748) },
1210 { PCI_DEVICE(0x1432, 0x7758) },
1211 { PCI_DEVICE(0x1432, 0x7768) },
1212 { PCI_DEVICE(0x1462, 0x891a) },
1213 { PCI_DEVICE(0x1a3b, 0x1059) },
a89534ed
WH		 1214#ifdef CONFIG_RT2800PCI_RT3290
1215 { PCI_DEVICE(0x1814, 0x3290) },
1216#endif
f93bc9b3 1217#ifdef CONFIG_RT2800PCI_RT33XX
e01ae27f 1218 { PCI_DEVICE(0x1814, 0x3390) },
f93bc9b3 1219#endif
de1ebdce 1220#ifdef CONFIG_RT2800PCI_RT35XX
e01ae27f
GW		 1221 { PCI_DEVICE(0x1432, 0x7711) },
1222 { PCI_DEVICE(0x1432, 0x7722) },
1223 { PCI_DEVICE(0x1814, 0x3060) },
1224 { PCI_DEVICE(0x1814, 0x3062) },
1225 { PCI_DEVICE(0x1814, 0x3562) },
1226 { PCI_DEVICE(0x1814, 0x3592) },
1227 { PCI_DEVICE(0x1814, 0x3593) },
c4806014 1228 { PCI_DEVICE(0x1814, 0x359f) },
60687ba7
RST		 1229#endif
1230#ifdef CONFIG_RT2800PCI_RT53XX
ccf91bd6 1231 { PCI_DEVICE(0x1814, 0x5360) },
f57d7b6c 1232 { PCI_DEVICE(0x1814, 0x5362) },
e01ae27f 1233 { PCI_DEVICE(0x1814, 0x5390) },
f57d7b6c 1234 { PCI_DEVICE(0x1814, 0x5392) },
5126d97e 1235 { PCI_DEVICE(0x1814, 0x539a) },
2aed6915 1236 { PCI_DEVICE(0x1814, 0x539b) },
71e0b38c 1237 { PCI_DEVICE(0x1814, 0x539f) },
de1ebdce 1238#endif
a9b3a9f7
ID		 1239 { 0, }
1240};
72c7296e 1241#endif /* CONFIG_PCI */
a9b3a9f7
ID		 1242
1243MODULE_AUTHOR(DRV_PROJECT);
1244MODULE_VERSION(DRV_VERSION);
1245MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1246MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
72c7296e 1247#ifdef CONFIG_PCI
a9b3a9f7
ID		 1248MODULE_FIRMWARE(FIRMWARE_RT2860);
1249MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
72c7296e 1250#endif /* CONFIG_PCI */
a9b3a9f7
ID		 1251MODULE_LICENSE("GPL");
1252
5818a46a 1253#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
714fa663
GW		 1254static int rt2800soc_probe(struct platform_device *pdev)
1255{
6e93d719 1256 return rt2x00soc_probe(pdev, &rt2800pci_ops);
714fa663 1257}
a9b3a9f7
ID		 1258
1259static struct platform_driver rt2800soc_driver = {
1260 .driver = {
1261 .name = "rt2800_wmac",
1262 .owner = THIS_MODULE,
1263 .mod_name = KBUILD_MODNAME,
1264 },
714fa663 1265 .probe = rt2800soc_probe,
69202359 1266 .remove = rt2x00soc_remove,
a9b3a9f7
ID		 1267 .suspend = rt2x00soc_suspend,
1268 .resume = rt2x00soc_resume,
1269};
5818a46a 1270#endif /* CONFIG_SOC_RT288X || CONFIG_SOC_RT305X */
a9b3a9f7 1271
72c7296e 1272#ifdef CONFIG_PCI
e01ae27f
GW		 1273static int rt2800pci_probe(struct pci_dev *pci_dev,
1274 const struct pci_device_id *id)
1275{
1276 return rt2x00pci_probe(pci_dev, &rt2800pci_ops);
1277}
1278
a9b3a9f7
ID		 1279static struct pci_driver rt2800pci_driver = {
1280 .name = KBUILD_MODNAME,
1281 .id_table = rt2800pci_device_table,
e01ae27f 1282 .probe = rt2800pci_probe,
69202359 1283 .remove = rt2x00pci_remove,
a9b3a9f7
ID		 1284 .suspend = rt2x00pci_suspend,
1285 .resume = rt2x00pci_resume,
1286};
72c7296e 1287#endif /* CONFIG_PCI */
a9b3a9f7
ID		 1288
1289static int __init rt2800pci_init(void)
1290{
1291 int ret = 0;
1292
5818a46a 1293#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
a9b3a9f7
ID		 1294 ret = platform_driver_register(&rt2800soc_driver);
1295 if (ret)
1296 return ret;
1297#endif
72c7296e 1298#ifdef CONFIG_PCI
a9b3a9f7
ID		 1299 ret = pci_register_driver(&rt2800pci_driver);
1300 if (ret) {
5818a46a 1301#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
a9b3a9f7
ID		 1302 platform_driver_unregister(&rt2800soc_driver);
1303#endif
1304 return ret;
1305 }
1306#endif
1307
1308 return ret;
1309}
1310
1311static void __exit rt2800pci_exit(void)
1312{
72c7296e 1313#ifdef CONFIG_PCI
a9b3a9f7
ID		 1314 pci_unregister_driver(&rt2800pci_driver);
1315#endif
5818a46a 1316#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
a9b3a9f7
ID		 1317 platform_driver_unregister(&rt2800soc_driver);
1318#endif
1319}
1320
1321module_init(rt2800pci_init);
1322module_exit(rt2800pci_exit);
Linux kernel - Deliverables
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