projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
rt2x00: Request TXWI pointer from driver
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2800pci.c
CommitLineData
a9b3a9f7 1/*
9c9a0d14
GW		 2 Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
a9b3a9f7
ID		 10 <http://rt2x00.serialmonkey.com>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 */
27
28/*
29 Module: rt2800pci
30 Abstract: rt2800pci device specific routines.
31 Supported chipsets: RT2800E & RT2800ED.
32 */
33
a9b3a9f7
ID		 34#include <linux/delay.h>
35#include <linux/etherdevice.h>
36#include <linux/init.h>
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/pci.h>
40#include <linux/platform_device.h>
41#include <linux/eeprom_93cx6.h>
42
43#include "rt2x00.h"
44#include "rt2x00pci.h"
45#include "rt2x00soc.h"
7ef5cc92 46#include "rt2800lib.h"
b54f78a8 47#include "rt2800.h"
a9b3a9f7
ID		 48#include "rt2800pci.h"
49
a9b3a9f7
ID		 50/*
51 * Allow hardware encryption to be disabled.
52 */
04f1e34d 53static int modparam_nohwcrypt = 0;
a9b3a9f7
ID		 54module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
55MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
56
a9b3a9f7
ID		 57static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
58{
59 unsigned int i;
60 u32 reg;
61
f18d4463
LC		 62 /*
63 * SOC devices don't support MCU requests.
64 */
65 if (rt2x00_is_soc(rt2x00dev))
66 return;
67
a9b3a9f7 68 for (i = 0; i < 200; i++) {
9ca21eb7 69 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
a9b3a9f7
ID		 70
71 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
72 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
73 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
74 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
75 break;
76
77 udelay(REGISTER_BUSY_DELAY);
78 }
79
80 if (i == 200)
81 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
82
9ca21eb7
BZ		 83 rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
84 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
a9b3a9f7
ID		 85}
86
00e23ce2 87#ifdef CONFIG_RT2800PCI_SOC
a9b3a9f7
ID		 88static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
89{
90 u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */
91
92 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
93}
94#else
95static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
96{
97}
00e23ce2 98#endif /* CONFIG_RT2800PCI_SOC */
a9b3a9f7
ID		 99
100#ifdef CONFIG_RT2800PCI_PCI
101static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
102{
103 struct rt2x00_dev *rt2x00dev = eeprom->data;
104 u32 reg;
105
9ca21eb7 106 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 107
108 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
109 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
110 eeprom->reg_data_clock =
111 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
112 eeprom->reg_chip_select =
113 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
114}
115
116static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
117{
118 struct rt2x00_dev *rt2x00dev = eeprom->data;
119 u32 reg = 0;
120
121 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
122 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
123 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
124 !!eeprom->reg_data_clock);
125 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
126 !!eeprom->reg_chip_select);
127
9ca21eb7 128 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
a9b3a9f7
ID		 129}
130
131static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
132{
133 struct eeprom_93cx6 eeprom;
134 u32 reg;
135
9ca21eb7 136 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 137
138 eeprom.data = rt2x00dev;
139 eeprom.register_read = rt2800pci_eepromregister_read;
140 eeprom.register_write = rt2800pci_eepromregister_write;
20f8b139
GW		 141 switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
142 {
143 case 0:
144 eeprom.width = PCI_EEPROM_WIDTH_93C46;
145 break;
146 case 1:
147 eeprom.width = PCI_EEPROM_WIDTH_93C66;
148 break;
149 default:
150 eeprom.width = PCI_EEPROM_WIDTH_93C86;
151 break;
152 }
a9b3a9f7
ID		 153 eeprom.reg_data_in = 0;
154 eeprom.reg_data_out = 0;
155 eeprom.reg_data_clock = 0;
156 eeprom.reg_chip_select = 0;
157
158 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
159 EEPROM_SIZE / sizeof(u16));
160}
161
a6598682
GW		 162static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
163{
30e84034 164 return rt2800_efuse_detect(rt2x00dev);
a9b3a9f7
ID		 165}
166
30e84034 167static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 168{
30e84034 169 rt2800_read_eeprom_efuse(rt2x00dev);
a9b3a9f7
ID		 170}
171#else
172static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
173{
174}
175
a6598682
GW		 176static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
177{
178 return 0;
179}
180
a9b3a9f7
ID		 181static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
182{
183}
184#endif /* CONFIG_RT2800PCI_PCI */
185
a9b3a9f7
ID		 186/*
187 * Firmware functions
188 */
189static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
190{
191 return FIRMWARE_RT2860;
192}
193
f31c9a8c 194static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
a9b3a9f7
ID		 195 const u8 *data, const size_t len)
196{
a9b3a9f7
ID		 197 u32 reg;
198
9ca21eb7 199 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
a9b3a9f7 200
a9b3a9f7
ID		 201 /*
202 * enable Host program ram write selection
203 */
204 reg = 0;
205 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
9ca21eb7 206 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
a9b3a9f7
ID		 207
208 /*
209 * Write firmware to device.
210 */
4f2732ce 211 rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
f31c9a8c 212 data, len);
a9b3a9f7 213
9ca21eb7
BZ		 214 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
215 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
a9b3a9f7 216
9ca21eb7
BZ		 217 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
218 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
a9b3a9f7
ID		 219
220 return 0;
221}
222
223/*
224 * Initialization functions.
225 */
226static bool rt2800pci_get_entry_state(struct queue_entry *entry)
227{
228 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
229 u32 word;
230
231 if (entry->queue->qid == QID_RX) {
232 rt2x00_desc_read(entry_priv->desc, 1, &word);
233
234 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
235 } else {
236 rt2x00_desc_read(entry_priv->desc, 1, &word);
237
238 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
239 }
240}
241
242static void rt2800pci_clear_entry(struct queue_entry *entry)
243{
244 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
245 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
246 u32 word;
247
248 if (entry->queue->qid == QID_RX) {
249 rt2x00_desc_read(entry_priv->desc, 0, &word);
250 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
251 rt2x00_desc_write(entry_priv->desc, 0, word);
252
253 rt2x00_desc_read(entry_priv->desc, 1, &word);
254 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
255 rt2x00_desc_write(entry_priv->desc, 1, word);
256 } else {
257 rt2x00_desc_read(entry_priv->desc, 1, &word);
258 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
259 rt2x00_desc_write(entry_priv->desc, 1, word);
260 }
261}
262
263static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
264{
265 struct queue_entry_priv_pci *entry_priv;
266 u32 reg;
267
a9b3a9f7
ID		 268 /*
269 * Initialize registers.
270 */
271 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
9ca21eb7
BZ		 272 rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
273 rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
274 rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
275 rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
a9b3a9f7
ID		 276
277 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
9ca21eb7
BZ		 278 rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
279 rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
280 rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
281 rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
a9b3a9f7
ID		 282
283 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
9ca21eb7
BZ		 284 rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
285 rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
286 rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
287 rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
a9b3a9f7
ID		 288
289 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
9ca21eb7
BZ		 290 rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
291 rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
292 rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
293 rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
a9b3a9f7
ID		 294
295 entry_priv = rt2x00dev->rx->entries[0].priv_data;
9ca21eb7
BZ		 296 rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
297 rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
298 rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
299 rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
a9b3a9f7
ID		 300
301 /*
302 * Enable global DMA configuration
303 */
9ca21eb7 304 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 305 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
306 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
307 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 308 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7 309
9ca21eb7 310 rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
a9b3a9f7
ID		 311
312 return 0;
313}
314
a9b3a9f7
ID		 315/*
316 * Device state switch handlers.
317 */
318static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
319 enum dev_state state)
320{
321 u32 reg;
322
9ca21eb7 323 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
a9b3a9f7
ID		 324 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
325 (state == STATE_RADIO_RX_ON) ||
326 (state == STATE_RADIO_RX_ON_LINK));
9ca21eb7 327 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
a9b3a9f7
ID		 328}
329
330static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
331 enum dev_state state)
332{
78e256c9
HS		 333 int mask = (state == STATE_RADIO_IRQ_ON) ||
334 (state == STATE_RADIO_IRQ_ON_ISR);
a9b3a9f7
ID		 335 u32 reg;
336
337 /*
338 * When interrupts are being enabled, the interrupt registers
339 * should clear the register to assure a clean state.
340 */
341 if (state == STATE_RADIO_IRQ_ON) {
9ca21eb7
BZ		 342 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
343 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
a9b3a9f7
ID		 344 }
345
9ca21eb7 346 rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
a9b3a9f7
ID		 347 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
348 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
349 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
350 rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
351 rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
352 rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
353 rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
354 rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
355 rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
356 rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
357 rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, mask);
358 rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
359 rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
360 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
361 rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
362 rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
363 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
364 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
9ca21eb7 365 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
a9b3a9f7
ID		 366}
367
e3a896b9
GW		 368static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
369{
370 u32 reg;
371
372 /*
373 * Reset DMA indexes
374 */
375 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
376 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
377 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
378 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
379 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
380 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
381 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
382 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
383 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
384
385 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
386 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
387
388 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
389
390 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
391 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
392 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
393 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
394
395 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
396
397 return 0;
398}
399
a9b3a9f7
ID		 400static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
401{
402 u32 reg;
403 u16 word;
404
405 /*
406 * Initialize all registers.
407 */
67a4c1e2 408 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
a9b3a9f7 409 rt2800pci_init_queues(rt2x00dev) ||
fcf51541 410 rt2800_init_registers(rt2x00dev) ||
67a4c1e2 411 rt2800_wait_wpdma_ready(rt2x00dev) ||
fcf51541
BZ		 412 rt2800_init_bbp(rt2x00dev) ||
413 rt2800_init_rfcsr(rt2x00dev)))
a9b3a9f7
ID		 414 return -EIO;
415
416 /*
417 * Send signal to firmware during boot time.
418 */
532bc2d5 419 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
a9b3a9f7
ID		 420
421 /*
422 * Enable RX.
423 */
9ca21eb7 424 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
a9b3a9f7
ID		 425 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
426 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
9ca21eb7 427 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
a9b3a9f7 428
9ca21eb7 429 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 430 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
431 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
432 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
433 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 434 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7 435
9ca21eb7 436 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
a9b3a9f7
ID		 437 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
438 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
9ca21eb7 439 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
a9b3a9f7
ID		 440
441 /*
442 * Initialize LED control
443 */
444 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
3a9e5b0f 445 rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
a9b3a9f7
ID		 446 word & 0xff, (word >> 8) & 0xff);
447
448 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
3a9e5b0f 449 rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
a9b3a9f7
ID		 450 word & 0xff, (word >> 8) & 0xff);
451
452 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
3a9e5b0f 453 rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
a9b3a9f7
ID		 454 word & 0xff, (word >> 8) & 0xff);
455
456 return 0;
457}
458
459static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
460{
461 u32 reg;
462
9ca21eb7 463 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 464 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
465 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
466 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
467 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
468 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 469 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7 470
9ca21eb7
BZ		 471 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
472 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
473 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
a9b3a9f7 474
9ca21eb7 475 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
a9b3a9f7 476
9ca21eb7 477 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
a9b3a9f7
ID		 478 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
479 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
480 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
481 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
482 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
483 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
484 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
9ca21eb7 485 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
a9b3a9f7 486
9ca21eb7
BZ		 487 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
488 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
a9b3a9f7
ID		 489
490 /* Wait for DMA, ignore error */
67a4c1e2 491 rt2800_wait_wpdma_ready(rt2x00dev);
a9b3a9f7
ID		 492}
493
494static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
495 enum dev_state state)
496{
497 /*
498 * Always put the device to sleep (even when we intend to wakeup!)
499 * if the device is booting and wasn't asleep it will return
500 * failure when attempting to wakeup.
501 */
3a9e5b0f 502 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
a9b3a9f7
ID		 503
504 if (state == STATE_AWAKE) {
3a9e5b0f 505 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
a9b3a9f7
ID		 506 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
507 }
508
509 return 0;
510}
511
512static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
513 enum dev_state state)
514{
515 int retval = 0;
516
517 switch (state) {
518 case STATE_RADIO_ON:
519 /*
520 * Before the radio can be enabled, the device first has
521 * to be woken up. After that it needs a bit of time
522 * to be fully awake and then the radio can be enabled.
523 */
524 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
525 msleep(1);
526 retval = rt2800pci_enable_radio(rt2x00dev);
527 break;
528 case STATE_RADIO_OFF:
529 /*
530 * After the radio has been disabled, the device should
531 * be put to sleep for powersaving.
532 */
533 rt2800pci_disable_radio(rt2x00dev);
534 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
535 break;
536 case STATE_RADIO_RX_ON:
537 case STATE_RADIO_RX_ON_LINK:
538 case STATE_RADIO_RX_OFF:
539 case STATE_RADIO_RX_OFF_LINK:
540 rt2800pci_toggle_rx(rt2x00dev, state);
541 break;
542 case STATE_RADIO_IRQ_ON:
78e256c9 543 case STATE_RADIO_IRQ_ON_ISR:
a9b3a9f7 544 case STATE_RADIO_IRQ_OFF:
78e256c9 545 case STATE_RADIO_IRQ_OFF_ISR:
a9b3a9f7
ID		 546 rt2800pci_toggle_irq(rt2x00dev, state);
547 break;
548 case STATE_DEEP_SLEEP:
549 case STATE_SLEEP:
550 case STATE_STANDBY:
551 case STATE_AWAKE:
552 retval = rt2800pci_set_state(rt2x00dev, state);
553 break;
554 default:
555 retval = -ENOTSUPP;
556 break;
557 }
558
559 if (unlikely(retval))
560 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
561 state, retval);
562
563 return retval;
564}
565
566/*
567 * TX descriptor initialization
568 */
0c5879bc 569static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)
a9b3a9f7 570{
0c5879bc 571 return (__le32 *) entry->skb->data;
745b1ae3
HS		 572}
573
745b1ae3
HS		 574static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
575 struct sk_buff *skb,
576 struct txentry_desc *txdesc)
577{
578 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
85b7a8b3
GW		 579 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
580 __le32 *txd = entry_priv->desc;
745b1ae3
HS		 581 u32 word;
582
a9b3a9f7
ID		 583 /*
584 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
585 * must contains a TXWI structure + 802.11 header + padding + 802.11
586 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
587 * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
588 * data. It means that LAST_SEC0 is always 0.
589 */
590
591 /*
592 * Initialize TX descriptor
593 */
594 rt2x00_desc_read(txd, 0, &word);
595 rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
596 rt2x00_desc_write(txd, 0, word);
597
598 rt2x00_desc_read(txd, 1, &word);
599 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
600 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
601 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
602 rt2x00_set_field32(&word, TXD_W1_BURST,
603 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
85b7a8b3 604 rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
a9b3a9f7
ID		 605 rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
606 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
607 rt2x00_desc_write(txd, 1, word);
608
609 rt2x00_desc_read(txd, 2, &word);
610 rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
85b7a8b3 611 skbdesc->skb_dma + TXWI_DESC_SIZE);
a9b3a9f7
ID		 612 rt2x00_desc_write(txd, 2, word);
613
614 rt2x00_desc_read(txd, 3, &word);
615 rt2x00_set_field32(&word, TXD_W3_WIV,
616 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
617 rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
618 rt2x00_desc_write(txd, 3, word);
85b7a8b3
GW		 619
620 /*
621 * Register descriptor details in skb frame descriptor.
622 */
623 skbdesc->desc = txd;
624 skbdesc->desc_len = TXD_DESC_SIZE;
a9b3a9f7
ID		 625}
626
627/*
628 * TX data initialization
629 */
a9b3a9f7
ID		 630static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
631 const enum data_queue_qid queue_idx)
632{
633 struct data_queue *queue;
634 unsigned int idx, qidx = 0;
a9b3a9f7
ID		 635
636 if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
637 return;
638
639 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
640 idx = queue->index[Q_INDEX];
641
642 if (queue_idx == QID_MGMT)
643 qidx = 5;
644 else
645 qidx = queue_idx;
646
9ca21eb7 647 rt2800_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
a9b3a9f7
ID		 648}
649
650static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
651 const enum data_queue_qid qid)
652{
653 u32 reg;
654
655 if (qid == QID_BEACON) {
9ca21eb7 656 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, 0);
a9b3a9f7
ID		 657 return;
658 }
659
9ca21eb7 660 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
a9b3a9f7
ID		 661 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
662 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
663 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
664 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
9ca21eb7 665 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
a9b3a9f7
ID		 666}
667
668/*
669 * RX control handlers
670 */
671static void rt2800pci_fill_rxdone(struct queue_entry *entry,
672 struct rxdone_entry_desc *rxdesc)
673{
674 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
a9b3a9f7
ID		 675 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
676 __le32 *rxd = entry_priv->desc;
2de64dd2
GW		 677 u32 word;
678
679 rt2x00_desc_read(rxd, 3, &word);
680
681 if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
a9b3a9f7
ID		 682 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
683
78b8f3b0
GW		 684 /*
685 * Unfortunately we don't know the cipher type used during
686 * decryption. This prevents us from correct providing
687 * correct statistics through debugfs.
688 */
2de64dd2 689 rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
a9b3a9f7 690
2de64dd2 691 if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
a9b3a9f7
ID		 692 /*
693 * Hardware has stripped IV/EIV data from 802.11 frame during
694 * decryption. Unfortunately the descriptor doesn't contain
695 * any fields with the EIV/IV data either, so they can't
696 * be restored by rt2x00lib.
697 */
698 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
699
700 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
701 rxdesc->flags |= RX_FLAG_DECRYPTED;
702 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
703 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
704 }
705
2de64dd2 706 if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
a9b3a9f7
ID		 707 rxdesc->dev_flags |= RXDONE_MY_BSS;
708
2de64dd2 709 if (rt2x00_get_field32(word, RXD_W3_L2PAD))
a9b3a9f7 710 rxdesc->dev_flags |= RXDONE_L2PAD;
a9b3a9f7 711
a9b3a9f7 712 /*
2de64dd2 713 * Process the RXWI structure that is at the start of the buffer.
a9b3a9f7 714 */
74861922 715 rt2800_process_rxwi(entry, rxdesc);
a9b3a9f7
ID		 716
717 /*
718 * Set RX IDX in register to inform hardware that we have handled
719 * this entry and it is available for reuse again.
720 */
9ca21eb7 721 rt2800_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
a9b3a9f7
ID		 722}
723
724/*
725 * Interrupt functions.
726 */
727static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
728{
729 struct data_queue *queue;
730 struct queue_entry *entry;
632dd959 731 __le32 *txwi;
a9b3a9f7
ID		 732 struct txdone_entry_desc txdesc;
733 u32 word;
734 u32 reg;
632dd959 735 int wcid, ack, pid, tx_wcid, tx_ack, tx_pid;
a9b3a9f7 736 u16 mcs, real_mcs;
3afa626a 737 int i;
a9b3a9f7
ID		 738
739 /*
3afa626a
HS		 740 * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
741 * at most X times and also stop processing once the TX_STA_FIFO_VALID
742 * flag is not set anymore.
743 *
744 * The legacy drivers use X=TX_RING_SIZE but state in a comment
745 * that the TX_STA_FIFO stack has a size of 16. We stick to our
746 * tx ring size for now.
a9b3a9f7 747 */
3afa626a 748 for (i = 0; i < TX_ENTRIES; i++) {
9ca21eb7 749 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
a9b3a9f7
ID		 750 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
751 break;
752
632dd959
AB		 753 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
754 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
755 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
756
a9b3a9f7
ID		 757 /*
758 * Skip this entry when it contains an invalid
759 * queue identication number.
760 */
632dd959 761 if (pid <= 0 || pid > QID_RX)
a9b3a9f7
ID		 762 continue;
763
632dd959 764 queue = rt2x00queue_get_queue(rt2x00dev, pid - 1);
a9b3a9f7
ID		 765 if (unlikely(!queue))
766 continue;
767
768 /*
632dd959
AB		 769 * Inside each queue, we process each entry in a chronological
770 * order. We first check that the queue is not empty.
a9b3a9f7 771 */
632dd959 772 if (rt2x00queue_empty(queue))
a9b3a9f7 773 continue;
632dd959 774 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
a9b3a9f7 775
632dd959
AB		 776 /* Check if we got a match by looking at WCID/ACK/PID
777 * fields */
0b8004aa 778 txwi = (__le32 *) entry->skb->data;
632dd959
AB		 779
780 rt2x00_desc_read(txwi, 1, &word);
781 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
782 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK);
783 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID);
784
785 if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid))
786 WARNING(rt2x00dev, "invalid TX_STA_FIFO content\n");
a9b3a9f7
ID		 787
788 /*
789 * Obtain the status about this packet.
790 */
791 txdesc.flags = 0;
bf18723d
AB		 792 rt2x00_desc_read(txwi, 0, &word);
793 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
794 real_mcs = rt2x00_get_field32(reg, TX_STA_FIFO_MCS);
a9b3a9f7
ID		 795
796 /*
797 * Ralink has a retry mechanism using a global fallback
bf18723d
AB		 798 * table. We setup this fallback table to try the immediate
799 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
800 * always contains the MCS used for the last transmission, be
801 * it successful or not.
a9b3a9f7 802 */
bf18723d
AB		 803 if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS)) {
804 /*
805 * Transmission succeeded. The number of retries is
806 * mcs - real_mcs
807 */
808 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
809 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
810 } else {
811 /*
812 * Transmission failed. The number of retries is
813 * always 7 in this case (for a total number of 8
814 * frames sent).
815 */
816 __set_bit(TXDONE_FAILURE, &txdesc.flags);
817 txdesc.retry = 7;
818 }
819
ecb7cab5
HS		 820 /*
821 * the frame was retried at least once
822 * -> hw used fallback rates
823 */
824 if (txdesc.retry)
825 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
a9b3a9f7 826
e513a0b6 827 rt2x00lib_txdone(entry, &txdesc);
a9b3a9f7
ID		 828 }
829}
830
4d66edc8
GW		 831static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
832{
833 struct ieee80211_conf conf = { .flags = 0 };
834 struct rt2x00lib_conf libconf = { .conf = &conf };
835
836 rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
837}
838
78e256c9 839static irqreturn_t rt2800pci_interrupt_thread(int irq, void *dev_instance)
a9b3a9f7
ID		 840{
841 struct rt2x00_dev *rt2x00dev = dev_instance;
78e256c9 842 u32 reg = rt2x00dev->irqvalue[0];
a9b3a9f7
ID		 843
844 /*
9f926fb5
HS		 845 * 1 - Pre TBTT interrupt.
846 */
847 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
848 rt2x00lib_pretbtt(rt2x00dev);
849
850 /*
851 * 2 - Beacondone interrupt.
852 */
853 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
854 rt2x00lib_beacondone(rt2x00dev);
855
856 /*
857 * 3 - Rx ring done interrupt.
a9b3a9f7
ID		 858 */
859 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
860 rt2x00pci_rxdone(rt2x00dev);
861
9f926fb5
HS		 862 /*
863 * 4 - Tx done interrupt.
864 */
a9b3a9f7
ID		 865 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
866 rt2800pci_txdone(rt2x00dev);
867
ad90319b 868 /*
9f926fb5 869 * 5 - Auto wakeup interrupt.
ad90319b 870 */
4d66edc8
GW		 871 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
872 rt2800pci_wakeup(rt2x00dev);
873
78e256c9
HS		 874 /* Enable interrupts again. */
875 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
876 STATE_RADIO_IRQ_ON_ISR);
877
a9b3a9f7
ID		 878 return IRQ_HANDLED;
879}
880
78e256c9
HS		 881static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
882{
883 struct rt2x00_dev *rt2x00dev = dev_instance;
884 u32 reg;
885
886 /* Read status and ACK all interrupts */
887 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
888 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
889
890 if (!reg)
891 return IRQ_NONE;
892
893 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
894 return IRQ_HANDLED;
895
896 /* Store irqvalue for use in the interrupt thread. */
897 rt2x00dev->irqvalue[0] = reg;
898
899 /* Disable interrupts, will be enabled again in the interrupt thread. */
900 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
901 STATE_RADIO_IRQ_OFF_ISR);
902
903
904 return IRQ_WAKE_THREAD;
905}
906
a9b3a9f7
ID		 907/*
908 * Device probe functions.
909 */
7ab71325
BZ		 910static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
911{
912 /*
913 * Read EEPROM into buffer
914 */
cea90e55 915 if (rt2x00_is_soc(rt2x00dev))
7ab71325 916 rt2800pci_read_eeprom_soc(rt2x00dev);
cea90e55
GW		 917 else if (rt2800pci_efuse_detect(rt2x00dev))
918 rt2800pci_read_eeprom_efuse(rt2x00dev);
919 else
920 rt2800pci_read_eeprom_pci(rt2x00dev);
7ab71325
BZ		 921
922 return rt2800_validate_eeprom(rt2x00dev);
923}
924
a9b3a9f7
ID		 925static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
926{
927 int retval;
928
929 /*
930 * Allocate eeprom data.
931 */
932 retval = rt2800pci_validate_eeprom(rt2x00dev);
933 if (retval)
934 return retval;
935
38bd7b8a 936 retval = rt2800_init_eeprom(rt2x00dev);
a9b3a9f7
ID		 937 if (retval)
938 return retval;
939
940 /*
941 * Initialize hw specifications.
942 */
4da2933f 943 retval = rt2800_probe_hw_mode(rt2x00dev);
a9b3a9f7
ID		 944 if (retval)
945 return retval;
946
947 /*
948 * This device has multiple filters for control frames
949 * and has a separate filter for PS Poll frames.
950 */
951 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
952 __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
953
9f926fb5
HS		 954 /*
955 * This device has a pre tbtt interrupt and thus fetches
956 * a new beacon directly prior to transmission.
957 */
958 __set_bit(DRIVER_SUPPORT_PRE_TBTT_INTERRUPT, &rt2x00dev->flags);
959
a9b3a9f7
ID		 960 /*
961 * This device requires firmware.
962 */
cea90e55 963 if (!rt2x00_is_soc(rt2x00dev))
a9b3a9f7
ID		 964 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
965 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
966 __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
967 if (!modparam_nohwcrypt)
968 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
27df2a9c 969 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
a9b3a9f7
ID		 970
971 /*
972 * Set the rssi offset.
973 */
974 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
975
976 return 0;
977}
978
e783619e
HS		 979static const struct ieee80211_ops rt2800pci_mac80211_ops = {
980 .tx = rt2x00mac_tx,
981 .start = rt2x00mac_start,
982 .stop = rt2x00mac_stop,
983 .add_interface = rt2x00mac_add_interface,
984 .remove_interface = rt2x00mac_remove_interface,
985 .config = rt2x00mac_config,
986 .configure_filter = rt2x00mac_configure_filter,
e783619e
HS		 987 .set_key = rt2x00mac_set_key,
988 .sw_scan_start = rt2x00mac_sw_scan_start,
989 .sw_scan_complete = rt2x00mac_sw_scan_complete,
990 .get_stats = rt2x00mac_get_stats,
991 .get_tkip_seq = rt2800_get_tkip_seq,
992 .set_rts_threshold = rt2800_set_rts_threshold,
993 .bss_info_changed = rt2x00mac_bss_info_changed,
994 .conf_tx = rt2800_conf_tx,
995 .get_tsf = rt2800_get_tsf,
996 .rfkill_poll = rt2x00mac_rfkill_poll,
997 .ampdu_action = rt2800_ampdu_action,
998};
999
e796643e
ID		 1000static const struct rt2800_ops rt2800pci_rt2800_ops = {
1001 .register_read = rt2x00pci_register_read,
1002 .register_read_lock = rt2x00pci_register_read, /* same for PCI */
1003 .register_write = rt2x00pci_register_write,
1004 .register_write_lock = rt2x00pci_register_write, /* same for PCI */
1005 .register_multiread = rt2x00pci_register_multiread,
1006 .register_multiwrite = rt2x00pci_register_multiwrite,
1007 .regbusy_read = rt2x00pci_regbusy_read,
1008 .drv_write_firmware = rt2800pci_write_firmware,
1009 .drv_init_registers = rt2800pci_init_registers,
0c5879bc 1010 .drv_get_txwi = rt2800pci_get_txwi,
e796643e
ID		 1011};
1012
a9b3a9f7
ID		 1013static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1014 .irq_handler = rt2800pci_interrupt,
78e256c9 1015 .irq_handler_thread = rt2800pci_interrupt_thread,
a9b3a9f7
ID		 1016 .probe_hw = rt2800pci_probe_hw,
1017 .get_firmware_name = rt2800pci_get_firmware_name,
f31c9a8c
ID		 1018 .check_firmware = rt2800_check_firmware,
1019 .load_firmware = rt2800_load_firmware,
a9b3a9f7
ID		 1020 .initialize = rt2x00pci_initialize,
1021 .uninitialize = rt2x00pci_uninitialize,
1022 .get_entry_state = rt2800pci_get_entry_state,
1023 .clear_entry = rt2800pci_clear_entry,
1024 .set_device_state = rt2800pci_set_device_state,
f4450616
BZ		 1025 .rfkill_poll = rt2800_rfkill_poll,
1026 .link_stats = rt2800_link_stats,
1027 .reset_tuner = rt2800_reset_tuner,
1028 .link_tuner = rt2800_link_tuner,
a9b3a9f7 1029 .write_tx_desc = rt2800pci_write_tx_desc,
0c5879bc 1030 .write_tx_data = rt2800_write_tx_data,
f0194b2d 1031 .write_beacon = rt2800_write_beacon,
a9b3a9f7
ID		 1032 .kick_tx_queue = rt2800pci_kick_tx_queue,
1033 .kill_tx_queue = rt2800pci_kill_tx_queue,
1034 .fill_rxdone = rt2800pci_fill_rxdone,
f4450616
BZ		 1035 .config_shared_key = rt2800_config_shared_key,
1036 .config_pairwise_key = rt2800_config_pairwise_key,
1037 .config_filter = rt2800_config_filter,
1038 .config_intf = rt2800_config_intf,
1039 .config_erp = rt2800_config_erp,
1040 .config_ant = rt2800_config_ant,
1041 .config = rt2800_config,
a9b3a9f7
ID		 1042};
1043
1044static const struct data_queue_desc rt2800pci_queue_rx = {
1045 .entry_num = RX_ENTRIES,
1046 .data_size = AGGREGATION_SIZE,
1047 .desc_size = RXD_DESC_SIZE,
1048 .priv_size = sizeof(struct queue_entry_priv_pci),
1049};
1050
1051static const struct data_queue_desc rt2800pci_queue_tx = {
1052 .entry_num = TX_ENTRIES,
1053 .data_size = AGGREGATION_SIZE,
1054 .desc_size = TXD_DESC_SIZE,
1055 .priv_size = sizeof(struct queue_entry_priv_pci),
1056};
1057
1058static const struct data_queue_desc rt2800pci_queue_bcn = {
1059 .entry_num = 8 * BEACON_ENTRIES,
1060 .data_size = 0, /* No DMA required for beacons */
1061 .desc_size = TXWI_DESC_SIZE,
1062 .priv_size = sizeof(struct queue_entry_priv_pci),
1063};
1064
1065static const struct rt2x00_ops rt2800pci_ops = {
04d0362e
GW		 1066 .name = KBUILD_MODNAME,
1067 .max_sta_intf = 1,
1068 .max_ap_intf = 8,
1069 .eeprom_size = EEPROM_SIZE,
1070 .rf_size = RF_SIZE,
1071 .tx_queues = NUM_TX_QUEUES,
e6218cc4 1072 .extra_tx_headroom = TXWI_DESC_SIZE,
04d0362e
GW		 1073 .rx = &rt2800pci_queue_rx,
1074 .tx = &rt2800pci_queue_tx,
1075 .bcn = &rt2800pci_queue_bcn,
1076 .lib = &rt2800pci_rt2x00_ops,
e796643e 1077 .drv = &rt2800pci_rt2800_ops,
e783619e 1078 .hw = &rt2800pci_mac80211_ops,
a9b3a9f7 1079#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 1080 .debugfs = &rt2800_rt2x00debug,
a9b3a9f7
ID		 1081#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1082};
1083
1084/*
1085 * RT2800pci module information.
1086 */
d6e36ec1 1087#ifdef CONFIG_RT2800PCI_PCI
a3aa1884 1088static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
de1ebdce
GW		 1089 { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
1090 { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
1091 { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
1092 { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
a9b3a9f7
ID		 1093 { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
1094 { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
1095 { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
1096 { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
1097 { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
1098 { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
1099 { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
de1ebdce
GW		 1100 { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
1101#ifdef CONFIG_RT2800PCI_RT30XX
a9b3a9f7
ID		 1102 { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
1103 { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
1104 { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
de1ebdce
GW		 1105 { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
1106#endif
1107#ifdef CONFIG_RT2800PCI_RT35XX
1108 { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
1109 { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
a9b3a9f7
ID		 1110 { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
1111 { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
6424bf70 1112 { PCI_DEVICE(0x1814, 0x3593), PCI_DEVICE_DATA(&rt2800pci_ops) },
de1ebdce 1113#endif
a9b3a9f7
ID		 1114 { 0, }
1115};
d6e36ec1 1116#endif /* CONFIG_RT2800PCI_PCI */
a9b3a9f7
ID		 1117
1118MODULE_AUTHOR(DRV_PROJECT);
1119MODULE_VERSION(DRV_VERSION);
1120MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1121MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1122#ifdef CONFIG_RT2800PCI_PCI
1123MODULE_FIRMWARE(FIRMWARE_RT2860);
1124MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1125#endif /* CONFIG_RT2800PCI_PCI */
1126MODULE_LICENSE("GPL");
1127
00e23ce2 1128#ifdef CONFIG_RT2800PCI_SOC
714fa663
GW		 1129static int rt2800soc_probe(struct platform_device *pdev)
1130{
6e93d719 1131 return rt2x00soc_probe(pdev, &rt2800pci_ops);
714fa663 1132}
a9b3a9f7
ID		 1133
1134static struct platform_driver rt2800soc_driver = {
1135 .driver = {
1136 .name = "rt2800_wmac",
1137 .owner = THIS_MODULE,
1138 .mod_name = KBUILD_MODNAME,
1139 },
714fa663 1140 .probe = rt2800soc_probe,
a9b3a9f7
ID		 1141 .remove = __devexit_p(rt2x00soc_remove),
1142 .suspend = rt2x00soc_suspend,
1143 .resume = rt2x00soc_resume,
1144};
00e23ce2 1145#endif /* CONFIG_RT2800PCI_SOC */
a9b3a9f7
ID		 1146
1147#ifdef CONFIG_RT2800PCI_PCI
1148static struct pci_driver rt2800pci_driver = {
1149 .name = KBUILD_MODNAME,
1150 .id_table = rt2800pci_device_table,
1151 .probe = rt2x00pci_probe,
1152 .remove = __devexit_p(rt2x00pci_remove),
1153 .suspend = rt2x00pci_suspend,
1154 .resume = rt2x00pci_resume,
1155};
1156#endif /* CONFIG_RT2800PCI_PCI */
1157
1158static int __init rt2800pci_init(void)
1159{
1160 int ret = 0;
1161
00e23ce2 1162#ifdef CONFIG_RT2800PCI_SOC
a9b3a9f7
ID		 1163 ret = platform_driver_register(&rt2800soc_driver);
1164 if (ret)
1165 return ret;
1166#endif
1167#ifdef CONFIG_RT2800PCI_PCI
1168 ret = pci_register_driver(&rt2800pci_driver);
1169 if (ret) {
00e23ce2 1170#ifdef CONFIG_RT2800PCI_SOC
a9b3a9f7
ID		 1171 platform_driver_unregister(&rt2800soc_driver);
1172#endif
1173 return ret;
1174 }
1175#endif
1176
1177 return ret;
1178}
1179
1180static void __exit rt2800pci_exit(void)
1181{
1182#ifdef CONFIG_RT2800PCI_PCI
1183 pci_unregister_driver(&rt2800pci_driver);
1184#endif
00e23ce2 1185#ifdef CONFIG_RT2800PCI_SOC
a9b3a9f7
ID		 1186 platform_driver_unregister(&rt2800soc_driver);
1187#endif
1188}
1189
1190module_init(rt2800pci_init);
1191module_exit(rt2800pci_exit);
Linux kernel - Deliverables
This page took 0.205018 seconds and 5 git commands to generate.