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rt2x00: move REGISTER_BUSY_* definitions to rt2x00.h
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2800pci.c
CommitLineData
a9b3a9f7
ID		 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2800pci
23 Abstract: rt2800pci device specific routines.
24 Supported chipsets: RT2800E & RT2800ED.
25 */
26
27#include <linux/crc-ccitt.h>
28#include <linux/delay.h>
29#include <linux/etherdevice.h>
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/pci.h>
34#include <linux/platform_device.h>
35#include <linux/eeprom_93cx6.h>
36
37#include "rt2x00.h"
38#include "rt2x00pci.h"
39#include "rt2x00soc.h"
7ef5cc92 40#include "rt2800lib.h"
b54f78a8 41#include "rt2800.h"
a9b3a9f7
ID		 42#include "rt2800pci.h"
43
44#ifdef CONFIG_RT2800PCI_PCI_MODULE
45#define CONFIG_RT2800PCI_PCI
46#endif
47
48#ifdef CONFIG_RT2800PCI_WISOC_MODULE
49#define CONFIG_RT2800PCI_WISOC
50#endif
51
52/*
53 * Allow hardware encryption to be disabled.
54 */
55static int modparam_nohwcrypt = 1;
56module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
57MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
58
a9b3a9f7
ID		 59static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
60{
61 unsigned int i;
62 u32 reg;
63
64 for (i = 0; i < 200; i++) {
9ca21eb7 65 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
a9b3a9f7
ID		 66
67 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
68 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
69 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
70 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
71 break;
72
73 udelay(REGISTER_BUSY_DELAY);
74 }
75
76 if (i == 200)
77 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
78
9ca21eb7
BZ		 79 rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
80 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
a9b3a9f7
ID		 81}
82
83#ifdef CONFIG_RT2800PCI_WISOC
84static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
85{
86 u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */
87
88 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
89}
90#else
91static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
92{
93}
94#endif /* CONFIG_RT2800PCI_WISOC */
95
96#ifdef CONFIG_RT2800PCI_PCI
97static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
98{
99 struct rt2x00_dev *rt2x00dev = eeprom->data;
100 u32 reg;
101
9ca21eb7 102 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 103
104 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
105 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
106 eeprom->reg_data_clock =
107 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
108 eeprom->reg_chip_select =
109 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
110}
111
112static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
113{
114 struct rt2x00_dev *rt2x00dev = eeprom->data;
115 u32 reg = 0;
116
117 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
118 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
119 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
120 !!eeprom->reg_data_clock);
121 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
122 !!eeprom->reg_chip_select);
123
9ca21eb7 124 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
a9b3a9f7
ID		 125}
126
127static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
128{
129 struct eeprom_93cx6 eeprom;
130 u32 reg;
131
9ca21eb7 132 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 133
134 eeprom.data = rt2x00dev;
135 eeprom.register_read = rt2800pci_eepromregister_read;
136 eeprom.register_write = rt2800pci_eepromregister_write;
137 eeprom.width = !rt2x00_get_field32(reg, E2PROM_CSR_TYPE) ?
138 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
139 eeprom.reg_data_in = 0;
140 eeprom.reg_data_out = 0;
141 eeprom.reg_data_clock = 0;
142 eeprom.reg_chip_select = 0;
143
144 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
145 EEPROM_SIZE / sizeof(u16));
146}
147
148static void rt2800pci_efuse_read(struct rt2x00_dev *rt2x00dev,
149 unsigned int i)
150{
151 u32 reg;
152
9ca21eb7 153 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
a9b3a9f7
ID		 154 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
155 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
156 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
9ca21eb7 157 rt2800_register_write(rt2x00dev, EFUSE_CTRL, reg);
a9b3a9f7
ID		 158
159 /* Wait until the EEPROM has been loaded */
b4a77d0d 160 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
a9b3a9f7
ID		 161
162 /* Apparently the data is read from end to start */
9ca21eb7 163 rt2800_register_read(rt2x00dev, EFUSE_DATA3,
a9b3a9f7 164 (u32 *)&rt2x00dev->eeprom[i]);
9ca21eb7 165 rt2800_register_read(rt2x00dev, EFUSE_DATA2,
a9b3a9f7 166 (u32 *)&rt2x00dev->eeprom[i + 2]);
9ca21eb7 167 rt2800_register_read(rt2x00dev, EFUSE_DATA1,
a9b3a9f7 168 (u32 *)&rt2x00dev->eeprom[i + 4]);
9ca21eb7 169 rt2800_register_read(rt2x00dev, EFUSE_DATA0,
a9b3a9f7
ID		 170 (u32 *)&rt2x00dev->eeprom[i + 6]);
171}
172
173static void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
174{
175 unsigned int i;
176
177 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
178 rt2800pci_efuse_read(rt2x00dev, i);
179}
180#else
181static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
182{
183}
184
185static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
186{
187}
188#endif /* CONFIG_RT2800PCI_PCI */
189
a9b3a9f7
ID		 190/*
191 * Firmware functions
192 */
193static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
194{
195 return FIRMWARE_RT2860;
196}
197
198static int rt2800pci_check_firmware(struct rt2x00_dev *rt2x00dev,
199 const u8 *data, const size_t len)
200{
201 u16 fw_crc;
202 u16 crc;
203
204 /*
205 * Only support 8kb firmware files.
206 */
207 if (len != 8192)
208 return FW_BAD_LENGTH;
209
210 /*
211 * The last 2 bytes in the firmware array are the crc checksum itself,
212 * this means that we should never pass those 2 bytes to the crc
213 * algorithm.
214 */
215 fw_crc = (data[len - 2] << 8 | data[len - 1]);
216
217 /*
218 * Use the crc ccitt algorithm.
219 * This will return the same value as the legacy driver which
220 * used bit ordering reversion on the both the firmware bytes
221 * before input input as well as on the final output.
222 * Obviously using crc ccitt directly is much more efficient.
223 */
224 crc = crc_ccitt(~0, data, len - 2);
225
226 /*
227 * There is a small difference between the crc-itu-t + bitrev and
228 * the crc-ccitt crc calculation. In the latter method the 2 bytes
229 * will be swapped, use swab16 to convert the crc to the correct
230 * value.
231 */
232 crc = swab16(crc);
233
234 return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
235}
236
237static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
238 const u8 *data, const size_t len)
239{
240 unsigned int i;
241 u32 reg;
242
243 /*
244 * Wait for stable hardware.
245 */
246 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9ca21eb7 247 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
a9b3a9f7
ID		 248 if (reg && reg != ~0)
249 break;
250 msleep(1);
251 }
252
253 if (i == REGISTER_BUSY_COUNT) {
254 ERROR(rt2x00dev, "Unstable hardware.\n");
255 return -EBUSY;
256 }
257
9ca21eb7
BZ		 258 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
259 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
a9b3a9f7
ID		 260
261 /*
262 * Disable DMA, will be reenabled later when enabling
263 * the radio.
264 */
9ca21eb7 265 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 266 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
267 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
268 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
269 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
270 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 271 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7
ID		 272
273 /*
274 * enable Host program ram write selection
275 */
276 reg = 0;
277 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
9ca21eb7 278 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
a9b3a9f7
ID		 279
280 /*
281 * Write firmware to device.
282 */
4f2732ce 283 rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
a9b3a9f7
ID		 284 data, len);
285
9ca21eb7
BZ		 286 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
287 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
a9b3a9f7
ID		 288
289 /*
290 * Wait for device to stabilize.
291 */
292 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9ca21eb7 293 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
a9b3a9f7
ID		 294 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
295 break;
296 msleep(1);
297 }
298
299 if (i == REGISTER_BUSY_COUNT) {
300 ERROR(rt2x00dev, "PBF system register not ready.\n");
301 return -EBUSY;
302 }
303
304 /*
305 * Disable interrupts
306 */
307 rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_OFF);
308
309 /*
310 * Initialize BBP R/W access agent
311 */
9ca21eb7
BZ		 312 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
313 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
a9b3a9f7
ID		 314
315 return 0;
316}
317
318/*
319 * Initialization functions.
320 */
321static bool rt2800pci_get_entry_state(struct queue_entry *entry)
322{
323 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
324 u32 word;
325
326 if (entry->queue->qid == QID_RX) {
327 rt2x00_desc_read(entry_priv->desc, 1, &word);
328
329 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
330 } else {
331 rt2x00_desc_read(entry_priv->desc, 1, &word);
332
333 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
334 }
335}
336
337static void rt2800pci_clear_entry(struct queue_entry *entry)
338{
339 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
340 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
341 u32 word;
342
343 if (entry->queue->qid == QID_RX) {
344 rt2x00_desc_read(entry_priv->desc, 0, &word);
345 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
346 rt2x00_desc_write(entry_priv->desc, 0, word);
347
348 rt2x00_desc_read(entry_priv->desc, 1, &word);
349 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
350 rt2x00_desc_write(entry_priv->desc, 1, word);
351 } else {
352 rt2x00_desc_read(entry_priv->desc, 1, &word);
353 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
354 rt2x00_desc_write(entry_priv->desc, 1, word);
355 }
356}
357
358static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
359{
360 struct queue_entry_priv_pci *entry_priv;
361 u32 reg;
362
9ca21eb7 363 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
a9b3a9f7
ID		 364 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
365 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
366 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
367 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
368 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
369 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
370 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
9ca21eb7 371 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
a9b3a9f7 372
9ca21eb7
BZ		 373 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
374 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
a9b3a9f7
ID		 375
376 /*
377 * Initialize registers.
378 */
379 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
9ca21eb7
BZ		 380 rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
381 rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
382 rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
383 rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
a9b3a9f7
ID		 384
385 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
9ca21eb7
BZ		 386 rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
387 rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
388 rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
389 rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
a9b3a9f7
ID		 390
391 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
9ca21eb7
BZ		 392 rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
393 rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
394 rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
395 rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
a9b3a9f7
ID		 396
397 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
9ca21eb7
BZ		 398 rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
399 rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
400 rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
401 rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
a9b3a9f7
ID		 402
403 entry_priv = rt2x00dev->rx->entries[0].priv_data;
9ca21eb7
BZ		 404 rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
405 rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
406 rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
407 rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
a9b3a9f7
ID		 408
409 /*
410 * Enable global DMA configuration
411 */
9ca21eb7 412 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 413 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
414 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
415 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 416 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7 417
9ca21eb7 418 rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
a9b3a9f7
ID		 419
420 return 0;
421}
422
423static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
424{
425 u32 reg;
426 unsigned int i;
427
4d6f8b9f
BZ		 428 if (rt2x00_intf_is_pci(rt2x00dev))
429 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
a9b3a9f7 430
9ca21eb7 431 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
a9b3a9f7
ID		 432 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
433 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
9ca21eb7 434 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
a9b3a9f7 435
9ca21eb7 436 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
a9b3a9f7 437
9ca21eb7 438 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
a9b3a9f7
ID		 439 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
440 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
441 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
442 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
9ca21eb7 443 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
a9b3a9f7 444
9ca21eb7 445 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
a9b3a9f7
ID		 446 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
447 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
448 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
449 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
9ca21eb7 450 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
a9b3a9f7 451
9ca21eb7
BZ		 452 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
453 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
a9b3a9f7 454
9ca21eb7 455 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
a9b3a9f7 456
9ca21eb7 457 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
a9b3a9f7
ID		 458 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
459 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
460 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
461 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
462 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
463 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
9ca21eb7 464 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
a9b3a9f7 465
9ca21eb7
BZ		 466 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
467 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
a9b3a9f7 468
9ca21eb7 469 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
a9b3a9f7
ID		 470 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
471 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
472 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
473 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
474 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
475 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
476 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
477 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
9ca21eb7 478 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
a9b3a9f7 479
9ca21eb7 480 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
a9b3a9f7
ID		 481 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
482 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
9ca21eb7 483 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
a9b3a9f7 484
9ca21eb7 485 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
a9b3a9f7
ID		 486 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
487 if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
488 rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
489 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
490 else
491 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
492 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
493 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
9ca21eb7 494 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
a9b3a9f7 495
9ca21eb7 496 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
a9b3a9f7 497
9ca21eb7 498 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
a9b3a9f7
ID		 499 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
500 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
501 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
502 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
503 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
9ca21eb7 504 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
a9b3a9f7 505
9ca21eb7 506 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9b3a9f7
ID		 507 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
508 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
509 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
510 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
511 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
512 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
513 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
514 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
515 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
9ca21eb7 516 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
a9b3a9f7 517
9ca21eb7 518 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9b3a9f7
ID		 519 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
520 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
521 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
522 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
523 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
524 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
525 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
526 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
527 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
9ca21eb7 528 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
a9b3a9f7 529
9ca21eb7 530 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
a9b3a9f7
ID		 531 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
532 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
533 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
534 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
535 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
536 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
537 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
538 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
539 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
9ca21eb7 540 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
a9b3a9f7 541
9ca21eb7 542 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
a9b3a9f7
ID		 543 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
544 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
545 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
546 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
547 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
548 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
549 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
550 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
551 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
9ca21eb7 552 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
a9b3a9f7 553
9ca21eb7 554 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
a9b3a9f7
ID		 555 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
556 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
557 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
558 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
559 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
560 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
561 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
562 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
563 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
9ca21eb7 564 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
a9b3a9f7 565
9ca21eb7 566 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
a9b3a9f7
ID		 567 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
568 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
569 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
570 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
571 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
572 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
573 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
574 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
575 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
9ca21eb7 576 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
a9b3a9f7 577
9ca21eb7
BZ		 578 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
579 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
a9b3a9f7 580
9ca21eb7 581 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
a9b3a9f7
ID		 582 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
583 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
584 IEEE80211_MAX_RTS_THRESHOLD);
585 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
9ca21eb7 586 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
a9b3a9f7 587
9ca21eb7
BZ		 588 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
589 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
a9b3a9f7
ID		 590
591 /*
592 * ASIC will keep garbage value after boot, clear encryption keys.
593 */
594 for (i = 0; i < 4; i++)
9ca21eb7 595 rt2800_register_write(rt2x00dev,
a9b3a9f7
ID		 596 SHARED_KEY_MODE_ENTRY(i), 0);
597
598 for (i = 0; i < 256; i++) {
599 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
4f2732ce 600 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
a9b3a9f7
ID		 601 wcid, sizeof(wcid));
602
9ca21eb7
BZ		 603 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
604 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
a9b3a9f7
ID		 605 }
606
607 /*
608 * Clear all beacons
609 * For the Beacon base registers we only need to clear
610 * the first byte since that byte contains the VALID and OWNER
611 * bits which (when set to 0) will invalidate the entire beacon.
612 */
9ca21eb7
BZ		 613 rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
614 rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
615 rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
616 rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
617 rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
618 rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
619 rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
620 rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
a9b3a9f7 621
9ca21eb7 622 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
a9b3a9f7
ID		 623 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
624 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
625 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
626 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
627 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
628 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
629 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
630 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
9ca21eb7 631 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
a9b3a9f7 632
9ca21eb7 633 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
a9b3a9f7
ID		 634 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
635 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
636 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
637 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
638 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
639 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
640 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
641 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
9ca21eb7 642 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
a9b3a9f7 643
9ca21eb7 644 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
a9b3a9f7
ID		 645 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
646 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
647 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
648 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
649 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
650 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
651 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
652 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
9ca21eb7 653 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
a9b3a9f7 654
9ca21eb7 655 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
a9b3a9f7
ID		 656 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
657 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
658 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
659 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
9ca21eb7 660 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
a9b3a9f7
ID		 661
662 /*
663 * We must clear the error counters.
664 * These registers are cleared on read,
665 * so we may pass a useless variable to store the value.
666 */
9ca21eb7
BZ		 667 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
668 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
669 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
670 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
671 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
672 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
a9b3a9f7
ID		 673
674 return 0;
675}
676
677static int rt2800pci_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
678{
679 unsigned int i;
680 u32 reg;
681
682 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9ca21eb7 683 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
a9b3a9f7
ID		 684 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
685 return 0;
686
687 udelay(REGISTER_BUSY_DELAY);
688 }
689
690 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
691 return -EACCES;
692}
693
694static int rt2800pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
695{
696 unsigned int i;
697 u8 value;
698
699 /*
700 * BBP was enabled after firmware was loaded,
701 * but we need to reactivate it now.
702 */
9ca21eb7
BZ		 703 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
704 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
a9b3a9f7
ID		 705 msleep(1);
706
707 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3e2c9df7 708 rt2800_bbp_read(rt2x00dev, 0, &value);
a9b3a9f7
ID		 709 if ((value != 0xff) && (value != 0x00))
710 return 0;
711 udelay(REGISTER_BUSY_DELAY);
712 }
713
714 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
715 return -EACCES;
716}
717
718static int rt2800pci_init_bbp(struct rt2x00_dev *rt2x00dev)
719{
720 unsigned int i;
721 u16 eeprom;
722 u8 reg_id;
723 u8 value;
724
725 if (unlikely(rt2800pci_wait_bbp_rf_ready(rt2x00dev) ||
726 rt2800pci_wait_bbp_ready(rt2x00dev)))
727 return -EACCES;
728
3e2c9df7
BZ		 729 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
730 rt2800_bbp_write(rt2x00dev, 66, 0x38);
731 rt2800_bbp_write(rt2x00dev, 69, 0x12);
732 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
733 rt2800_bbp_write(rt2x00dev, 73, 0x10);
734 rt2800_bbp_write(rt2x00dev, 81, 0x37);
735 rt2800_bbp_write(rt2x00dev, 82, 0x62);
736 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
737 rt2800_bbp_write(rt2x00dev, 84, 0x99);
738 rt2800_bbp_write(rt2x00dev, 86, 0x00);
739 rt2800_bbp_write(rt2x00dev, 91, 0x04);
740 rt2800_bbp_write(rt2x00dev, 92, 0x00);
741 rt2800_bbp_write(rt2x00dev, 103, 0x00);
742 rt2800_bbp_write(rt2x00dev, 105, 0x05);
a9b3a9f7
ID		 743
744 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
3e2c9df7
BZ		 745 rt2800_bbp_write(rt2x00dev, 69, 0x16);
746 rt2800_bbp_write(rt2x00dev, 73, 0x12);
a9b3a9f7
ID		 747 }
748
749 if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION)
3e2c9df7 750 rt2800_bbp_write(rt2x00dev, 84, 0x19);
a9b3a9f7 751
4d6f8b9f
BZ		 752 if (rt2x00_intf_is_pci(rt2x00dev) &&
753 rt2x00_rt(&rt2x00dev->chip, RT3052)) {
3e2c9df7
BZ		 754 rt2800_bbp_write(rt2x00dev, 31, 0x08);
755 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
756 rt2800_bbp_write(rt2x00dev, 80, 0x08);
a9b3a9f7
ID		 757 }
758
759 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
760 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
761
762 if (eeprom != 0xffff && eeprom != 0x0000) {
763 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
764 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
3e2c9df7 765 rt2800_bbp_write(rt2x00dev, reg_id, value);
a9b3a9f7
ID		 766 }
767 }
768
769 return 0;
770}
771
772static u8 rt2800pci_init_rx_filter(struct rt2x00_dev *rt2x00dev,
773 bool bw40, u8 rfcsr24, u8 filter_target)
774{
775 unsigned int i;
776 u8 bbp;
777 u8 rfcsr;
778 u8 passband;
779 u8 stopband;
780 u8 overtuned = 0;
781
1af68f75 782 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
a9b3a9f7 783
3e2c9df7 784 rt2800_bbp_read(rt2x00dev, 4, &bbp);
a9b3a9f7 785 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
3e2c9df7 786 rt2800_bbp_write(rt2x00dev, 4, bbp);
a9b3a9f7 787
1af68f75 788 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
a9b3a9f7 789 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1af68f75 790 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
a9b3a9f7
ID		 791
792 /*
793 * Set power & frequency of passband test tone
794 */
3e2c9df7 795 rt2800_bbp_write(rt2x00dev, 24, 0);
a9b3a9f7
ID		 796
797 for (i = 0; i < 100; i++) {
3e2c9df7 798 rt2800_bbp_write(rt2x00dev, 25, 0x90);
a9b3a9f7
ID		 799 msleep(1);
800
3e2c9df7 801 rt2800_bbp_read(rt2x00dev, 55, &passband);
a9b3a9f7
ID		 802 if (passband)
803 break;
804 }
805
806 /*
807 * Set power & frequency of stopband test tone
808 */
3e2c9df7 809 rt2800_bbp_write(rt2x00dev, 24, 0x06);
a9b3a9f7
ID		 810
811 for (i = 0; i < 100; i++) {
3e2c9df7 812 rt2800_bbp_write(rt2x00dev, 25, 0x90);
a9b3a9f7
ID		 813 msleep(1);
814
3e2c9df7 815 rt2800_bbp_read(rt2x00dev, 55, &stopband);
a9b3a9f7
ID		 816
817 if ((passband - stopband) <= filter_target) {
818 rfcsr24++;
819 overtuned += ((passband - stopband) == filter_target);
820 } else
821 break;
822
1af68f75 823 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
a9b3a9f7
ID		 824 }
825
826 rfcsr24 -= !!overtuned;
827
1af68f75 828 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
a9b3a9f7
ID		 829 return rfcsr24;
830}
831
832static int rt2800pci_init_rfcsr(struct rt2x00_dev *rt2x00dev)
833{
834 u8 rfcsr;
835 u8 bbp;
836
4d6f8b9f
BZ		 837 if (rt2x00_intf_is_pci(rt2x00dev)) {
838 if (!rt2x00_rf(&rt2x00dev->chip, RF3020) &&
839 !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
840 !rt2x00_rf(&rt2x00dev->chip, RF3022))
841 return 0;
842 }
a9b3a9f7
ID		 843
844 /*
845 * Init RF calibration.
846 */
1af68f75 847 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
a9b3a9f7 848 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1af68f75 849 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
a9b3a9f7
ID		 850 msleep(1);
851 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1af68f75
BZ		 852 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
853
4d6f8b9f
BZ		 854 if (rt2x00_intf_is_pci(rt2x00dev)) {
855 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
856 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
857 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
858 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
859 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
860 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
861 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
862 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
863 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
864 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
865 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
866 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
867 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
868 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
869 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
870 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
871 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
872 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
873 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
874 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
875 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
876 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
877 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
878 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
879 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
880 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
881 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
882 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
883 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
884 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
885 }
a9b3a9f7
ID		 886
887 /*
888 * Set RX Filter calibration for 20MHz and 40MHz
889 */
890 rt2x00dev->calibration[0] =
891 rt2800pci_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
892 rt2x00dev->calibration[1] =
893 rt2800pci_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
894
895 /*
896 * Set back to initial state
897 */
3e2c9df7 898 rt2800_bbp_write(rt2x00dev, 24, 0);
a9b3a9f7 899
1af68f75 900 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
a9b3a9f7 901 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1af68f75 902 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
a9b3a9f7
ID		 903
904 /*
905 * set BBP back to BW20
906 */
3e2c9df7 907 rt2800_bbp_read(rt2x00dev, 4, &bbp);
a9b3a9f7 908 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
3e2c9df7 909 rt2800_bbp_write(rt2x00dev, 4, bbp);
a9b3a9f7
ID		 910
911 return 0;
912}
913
914/*
915 * Device state switch handlers.
916 */
917static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
918 enum dev_state state)
919{
920 u32 reg;
921
9ca21eb7 922 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
a9b3a9f7
ID		 923 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
924 (state == STATE_RADIO_RX_ON) ||
925 (state == STATE_RADIO_RX_ON_LINK));
9ca21eb7 926 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
a9b3a9f7
ID		 927}
928
929static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
930 enum dev_state state)
931{
932 int mask = (state == STATE_RADIO_IRQ_ON);
933 u32 reg;
934
935 /*
936 * When interrupts are being enabled, the interrupt registers
937 * should clear the register to assure a clean state.
938 */
939 if (state == STATE_RADIO_IRQ_ON) {
9ca21eb7
BZ		 940 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
941 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
a9b3a9f7
ID		 942 }
943
9ca21eb7 944 rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
a9b3a9f7
ID		 945 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
946 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
947 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
948 rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
949 rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
950 rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
951 rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
952 rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
953 rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
954 rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
955 rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, mask);
956 rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
957 rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
958 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
959 rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
960 rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
961 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
962 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
9ca21eb7 963 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
a9b3a9f7
ID		 964}
965
966static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
967{
968 unsigned int i;
969 u32 reg;
970
971 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9ca21eb7 972 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 973 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
974 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
975 return 0;
976
977 msleep(1);
978 }
979
980 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
981 return -EACCES;
982}
983
984static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
985{
986 u32 reg;
987 u16 word;
988
989 /*
990 * Initialize all registers.
991 */
992 if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) ||
993 rt2800pci_init_queues(rt2x00dev) ||
994 rt2800pci_init_registers(rt2x00dev) ||
995 rt2800pci_wait_wpdma_ready(rt2x00dev) ||
996 rt2800pci_init_bbp(rt2x00dev) ||
997 rt2800pci_init_rfcsr(rt2x00dev)))
998 return -EIO;
999
1000 /*
1001 * Send signal to firmware during boot time.
1002 */
3a9e5b0f 1003 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
a9b3a9f7
ID		 1004
1005 /*
1006 * Enable RX.
1007 */
9ca21eb7 1008 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
a9b3a9f7
ID		 1009 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1010 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
9ca21eb7 1011 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
a9b3a9f7 1012
9ca21eb7 1013 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 1014 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
1015 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
1016 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
1017 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 1018 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7 1019
9ca21eb7 1020 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
a9b3a9f7
ID		 1021 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1022 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
9ca21eb7 1023 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
a9b3a9f7
ID		 1024
1025 /*
1026 * Initialize LED control
1027 */
1028 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
3a9e5b0f 1029 rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
a9b3a9f7
ID		 1030 word & 0xff, (word >> 8) & 0xff);
1031
1032 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
3a9e5b0f 1033 rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
a9b3a9f7
ID		 1034 word & 0xff, (word >> 8) & 0xff);
1035
1036 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
3a9e5b0f 1037 rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
a9b3a9f7
ID		 1038 word & 0xff, (word >> 8) & 0xff);
1039
1040 return 0;
1041}
1042
1043static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1044{
1045 u32 reg;
1046
9ca21eb7 1047 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 1048 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1049 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1050 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1051 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1052 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 1053 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7 1054
9ca21eb7
BZ		 1055 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
1056 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
1057 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
a9b3a9f7 1058
9ca21eb7 1059 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
a9b3a9f7 1060
9ca21eb7 1061 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
a9b3a9f7
ID		 1062 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
1063 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
1064 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
1065 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
1066 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
1067 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
1068 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
9ca21eb7 1069 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
a9b3a9f7 1070
9ca21eb7
BZ		 1071 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
1072 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
a9b3a9f7
ID		 1073
1074 /* Wait for DMA, ignore error */
1075 rt2800pci_wait_wpdma_ready(rt2x00dev);
1076}
1077
1078static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
1079 enum dev_state state)
1080{
1081 /*
1082 * Always put the device to sleep (even when we intend to wakeup!)
1083 * if the device is booting and wasn't asleep it will return
1084 * failure when attempting to wakeup.
1085 */
3a9e5b0f 1086 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
a9b3a9f7
ID		 1087
1088 if (state == STATE_AWAKE) {
3a9e5b0f 1089 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
a9b3a9f7
ID		 1090 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
1091 }
1092
1093 return 0;
1094}
1095
1096static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1097 enum dev_state state)
1098{
1099 int retval = 0;
1100
1101 switch (state) {
1102 case STATE_RADIO_ON:
1103 /*
1104 * Before the radio can be enabled, the device first has
1105 * to be woken up. After that it needs a bit of time
1106 * to be fully awake and then the radio can be enabled.
1107 */
1108 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
1109 msleep(1);
1110 retval = rt2800pci_enable_radio(rt2x00dev);
1111 break;
1112 case STATE_RADIO_OFF:
1113 /*
1114 * After the radio has been disabled, the device should
1115 * be put to sleep for powersaving.
1116 */
1117 rt2800pci_disable_radio(rt2x00dev);
1118 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
1119 break;
1120 case STATE_RADIO_RX_ON:
1121 case STATE_RADIO_RX_ON_LINK:
1122 case STATE_RADIO_RX_OFF:
1123 case STATE_RADIO_RX_OFF_LINK:
1124 rt2800pci_toggle_rx(rt2x00dev, state);
1125 break;
1126 case STATE_RADIO_IRQ_ON:
1127 case STATE_RADIO_IRQ_OFF:
1128 rt2800pci_toggle_irq(rt2x00dev, state);
1129 break;
1130 case STATE_DEEP_SLEEP:
1131 case STATE_SLEEP:
1132 case STATE_STANDBY:
1133 case STATE_AWAKE:
1134 retval = rt2800pci_set_state(rt2x00dev, state);
1135 break;
1136 default:
1137 retval = -ENOTSUPP;
1138 break;
1139 }
1140
1141 if (unlikely(retval))
1142 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1143 state, retval);
1144
1145 return retval;
1146}
1147
1148/*
1149 * TX descriptor initialization
1150 */
1151static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1152 struct sk_buff *skb,
1153 struct txentry_desc *txdesc)
1154{
1155 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1156 __le32 *txd = skbdesc->desc;
1157 __le32 *txwi = (__le32 *)(skb->data - rt2x00dev->hw->extra_tx_headroom);
1158 u32 word;
1159
1160 /*
1161 * Initialize TX Info descriptor
1162 */
1163 rt2x00_desc_read(txwi, 0, &word);
1164 rt2x00_set_field32(&word, TXWI_W0_FRAG,
1165 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1166 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
1167 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
1168 rt2x00_set_field32(&word, TXWI_W0_TS,
1169 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1170 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
1171 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
1172 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
1173 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
1174 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
1175 rt2x00_set_field32(&word, TXWI_W0_BW,
1176 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
1177 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
1178 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
1179 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
1180 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
1181 rt2x00_desc_write(txwi, 0, word);
1182
1183 rt2x00_desc_read(txwi, 1, &word);
1184 rt2x00_set_field32(&word, TXWI_W1_ACK,
1185 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1186 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
1187 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1188 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
1189 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
1190 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
f644fea1 1191 txdesc->key_idx : 0xff);
a9b3a9f7
ID		 1192 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
1193 skb->len - txdesc->l2pad);
1194 rt2x00_set_field32(&word, TXWI_W1_PACKETID,
1195 skbdesc->entry->queue->qid + 1);
1196 rt2x00_desc_write(txwi, 1, word);
1197
1198 /*
1199 * Always write 0 to IV/EIV fields, hardware will insert the IV
77dba493
BZ		 1200 * from the IVEIV register when TXD_W3_WIV is set to 0.
1201 * When TXD_W3_WIV is set to 1 it will use the IV data
a9b3a9f7
ID		 1202 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
1203 * crypto entry in the registers should be used to encrypt the frame.
1204 */
1205 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
1206 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
1207
1208 /*
1209 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
1210 * must contains a TXWI structure + 802.11 header + padding + 802.11
1211 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
1212 * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
1213 * data. It means that LAST_SEC0 is always 0.
1214 */
1215
1216 /*
1217 * Initialize TX descriptor
1218 */
1219 rt2x00_desc_read(txd, 0, &word);
1220 rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
1221 rt2x00_desc_write(txd, 0, word);
1222
1223 rt2x00_desc_read(txd, 1, &word);
1224 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
1225 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
1226 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1227 rt2x00_set_field32(&word, TXD_W1_BURST,
1228 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1229 rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
1230 rt2x00dev->hw->extra_tx_headroom);
1231 rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
1232 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
1233 rt2x00_desc_write(txd, 1, word);
1234
1235 rt2x00_desc_read(txd, 2, &word);
1236 rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
1237 skbdesc->skb_dma + rt2x00dev->hw->extra_tx_headroom);
1238 rt2x00_desc_write(txd, 2, word);
1239
1240 rt2x00_desc_read(txd, 3, &word);
1241 rt2x00_set_field32(&word, TXD_W3_WIV,
1242 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
1243 rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
1244 rt2x00_desc_write(txd, 3, word);
1245}
1246
1247/*
1248 * TX data initialization
1249 */
1250static void rt2800pci_write_beacon(struct queue_entry *entry)
1251{
1252 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1253 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1254 unsigned int beacon_base;
1255 u32 reg;
1256
1257 /*
1258 * Disable beaconing while we are reloading the beacon data,
1259 * otherwise we might be sending out invalid data.
1260 */
9ca21eb7 1261 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
a9b3a9f7 1262 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
9ca21eb7 1263 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
a9b3a9f7
ID		 1264
1265 /*
1266 * Write entire beacon with descriptor to register.
1267 */
1268 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
4f2732ce 1269 rt2800_register_multiwrite(rt2x00dev,
a9b3a9f7
ID		 1270 beacon_base,
1271 skbdesc->desc, skbdesc->desc_len);
4f2732ce 1272 rt2800_register_multiwrite(rt2x00dev,
a9b3a9f7
ID		 1273 beacon_base + skbdesc->desc_len,
1274 entry->skb->data, entry->skb->len);
1275
1276 /*
1277 * Clean up beacon skb.
1278 */
1279 dev_kfree_skb_any(entry->skb);
1280 entry->skb = NULL;
1281}
1282
1283static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1284 const enum data_queue_qid queue_idx)
1285{
1286 struct data_queue *queue;
1287 unsigned int idx, qidx = 0;
1288 u32 reg;
1289
1290 if (queue_idx == QID_BEACON) {
9ca21eb7 1291 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
a9b3a9f7
ID		 1292 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
1293 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
1294 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
1295 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
9ca21eb7 1296 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
a9b3a9f7
ID		 1297 }
1298 return;
1299 }
1300
1301 if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
1302 return;
1303
1304 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1305 idx = queue->index[Q_INDEX];
1306
1307 if (queue_idx == QID_MGMT)
1308 qidx = 5;
1309 else
1310 qidx = queue_idx;
1311
9ca21eb7 1312 rt2800_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
a9b3a9f7
ID		 1313}
1314
1315static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
1316 const enum data_queue_qid qid)
1317{
1318 u32 reg;
1319
1320 if (qid == QID_BEACON) {
9ca21eb7 1321 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, 0);
a9b3a9f7
ID		 1322 return;
1323 }
1324
9ca21eb7 1325 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
a9b3a9f7
ID		 1326 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
1327 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
1328 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
1329 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
9ca21eb7 1330 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
a9b3a9f7
ID		 1331}
1332
1333/*
1334 * RX control handlers
1335 */
1336static void rt2800pci_fill_rxdone(struct queue_entry *entry,
1337 struct rxdone_entry_desc *rxdesc)
1338{
1339 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1340 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1341 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1342 __le32 *rxd = entry_priv->desc;
1343 __le32 *rxwi = (__le32 *)entry->skb->data;
1344 u32 rxd3;
1345 u32 rxwi0;
1346 u32 rxwi1;
1347 u32 rxwi2;
1348 u32 rxwi3;
1349
1350 rt2x00_desc_read(rxd, 3, &rxd3);
1351 rt2x00_desc_read(rxwi, 0, &rxwi0);
1352 rt2x00_desc_read(rxwi, 1, &rxwi1);
1353 rt2x00_desc_read(rxwi, 2, &rxwi2);
1354 rt2x00_desc_read(rxwi, 3, &rxwi3);
1355
1356 if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR))
1357 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1358
1359 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1360 /*
1361 * Unfortunately we don't know the cipher type used during
1362 * decryption. This prevents us from correct providing
1363 * correct statistics through debugfs.
1364 */
1365 rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
1366 rxdesc->cipher_status =
1367 rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);
1368 }
1369
1370 if (rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED)) {
1371 /*
1372 * Hardware has stripped IV/EIV data from 802.11 frame during
1373 * decryption. Unfortunately the descriptor doesn't contain
1374 * any fields with the EIV/IV data either, so they can't
1375 * be restored by rt2x00lib.
1376 */
1377 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1378
1379 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1380 rxdesc->flags |= RX_FLAG_DECRYPTED;
1381 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1382 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1383 }
1384
1385 if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS))
1386 rxdesc->dev_flags |= RXDONE_MY_BSS;
1387
1388 if (rt2x00_get_field32(rxd3, RXD_W3_L2PAD)) {
1389 rxdesc->dev_flags |= RXDONE_L2PAD;
1390 skbdesc->flags |= SKBDESC_L2_PADDED;
1391 }
1392
1393 if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
1394 rxdesc->flags |= RX_FLAG_SHORT_GI;
1395
1396 if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
1397 rxdesc->flags |= RX_FLAG_40MHZ;
1398
1399 /*
1400 * Detect RX rate, always use MCS as signal type.
1401 */
1402 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
1403 rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
1404 rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
1405
1406 /*
1407 * Mask of 0x8 bit to remove the short preamble flag.
1408 */
1409 if (rxdesc->rate_mode == RATE_MODE_CCK)
1410 rxdesc->signal &= ~0x8;
1411
1412 rxdesc->rssi =
1413 (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
1414 rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
1415
1416 rxdesc->noise =
1417 (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
1418 rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
1419
1420 rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
1421
1422 /*
1423 * Set RX IDX in register to inform hardware that we have handled
1424 * this entry and it is available for reuse again.
1425 */
9ca21eb7 1426 rt2800_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
a9b3a9f7
ID		 1427
1428 /*
1429 * Remove TXWI descriptor from start of buffer.
1430 */
1431 skb_pull(entry->skb, RXWI_DESC_SIZE);
1432 skb_trim(entry->skb, rxdesc->size);
1433}
1434
1435/*
1436 * Interrupt functions.
1437 */
1438static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
1439{
1440 struct data_queue *queue;
1441 struct queue_entry *entry;
1442 struct queue_entry *entry_done;
1443 struct queue_entry_priv_pci *entry_priv;
1444 struct txdone_entry_desc txdesc;
1445 u32 word;
1446 u32 reg;
1447 u32 old_reg;
1448 unsigned int type;
1449 unsigned int index;
1450 u16 mcs, real_mcs;
1451
1452 /*
1453 * During each loop we will compare the freshly read
1454 * TX_STA_FIFO register value with the value read from
1455 * the previous loop. If the 2 values are equal then
1456 * we should stop processing because the chance it
1457 * quite big that the device has been unplugged and
1458 * we risk going into an endless loop.
1459 */
1460 old_reg = 0;
1461
1462 while (1) {
9ca21eb7 1463 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
a9b3a9f7
ID		 1464 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
1465 break;
1466
1467 if (old_reg == reg)
1468 break;
1469 old_reg = reg;
1470
1471 /*
1472 * Skip this entry when it contains an invalid
1473 * queue identication number.
1474 */
1475 type = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE) - 1;
1476 if (type >= QID_RX)
1477 continue;
1478
1479 queue = rt2x00queue_get_queue(rt2x00dev, type);
1480 if (unlikely(!queue))
1481 continue;
1482
1483 /*
1484 * Skip this entry when it contains an invalid
1485 * index number.
1486 */
1487 index = rt2x00_get_field32(reg, TX_STA_FIFO_WCID) - 1;
1488 if (unlikely(index >= queue->limit))
1489 continue;
1490
1491 entry = &queue->entries[index];
1492 entry_priv = entry->priv_data;
1493 rt2x00_desc_read((__le32 *)entry->skb->data, 0, &word);
1494
1495 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1496 while (entry != entry_done) {
1497 /*
1498 * Catch up.
1499 * Just report any entries we missed as failed.
1500 */
1501 WARNING(rt2x00dev,
1502 "TX status report missed for entry %d\n",
1503 entry_done->entry_idx);
1504
1505 txdesc.flags = 0;
1506 __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
1507 txdesc.retry = 0;
1508
1509 rt2x00lib_txdone(entry_done, &txdesc);
1510 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1511 }
1512
1513 /*
1514 * Obtain the status about this packet.
1515 */
1516 txdesc.flags = 0;
1517 if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS))
1518 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1519 else
1520 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1521
1522 /*
1523 * Ralink has a retry mechanism using a global fallback
1524 * table. We setup this fallback table to try immediate
1525 * lower rate for all rates. In the TX_STA_FIFO,
1526 * the MCS field contains the MCS used for the successfull
1527 * transmission. If the first transmission succeed,
1528 * we have mcs == tx_mcs. On the second transmission,
1529 * we have mcs = tx_mcs - 1. So the number of
1530 * retry is (tx_mcs - mcs).
1531 */
1532 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
1533 real_mcs = rt2x00_get_field32(reg, TX_STA_FIFO_MCS);
1534 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
1535 txdesc.retry = mcs - min(mcs, real_mcs);
1536
1537 rt2x00lib_txdone(entry, &txdesc);
1538 }
1539}
1540
1541static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
1542{
1543 struct rt2x00_dev *rt2x00dev = dev_instance;
1544 u32 reg;
1545
1546 /* Read status and ACK all interrupts */
9ca21eb7
BZ		 1547 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1548 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
a9b3a9f7
ID		 1549
1550 if (!reg)
1551 return IRQ_NONE;
1552
1553 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1554 return IRQ_HANDLED;
1555
1556 /*
1557 * 1 - Rx ring done interrupt.
1558 */
1559 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
1560 rt2x00pci_rxdone(rt2x00dev);
1561
1562 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
1563 rt2800pci_txdone(rt2x00dev);
1564
1565 return IRQ_HANDLED;
1566}
1567
1568/*
1569 * Device probe functions.
1570 */
1571static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1572{
1573 u16 word;
1574 u8 *mac;
1575 u8 default_lna_gain;
1576
1577 /*
1578 * Read EEPROM into buffer
1579 */
1580 switch(rt2x00dev->chip.rt) {
1581 case RT2880:
1582 case RT3052:
1583 rt2800pci_read_eeprom_soc(rt2x00dev);
1584 break;
1585 case RT3090:
1586 rt2800pci_read_eeprom_efuse(rt2x00dev);
1587 break;
1588 default:
1589 rt2800pci_read_eeprom_pci(rt2x00dev);
1590 break;
1591 }
1592
1593 /*
1594 * Start validation of the data that has been read.
1595 */
1596 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1597 if (!is_valid_ether_addr(mac)) {
1598 random_ether_addr(mac);
1599 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1600 }
1601
1602 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1603 if (word == 0xffff) {
1604 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
1605 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
1606 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
1607 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1608 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1609 } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) {
1610 /*
1611 * There is a max of 2 RX streams for RT2860 series
1612 */
1613 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
1614 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
1615 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1616 }
1617
1618 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1619 if (word == 0xffff) {
1620 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
1621 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
1622 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1623 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1624 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1625 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
1626 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
1627 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
1628 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
1629 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
1630 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1631 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1632 }
1633
1634 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1635 if ((word & 0x00ff) == 0x00ff) {
1636 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1637 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
1638 LED_MODE_TXRX_ACTIVITY);
1639 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
1640 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1641 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
1642 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
1643 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
1644 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1645 }
1646
1647 /*
1648 * During the LNA validation we are going to use
1649 * lna0 as correct value. Note that EEPROM_LNA
1650 * is never validated.
1651 */
1652 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
1653 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
1654
1655 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
1656 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
1657 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
1658 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
1659 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
1660 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
1661
1662 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
1663 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
1664 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
1665 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
1666 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
1667 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
1668 default_lna_gain);
1669 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
1670
1671 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
1672 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
1673 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
1674 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
1675 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
1676 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
1677
1678 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
1679 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
1680 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
1681 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
1682 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
1683 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
1684 default_lna_gain);
1685 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
1686
1687 return 0;
1688}
1689
1690static int rt2800pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1691{
1692 u32 reg;
1693 u16 value;
1694 u16 eeprom;
1695
1696 /*
1697 * Read EEPROM word for configuration.
1698 */
1699 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1700
1701 /*
1702 * Identify RF chipset.
1703 */
1704 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
9ca21eb7 1705 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
a9b3a9f7
ID		 1706 rt2x00_set_chip_rf(rt2x00dev, value, reg);
1707
1708 if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
1709 !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
1710 !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
1711 !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
1712 !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
1713 !rt2x00_rf(&rt2x00dev->chip, RF2020) &&
1714 !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
1715 !rt2x00_rf(&rt2x00dev->chip, RF3022)) {
1716 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1717 return -ENODEV;
1718 }
1719
1720 /*
1721 * Identify default antenna configuration.
1722 */
1723 rt2x00dev->default_ant.tx =
1724 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
1725 rt2x00dev->default_ant.rx =
1726 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
1727
1728 /*
1729 * Read frequency offset and RF programming sequence.
1730 */
1731 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1732 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1733
1734 /*
1735 * Read external LNA informations.
1736 */
1737 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1738
1739 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
1740 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1741 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
1742 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1743
1744 /*
1745 * Detect if this device has an hardware controlled radio.
1746 */
1747 if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
1748 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1749
1750 /*
1751 * Store led settings, for correct led behaviour.
1752 */
1753#ifdef CONFIG_RT2X00_LIB_LEDS
f4450616
BZ		 1754 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1755 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1756 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
a9b3a9f7
ID		 1757
1758 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
1759#endif /* CONFIG_RT2X00_LIB_LEDS */
1760
1761 return 0;
1762}
1763
1764/*
1765 * RF value list for rt2860
1766 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
1767 */
1768static const struct rf_channel rf_vals[] = {
1769 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
1770 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
1771 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
1772 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
1773 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
1774 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
1775 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
1776 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
1777 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
1778 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
1779 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
1780 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
1781 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
1782 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
1783
1784 /* 802.11 UNI / HyperLan 2 */
1785 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
1786 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
1787 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
1788 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
1789 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
1790 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
1791 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
1792 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
1793 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
1794 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
1795 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
1796 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
1797
1798 /* 802.11 HyperLan 2 */
1799 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
1800 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
1801 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
1802 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
1803 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
1804 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
1805 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
1806 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
1807 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
1808 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
1809 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
1810 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
1811 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
1812 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
1813 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
1814 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
1815
1816 /* 802.11 UNII */
1817 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
1818 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
1819 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
1820 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
1821 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
1822 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
1823 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
1824
1825 /* 802.11 Japan */
1826 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
1827 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
1828 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
1829 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
1830 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
1831 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
1832 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
1833};
1834
1835static int rt2800pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1836{
1837 struct hw_mode_spec *spec = &rt2x00dev->spec;
1838 struct channel_info *info;
1839 char *tx_power1;
1840 char *tx_power2;
1841 unsigned int i;
1842 u16 eeprom;
1843
1844 /*
1845 * Initialize all hw fields.
1846 */
1847 rt2x00dev->hw->flags =
1848 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1849 IEEE80211_HW_SIGNAL_DBM |
1850 IEEE80211_HW_SUPPORTS_PS |
1851 IEEE80211_HW_PS_NULLFUNC_STACK;
1852 rt2x00dev->hw->extra_tx_headroom = TXWI_DESC_SIZE;
1853
1854 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1855 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1856 rt2x00_eeprom_addr(rt2x00dev,
1857 EEPROM_MAC_ADDR_0));
1858
1859 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1860
1861 /*
1862 * Initialize hw_mode information.
1863 */
1864 spec->supported_bands = SUPPORT_BAND_2GHZ;
1865 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1866
1867 if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
1868 rt2x00_rf(&rt2x00dev->chip, RF2720) ||
1869 rt2x00_rf(&rt2x00dev->chip, RF3020) ||
1870 rt2x00_rf(&rt2x00dev->chip, RF3021) ||
1871 rt2x00_rf(&rt2x00dev->chip, RF3022) ||
1872 rt2x00_rf(&rt2x00dev->chip, RF2020) ||
1873 rt2x00_rf(&rt2x00dev->chip, RF3052)) {
1874 spec->num_channels = 14;
1875 spec->channels = rf_vals;
1876 } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
1877 rt2x00_rf(&rt2x00dev->chip, RF2750)) {
1878 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1879 spec->num_channels = ARRAY_SIZE(rf_vals);
1880 spec->channels = rf_vals;
1881 }
1882
1883 /*
1884 * Initialize HT information.
1885 */
1886 spec->ht.ht_supported = true;
1887 spec->ht.cap =
1888 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
1889 IEEE80211_HT_CAP_GRN_FLD |
1890 IEEE80211_HT_CAP_SGI_20 |
1891 IEEE80211_HT_CAP_SGI_40 |
1892 IEEE80211_HT_CAP_TX_STBC |
1893 IEEE80211_HT_CAP_RX_STBC |
1894 IEEE80211_HT_CAP_PSMP_SUPPORT;
1895 spec->ht.ampdu_factor = 3;
1896 spec->ht.ampdu_density = 4;
1897 spec->ht.mcs.tx_params =
1898 IEEE80211_HT_MCS_TX_DEFINED |
1899 IEEE80211_HT_MCS_TX_RX_DIFF |
1900 ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
1901 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
1902
1903 switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
1904 case 3:
1905 spec->ht.mcs.rx_mask[2] = 0xff;
1906 case 2:
1907 spec->ht.mcs.rx_mask[1] = 0xff;
1908 case 1:
1909 spec->ht.mcs.rx_mask[0] = 0xff;
1910 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
1911 break;
1912 }
1913
1914 /*
1915 * Create channel information array
1916 */
1917 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1918 if (!info)
1919 return -ENOMEM;
1920
1921 spec->channels_info = info;
1922
1923 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
1924 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
1925
1926 for (i = 0; i < 14; i++) {
1927 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
1928 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
1929 }
1930
1931 if (spec->num_channels > 14) {
1932 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
1933 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
1934
1935 for (i = 14; i < spec->num_channels; i++) {
1936 info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
1937 info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
1938 }
1939 }
1940
1941 return 0;
1942}
1943
b0a1edab
BZ		 1944static const struct rt2800_ops rt2800pci_rt2800_ops = {
1945 .register_read = rt2x00pci_register_read,
1946 .register_write = rt2x00pci_register_write,
1947 .register_write_lock = rt2x00pci_register_write, /* same for PCI */
1948
1949 .register_multiread = rt2x00pci_register_multiread,
1950 .register_multiwrite = rt2x00pci_register_multiwrite,
1951
1952 .regbusy_read = rt2x00pci_regbusy_read,
1953};
1954
a9b3a9f7
ID		 1955static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1956{
1957 int retval;
1958
4d6f8b9f
BZ		 1959 rt2x00_set_chip_intf(rt2x00dev, RT2X00_CHIP_INTF_PCI);
1960
b0a1edab
BZ		 1961 rt2x00dev->priv = (void *)&rt2800pci_rt2800_ops;
1962
a9b3a9f7
ID		 1963 /*
1964 * Allocate eeprom data.
1965 */
1966 retval = rt2800pci_validate_eeprom(rt2x00dev);
1967 if (retval)
1968 return retval;
1969
1970 retval = rt2800pci_init_eeprom(rt2x00dev);
1971 if (retval)
1972 return retval;
1973
1974 /*
1975 * Initialize hw specifications.
1976 */
1977 retval = rt2800pci_probe_hw_mode(rt2x00dev);
1978 if (retval)
1979 return retval;
1980
1981 /*
1982 * This device has multiple filters for control frames
1983 * and has a separate filter for PS Poll frames.
1984 */
1985 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
1986 __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
1987
1988 /*
1989 * This device requires firmware.
1990 */
1991 if (!rt2x00_rt(&rt2x00dev->chip, RT2880) &&
1992 !rt2x00_rt(&rt2x00dev->chip, RT3052))
1993 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
1994 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1995 __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
1996 if (!modparam_nohwcrypt)
1997 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
1998
1999 /*
2000 * Set the rssi offset.
2001 */
2002 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2003
2004 return 0;
2005}
2006
2007/*
2008 * IEEE80211 stack callback functions.
2009 */
2010static void rt2800pci_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2011 u32 *iv32, u16 *iv16)
2012{
2013 struct rt2x00_dev *rt2x00dev = hw->priv;
2014 struct mac_iveiv_entry iveiv_entry;
2015 u32 offset;
2016
2017 offset = MAC_IVEIV_ENTRY(hw_key_idx);
4f2732ce 2018 rt2800_register_multiread(rt2x00dev, offset,
a9b3a9f7
ID		 2019 &iveiv_entry, sizeof(iveiv_entry));
2020
2021 memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
2022 memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
2023}
2024
2025static int rt2800pci_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2026{
2027 struct rt2x00_dev *rt2x00dev = hw->priv;
2028 u32 reg;
2029 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2030
9ca21eb7 2031 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
a9b3a9f7 2032 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
9ca21eb7 2033 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
a9b3a9f7 2034
9ca21eb7 2035 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9b3a9f7 2036 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
9ca21eb7 2037 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
a9b3a9f7 2038
9ca21eb7 2039 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9b3a9f7 2040 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
9ca21eb7 2041 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
a9b3a9f7 2042
9ca21eb7 2043 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
a9b3a9f7 2044 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
9ca21eb7 2045 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
a9b3a9f7 2046
9ca21eb7 2047 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
a9b3a9f7 2048 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
9ca21eb7 2049 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
a9b3a9f7 2050
9ca21eb7 2051 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
a9b3a9f7 2052 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
9ca21eb7 2053 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
a9b3a9f7 2054
9ca21eb7 2055 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
a9b3a9f7 2056 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
9ca21eb7 2057 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
a9b3a9f7
ID		 2058
2059 return 0;
2060}
2061
2062static int rt2800pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2063 const struct ieee80211_tx_queue_params *params)
2064{
2065 struct rt2x00_dev *rt2x00dev = hw->priv;
2066 struct data_queue *queue;
2067 struct rt2x00_field32 field;
2068 int retval;
2069 u32 reg;
2070 u32 offset;
2071
2072 /*
2073 * First pass the configuration through rt2x00lib, that will
2074 * update the queue settings and validate the input. After that
2075 * we are free to update the registers based on the value
2076 * in the queue parameter.
2077 */
2078 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2079 if (retval)
2080 return retval;
2081
2082 /*
2083 * We only need to perform additional register initialization
2084 * for WMM queues/
2085 */
2086 if (queue_idx >= 4)
2087 return 0;
2088
2089 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2090
2091 /* Update WMM TXOP register */
2092 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2093 field.bit_offset = (queue_idx & 1) * 16;
2094 field.bit_mask = 0xffff << field.bit_offset;
2095
9ca21eb7 2096 rt2800_register_read(rt2x00dev, offset, &reg);
a9b3a9f7 2097 rt2x00_set_field32(&reg, field, queue->txop);
9ca21eb7 2098 rt2800_register_write(rt2x00dev, offset, reg);
a9b3a9f7
ID		 2099
2100 /* Update WMM registers */
2101 field.bit_offset = queue_idx * 4;
2102 field.bit_mask = 0xf << field.bit_offset;
2103
9ca21eb7 2104 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
a9b3a9f7 2105 rt2x00_set_field32(&reg, field, queue->aifs);
9ca21eb7 2106 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
a9b3a9f7 2107
9ca21eb7 2108 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
a9b3a9f7 2109 rt2x00_set_field32(&reg, field, queue->cw_min);
9ca21eb7 2110 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
a9b3a9f7 2111
9ca21eb7 2112 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
a9b3a9f7 2113 rt2x00_set_field32(&reg, field, queue->cw_max);
9ca21eb7 2114 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
a9b3a9f7
ID		 2115
2116 /* Update EDCA registers */
2117 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2118
9ca21eb7 2119 rt2800_register_read(rt2x00dev, offset, &reg);
a9b3a9f7
ID		 2120 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2121 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2122 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2123 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
9ca21eb7 2124 rt2800_register_write(rt2x00dev, offset, reg);
a9b3a9f7
ID		 2125
2126 return 0;
2127}
2128
2129static u64 rt2800pci_get_tsf(struct ieee80211_hw *hw)
2130{
2131 struct rt2x00_dev *rt2x00dev = hw->priv;
2132 u64 tsf;
2133 u32 reg;
2134
9ca21eb7 2135 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
a9b3a9f7 2136 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
9ca21eb7 2137 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
a9b3a9f7
ID		 2138 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2139
2140 return tsf;
2141}
2142
2143static const struct ieee80211_ops rt2800pci_mac80211_ops = {
2144 .tx = rt2x00mac_tx,
2145 .start = rt2x00mac_start,
2146 .stop = rt2x00mac_stop,
2147 .add_interface = rt2x00mac_add_interface,
2148 .remove_interface = rt2x00mac_remove_interface,
2149 .config = rt2x00mac_config,
2150 .configure_filter = rt2x00mac_configure_filter,
2151 .set_key = rt2x00mac_set_key,
2152 .get_stats = rt2x00mac_get_stats,
2153 .get_tkip_seq = rt2800pci_get_tkip_seq,
2154 .set_rts_threshold = rt2800pci_set_rts_threshold,
2155 .bss_info_changed = rt2x00mac_bss_info_changed,
2156 .conf_tx = rt2800pci_conf_tx,
2157 .get_tx_stats = rt2x00mac_get_tx_stats,
2158 .get_tsf = rt2800pci_get_tsf,
2159 .rfkill_poll = rt2x00mac_rfkill_poll,
2160};
2161
2162static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
2163 .irq_handler = rt2800pci_interrupt,
2164 .probe_hw = rt2800pci_probe_hw,
2165 .get_firmware_name = rt2800pci_get_firmware_name,
2166 .check_firmware = rt2800pci_check_firmware,
2167 .load_firmware = rt2800pci_load_firmware,
2168 .initialize = rt2x00pci_initialize,
2169 .uninitialize = rt2x00pci_uninitialize,
2170 .get_entry_state = rt2800pci_get_entry_state,
2171 .clear_entry = rt2800pci_clear_entry,
2172 .set_device_state = rt2800pci_set_device_state,
f4450616
BZ		 2173 .rfkill_poll = rt2800_rfkill_poll,
2174 .link_stats = rt2800_link_stats,
2175 .reset_tuner = rt2800_reset_tuner,
2176 .link_tuner = rt2800_link_tuner,
a9b3a9f7
ID		 2177 .write_tx_desc = rt2800pci_write_tx_desc,
2178 .write_tx_data = rt2x00pci_write_tx_data,
2179 .write_beacon = rt2800pci_write_beacon,
2180 .kick_tx_queue = rt2800pci_kick_tx_queue,
2181 .kill_tx_queue = rt2800pci_kill_tx_queue,
2182 .fill_rxdone = rt2800pci_fill_rxdone,
f4450616
BZ		 2183 .config_shared_key = rt2800_config_shared_key,
2184 .config_pairwise_key = rt2800_config_pairwise_key,
2185 .config_filter = rt2800_config_filter,
2186 .config_intf = rt2800_config_intf,
2187 .config_erp = rt2800_config_erp,
2188 .config_ant = rt2800_config_ant,
2189 .config = rt2800_config,
a9b3a9f7
ID		 2190};
2191
2192static const struct data_queue_desc rt2800pci_queue_rx = {
2193 .entry_num = RX_ENTRIES,
2194 .data_size = AGGREGATION_SIZE,
2195 .desc_size = RXD_DESC_SIZE,
2196 .priv_size = sizeof(struct queue_entry_priv_pci),
2197};
2198
2199static const struct data_queue_desc rt2800pci_queue_tx = {
2200 .entry_num = TX_ENTRIES,
2201 .data_size = AGGREGATION_SIZE,
2202 .desc_size = TXD_DESC_SIZE,
2203 .priv_size = sizeof(struct queue_entry_priv_pci),
2204};
2205
2206static const struct data_queue_desc rt2800pci_queue_bcn = {
2207 .entry_num = 8 * BEACON_ENTRIES,
2208 .data_size = 0, /* No DMA required for beacons */
2209 .desc_size = TXWI_DESC_SIZE,
2210 .priv_size = sizeof(struct queue_entry_priv_pci),
2211};
2212
2213static const struct rt2x00_ops rt2800pci_ops = {
2214 .name = KBUILD_MODNAME,
2215 .max_sta_intf = 1,
2216 .max_ap_intf = 8,
2217 .eeprom_size = EEPROM_SIZE,
2218 .rf_size = RF_SIZE,
2219 .tx_queues = NUM_TX_QUEUES,
2220 .rx = &rt2800pci_queue_rx,
2221 .tx = &rt2800pci_queue_tx,
2222 .bcn = &rt2800pci_queue_bcn,
2223 .lib = &rt2800pci_rt2x00_ops,
2224 .hw = &rt2800pci_mac80211_ops,
2225#ifdef CONFIG_RT2X00_LIB_DEBUGFS
f4450616 2226 .debugfs = &rt2800_rt2x00debug,
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ID		 2227#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2228};
2229
2230/*
2231 * RT2800pci module information.
2232 */
2233static struct pci_device_id rt2800pci_device_table[] = {
2234 { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
2235 { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
2236 { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
2237 { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
2238 { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
2239 { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
2240 { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
2241 { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
2242 { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
2243 { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
2244 { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
2245 { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
2246 { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
2247 { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
2248 { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
2249 { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
2250 { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
2251 { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
2252 { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
2253 { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
2254 { 0, }
2255};
2256
2257MODULE_AUTHOR(DRV_PROJECT);
2258MODULE_VERSION(DRV_VERSION);
2259MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
2260MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
2261#ifdef CONFIG_RT2800PCI_PCI
2262MODULE_FIRMWARE(FIRMWARE_RT2860);
2263MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
2264#endif /* CONFIG_RT2800PCI_PCI */
2265MODULE_LICENSE("GPL");
2266
2267#ifdef CONFIG_RT2800PCI_WISOC
2268#if defined(CONFIG_RALINK_RT288X)
2269__rt2x00soc_probe(RT2880, &rt2800pci_ops);
2270#elif defined(CONFIG_RALINK_RT305X)
2271__rt2x00soc_probe(RT3052, &rt2800pci_ops);
2272#endif
2273
2274static struct platform_driver rt2800soc_driver = {
2275 .driver = {
2276 .name = "rt2800_wmac",
2277 .owner = THIS_MODULE,
2278 .mod_name = KBUILD_MODNAME,
2279 },
2280 .probe = __rt2x00soc_probe,
2281 .remove = __devexit_p(rt2x00soc_remove),
2282 .suspend = rt2x00soc_suspend,
2283 .resume = rt2x00soc_resume,
2284};
2285#endif /* CONFIG_RT2800PCI_WISOC */
2286
2287#ifdef CONFIG_RT2800PCI_PCI
2288static struct pci_driver rt2800pci_driver = {
2289 .name = KBUILD_MODNAME,
2290 .id_table = rt2800pci_device_table,
2291 .probe = rt2x00pci_probe,
2292 .remove = __devexit_p(rt2x00pci_remove),
2293 .suspend = rt2x00pci_suspend,
2294 .resume = rt2x00pci_resume,
2295};
2296#endif /* CONFIG_RT2800PCI_PCI */
2297
2298static int __init rt2800pci_init(void)
2299{
2300 int ret = 0;
2301
2302#ifdef CONFIG_RT2800PCI_WISOC
2303 ret = platform_driver_register(&rt2800soc_driver);
2304 if (ret)
2305 return ret;
2306#endif
2307#ifdef CONFIG_RT2800PCI_PCI
2308 ret = pci_register_driver(&rt2800pci_driver);
2309 if (ret) {
2310#ifdef CONFIG_RT2800PCI_WISOC
2311 platform_driver_unregister(&rt2800soc_driver);
2312#endif
2313 return ret;
2314 }
2315#endif
2316
2317 return ret;
2318}
2319
2320static void __exit rt2800pci_exit(void)
2321{
2322#ifdef CONFIG_RT2800PCI_PCI
2323 pci_unregister_driver(&rt2800pci_driver);
2324#endif
2325#ifdef CONFIG_RT2800PCI_WISOC
2326 platform_driver_unregister(&rt2800soc_driver);
2327#endif
2328}
2329
2330module_init(rt2800pci_init);
2331module_exit(rt2800pci_exit);
Linux kernel - Deliverables
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