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rt2x00: Make rt2800_write_beacon only export to GPL
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2800pci.c
CommitLineData
a9b3a9f7 1/*
9c9a0d14
GW		 2 Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
a9b3a9f7
ID		 10 <http://rt2x00.serialmonkey.com>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 */
27
28/*
29 Module: rt2800pci
30 Abstract: rt2800pci device specific routines.
31 Supported chipsets: RT2800E & RT2800ED.
32 */
33
34#include <linux/crc-ccitt.h>
35#include <linux/delay.h>
36#include <linux/etherdevice.h>
37#include <linux/init.h>
38#include <linux/kernel.h>
39#include <linux/module.h>
40#include <linux/pci.h>
41#include <linux/platform_device.h>
42#include <linux/eeprom_93cx6.h>
43
44#include "rt2x00.h"
45#include "rt2x00pci.h"
46#include "rt2x00soc.h"
7ef5cc92 47#include "rt2800lib.h"
b54f78a8 48#include "rt2800.h"
a9b3a9f7
ID		 49#include "rt2800pci.h"
50
a9b3a9f7
ID		 51/*
52 * Allow hardware encryption to be disabled.
53 */
04f1e34d 54static int modparam_nohwcrypt = 0;
a9b3a9f7
ID		 55module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
56MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
57
a9b3a9f7
ID		 58static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
59{
60 unsigned int i;
61 u32 reg;
62
f18d4463
LC		 63 /*
64 * SOC devices don't support MCU requests.
65 */
66 if (rt2x00_is_soc(rt2x00dev))
67 return;
68
a9b3a9f7 69 for (i = 0; i < 200; i++) {
9ca21eb7 70 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
a9b3a9f7
ID		 71
72 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
73 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
74 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
75 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
76 break;
77
78 udelay(REGISTER_BUSY_DELAY);
79 }
80
81 if (i == 200)
82 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
83
9ca21eb7
BZ		 84 rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
85 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
a9b3a9f7
ID		 86}
87
00e23ce2 88#ifdef CONFIG_RT2800PCI_SOC
a9b3a9f7
ID		 89static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
90{
91 u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */
92
93 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
94}
95#else
96static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
97{
98}
00e23ce2 99#endif /* CONFIG_RT2800PCI_SOC */
a9b3a9f7
ID		 100
101#ifdef CONFIG_RT2800PCI_PCI
102static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
103{
104 struct rt2x00_dev *rt2x00dev = eeprom->data;
105 u32 reg;
106
9ca21eb7 107 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 108
109 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
110 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
111 eeprom->reg_data_clock =
112 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
113 eeprom->reg_chip_select =
114 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
115}
116
117static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
118{
119 struct rt2x00_dev *rt2x00dev = eeprom->data;
120 u32 reg = 0;
121
122 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
123 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
124 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
125 !!eeprom->reg_data_clock);
126 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
127 !!eeprom->reg_chip_select);
128
9ca21eb7 129 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
a9b3a9f7
ID		 130}
131
132static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
133{
134 struct eeprom_93cx6 eeprom;
135 u32 reg;
136
9ca21eb7 137 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 138
139 eeprom.data = rt2x00dev;
140 eeprom.register_read = rt2800pci_eepromregister_read;
141 eeprom.register_write = rt2800pci_eepromregister_write;
20f8b139
GW		 142 switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
143 {
144 case 0:
145 eeprom.width = PCI_EEPROM_WIDTH_93C46;
146 break;
147 case 1:
148 eeprom.width = PCI_EEPROM_WIDTH_93C66;
149 break;
150 default:
151 eeprom.width = PCI_EEPROM_WIDTH_93C86;
152 break;
153 }
a9b3a9f7
ID		 154 eeprom.reg_data_in = 0;
155 eeprom.reg_data_out = 0;
156 eeprom.reg_data_clock = 0;
157 eeprom.reg_chip_select = 0;
158
159 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
160 EEPROM_SIZE / sizeof(u16));
161}
162
a6598682
GW		 163static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
164{
30e84034 165 return rt2800_efuse_detect(rt2x00dev);
a9b3a9f7
ID		 166}
167
30e84034 168static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 169{
30e84034 170 rt2800_read_eeprom_efuse(rt2x00dev);
a9b3a9f7
ID		 171}
172#else
173static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
174{
175}
176
a6598682
GW		 177static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
178{
179 return 0;
180}
181
a9b3a9f7
ID		 182static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
183{
184}
185#endif /* CONFIG_RT2800PCI_PCI */
186
a9b3a9f7
ID		 187/*
188 * Firmware functions
189 */
190static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
191{
192 return FIRMWARE_RT2860;
193}
194
195static int rt2800pci_check_firmware(struct rt2x00_dev *rt2x00dev,
196 const u8 *data, const size_t len)
197{
198 u16 fw_crc;
199 u16 crc;
200
201 /*
202 * Only support 8kb firmware files.
203 */
204 if (len != 8192)
205 return FW_BAD_LENGTH;
206
207 /*
208 * The last 2 bytes in the firmware array are the crc checksum itself,
209 * this means that we should never pass those 2 bytes to the crc
210 * algorithm.
211 */
212 fw_crc = (data[len - 2] << 8 | data[len - 1]);
213
214 /*
215 * Use the crc ccitt algorithm.
216 * This will return the same value as the legacy driver which
217 * used bit ordering reversion on the both the firmware bytes
218 * before input input as well as on the final output.
219 * Obviously using crc ccitt directly is much more efficient.
220 */
221 crc = crc_ccitt(~0, data, len - 2);
222
223 /*
224 * There is a small difference between the crc-itu-t + bitrev and
225 * the crc-ccitt crc calculation. In the latter method the 2 bytes
226 * will be swapped, use swab16 to convert the crc to the correct
227 * value.
228 */
229 crc = swab16(crc);
230
231 return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
232}
233
234static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
235 const u8 *data, const size_t len)
236{
237 unsigned int i;
238 u32 reg;
239
240 /*
241 * Wait for stable hardware.
242 */
243 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9ca21eb7 244 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
a9b3a9f7
ID		 245 if (reg && reg != ~0)
246 break;
247 msleep(1);
248 }
249
250 if (i == REGISTER_BUSY_COUNT) {
251 ERROR(rt2x00dev, "Unstable hardware.\n");
252 return -EBUSY;
253 }
254
9ca21eb7
BZ		 255 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
256 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
a9b3a9f7
ID		 257
258 /*
259 * Disable DMA, will be reenabled later when enabling
260 * the radio.
261 */
9ca21eb7 262 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 263 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
264 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
265 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
266 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
267 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 268 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7
ID		 269
270 /*
271 * enable Host program ram write selection
272 */
273 reg = 0;
274 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
9ca21eb7 275 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
a9b3a9f7
ID		 276
277 /*
278 * Write firmware to device.
279 */
4f2732ce 280 rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
a9b3a9f7
ID		 281 data, len);
282
9ca21eb7
BZ		 283 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
284 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
a9b3a9f7
ID		 285
286 /*
287 * Wait for device to stabilize.
288 */
289 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9ca21eb7 290 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
a9b3a9f7
ID		 291 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
292 break;
293 msleep(1);
294 }
295
296 if (i == REGISTER_BUSY_COUNT) {
297 ERROR(rt2x00dev, "PBF system register not ready.\n");
298 return -EBUSY;
299 }
300
301 /*
302 * Disable interrupts
303 */
304 rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_OFF);
305
306 /*
307 * Initialize BBP R/W access agent
308 */
9ca21eb7
BZ		 309 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
310 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
a9b3a9f7
ID		 311
312 return 0;
313}
314
315/*
316 * Initialization functions.
317 */
318static bool rt2800pci_get_entry_state(struct queue_entry *entry)
319{
320 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
321 u32 word;
322
323 if (entry->queue->qid == QID_RX) {
324 rt2x00_desc_read(entry_priv->desc, 1, &word);
325
326 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
327 } else {
328 rt2x00_desc_read(entry_priv->desc, 1, &word);
329
330 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
331 }
332}
333
334static void rt2800pci_clear_entry(struct queue_entry *entry)
335{
336 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
337 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
338 u32 word;
339
340 if (entry->queue->qid == QID_RX) {
341 rt2x00_desc_read(entry_priv->desc, 0, &word);
342 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
343 rt2x00_desc_write(entry_priv->desc, 0, word);
344
345 rt2x00_desc_read(entry_priv->desc, 1, &word);
346 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
347 rt2x00_desc_write(entry_priv->desc, 1, word);
348 } else {
349 rt2x00_desc_read(entry_priv->desc, 1, &word);
350 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
351 rt2x00_desc_write(entry_priv->desc, 1, word);
352 }
353}
354
355static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
356{
357 struct queue_entry_priv_pci *entry_priv;
358 u32 reg;
359
a9b3a9f7
ID		 360 /*
361 * Initialize registers.
362 */
363 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
9ca21eb7
BZ		 364 rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
365 rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
366 rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
367 rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
a9b3a9f7
ID		 368
369 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
9ca21eb7
BZ		 370 rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
371 rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
372 rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
373 rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
a9b3a9f7
ID		 374
375 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
9ca21eb7
BZ		 376 rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
377 rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
378 rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
379 rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
a9b3a9f7
ID		 380
381 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
9ca21eb7
BZ		 382 rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
383 rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
384 rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
385 rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
a9b3a9f7
ID		 386
387 entry_priv = rt2x00dev->rx->entries[0].priv_data;
9ca21eb7
BZ		 388 rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
389 rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
390 rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
391 rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
a9b3a9f7
ID		 392
393 /*
394 * Enable global DMA configuration
395 */
9ca21eb7 396 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 397 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
398 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
399 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 400 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7 401
9ca21eb7 402 rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
a9b3a9f7
ID		 403
404 return 0;
405}
406
a9b3a9f7
ID		 407/*
408 * Device state switch handlers.
409 */
410static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
411 enum dev_state state)
412{
413 u32 reg;
414
9ca21eb7 415 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
a9b3a9f7
ID		 416 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
417 (state == STATE_RADIO_RX_ON) ||
418 (state == STATE_RADIO_RX_ON_LINK));
9ca21eb7 419 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
a9b3a9f7
ID		 420}
421
422static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
423 enum dev_state state)
424{
425 int mask = (state == STATE_RADIO_IRQ_ON);
426 u32 reg;
427
428 /*
429 * When interrupts are being enabled, the interrupt registers
430 * should clear the register to assure a clean state.
431 */
432 if (state == STATE_RADIO_IRQ_ON) {
9ca21eb7
BZ		 433 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
434 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
a9b3a9f7
ID		 435 }
436
9ca21eb7 437 rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
a9b3a9f7
ID		 438 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
439 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
440 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
441 rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
442 rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
443 rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
444 rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
445 rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
446 rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
447 rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
448 rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, mask);
449 rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
450 rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
451 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
452 rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
453 rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
454 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
455 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
9ca21eb7 456 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
a9b3a9f7
ID		 457}
458
e3a896b9
GW		 459static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
460{
461 u32 reg;
462
463 /*
464 * Reset DMA indexes
465 */
466 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
467 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
468 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
469 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
470 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
471 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
472 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
473 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
474 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
475
476 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
477 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
478
479 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
480
481 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
482 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
483 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
484 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
485
486 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
487
488 return 0;
489}
490
a9b3a9f7
ID		 491static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
492{
493 u32 reg;
494 u16 word;
495
496 /*
497 * Initialize all registers.
498 */
67a4c1e2 499 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
a9b3a9f7 500 rt2800pci_init_queues(rt2x00dev) ||
fcf51541 501 rt2800_init_registers(rt2x00dev) ||
67a4c1e2 502 rt2800_wait_wpdma_ready(rt2x00dev) ||
fcf51541
BZ		 503 rt2800_init_bbp(rt2x00dev) ||
504 rt2800_init_rfcsr(rt2x00dev)))
a9b3a9f7
ID		 505 return -EIO;
506
507 /*
508 * Send signal to firmware during boot time.
509 */
532bc2d5 510 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
a9b3a9f7
ID		 511
512 /*
513 * Enable RX.
514 */
9ca21eb7 515 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
a9b3a9f7
ID		 516 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
517 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
9ca21eb7 518 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
a9b3a9f7 519
9ca21eb7 520 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 521 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
522 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
523 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
524 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 525 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7 526
9ca21eb7 527 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
a9b3a9f7
ID		 528 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
529 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
9ca21eb7 530 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
a9b3a9f7
ID		 531
532 /*
533 * Initialize LED control
534 */
535 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
3a9e5b0f 536 rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
a9b3a9f7
ID		 537 word & 0xff, (word >> 8) & 0xff);
538
539 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
3a9e5b0f 540 rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
a9b3a9f7
ID		 541 word & 0xff, (word >> 8) & 0xff);
542
543 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
3a9e5b0f 544 rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
a9b3a9f7
ID		 545 word & 0xff, (word >> 8) & 0xff);
546
547 return 0;
548}
549
550static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
551{
552 u32 reg;
553
9ca21eb7 554 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 555 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
556 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
557 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
558 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
559 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 560 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7 561
9ca21eb7
BZ		 562 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
563 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
564 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
a9b3a9f7 565
9ca21eb7 566 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
a9b3a9f7 567
9ca21eb7 568 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
a9b3a9f7
ID		 569 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
570 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
571 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
572 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
573 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
574 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
575 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
9ca21eb7 576 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
a9b3a9f7 577
9ca21eb7
BZ		 578 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
579 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
a9b3a9f7
ID		 580
581 /* Wait for DMA, ignore error */
67a4c1e2 582 rt2800_wait_wpdma_ready(rt2x00dev);
a9b3a9f7
ID		 583}
584
585static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
586 enum dev_state state)
587{
588 /*
589 * Always put the device to sleep (even when we intend to wakeup!)
590 * if the device is booting and wasn't asleep it will return
591 * failure when attempting to wakeup.
592 */
3a9e5b0f 593 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
a9b3a9f7
ID		 594
595 if (state == STATE_AWAKE) {
3a9e5b0f 596 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
a9b3a9f7
ID		 597 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
598 }
599
600 return 0;
601}
602
603static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
604 enum dev_state state)
605{
606 int retval = 0;
607
608 switch (state) {
609 case STATE_RADIO_ON:
610 /*
611 * Before the radio can be enabled, the device first has
612 * to be woken up. After that it needs a bit of time
613 * to be fully awake and then the radio can be enabled.
614 */
615 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
616 msleep(1);
617 retval = rt2800pci_enable_radio(rt2x00dev);
618 break;
619 case STATE_RADIO_OFF:
620 /*
621 * After the radio has been disabled, the device should
622 * be put to sleep for powersaving.
623 */
624 rt2800pci_disable_radio(rt2x00dev);
625 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
626 break;
627 case STATE_RADIO_RX_ON:
628 case STATE_RADIO_RX_ON_LINK:
629 case STATE_RADIO_RX_OFF:
630 case STATE_RADIO_RX_OFF_LINK:
631 rt2800pci_toggle_rx(rt2x00dev, state);
632 break;
633 case STATE_RADIO_IRQ_ON:
634 case STATE_RADIO_IRQ_OFF:
635 rt2800pci_toggle_irq(rt2x00dev, state);
636 break;
637 case STATE_DEEP_SLEEP:
638 case STATE_SLEEP:
639 case STATE_STANDBY:
640 case STATE_AWAKE:
641 retval = rt2800pci_set_state(rt2x00dev, state);
642 break;
643 default:
644 retval = -ENOTSUPP;
645 break;
646 }
647
648 if (unlikely(retval))
649 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
650 state, retval);
651
652 return retval;
653}
654
655/*
656 * TX descriptor initialization
657 */
76dd5ddf
GW		 658static void rt2800pci_write_tx_data(struct queue_entry* entry,
659 struct txentry_desc *txdesc)
a9b3a9f7 660{
9cf4cb05
GW		 661 __le32 *txwi = (__le32 *) entry->skb->data;
662
663 rt2800_write_txwi(txwi, txdesc);
745b1ae3
HS		 664}
665
666
667static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
668 struct sk_buff *skb,
669 struct txentry_desc *txdesc)
670{
671 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
85b7a8b3
GW		 672 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
673 __le32 *txd = entry_priv->desc;
745b1ae3
HS		 674 u32 word;
675
a9b3a9f7
ID		 676 /*
677 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
678 * must contains a TXWI structure + 802.11 header + padding + 802.11
679 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
680 * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
681 * data. It means that LAST_SEC0 is always 0.
682 */
683
684 /*
685 * Initialize TX descriptor
686 */
687 rt2x00_desc_read(txd, 0, &word);
688 rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
689 rt2x00_desc_write(txd, 0, word);
690
691 rt2x00_desc_read(txd, 1, &word);
692 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
693 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
694 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
695 rt2x00_set_field32(&word, TXD_W1_BURST,
696 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
85b7a8b3 697 rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
a9b3a9f7
ID		 698 rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
699 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
700 rt2x00_desc_write(txd, 1, word);
701
702 rt2x00_desc_read(txd, 2, &word);
703 rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
85b7a8b3 704 skbdesc->skb_dma + TXWI_DESC_SIZE);
a9b3a9f7
ID		 705 rt2x00_desc_write(txd, 2, word);
706
707 rt2x00_desc_read(txd, 3, &word);
708 rt2x00_set_field32(&word, TXD_W3_WIV,
709 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
710 rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
711 rt2x00_desc_write(txd, 3, word);
85b7a8b3
GW		 712
713 /*
714 * Register descriptor details in skb frame descriptor.
715 */
716 skbdesc->desc = txd;
717 skbdesc->desc_len = TXD_DESC_SIZE;
a9b3a9f7
ID		 718}
719
720/*
721 * TX data initialization
722 */
a9b3a9f7
ID		 723static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
724 const enum data_queue_qid queue_idx)
725{
726 struct data_queue *queue;
727 unsigned int idx, qidx = 0;
a9b3a9f7
ID		 728
729 if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
730 return;
731
732 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
733 idx = queue->index[Q_INDEX];
734
735 if (queue_idx == QID_MGMT)
736 qidx = 5;
737 else
738 qidx = queue_idx;
739
9ca21eb7 740 rt2800_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
a9b3a9f7
ID		 741}
742
743static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
744 const enum data_queue_qid qid)
745{
746 u32 reg;
747
748 if (qid == QID_BEACON) {
9ca21eb7 749 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, 0);
a9b3a9f7
ID		 750 return;
751 }
752
9ca21eb7 753 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
a9b3a9f7
ID		 754 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
755 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
756 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
757 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
9ca21eb7 758 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
a9b3a9f7
ID		 759}
760
761/*
762 * RX control handlers
763 */
764static void rt2800pci_fill_rxdone(struct queue_entry *entry,
765 struct rxdone_entry_desc *rxdesc)
766{
767 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
a9b3a9f7
ID		 768 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
769 __le32 *rxd = entry_priv->desc;
2de64dd2
GW		 770 u32 word;
771
772 rt2x00_desc_read(rxd, 3, &word);
773
774 if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
a9b3a9f7
ID		 775 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
776
78b8f3b0
GW		 777 /*
778 * Unfortunately we don't know the cipher type used during
779 * decryption. This prevents us from correct providing
780 * correct statistics through debugfs.
781 */
2de64dd2 782 rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
a9b3a9f7 783
2de64dd2 784 if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
a9b3a9f7
ID		 785 /*
786 * Hardware has stripped IV/EIV data from 802.11 frame during
787 * decryption. Unfortunately the descriptor doesn't contain
788 * any fields with the EIV/IV data either, so they can't
789 * be restored by rt2x00lib.
790 */
791 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
792
793 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
794 rxdesc->flags |= RX_FLAG_DECRYPTED;
795 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
796 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
797 }
798
2de64dd2 799 if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
a9b3a9f7
ID		 800 rxdesc->dev_flags |= RXDONE_MY_BSS;
801
2de64dd2 802 if (rt2x00_get_field32(word, RXD_W3_L2PAD))
a9b3a9f7 803 rxdesc->dev_flags |= RXDONE_L2PAD;
a9b3a9f7 804
a9b3a9f7 805 /*
2de64dd2 806 * Process the RXWI structure that is at the start of the buffer.
a9b3a9f7 807 */
74861922 808 rt2800_process_rxwi(entry, rxdesc);
a9b3a9f7
ID		 809
810 /*
811 * Set RX IDX in register to inform hardware that we have handled
812 * this entry and it is available for reuse again.
813 */
9ca21eb7 814 rt2800_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
a9b3a9f7
ID		 815}
816
817/*
818 * Interrupt functions.
819 */
820static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
821{
822 struct data_queue *queue;
823 struct queue_entry *entry;
632dd959 824 __le32 *txwi;
a9b3a9f7
ID		 825 struct txdone_entry_desc txdesc;
826 u32 word;
827 u32 reg;
632dd959 828 int wcid, ack, pid, tx_wcid, tx_ack, tx_pid;
a9b3a9f7 829 u16 mcs, real_mcs;
3afa626a 830 int i;
a9b3a9f7
ID		 831
832 /*
3afa626a
HS		 833 * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
834 * at most X times and also stop processing once the TX_STA_FIFO_VALID
835 * flag is not set anymore.
836 *
837 * The legacy drivers use X=TX_RING_SIZE but state in a comment
838 * that the TX_STA_FIFO stack has a size of 16. We stick to our
839 * tx ring size for now.
a9b3a9f7 840 */
3afa626a 841 for (i = 0; i < TX_ENTRIES; i++) {
9ca21eb7 842 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
a9b3a9f7
ID		 843 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
844 break;
845
632dd959
AB		 846 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
847 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
848 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
849
a9b3a9f7
ID		 850 /*
851 * Skip this entry when it contains an invalid
852 * queue identication number.
853 */
632dd959 854 if (pid <= 0 || pid > QID_RX)
a9b3a9f7
ID		 855 continue;
856
632dd959 857 queue = rt2x00queue_get_queue(rt2x00dev, pid - 1);
a9b3a9f7
ID		 858 if (unlikely(!queue))
859 continue;
860
861 /*
632dd959
AB		 862 * Inside each queue, we process each entry in a chronological
863 * order. We first check that the queue is not empty.
a9b3a9f7 864 */
632dd959 865 if (rt2x00queue_empty(queue))
a9b3a9f7 866 continue;
632dd959 867 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
a9b3a9f7 868
632dd959
AB		 869 /* Check if we got a match by looking at WCID/ACK/PID
870 * fields */
0b8004aa 871 txwi = (__le32 *) entry->skb->data;
632dd959
AB		 872
873 rt2x00_desc_read(txwi, 1, &word);
874 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
875 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK);
876 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID);
877
878 if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid))
879 WARNING(rt2x00dev, "invalid TX_STA_FIFO content\n");
a9b3a9f7
ID		 880
881 /*
882 * Obtain the status about this packet.
883 */
884 txdesc.flags = 0;
bf18723d
AB		 885 rt2x00_desc_read(txwi, 0, &word);
886 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
887 real_mcs = rt2x00_get_field32(reg, TX_STA_FIFO_MCS);
a9b3a9f7
ID		 888
889 /*
890 * Ralink has a retry mechanism using a global fallback
bf18723d
AB		 891 * table. We setup this fallback table to try the immediate
892 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
893 * always contains the MCS used for the last transmission, be
894 * it successful or not.
a9b3a9f7 895 */
bf18723d
AB		 896 if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS)) {
897 /*
898 * Transmission succeeded. The number of retries is
899 * mcs - real_mcs
900 */
901 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
902 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
903 } else {
904 /*
905 * Transmission failed. The number of retries is
906 * always 7 in this case (for a total number of 8
907 * frames sent).
908 */
909 __set_bit(TXDONE_FAILURE, &txdesc.flags);
910 txdesc.retry = 7;
911 }
912
ecb7cab5
HS		 913 /*
914 * the frame was retried at least once
915 * -> hw used fallback rates
916 */
917 if (txdesc.retry)
918 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
a9b3a9f7 919
e513a0b6 920 rt2x00lib_txdone(entry, &txdesc);
a9b3a9f7
ID		 921 }
922}
923
4d66edc8
GW		 924static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
925{
926 struct ieee80211_conf conf = { .flags = 0 };
927 struct rt2x00lib_conf libconf = { .conf = &conf };
928
929 rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
930}
931
a9b3a9f7
ID		 932static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
933{
934 struct rt2x00_dev *rt2x00dev = dev_instance;
935 u32 reg;
936
937 /* Read status and ACK all interrupts */
9ca21eb7
BZ		 938 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
939 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
a9b3a9f7
ID		 940
941 if (!reg)
942 return IRQ_NONE;
943
944 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
945 return IRQ_HANDLED;
946
947 /*
948 * 1 - Rx ring done interrupt.
949 */
950 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
951 rt2x00pci_rxdone(rt2x00dev);
952
953 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
954 rt2800pci_txdone(rt2x00dev);
955
ad90319b
HS		 956 /*
957 * Current beacon was sent out, fetch the next one
958 */
959 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
960 rt2x00lib_beacondone(rt2x00dev);
961
4d66edc8
GW		 962 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
963 rt2800pci_wakeup(rt2x00dev);
964
a9b3a9f7
ID		 965 return IRQ_HANDLED;
966}
967
968/*
969 * Device probe functions.
970 */
7ab71325
BZ		 971static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
972{
973 /*
974 * Read EEPROM into buffer
975 */
cea90e55 976 if (rt2x00_is_soc(rt2x00dev))
7ab71325 977 rt2800pci_read_eeprom_soc(rt2x00dev);
cea90e55
GW		 978 else if (rt2800pci_efuse_detect(rt2x00dev))
979 rt2800pci_read_eeprom_efuse(rt2x00dev);
980 else
981 rt2800pci_read_eeprom_pci(rt2x00dev);
7ab71325
BZ		 982
983 return rt2800_validate_eeprom(rt2x00dev);
984}
985
b0a1edab
BZ		 986static const struct rt2800_ops rt2800pci_rt2800_ops = {
987 .register_read = rt2x00pci_register_read,
31a4cf1f 988 .register_read_lock = rt2x00pci_register_read, /* same for PCI */
b0a1edab
BZ		 989 .register_write = rt2x00pci_register_write,
990 .register_write_lock = rt2x00pci_register_write, /* same for PCI */
991
992 .register_multiread = rt2x00pci_register_multiread,
993 .register_multiwrite = rt2x00pci_register_multiwrite,
994
995 .regbusy_read = rt2x00pci_regbusy_read,
e3a896b9
GW		 996
997 .drv_init_registers = rt2800pci_init_registers,
b0a1edab
BZ		 998};
999
a9b3a9f7
ID		 1000static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1001{
1002 int retval;
1003
b0a1edab
BZ		 1004 rt2x00dev->priv = (void *)&rt2800pci_rt2800_ops;
1005
a9b3a9f7
ID		 1006 /*
1007 * Allocate eeprom data.
1008 */
1009 retval = rt2800pci_validate_eeprom(rt2x00dev);
1010 if (retval)
1011 return retval;
1012
38bd7b8a 1013 retval = rt2800_init_eeprom(rt2x00dev);
a9b3a9f7
ID		 1014 if (retval)
1015 return retval;
1016
1017 /*
1018 * Initialize hw specifications.
1019 */
4da2933f 1020 retval = rt2800_probe_hw_mode(rt2x00dev);
a9b3a9f7
ID		 1021 if (retval)
1022 return retval;
1023
1024 /*
1025 * This device has multiple filters for control frames
1026 * and has a separate filter for PS Poll frames.
1027 */
1028 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
1029 __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
1030
1031 /*
1032 * This device requires firmware.
1033 */
cea90e55 1034 if (!rt2x00_is_soc(rt2x00dev))
a9b3a9f7
ID		 1035 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
1036 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1037 __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
1038 if (!modparam_nohwcrypt)
1039 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
27df2a9c 1040 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
a9b3a9f7
ID		 1041
1042 /*
1043 * Set the rssi offset.
1044 */
1045 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1046
1047 return 0;
1048}
1049
a9b3a9f7
ID		 1050static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1051 .irq_handler = rt2800pci_interrupt,
1052 .probe_hw = rt2800pci_probe_hw,
1053 .get_firmware_name = rt2800pci_get_firmware_name,
1054 .check_firmware = rt2800pci_check_firmware,
1055 .load_firmware = rt2800pci_load_firmware,
1056 .initialize = rt2x00pci_initialize,
1057 .uninitialize = rt2x00pci_uninitialize,
1058 .get_entry_state = rt2800pci_get_entry_state,
1059 .clear_entry = rt2800pci_clear_entry,
1060 .set_device_state = rt2800pci_set_device_state,
f4450616
BZ		 1061 .rfkill_poll = rt2800_rfkill_poll,
1062 .link_stats = rt2800_link_stats,
1063 .reset_tuner = rt2800_reset_tuner,
1064 .link_tuner = rt2800_link_tuner,
a9b3a9f7 1065 .write_tx_desc = rt2800pci_write_tx_desc,
76dd5ddf 1066 .write_tx_data = rt2800pci_write_tx_data,
f0194b2d 1067 .write_beacon = rt2800_write_beacon,
a9b3a9f7
ID		 1068 .kick_tx_queue = rt2800pci_kick_tx_queue,
1069 .kill_tx_queue = rt2800pci_kill_tx_queue,
1070 .fill_rxdone = rt2800pci_fill_rxdone,
f4450616
BZ		 1071 .config_shared_key = rt2800_config_shared_key,
1072 .config_pairwise_key = rt2800_config_pairwise_key,
1073 .config_filter = rt2800_config_filter,
1074 .config_intf = rt2800_config_intf,
1075 .config_erp = rt2800_config_erp,
1076 .config_ant = rt2800_config_ant,
1077 .config = rt2800_config,
a9b3a9f7
ID		 1078};
1079
1080static const struct data_queue_desc rt2800pci_queue_rx = {
1081 .entry_num = RX_ENTRIES,
1082 .data_size = AGGREGATION_SIZE,
1083 .desc_size = RXD_DESC_SIZE,
1084 .priv_size = sizeof(struct queue_entry_priv_pci),
1085};
1086
1087static const struct data_queue_desc rt2800pci_queue_tx = {
1088 .entry_num = TX_ENTRIES,
1089 .data_size = AGGREGATION_SIZE,
1090 .desc_size = TXD_DESC_SIZE,
1091 .priv_size = sizeof(struct queue_entry_priv_pci),
1092};
1093
1094static const struct data_queue_desc rt2800pci_queue_bcn = {
1095 .entry_num = 8 * BEACON_ENTRIES,
1096 .data_size = 0, /* No DMA required for beacons */
1097 .desc_size = TXWI_DESC_SIZE,
1098 .priv_size = sizeof(struct queue_entry_priv_pci),
1099};
1100
1101static const struct rt2x00_ops rt2800pci_ops = {
04d0362e
GW		 1102 .name = KBUILD_MODNAME,
1103 .max_sta_intf = 1,
1104 .max_ap_intf = 8,
1105 .eeprom_size = EEPROM_SIZE,
1106 .rf_size = RF_SIZE,
1107 .tx_queues = NUM_TX_QUEUES,
e6218cc4 1108 .extra_tx_headroom = TXWI_DESC_SIZE,
04d0362e
GW		 1109 .rx = &rt2800pci_queue_rx,
1110 .tx = &rt2800pci_queue_tx,
1111 .bcn = &rt2800pci_queue_bcn,
1112 .lib = &rt2800pci_rt2x00_ops,
1113 .hw = &rt2800_mac80211_ops,
a9b3a9f7 1114#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 1115 .debugfs = &rt2800_rt2x00debug,
a9b3a9f7
ID		 1116#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1117};
1118
1119/*
1120 * RT2800pci module information.
1121 */
d6e36ec1 1122#ifdef CONFIG_RT2800PCI_PCI
a3aa1884 1123static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
de1ebdce
GW		 1124 { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
1125 { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
1126 { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
1127 { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
a9b3a9f7
ID		 1128 { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
1129 { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
1130 { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
1131 { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
1132 { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
1133 { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
1134 { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
de1ebdce
GW		 1135 { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
1136#ifdef CONFIG_RT2800PCI_RT30XX
a9b3a9f7
ID		 1137 { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
1138 { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
1139 { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
de1ebdce
GW		 1140 { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
1141#endif
1142#ifdef CONFIG_RT2800PCI_RT35XX
1143 { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
1144 { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
a9b3a9f7
ID		 1145 { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
1146 { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
6424bf70 1147 { PCI_DEVICE(0x1814, 0x3593), PCI_DEVICE_DATA(&rt2800pci_ops) },
de1ebdce 1148#endif
a9b3a9f7
ID		 1149 { 0, }
1150};
d6e36ec1 1151#endif /* CONFIG_RT2800PCI_PCI */
a9b3a9f7
ID		 1152
1153MODULE_AUTHOR(DRV_PROJECT);
1154MODULE_VERSION(DRV_VERSION);
1155MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1156MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1157#ifdef CONFIG_RT2800PCI_PCI
1158MODULE_FIRMWARE(FIRMWARE_RT2860);
1159MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1160#endif /* CONFIG_RT2800PCI_PCI */
1161MODULE_LICENSE("GPL");
1162
00e23ce2 1163#ifdef CONFIG_RT2800PCI_SOC
714fa663
GW		 1164static int rt2800soc_probe(struct platform_device *pdev)
1165{
6e93d719 1166 return rt2x00soc_probe(pdev, &rt2800pci_ops);
714fa663 1167}
a9b3a9f7
ID		 1168
1169static struct platform_driver rt2800soc_driver = {
1170 .driver = {
1171 .name = "rt2800_wmac",
1172 .owner = THIS_MODULE,
1173 .mod_name = KBUILD_MODNAME,
1174 },
714fa663 1175 .probe = rt2800soc_probe,
a9b3a9f7
ID		 1176 .remove = __devexit_p(rt2x00soc_remove),
1177 .suspend = rt2x00soc_suspend,
1178 .resume = rt2x00soc_resume,
1179};
00e23ce2 1180#endif /* CONFIG_RT2800PCI_SOC */
a9b3a9f7
ID		 1181
1182#ifdef CONFIG_RT2800PCI_PCI
1183static struct pci_driver rt2800pci_driver = {
1184 .name = KBUILD_MODNAME,
1185 .id_table = rt2800pci_device_table,
1186 .probe = rt2x00pci_probe,
1187 .remove = __devexit_p(rt2x00pci_remove),
1188 .suspend = rt2x00pci_suspend,
1189 .resume = rt2x00pci_resume,
1190};
1191#endif /* CONFIG_RT2800PCI_PCI */
1192
1193static int __init rt2800pci_init(void)
1194{
1195 int ret = 0;
1196
00e23ce2 1197#ifdef CONFIG_RT2800PCI_SOC
a9b3a9f7
ID		 1198 ret = platform_driver_register(&rt2800soc_driver);
1199 if (ret)
1200 return ret;
1201#endif
1202#ifdef CONFIG_RT2800PCI_PCI
1203 ret = pci_register_driver(&rt2800pci_driver);
1204 if (ret) {
00e23ce2 1205#ifdef CONFIG_RT2800PCI_SOC
a9b3a9f7
ID		 1206 platform_driver_unregister(&rt2800soc_driver);
1207#endif
1208 return ret;
1209 }
1210#endif
1211
1212 return ret;
1213}
1214
1215static void __exit rt2800pci_exit(void)
1216{
1217#ifdef CONFIG_RT2800PCI_PCI
1218 pci_unregister_driver(&rt2800pci_driver);
1219#endif
00e23ce2 1220#ifdef CONFIG_RT2800PCI_SOC
a9b3a9f7
ID		 1221 platform_driver_unregister(&rt2800soc_driver);
1222#endif
1223}
1224
1225module_init(rt2800pci_init);
1226module_exit(rt2800pci_exit);
Linux kernel - Deliverables
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