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rt2x00: Fix stuck queue in tx failure case
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2800pci.c
CommitLineData
a9b3a9f7 1/*
96481b20 2 Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14
GW		 3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
a9b3a9f7
ID		 10 <http://rt2x00.serialmonkey.com>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 */
27
28/*
29 Module: rt2800pci
30 Abstract: rt2800pci device specific routines.
31 Supported chipsets: RT2800E & RT2800ED.
32 */
33
a9b3a9f7
ID		 34#include <linux/delay.h>
35#include <linux/etherdevice.h>
36#include <linux/init.h>
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/pci.h>
40#include <linux/platform_device.h>
41#include <linux/eeprom_93cx6.h>
42
43#include "rt2x00.h"
44#include "rt2x00pci.h"
45#include "rt2x00soc.h"
7ef5cc92 46#include "rt2800lib.h"
b54f78a8 47#include "rt2800.h"
a9b3a9f7
ID		 48#include "rt2800pci.h"
49
a9b3a9f7
ID		 50/*
51 * Allow hardware encryption to be disabled.
52 */
04f1e34d 53static int modparam_nohwcrypt = 0;
a9b3a9f7
ID		 54module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
55MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
56
a9b3a9f7
ID		 57static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
58{
59 unsigned int i;
60 u32 reg;
61
f18d4463
LC		 62 /*
63 * SOC devices don't support MCU requests.
64 */
65 if (rt2x00_is_soc(rt2x00dev))
66 return;
67
a9b3a9f7 68 for (i = 0; i < 200; i++) {
9ca21eb7 69 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
a9b3a9f7
ID		 70
71 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
72 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
73 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
74 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
75 break;
76
77 udelay(REGISTER_BUSY_DELAY);
78 }
79
80 if (i == 200)
81 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
82
9ca21eb7
BZ		 83 rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
84 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
a9b3a9f7
ID		 85}
86
72c7296e 87#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
a9b3a9f7
ID		 88static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
89{
ef8397cf 90 void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
a9b3a9f7
ID		 91
92 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
ef8397cf
GW		 93
94 iounmap(base_addr);
a9b3a9f7
ID		 95}
96#else
97static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
98{
99}
72c7296e 100#endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
a9b3a9f7 101
72c7296e 102#ifdef CONFIG_PCI
a9b3a9f7
ID		 103static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
104{
105 struct rt2x00_dev *rt2x00dev = eeprom->data;
106 u32 reg;
107
9ca21eb7 108 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 109
110 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
111 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
112 eeprom->reg_data_clock =
113 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
114 eeprom->reg_chip_select =
115 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
116}
117
118static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
119{
120 struct rt2x00_dev *rt2x00dev = eeprom->data;
121 u32 reg = 0;
122
123 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
124 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
125 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
126 !!eeprom->reg_data_clock);
127 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
128 !!eeprom->reg_chip_select);
129
9ca21eb7 130 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
a9b3a9f7
ID		 131}
132
133static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
134{
135 struct eeprom_93cx6 eeprom;
136 u32 reg;
137
9ca21eb7 138 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 139
140 eeprom.data = rt2x00dev;
141 eeprom.register_read = rt2800pci_eepromregister_read;
142 eeprom.register_write = rt2800pci_eepromregister_write;
20f8b139
GW		 143 switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
144 {
145 case 0:
146 eeprom.width = PCI_EEPROM_WIDTH_93C46;
147 break;
148 case 1:
149 eeprom.width = PCI_EEPROM_WIDTH_93C66;
150 break;
151 default:
152 eeprom.width = PCI_EEPROM_WIDTH_93C86;
153 break;
154 }
a9b3a9f7
ID		 155 eeprom.reg_data_in = 0;
156 eeprom.reg_data_out = 0;
157 eeprom.reg_data_clock = 0;
158 eeprom.reg_chip_select = 0;
159
160 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
161 EEPROM_SIZE / sizeof(u16));
162}
163
a6598682
GW		 164static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
165{
30e84034 166 return rt2800_efuse_detect(rt2x00dev);
a9b3a9f7
ID		 167}
168
30e84034 169static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 170{
30e84034 171 rt2800_read_eeprom_efuse(rt2x00dev);
a9b3a9f7
ID		 172}
173#else
174static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
175{
176}
177
a6598682
GW		 178static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
179{
180 return 0;
181}
182
a9b3a9f7
ID		 183static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
184{
185}
72c7296e 186#endif /* CONFIG_PCI */
a9b3a9f7 187
5450b7e2
ID		 188/*
189 * Queue handlers.
190 */
191static void rt2800pci_start_queue(struct data_queue *queue)
192{
193 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
194 u32 reg;
195
196 switch (queue->qid) {
197 case QID_RX:
198 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
199 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
200 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
201 break;
202 case QID_BEACON:
a9d61e9e
HS		 203 /*
204 * Allow beacon tasklets to be scheduled for periodic
205 * beacon updates.
206 */
207 tasklet_enable(&rt2x00dev->tbtt_tasklet);
208 tasklet_enable(&rt2x00dev->pretbtt_tasklet);
209
5450b7e2
ID		 210 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
211 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
212 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
213 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
214 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
69cf36a4
HS		 215
216 rt2800_register_read(rt2x00dev, INT_TIMER_EN, &reg);
217 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 1);
218 rt2800_register_write(rt2x00dev, INT_TIMER_EN, reg);
5450b7e2
ID		 219 break;
220 default:
221 break;
222 };
223}
224
225static void rt2800pci_kick_queue(struct data_queue *queue)
226{
227 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
228 struct queue_entry *entry;
229
230 switch (queue->qid) {
f615e9a3
ID		 231 case QID_AC_VO:
232 case QID_AC_VI:
5450b7e2
ID		 233 case QID_AC_BE:
234 case QID_AC_BK:
5450b7e2
ID		 235 entry = rt2x00queue_get_entry(queue, Q_INDEX);
236 rt2800_register_write(rt2x00dev, TX_CTX_IDX(queue->qid), entry->entry_idx);
237 break;
238 case QID_MGMT:
239 entry = rt2x00queue_get_entry(queue, Q_INDEX);
240 rt2800_register_write(rt2x00dev, TX_CTX_IDX(5), entry->entry_idx);
241 break;
242 default:
243 break;
244 }
245}
246
247static void rt2800pci_stop_queue(struct data_queue *queue)
248{
249 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
250 u32 reg;
251
252 switch (queue->qid) {
253 case QID_RX:
254 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
255 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
256 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
257 break;
258 case QID_BEACON:
259 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
260 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
261 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
262 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
263 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
69cf36a4
HS		 264
265 rt2800_register_read(rt2x00dev, INT_TIMER_EN, &reg);
266 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 0);
267 rt2800_register_write(rt2x00dev, INT_TIMER_EN, reg);
a9d61e9e
HS		 268
269 /*
270 * Wait for tbtt tasklets to finish.
271 */
272 tasklet_disable(&rt2x00dev->tbtt_tasklet);
273 tasklet_disable(&rt2x00dev->pretbtt_tasklet);
5450b7e2
ID		 274 break;
275 default:
276 break;
277 }
278}
279
a9b3a9f7
ID		 280/*
281 * Firmware functions
282 */
283static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
284{
285 return FIRMWARE_RT2860;
286}
287
f31c9a8c 288static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
a9b3a9f7
ID		 289 const u8 *data, const size_t len)
290{
a9b3a9f7
ID		 291 u32 reg;
292
a9b3a9f7
ID		 293 /*
294 * enable Host program ram write selection
295 */
296 reg = 0;
297 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
9ca21eb7 298 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
a9b3a9f7
ID		 299
300 /*
301 * Write firmware to device.
302 */
4f2732ce 303 rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
f31c9a8c 304 data, len);
a9b3a9f7 305
9ca21eb7
BZ		 306 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
307 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
a9b3a9f7 308
9ca21eb7
BZ		 309 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
310 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
a9b3a9f7
ID		 311
312 return 0;
313}
314
315/*
316 * Initialization functions.
317 */
318static bool rt2800pci_get_entry_state(struct queue_entry *entry)
319{
320 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
321 u32 word;
322
323 if (entry->queue->qid == QID_RX) {
324 rt2x00_desc_read(entry_priv->desc, 1, &word);
325
326 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
327 } else {
328 rt2x00_desc_read(entry_priv->desc, 1, &word);
329
330 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
331 }
332}
333
334static void rt2800pci_clear_entry(struct queue_entry *entry)
335{
336 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
337 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95192339 338 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
a9b3a9f7
ID		 339 u32 word;
340
341 if (entry->queue->qid == QID_RX) {
342 rt2x00_desc_read(entry_priv->desc, 0, &word);
343 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
344 rt2x00_desc_write(entry_priv->desc, 0, word);
345
346 rt2x00_desc_read(entry_priv->desc, 1, &word);
347 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
348 rt2x00_desc_write(entry_priv->desc, 1, word);
95192339
HS		 349
350 /*
351 * Set RX IDX in register to inform hardware that we have
352 * handled this entry and it is available for reuse again.
353 */
354 rt2800_register_write(rt2x00dev, RX_CRX_IDX,
355 entry->entry_idx);
a9b3a9f7
ID		 356 } else {
357 rt2x00_desc_read(entry_priv->desc, 1, &word);
358 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
359 rt2x00_desc_write(entry_priv->desc, 1, word);
360 }
361}
362
363static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
364{
365 struct queue_entry_priv_pci *entry_priv;
366 u32 reg;
367
a9b3a9f7
ID		 368 /*
369 * Initialize registers.
370 */
371 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
9ca21eb7
BZ		 372 rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
373 rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
374 rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
375 rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
a9b3a9f7
ID		 376
377 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
9ca21eb7
BZ		 378 rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
379 rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
380 rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
381 rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
a9b3a9f7
ID		 382
383 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
9ca21eb7
BZ		 384 rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
385 rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
386 rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
387 rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
a9b3a9f7
ID		 388
389 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
9ca21eb7
BZ		 390 rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
391 rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
392 rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
393 rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
a9b3a9f7
ID		 394
395 entry_priv = rt2x00dev->rx->entries[0].priv_data;
9ca21eb7
BZ		 396 rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
397 rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
398 rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
399 rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
a9b3a9f7
ID		 400
401 /*
402 * Enable global DMA configuration
403 */
9ca21eb7 404 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 405 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
406 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
407 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 408 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7 409
9ca21eb7 410 rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
a9b3a9f7
ID		 411
412 return 0;
413}
414
a9b3a9f7
ID		 415/*
416 * Device state switch handlers.
417 */
a9b3a9f7
ID		 418static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
419 enum dev_state state)
420{
b550911a 421 int mask = (state == STATE_RADIO_IRQ_ON);
a9b3a9f7 422 u32 reg;
a9d61e9e 423 unsigned long flags;
a9b3a9f7
ID		 424
425 /*
426 * When interrupts are being enabled, the interrupt registers
427 * should clear the register to assure a clean state.
428 */
429 if (state == STATE_RADIO_IRQ_ON) {
9ca21eb7
BZ		 430 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
431 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
c8e15a1e 432
a9d61e9e
HS		 433 /*
434 * Enable tasklets. The beacon related tasklets are
435 * enabled when the beacon queue is started.
436 */
c8e15a1e 437 tasklet_enable(&rt2x00dev->txstatus_tasklet);
a9d61e9e
HS		 438 tasklet_enable(&rt2x00dev->rxdone_tasklet);
439 tasklet_enable(&rt2x00dev->autowake_tasklet);
440 }
a9b3a9f7 441
a9d61e9e 442 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
9ca21eb7 443 rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
93149cf8
HS		 444 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, 0);
445 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, 0);
a9b3a9f7 446 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
93149cf8
HS		 447 rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, 0);
448 rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, 0);
449 rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, 0);
450 rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, 0);
451 rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, 0);
452 rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, 0);
453 rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, 0);
454 rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, 0);
a9b3a9f7
ID		 455 rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
456 rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
457 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
458 rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
93149cf8
HS		 459 rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, 0);
460 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, 0);
461 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, 0);
9ca21eb7 462 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
a9d61e9e
HS		 463 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
464
465 if (state == STATE_RADIO_IRQ_OFF) {
466 /*
467 * Ensure that all tasklets are finished before
468 * disabling the interrupts.
469 */
470 tasklet_disable(&rt2x00dev->txstatus_tasklet);
471 tasklet_disable(&rt2x00dev->rxdone_tasklet);
472 tasklet_disable(&rt2x00dev->autowake_tasklet);
473 }
a9b3a9f7
ID		 474}
475
e3a896b9
GW		 476static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
477{
478 u32 reg;
479
480 /*
481 * Reset DMA indexes
482 */
483 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
484 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
485 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
486 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
487 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
488 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
489 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
490 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
491 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
492
493 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
494 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
495
adde5882
GJ		 496 if (rt2x00_rt(rt2x00dev, RT5390)) {
497 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
498 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
499 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
500 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
501 }
60687ba7 502
e3a896b9
GW		 503 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
504
505 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
506 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
507 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
508 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
509
510 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
511
512 return 0;
513}
514
a9b3a9f7
ID		 515static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
516{
67a4c1e2 517 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
b9a07ae9 518 rt2800pci_init_queues(rt2x00dev)))
a9b3a9f7
ID		 519 return -EIO;
520
b9a07ae9 521 return rt2800_enable_radio(rt2x00dev);
a9b3a9f7
ID		 522}
523
524static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
525{
7f6e144f
RJH		 526 if (rt2x00_is_soc(rt2x00dev)) {
527 rt2800_disable_radio(rt2x00dev);
528 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
529 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
530 }
a9b3a9f7
ID		 531}
532
533static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
534 enum dev_state state)
535{
a9b3a9f7 536 if (state == STATE_AWAKE) {
7f6e144f 537 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0x02);
a9b3a9f7 538 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
7f6e144f
RJH		 539 } else if (state == STATE_SLEEP) {
540 rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, 0xffffffff);
541 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, 0xffffffff);
542 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0x01, 0xff, 0x01);
a9b3a9f7
ID		 543 }
544
545 return 0;
546}
547
548static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
549 enum dev_state state)
550{
551 int retval = 0;
552
553 switch (state) {
554 case STATE_RADIO_ON:
555 /*
556 * Before the radio can be enabled, the device first has
557 * to be woken up. After that it needs a bit of time
558 * to be fully awake and then the radio can be enabled.
559 */
560 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
561 msleep(1);
562 retval = rt2800pci_enable_radio(rt2x00dev);
563 break;
564 case STATE_RADIO_OFF:
565 /*
566 * After the radio has been disabled, the device should
567 * be put to sleep for powersaving.
568 */
569 rt2800pci_disable_radio(rt2x00dev);
570 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
571 break;
a9b3a9f7
ID		 572 case STATE_RADIO_IRQ_ON:
573 case STATE_RADIO_IRQ_OFF:
574 rt2800pci_toggle_irq(rt2x00dev, state);
575 break;
576 case STATE_DEEP_SLEEP:
577 case STATE_SLEEP:
578 case STATE_STANDBY:
579 case STATE_AWAKE:
580 retval = rt2800pci_set_state(rt2x00dev, state);
581 break;
582 default:
583 retval = -ENOTSUPP;
584 break;
585 }
586
587 if (unlikely(retval))
588 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
589 state, retval);
590
591 return retval;
592}
593
594/*
595 * TX descriptor initialization
596 */
0c5879bc 597static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)
a9b3a9f7 598{
0c5879bc 599 return (__le32 *) entry->skb->data;
745b1ae3
HS		 600}
601
93331458 602static void rt2800pci_write_tx_desc(struct queue_entry *entry,
745b1ae3
HS		 603 struct txentry_desc *txdesc)
604{
93331458
ID		 605 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
606 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
85b7a8b3 607 __le32 *txd = entry_priv->desc;
745b1ae3
HS		 608 u32 word;
609
a9b3a9f7
ID		 610 /*
611 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
612 * must contains a TXWI structure + 802.11 header + padding + 802.11
613 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
614 * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
615 * data. It means that LAST_SEC0 is always 0.
616 */
617
618 /*
619 * Initialize TX descriptor
620 */
621 rt2x00_desc_read(txd, 0, &word);
622 rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
623 rt2x00_desc_write(txd, 0, word);
624
625 rt2x00_desc_read(txd, 1, &word);
93331458 626 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);
a9b3a9f7
ID		 627 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
628 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
629 rt2x00_set_field32(&word, TXD_W1_BURST,
630 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
85b7a8b3 631 rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
a9b3a9f7
ID		 632 rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
633 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
634 rt2x00_desc_write(txd, 1, word);
635
636 rt2x00_desc_read(txd, 2, &word);
637 rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
85b7a8b3 638 skbdesc->skb_dma + TXWI_DESC_SIZE);
a9b3a9f7
ID		 639 rt2x00_desc_write(txd, 2, word);
640
641 rt2x00_desc_read(txd, 3, &word);
642 rt2x00_set_field32(&word, TXD_W3_WIV,
643 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
644 rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
645 rt2x00_desc_write(txd, 3, word);
85b7a8b3
GW		 646
647 /*
648 * Register descriptor details in skb frame descriptor.
649 */
650 skbdesc->desc = txd;
651 skbdesc->desc_len = TXD_DESC_SIZE;
a9b3a9f7
ID		 652}
653
a9b3a9f7
ID		 654/*
655 * RX control handlers
656 */
657static void rt2800pci_fill_rxdone(struct queue_entry *entry,
658 struct rxdone_entry_desc *rxdesc)
659{
a9b3a9f7
ID		 660 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
661 __le32 *rxd = entry_priv->desc;
2de64dd2
GW		 662 u32 word;
663
664 rt2x00_desc_read(rxd, 3, &word);
665
666 if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
a9b3a9f7
ID		 667 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
668
78b8f3b0
GW		 669 /*
670 * Unfortunately we don't know the cipher type used during
671 * decryption. This prevents us from correct providing
672 * correct statistics through debugfs.
673 */
2de64dd2 674 rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
a9b3a9f7 675
2de64dd2 676 if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
a9b3a9f7
ID		 677 /*
678 * Hardware has stripped IV/EIV data from 802.11 frame during
679 * decryption. Unfortunately the descriptor doesn't contain
680 * any fields with the EIV/IV data either, so they can't
681 * be restored by rt2x00lib.
682 */
683 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
684
a45f369d
GW		 685 /*
686 * The hardware has already checked the Michael Mic and has
687 * stripped it from the frame. Signal this to mac80211.
688 */
689 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
690
a9b3a9f7
ID		 691 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
692 rxdesc->flags |= RX_FLAG_DECRYPTED;
693 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
694 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
695 }
696
2de64dd2 697 if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
a9b3a9f7
ID		 698 rxdesc->dev_flags |= RXDONE_MY_BSS;
699
2de64dd2 700 if (rt2x00_get_field32(word, RXD_W3_L2PAD))
a9b3a9f7 701 rxdesc->dev_flags |= RXDONE_L2PAD;
a9b3a9f7 702
a9b3a9f7 703 /*
2de64dd2 704 * Process the RXWI structure that is at the start of the buffer.
a9b3a9f7 705 */
74861922 706 rt2800_process_rxwi(entry, rxdesc);
a9b3a9f7
ID		 707}
708
709/*
710 * Interrupt functions.
711 */
4d66edc8
GW		 712static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
713{
714 struct ieee80211_conf conf = { .flags = 0 };
715 struct rt2x00lib_conf libconf = { .conf = &conf };
716
717 rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
718}
719
2e7798b7 720static bool rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
96c3da7d
HS		 721{
722 struct data_queue *queue;
723 struct queue_entry *entry;
724 u32 status;
725 u8 qid;
2e7798b7 726 int max_tx_done = 16;
96c3da7d 727
c4d63244 728 while (kfifo_get(&rt2x00dev->txstatus_fifo, &status)) {
12eec2cc 729 qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
87443e87 730 if (unlikely(qid >= QID_RX)) {
96c3da7d
HS		 731 /*
732 * Unknown queue, this shouldn't happen. Just drop
733 * this tx status.
734 */
735 WARNING(rt2x00dev, "Got TX status report with "
094a1d92 736 "unexpected pid %u, dropping\n", qid);
96c3da7d
HS		 737 break;
738 }
739
11f818e0 740 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
96c3da7d
HS		 741 if (unlikely(queue == NULL)) {
742 /*
743 * The queue is NULL, this shouldn't happen. Stop
744 * processing here and drop the tx status
745 */
746 WARNING(rt2x00dev, "Got TX status for an unavailable "
094a1d92 747 "queue %u, dropping\n", qid);
96c3da7d
HS		 748 break;
749 }
750
87443e87 751 if (unlikely(rt2x00queue_empty(queue))) {
96c3da7d
HS		 752 /*
753 * The queue is empty. Stop processing here
754 * and drop the tx status.
755 */
756 WARNING(rt2x00dev, "Got TX status for an empty "
094a1d92 757 "queue %u, dropping\n", qid);
96c3da7d
HS		 758 break;
759 }
760
761 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
762 rt2800_txdone_entry(entry, status);
2e7798b7
HS		 763
764 if (--max_tx_done == 0)
765 break;
96c3da7d 766 }
2e7798b7
HS		 767
768 return !max_tx_done;
96c3da7d
HS		 769}
770
a9d61e9e
HS		 771static void rt2800pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
772 struct rt2x00_field32 irq_field)
a9b3a9f7 773{
a9d61e9e 774 u32 reg;
a9b3a9f7
ID		 775
776 /*
a9d61e9e
HS		 777 * Enable a single interrupt. The interrupt mask register
778 * access needs locking.
9f926fb5 779 */
0aa13b2e 780 spin_lock_irq(&rt2x00dev->irqmask_lock);
a9d61e9e
HS		 781 rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
782 rt2x00_set_field32(&reg, irq_field, 1);
783 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
0aa13b2e 784 spin_unlock_irq(&rt2x00dev->irqmask_lock);
a9d61e9e 785}
9f926fb5 786
a9d61e9e
HS		 787static void rt2800pci_txstatus_tasklet(unsigned long data)
788{
2e7798b7
HS		 789 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
790 if (rt2800pci_txdone(rt2x00dev))
791 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
9f926fb5
HS		 792
793 /*
a9d61e9e
HS		 794 * No need to enable the tx status interrupt here as we always
795 * leave it enabled to minimize the possibility of a tx status
796 * register overflow. See comment in interrupt handler.
a9b3a9f7 797 */
a9d61e9e 798}
a9b3a9f7 799
a9d61e9e
HS		 800static void rt2800pci_pretbtt_tasklet(unsigned long data)
801{
802 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
803 rt2x00lib_pretbtt(rt2x00dev);
804 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_PRE_TBTT);
805}
4d66edc8 806
a9d61e9e
HS		 807static void rt2800pci_tbtt_tasklet(unsigned long data)
808{
809 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
810 rt2x00lib_beacondone(rt2x00dev);
811 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TBTT);
812}
78e256c9 813
a9d61e9e
HS		 814static void rt2800pci_rxdone_tasklet(unsigned long data)
815{
816 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
16638937
HS		 817 if (rt2x00pci_rxdone(rt2x00dev))
818 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
819 else
820 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RX_DONE);
a9d61e9e
HS		 821}
822
823static void rt2800pci_autowake_tasklet(unsigned long data)
824{
825 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
826 rt2800pci_wakeup(rt2x00dev);
827 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_AUTO_WAKEUP);
a9b3a9f7
ID		 828}
829
96c3da7d
HS		 830static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
831{
832 u32 status;
833 int i;
834
835 /*
836 * The TX_FIFO_STATUS interrupt needs special care. We should
837 * read TX_STA_FIFO but we should do it immediately as otherwise
838 * the register can overflow and we would lose status reports.
839 *
840 * Hence, read the TX_STA_FIFO register and copy all tx status
841 * reports into a kernel FIFO which is handled in the txstatus
842 * tasklet. We use a tasklet to process the tx status reports
843 * because we can schedule the tasklet multiple times (when the
844 * interrupt fires again during tx status processing).
845 *
846 * Furthermore we don't disable the TX_FIFO_STATUS
847 * interrupt here but leave it enabled so that the TX_STA_FIFO
3736fe58 848 * can also be read while the tx status tasklet gets executed.
96c3da7d
HS		 849 *
850 * Since we have only one producer and one consumer we don't
851 * need to lock the kfifo.
852 */
efd2f271 853 for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
96c3da7d
HS		 854 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &status);
855
856 if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
857 break;
858
c4d63244 859 if (!kfifo_put(&rt2x00dev->txstatus_fifo, &status)) {
96c3da7d
HS		 860 WARNING(rt2x00dev, "TX status FIFO overrun,"
861 "drop tx status report.\n");
862 break;
863 }
864 }
865
866 /* Schedule the tasklet for processing the tx status. */
867 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
868}
869
78e256c9
HS		 870static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
871{
872 struct rt2x00_dev *rt2x00dev = dev_instance;
a9d61e9e 873 u32 reg, mask;
78e256c9
HS		 874
875 /* Read status and ACK all interrupts */
876 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
877 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
878
879 if (!reg)
880 return IRQ_NONE;
881
882 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
883 return IRQ_HANDLED;
884
a9d61e9e
HS		 885 /*
886 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
887 * for interrupts and interrupt masks we can just use the value of
888 * INT_SOURCE_CSR to create the interrupt mask.
889 */
890 mask = ~reg;
78e256c9 891
a9d61e9e
HS		 892 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) {
893 rt2800pci_txstatus_interrupt(rt2x00dev);
96c3da7d 894 /*
a9d61e9e 895 * Never disable the TX_FIFO_STATUS interrupt.
96c3da7d 896 */
a9d61e9e
HS		 897 rt2x00_set_field32(&mask, INT_MASK_CSR_TX_FIFO_STATUS, 1);
898 }
96c3da7d 899
a9d61e9e
HS		 900 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
901 tasklet_hi_schedule(&rt2x00dev->pretbtt_tasklet);
78e256c9 902
a9d61e9e
HS		 903 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
904 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
96c3da7d 905
a9d61e9e
HS		 906 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
907 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
78e256c9 908
a9d61e9e
HS		 909 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
910 tasklet_schedule(&rt2x00dev->autowake_tasklet);
911
912 /*
913 * Disable all interrupts for which a tasklet was scheduled right now,
914 * the tasklet will reenable the appropriate interrupts.
915 */
0aa13b2e 916 spin_lock(&rt2x00dev->irqmask_lock);
a9d61e9e
HS		 917 rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
918 reg &= mask;
919 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
0aa13b2e 920 spin_unlock(&rt2x00dev->irqmask_lock);
a9d61e9e
HS		 921
922 return IRQ_HANDLED;
78e256c9
HS		 923}
924
a9b3a9f7
ID		 925/*
926 * Device probe functions.
927 */
7ab71325
BZ		 928static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
929{
930 /*
931 * Read EEPROM into buffer
932 */
cea90e55 933 if (rt2x00_is_soc(rt2x00dev))
7ab71325 934 rt2800pci_read_eeprom_soc(rt2x00dev);
cea90e55
GW		 935 else if (rt2800pci_efuse_detect(rt2x00dev))
936 rt2800pci_read_eeprom_efuse(rt2x00dev);
937 else
938 rt2800pci_read_eeprom_pci(rt2x00dev);
7ab71325
BZ		 939
940 return rt2800_validate_eeprom(rt2x00dev);
941}
942
a9b3a9f7
ID		 943static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
944{
945 int retval;
946
947 /*
948 * Allocate eeprom data.
949 */
950 retval = rt2800pci_validate_eeprom(rt2x00dev);
951 if (retval)
952 return retval;
953
38bd7b8a 954 retval = rt2800_init_eeprom(rt2x00dev);
a9b3a9f7
ID		 955 if (retval)
956 return retval;
957
958 /*
959 * Initialize hw specifications.
960 */
4da2933f 961 retval = rt2800_probe_hw_mode(rt2x00dev);
a9b3a9f7
ID		 962 if (retval)
963 return retval;
964
965 /*
966 * This device has multiple filters for control frames
967 * and has a separate filter for PS Poll frames.
968 */
969 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
970 __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
971
9f926fb5
HS		 972 /*
973 * This device has a pre tbtt interrupt and thus fetches
974 * a new beacon directly prior to transmission.
975 */
976 __set_bit(DRIVER_SUPPORT_PRE_TBTT_INTERRUPT, &rt2x00dev->flags);
977
a9b3a9f7
ID		 978 /*
979 * This device requires firmware.
980 */
cea90e55 981 if (!rt2x00_is_soc(rt2x00dev))
a9b3a9f7
ID		 982 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
983 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
984 __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
96c3da7d 985 __set_bit(DRIVER_REQUIRE_TXSTATUS_FIFO, &rt2x00dev->flags);
20ed3166 986 __set_bit(DRIVER_REQUIRE_TASKLET_CONTEXT, &rt2x00dev->flags);
a9b3a9f7
ID		 987 if (!modparam_nohwcrypt)
988 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
27df2a9c 989 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
26a1d07f 990 __set_bit(DRIVER_REQUIRE_HT_TX_DESC, &rt2x00dev->flags);
a9b3a9f7
ID		 991
992 /*
993 * Set the rssi offset.
994 */
995 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
996
997 return 0;
998}
999
e783619e
HS		 1000static const struct ieee80211_ops rt2800pci_mac80211_ops = {
1001 .tx = rt2x00mac_tx,
1002 .start = rt2x00mac_start,
1003 .stop = rt2x00mac_stop,
1004 .add_interface = rt2x00mac_add_interface,
1005 .remove_interface = rt2x00mac_remove_interface,
1006 .config = rt2x00mac_config,
1007 .configure_filter = rt2x00mac_configure_filter,
e783619e
HS		 1008 .set_key = rt2x00mac_set_key,
1009 .sw_scan_start = rt2x00mac_sw_scan_start,
1010 .sw_scan_complete = rt2x00mac_sw_scan_complete,
1011 .get_stats = rt2x00mac_get_stats,
1012 .get_tkip_seq = rt2800_get_tkip_seq,
1013 .set_rts_threshold = rt2800_set_rts_threshold,
1014 .bss_info_changed = rt2x00mac_bss_info_changed,
1015 .conf_tx = rt2800_conf_tx,
1016 .get_tsf = rt2800_get_tsf,
1017 .rfkill_poll = rt2x00mac_rfkill_poll,
1018 .ampdu_action = rt2800_ampdu_action,
f44df18c 1019 .flush = rt2x00mac_flush,
977206d7 1020 .get_survey = rt2800_get_survey,
e783619e
HS		 1021};
1022
e796643e
ID		 1023static const struct rt2800_ops rt2800pci_rt2800_ops = {
1024 .register_read = rt2x00pci_register_read,
1025 .register_read_lock = rt2x00pci_register_read, /* same for PCI */
1026 .register_write = rt2x00pci_register_write,
1027 .register_write_lock = rt2x00pci_register_write, /* same for PCI */
1028 .register_multiread = rt2x00pci_register_multiread,
1029 .register_multiwrite = rt2x00pci_register_multiwrite,
1030 .regbusy_read = rt2x00pci_regbusy_read,
1031 .drv_write_firmware = rt2800pci_write_firmware,
1032 .drv_init_registers = rt2800pci_init_registers,
0c5879bc 1033 .drv_get_txwi = rt2800pci_get_txwi,
e796643e
ID		 1034};
1035
a9b3a9f7
ID		 1036static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1037 .irq_handler = rt2800pci_interrupt,
a9d61e9e
HS		 1038 .txstatus_tasklet = rt2800pci_txstatus_tasklet,
1039 .pretbtt_tasklet = rt2800pci_pretbtt_tasklet,
1040 .tbtt_tasklet = rt2800pci_tbtt_tasklet,
1041 .rxdone_tasklet = rt2800pci_rxdone_tasklet,
1042 .autowake_tasklet = rt2800pci_autowake_tasklet,
a9b3a9f7
ID		 1043 .probe_hw = rt2800pci_probe_hw,
1044 .get_firmware_name = rt2800pci_get_firmware_name,
f31c9a8c
ID		 1045 .check_firmware = rt2800_check_firmware,
1046 .load_firmware = rt2800_load_firmware,
a9b3a9f7
ID		 1047 .initialize = rt2x00pci_initialize,
1048 .uninitialize = rt2x00pci_uninitialize,
1049 .get_entry_state = rt2800pci_get_entry_state,
1050 .clear_entry = rt2800pci_clear_entry,
1051 .set_device_state = rt2800pci_set_device_state,
f4450616
BZ		 1052 .rfkill_poll = rt2800_rfkill_poll,
1053 .link_stats = rt2800_link_stats,
1054 .reset_tuner = rt2800_reset_tuner,
1055 .link_tuner = rt2800_link_tuner,
9e33a355 1056 .gain_calibration = rt2800_gain_calibration,
dbba306f
ID		 1057 .start_queue = rt2800pci_start_queue,
1058 .kick_queue = rt2800pci_kick_queue,
1059 .stop_queue = rt2800pci_stop_queue,
a9b3a9f7 1060 .write_tx_desc = rt2800pci_write_tx_desc,
0c5879bc 1061 .write_tx_data = rt2800_write_tx_data,
f0194b2d 1062 .write_beacon = rt2800_write_beacon,
69cf36a4 1063 .clear_beacon = rt2800_clear_beacon,
a9b3a9f7 1064 .fill_rxdone = rt2800pci_fill_rxdone,
f4450616
BZ		 1065 .config_shared_key = rt2800_config_shared_key,
1066 .config_pairwise_key = rt2800_config_pairwise_key,
1067 .config_filter = rt2800_config_filter,
1068 .config_intf = rt2800_config_intf,
1069 .config_erp = rt2800_config_erp,
1070 .config_ant = rt2800_config_ant,
1071 .config = rt2800_config,
a9b3a9f7
ID		 1072};
1073
1074static const struct data_queue_desc rt2800pci_queue_rx = {
efd2f271 1075 .entry_num = 128,
a9b3a9f7
ID		 1076 .data_size = AGGREGATION_SIZE,
1077 .desc_size = RXD_DESC_SIZE,
1078 .priv_size = sizeof(struct queue_entry_priv_pci),
1079};
1080
1081static const struct data_queue_desc rt2800pci_queue_tx = {
efd2f271 1082 .entry_num = 64,
a9b3a9f7
ID		 1083 .data_size = AGGREGATION_SIZE,
1084 .desc_size = TXD_DESC_SIZE,
1085 .priv_size = sizeof(struct queue_entry_priv_pci),
1086};
1087
1088static const struct data_queue_desc rt2800pci_queue_bcn = {
efd2f271 1089 .entry_num = 8,
a9b3a9f7
ID		 1090 .data_size = 0, /* No DMA required for beacons */
1091 .desc_size = TXWI_DESC_SIZE,
1092 .priv_size = sizeof(struct queue_entry_priv_pci),
1093};
1094
1095static const struct rt2x00_ops rt2800pci_ops = {
04d0362e
GW		 1096 .name = KBUILD_MODNAME,
1097 .max_sta_intf = 1,
1098 .max_ap_intf = 8,
1099 .eeprom_size = EEPROM_SIZE,
1100 .rf_size = RF_SIZE,
1101 .tx_queues = NUM_TX_QUEUES,
e6218cc4 1102 .extra_tx_headroom = TXWI_DESC_SIZE,
04d0362e
GW		 1103 .rx = &rt2800pci_queue_rx,
1104 .tx = &rt2800pci_queue_tx,
1105 .bcn = &rt2800pci_queue_bcn,
1106 .lib = &rt2800pci_rt2x00_ops,
e796643e 1107 .drv = &rt2800pci_rt2800_ops,
e783619e 1108 .hw = &rt2800pci_mac80211_ops,
a9b3a9f7 1109#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 1110 .debugfs = &rt2800_rt2x00debug,
a9b3a9f7
ID		 1111#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1112};
1113
1114/*
1115 * RT2800pci module information.
1116 */
72c7296e 1117#ifdef CONFIG_PCI
a3aa1884 1118static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
de1ebdce
GW		 1119 { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
1120 { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
1121 { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
1122 { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
a6a8d66e
GW		 1123 { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
1124 { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
1125 { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
a9b3a9f7
ID		 1126 { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
1127 { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
1128 { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
1129 { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
1130 { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
1131 { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
1132 { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
de1ebdce 1133 { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
a6a8d66e 1134 { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
f93bc9b3
GW		 1135#ifdef CONFIG_RT2800PCI_RT33XX
1136 { PCI_DEVICE(0x1814, 0x3390), PCI_DEVICE_DATA(&rt2800pci_ops) },
1137#endif
de1ebdce 1138#ifdef CONFIG_RT2800PCI_RT35XX
00781a74
XVP		 1139 { PCI_DEVICE(0x1432, 0x7711), PCI_DEVICE_DATA(&rt2800pci_ops) },
1140 { PCI_DEVICE(0x1432, 0x7722), PCI_DEVICE_DATA(&rt2800pci_ops) },
de1ebdce
GW		 1141 { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
1142 { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
a9b3a9f7
ID		 1143 { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
1144 { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
6424bf70 1145 { PCI_DEVICE(0x1814, 0x3593), PCI_DEVICE_DATA(&rt2800pci_ops) },
60687ba7
RST		 1146#endif
1147#ifdef CONFIG_RT2800PCI_RT53XX
adde5882 1148 { PCI_DEVICE(0x1814, 0x5390), PCI_DEVICE_DATA(&rt2800pci_ops) },
de1ebdce 1149#endif
a9b3a9f7
ID		 1150 { 0, }
1151};
72c7296e 1152#endif /* CONFIG_PCI */
a9b3a9f7
ID		 1153
1154MODULE_AUTHOR(DRV_PROJECT);
1155MODULE_VERSION(DRV_VERSION);
1156MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1157MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
72c7296e 1158#ifdef CONFIG_PCI
a9b3a9f7
ID		 1159MODULE_FIRMWARE(FIRMWARE_RT2860);
1160MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
72c7296e 1161#endif /* CONFIG_PCI */
a9b3a9f7
ID		 1162MODULE_LICENSE("GPL");
1163
72c7296e 1164#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
714fa663
GW		 1165static int rt2800soc_probe(struct platform_device *pdev)
1166{
6e93d719 1167 return rt2x00soc_probe(pdev, &rt2800pci_ops);
714fa663 1168}
a9b3a9f7
ID		 1169
1170static struct platform_driver rt2800soc_driver = {
1171 .driver = {
1172 .name = "rt2800_wmac",
1173 .owner = THIS_MODULE,
1174 .mod_name = KBUILD_MODNAME,
1175 },
714fa663 1176 .probe = rt2800soc_probe,
a9b3a9f7
ID		 1177 .remove = __devexit_p(rt2x00soc_remove),
1178 .suspend = rt2x00soc_suspend,
1179 .resume = rt2x00soc_resume,
1180};
72c7296e 1181#endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
a9b3a9f7 1182
72c7296e 1183#ifdef CONFIG_PCI
a9b3a9f7
ID		 1184static struct pci_driver rt2800pci_driver = {
1185 .name = KBUILD_MODNAME,
1186 .id_table = rt2800pci_device_table,
1187 .probe = rt2x00pci_probe,
1188 .remove = __devexit_p(rt2x00pci_remove),
1189 .suspend = rt2x00pci_suspend,
1190 .resume = rt2x00pci_resume,
1191};
72c7296e 1192#endif /* CONFIG_PCI */
a9b3a9f7
ID		 1193
1194static int __init rt2800pci_init(void)
1195{
1196 int ret = 0;
1197
72c7296e 1198#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
a9b3a9f7
ID		 1199 ret = platform_driver_register(&rt2800soc_driver);
1200 if (ret)
1201 return ret;
1202#endif
72c7296e 1203#ifdef CONFIG_PCI
a9b3a9f7
ID		 1204 ret = pci_register_driver(&rt2800pci_driver);
1205 if (ret) {
72c7296e 1206#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
a9b3a9f7
ID		 1207 platform_driver_unregister(&rt2800soc_driver);
1208#endif
1209 return ret;
1210 }
1211#endif
1212
1213 return ret;
1214}
1215
1216static void __exit rt2800pci_exit(void)
1217{
72c7296e 1218#ifdef CONFIG_PCI
a9b3a9f7
ID		 1219 pci_unregister_driver(&rt2800pci_driver);
1220#endif
72c7296e 1221#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
a9b3a9f7
ID		 1222 platform_driver_unregister(&rt2800soc_driver);
1223#endif
1224}
1225
1226module_init(rt2800pci_init);
1227module_exit(rt2800pci_exit);
Linux kernel - Deliverables
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