projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| a9b3a9f7 | 1 | /* |
| 96481b20 | 2 | Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com> |
| 9c9a0d14 GW |
3 | Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> |
| 4 | Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> | |
| 5 | Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> | |
| 6 | Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de> | |
| 7 | Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com> | |
| 8 | Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com> | |
| 9 | Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com> | |
| a9b3a9f7 ID |
10 | <http://rt2x00.serialmonkey.com> |
| 11 | ||
| 12 | This program is free software; you can redistribute it and/or modify | |
| 13 | it under the terms of the GNU General Public License as published by | |
| 14 | the Free Software Foundation; either version 2 of the License, or | |
| 15 | (at your option) any later version. | |
| 16 | ||
| 17 | This program is distributed in the hope that it will be useful, | |
| 18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 20 | GNU General Public License for more details. | |
| 21 | ||
| 22 | You should have received a copy of the GNU General Public License | |
| 23 | along with this program; if not, write to the | |
| 24 | Free Software Foundation, Inc., | |
| 25 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
| 26 | */ | |
| 27 | ||
| 28 | /* | |
| 29 | Module: rt2800pci | |
| 30 | Abstract: rt2800pci device specific routines. | |
| 31 | Supported chipsets: RT2800E & RT2800ED. | |
| 32 | */ | |
| 33 | ||
| a9b3a9f7 ID |
34 | #include <linux/delay.h> |
| 35 | #include <linux/etherdevice.h> | |
| 36 | #include <linux/init.h> | |
| 37 | #include <linux/kernel.h> | |
| 38 | #include <linux/module.h> | |
| 39 | #include <linux/pci.h> | |
| 40 | #include <linux/platform_device.h> | |
| 41 | #include <linux/eeprom_93cx6.h> | |
| 42 | ||
| 43 | #include "rt2x00.h" | |
| 69a2bac8 | 44 | #include "rt2x00mmio.h" |
| a9b3a9f7 ID |
45 | #include "rt2x00pci.h" |
| 46 | #include "rt2x00soc.h" | |
| 7ef5cc92 | 47 | #include "rt2800lib.h" |
| 0bc202b3 | 48 | #include "rt2800mmio.h" |
| b54f78a8 | 49 | #include "rt2800.h" |
| a9b3a9f7 ID |
50 | #include "rt2800pci.h" |
| 51 | ||
| a9b3a9f7 ID |
52 | /* |
| 53 | * Allow hardware encryption to be disabled. | |
| 54 | */ | |
| eb939922 | 55 | static bool modparam_nohwcrypt = false; |
| a9b3a9f7 ID |
56 | module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO); |
| 57 | MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); | |
| 58 | ||
| ad417a53 GW |
59 | static bool rt2800pci_hwcrypt_disabled(struct rt2x00_dev *rt2x00dev) |
| 60 | { | |
| 61 | return modparam_nohwcrypt; | |
| 62 | } | |
| 63 | ||
| a9b3a9f7 ID |
64 | static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token) |
| 65 | { | |
| 66 | unsigned int i; | |
| 67 | u32 reg; | |
| 68 | ||
| f18d4463 LC |
69 | /* |
| 70 | * SOC devices don't support MCU requests. | |
| 71 | */ | |
| 72 | if (rt2x00_is_soc(rt2x00dev)) | |
| 73 | return; | |
| 74 | ||
| a9b3a9f7 | 75 | for (i = 0; i < 200; i++) { |
| b9570b66 | 76 | rt2x00mmio_register_read(rt2x00dev, H2M_MAILBOX_CID, ®); |
| a9b3a9f7 ID |
77 | |
| 78 | if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) || | |
| 79 | (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) || | |
| 80 | (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) || | |
| 81 | (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token)) | |
| 82 | break; | |
| 83 | ||
| 84 | udelay(REGISTER_BUSY_DELAY); | |
| 85 | } | |
| 86 | ||
| 87 | if (i == 200) | |
| ec9c4989 | 88 | rt2x00_err(rt2x00dev, "MCU request failed, no response from hardware\n"); |
| a9b3a9f7 | 89 | |
| b9570b66 GJ |
90 | rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0); |
| 91 | rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0); | |
| a9b3a9f7 ID |
92 | } |
| 93 | ||
| 72c7296e | 94 | #ifdef CONFIG_PCI |
| a9b3a9f7 ID |
95 | static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom) |
| 96 | { | |
| 97 | struct rt2x00_dev *rt2x00dev = eeprom->data; | |
| 98 | u32 reg; | |
| 99 | ||
| b9570b66 | 100 | rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, ®); |
| a9b3a9f7 ID |
101 | |
| 102 | eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN); | |
| 103 | eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT); | |
| 104 | eeprom->reg_data_clock = | |
| 105 | !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK); | |
| 106 | eeprom->reg_chip_select = | |
| 107 | !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT); | |
| 108 | } | |
| 109 | ||
| 110 | static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom) | |
| 111 | { | |
| 112 | struct rt2x00_dev *rt2x00dev = eeprom->data; | |
| 113 | u32 reg = 0; | |
| 114 | ||
| 115 | rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in); | |
| 116 | rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out); | |
| 117 | rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, | |
| 118 | !!eeprom->reg_data_clock); | |
| 119 | rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT, | |
| 120 | !!eeprom->reg_chip_select); | |
| 121 | ||
| b9570b66 | 122 | rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg); |
| a9b3a9f7 ID |
123 | } |
| 124 | ||
| a02308e9 | 125 | static int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev) |
| a9b3a9f7 ID |
126 | { |
| 127 | struct eeprom_93cx6 eeprom; | |
| 128 | u32 reg; | |
| 129 | ||
| b9570b66 | 130 | rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, ®); |
| a9b3a9f7 ID |
131 | |
| 132 | eeprom.data = rt2x00dev; | |
| 133 | eeprom.register_read = rt2800pci_eepromregister_read; | |
| 134 | eeprom.register_write = rt2800pci_eepromregister_write; | |
| 20f8b139 GW |
135 | switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE)) |
| 136 | { | |
| 137 | case 0: | |
| 138 | eeprom.width = PCI_EEPROM_WIDTH_93C46; | |
| 139 | break; | |
| 140 | case 1: | |
| 141 | eeprom.width = PCI_EEPROM_WIDTH_93C66; | |
| 142 | break; | |
| 143 | default: | |
| 144 | eeprom.width = PCI_EEPROM_WIDTH_93C86; | |
| 145 | break; | |
| 146 | } | |
| a9b3a9f7 ID |
147 | eeprom.reg_data_in = 0; |
| 148 | eeprom.reg_data_out = 0; | |
| 149 | eeprom.reg_data_clock = 0; | |
| 150 | eeprom.reg_chip_select = 0; | |
| 151 | ||
| 152 | eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom, | |
| 153 | EEPROM_SIZE / sizeof(u16)); | |
| a02308e9 GJ |
154 | |
| 155 | return 0; | |
| a9b3a9f7 ID |
156 | } |
| 157 | ||
| a6598682 GW |
158 | static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev) |
| 159 | { | |
| 30e84034 | 160 | return rt2800_efuse_detect(rt2x00dev); |
| a9b3a9f7 ID |
161 | } |
| 162 | ||
| a02308e9 | 163 | static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev) |
| a9b3a9f7 | 164 | { |
| a02308e9 | 165 | return rt2800_read_eeprom_efuse(rt2x00dev); |
| a9b3a9f7 | 166 | } |
| 72c7296e | 167 | #endif /* CONFIG_PCI */ |
| a9b3a9f7 | 168 | |
| a9b3a9f7 ID |
169 | /* |
| 170 | * Firmware functions | |
| 171 | */ | |
| 172 | static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev) | |
| 173 | { | |
| a89534ed WH |
174 | /* |
| 175 | * Chip rt3290 use specific 4KB firmware named rt3290.bin. | |
| 176 | */ | |
| 177 | if (rt2x00_rt(rt2x00dev, RT3290)) | |
| 178 | return FIRMWARE_RT3290; | |
| 179 | else | |
| 180 | return FIRMWARE_RT2860; | |
| a9b3a9f7 ID |
181 | } |
| 182 | ||
| f31c9a8c | 183 | static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev, |
| a9b3a9f7 ID |
184 | const u8 *data, const size_t len) |
| 185 | { | |
| a9b3a9f7 ID |
186 | u32 reg; |
| 187 | ||
| a9b3a9f7 ID |
188 | /* |
| 189 | * enable Host program ram write selection | |
| 190 | */ | |
| 191 | reg = 0; | |
| 192 | rt2x00_set_field32(®, PBF_SYS_CTRL_HOST_RAM_WRITE, 1); | |
| b9570b66 | 193 | rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, reg); |
| a9b3a9f7 ID |
194 | |
| 195 | /* | |
| 196 | * Write firmware to device. | |
| 197 | */ | |
| b9570b66 GJ |
198 | rt2x00mmio_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, |
| 199 | data, len); | |
| a9b3a9f7 | 200 | |
| b9570b66 GJ |
201 | rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000); |
| 202 | rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001); | |
| a9b3a9f7 | 203 | |
| b9570b66 GJ |
204 | rt2x00mmio_register_write(rt2x00dev, H2M_BBP_AGENT, 0); |
| 205 | rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); | |
| a9b3a9f7 ID |
206 | |
| 207 | return 0; | |
| 208 | } | |
| 209 | ||
| a9b3a9f7 ID |
210 | /* |
| 211 | * Device state switch handlers. | |
| 212 | */ | |
| a9b3a9f7 ID |
213 | static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev) |
| 214 | { | |
| e8b461c3 JK |
215 | int retval; |
| 216 | ||
| 52b8243b JK |
217 | /* Wait for DMA, ignore error until we initialize queues. */ |
| 218 | rt2800_wait_wpdma_ready(rt2x00dev); | |
| 219 | ||
| 7573afdf | 220 | if (unlikely(rt2800mmio_init_queues(rt2x00dev))) |
| a9b3a9f7 ID |
221 | return -EIO; |
| 222 | ||
| e8b461c3 JK |
223 | retval = rt2800_enable_radio(rt2x00dev); |
| 224 | if (retval) | |
| 225 | return retval; | |
| 226 | ||
| 227 | /* After resume MCU_BOOT_SIGNAL will trash these. */ | |
| b9570b66 GJ |
228 | rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0); |
| 229 | rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0); | |
| e8b461c3 JK |
230 | |
| 231 | rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_RADIO_OFF, 0xff, 0x02); | |
| 232 | rt2800pci_mcu_status(rt2x00dev, TOKEN_RADIO_OFF); | |
| 233 | ||
| 234 | rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP, 0, 0); | |
| 235 | rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP); | |
| 236 | ||
| 237 | return retval; | |
| a9b3a9f7 ID |
238 | } |
| 239 | ||
| 240 | static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev) | |
| 241 | { | |
| 7f6e144f RJH |
242 | if (rt2x00_is_soc(rt2x00dev)) { |
| 243 | rt2800_disable_radio(rt2x00dev); | |
| b9570b66 GJ |
244 | rt2x00mmio_register_write(rt2x00dev, PWR_PIN_CFG, 0); |
| 245 | rt2x00mmio_register_write(rt2x00dev, TX_PIN_CFG, 0); | |
| 7f6e144f | 246 | } |
| a9b3a9f7 ID |
247 | } |
| 248 | ||
| 249 | static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev, | |
| 250 | enum dev_state state) | |
| 251 | { | |
| a9b3a9f7 | 252 | if (state == STATE_AWAKE) { |
| 09a3311c JK |
253 | rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP, |
| 254 | 0, 0x02); | |
| 255 | rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP); | |
| 7f6e144f | 256 | } else if (state == STATE_SLEEP) { |
| b9570b66 GJ |
257 | rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, |
| 258 | 0xffffffff); | |
| 259 | rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, | |
| 260 | 0xffffffff); | |
| 09a3311c JK |
261 | rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_SLEEP, |
| 262 | 0xff, 0x01); | |
| a9b3a9f7 ID |
263 | } |
| 264 | ||
| 265 | return 0; | |
| 266 | } | |
| 267 | ||
| 268 | static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev, | |
| 269 | enum dev_state state) | |
| 270 | { | |
| 271 | int retval = 0; | |
| 272 | ||
| 273 | switch (state) { | |
| 274 | case STATE_RADIO_ON: | |
| a9b3a9f7 ID |
275 | retval = rt2800pci_enable_radio(rt2x00dev); |
| 276 | break; | |
| 277 | case STATE_RADIO_OFF: | |
| 278 | /* | |
| 279 | * After the radio has been disabled, the device should | |
| 280 | * be put to sleep for powersaving. | |
| 281 | */ | |
| 282 | rt2800pci_disable_radio(rt2x00dev); | |
| 283 | rt2800pci_set_state(rt2x00dev, STATE_SLEEP); | |
| 284 | break; | |
| a9b3a9f7 ID |
285 | case STATE_RADIO_IRQ_ON: |
| 286 | case STATE_RADIO_IRQ_OFF: | |
| b5cfde3f | 287 | rt2800mmio_toggle_irq(rt2x00dev, state); |
| a9b3a9f7 ID |
288 | break; |
| 289 | case STATE_DEEP_SLEEP: | |
| 290 | case STATE_SLEEP: | |
| 291 | case STATE_STANDBY: | |
| 292 | case STATE_AWAKE: | |
| 293 | retval = rt2800pci_set_state(rt2x00dev, state); | |
| 294 | break; | |
| 295 | default: | |
| 296 | retval = -ENOTSUPP; | |
| 297 | break; | |
| 298 | } | |
| 299 | ||
| 300 | if (unlikely(retval)) | |
| ec9c4989 JP |
301 | rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n", |
| 302 | state, retval); | |
| a9b3a9f7 ID |
303 | |
| 304 | return retval; | |
| 305 | } | |
| 306 | ||
| 68597ea8 | 307 | #ifdef CONFIG_PCI |
| a9b3a9f7 ID |
308 | /* |
| 309 | * Device probe functions. | |
| 310 | */ | |
| a02308e9 | 311 | static int rt2800pci_read_eeprom(struct rt2x00_dev *rt2x00dev) |
| 7ab71325 | 312 | { |
| a02308e9 GJ |
313 | int retval; |
| 314 | ||
| 68597ea8 | 315 | if (rt2800pci_efuse_detect(rt2x00dev)) |
| a02308e9 | 316 | retval = rt2800pci_read_eeprom_efuse(rt2x00dev); |
| cea90e55 | 317 | else |
| a02308e9 GJ |
318 | retval = rt2800pci_read_eeprom_pci(rt2x00dev); |
| 319 | ||
| 320 | return retval; | |
| a9b3a9f7 ID |
321 | } |
| 322 | ||
| e783619e HS |
323 | static const struct ieee80211_ops rt2800pci_mac80211_ops = { |
| 324 | .tx = rt2x00mac_tx, | |
| 325 | .start = rt2x00mac_start, | |
| 326 | .stop = rt2x00mac_stop, | |
| 327 | .add_interface = rt2x00mac_add_interface, | |
| 328 | .remove_interface = rt2x00mac_remove_interface, | |
| 329 | .config = rt2x00mac_config, | |
| 330 | .configure_filter = rt2x00mac_configure_filter, | |
| e783619e HS |
331 | .set_key = rt2x00mac_set_key, |
| 332 | .sw_scan_start = rt2x00mac_sw_scan_start, | |
| 333 | .sw_scan_complete = rt2x00mac_sw_scan_complete, | |
| 334 | .get_stats = rt2x00mac_get_stats, | |
| 335 | .get_tkip_seq = rt2800_get_tkip_seq, | |
| 336 | .set_rts_threshold = rt2800_set_rts_threshold, | |
| a2b1328a HS |
337 | .sta_add = rt2x00mac_sta_add, |
| 338 | .sta_remove = rt2x00mac_sta_remove, | |
| e783619e HS |
339 | .bss_info_changed = rt2x00mac_bss_info_changed, |
| 340 | .conf_tx = rt2800_conf_tx, | |
| 341 | .get_tsf = rt2800_get_tsf, | |
| 342 | .rfkill_poll = rt2x00mac_rfkill_poll, | |
| 343 | .ampdu_action = rt2800_ampdu_action, | |
| f44df18c | 344 | .flush = rt2x00mac_flush, |
| 977206d7 | 345 | .get_survey = rt2800_get_survey, |
| e7dee444 | 346 | .get_ringparam = rt2x00mac_get_ringparam, |
| 5f0dd296 | 347 | .tx_frames_pending = rt2x00mac_tx_frames_pending, |
| e783619e HS |
348 | }; |
| 349 | ||
| e796643e | 350 | static const struct rt2800_ops rt2800pci_rt2800_ops = { |
| b9570b66 GJ |
351 | .register_read = rt2x00mmio_register_read, |
| 352 | .register_read_lock = rt2x00mmio_register_read, /* same for PCI */ | |
| 353 | .register_write = rt2x00mmio_register_write, | |
| 354 | .register_write_lock = rt2x00mmio_register_write, /* same for PCI */ | |
| 355 | .register_multiread = rt2x00mmio_register_multiread, | |
| 356 | .register_multiwrite = rt2x00mmio_register_multiwrite, | |
| 357 | .regbusy_read = rt2x00mmio_regbusy_read, | |
| ad417a53 GW |
358 | .read_eeprom = rt2800pci_read_eeprom, |
| 359 | .hwcrypt_disabled = rt2800pci_hwcrypt_disabled, | |
| e796643e | 360 | .drv_write_firmware = rt2800pci_write_firmware, |
| 7573afdf | 361 | .drv_init_registers = rt2800mmio_init_registers, |
| 45c67550 | 362 | .drv_get_txwi = rt2800mmio_get_txwi, |
| e796643e ID |
363 | }; |
| 364 | ||
| a9b3a9f7 | 365 | static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = { |
| b5cfde3f GJ |
366 | .irq_handler = rt2800mmio_interrupt, |
| 367 | .txstatus_tasklet = rt2800mmio_txstatus_tasklet, | |
| 368 | .pretbtt_tasklet = rt2800mmio_pretbtt_tasklet, | |
| 369 | .tbtt_tasklet = rt2800mmio_tbtt_tasklet, | |
| 370 | .rxdone_tasklet = rt2800mmio_rxdone_tasklet, | |
| 371 | .autowake_tasklet = rt2800mmio_autowake_tasklet, | |
| ad417a53 | 372 | .probe_hw = rt2800_probe_hw, |
| a9b3a9f7 | 373 | .get_firmware_name = rt2800pci_get_firmware_name, |
| f31c9a8c ID |
374 | .check_firmware = rt2800_check_firmware, |
| 375 | .load_firmware = rt2800_load_firmware, | |
| b9570b66 GJ |
376 | .initialize = rt2x00mmio_initialize, |
| 377 | .uninitialize = rt2x00mmio_uninitialize, | |
| 7573afdf GJ |
378 | .get_entry_state = rt2800mmio_get_entry_state, |
| 379 | .clear_entry = rt2800mmio_clear_entry, | |
| a9b3a9f7 | 380 | .set_device_state = rt2800pci_set_device_state, |
| f4450616 BZ |
381 | .rfkill_poll = rt2800_rfkill_poll, |
| 382 | .link_stats = rt2800_link_stats, | |
| 383 | .reset_tuner = rt2800_reset_tuner, | |
| 384 | .link_tuner = rt2800_link_tuner, | |
| 9e33a355 | 385 | .gain_calibration = rt2800_gain_calibration, |
| 2e9c43dd | 386 | .vco_calibration = rt2800_vco_calibration, |
| 51e62469 GJ |
387 | .start_queue = rt2800mmio_start_queue, |
| 388 | .kick_queue = rt2800mmio_kick_queue, | |
| 389 | .stop_queue = rt2800mmio_stop_queue, | |
| b9570b66 | 390 | .flush_queue = rt2x00mmio_flush_queue, |
| 45c67550 | 391 | .write_tx_desc = rt2800mmio_write_tx_desc, |
| 0c5879bc | 392 | .write_tx_data = rt2800_write_tx_data, |
| f0194b2d | 393 | .write_beacon = rt2800_write_beacon, |
| 69cf36a4 | 394 | .clear_beacon = rt2800_clear_beacon, |
| d10b7547 | 395 | .fill_rxdone = rt2800mmio_fill_rxdone, |
| f4450616 BZ |
396 | .config_shared_key = rt2800_config_shared_key, |
| 397 | .config_pairwise_key = rt2800_config_pairwise_key, | |
| 398 | .config_filter = rt2800_config_filter, | |
| 399 | .config_intf = rt2800_config_intf, | |
| 400 | .config_erp = rt2800_config_erp, | |
| 401 | .config_ant = rt2800_config_ant, | |
| 402 | .config = rt2800_config, | |
| a2b1328a HS |
403 | .sta_add = rt2800_sta_add, |
| 404 | .sta_remove = rt2800_sta_remove, | |
| a9b3a9f7 ID |
405 | }; |
| 406 | ||
| a9b3a9f7 | 407 | static const struct rt2x00_ops rt2800pci_ops = { |
| 04d0362e | 408 | .name = KBUILD_MODNAME, |
| 3a1c0128 | 409 | .drv_data_size = sizeof(struct rt2800_drv_data), |
| 04d0362e GW |
410 | .max_ap_intf = 8, |
| 411 | .eeprom_size = EEPROM_SIZE, | |
| 412 | .rf_size = RF_SIZE, | |
| 413 | .tx_queues = NUM_TX_QUEUES, | |
| 51e62469 | 414 | .queue_init = rt2800mmio_queue_init, |
| 04d0362e | 415 | .lib = &rt2800pci_rt2x00_ops, |
| e796643e | 416 | .drv = &rt2800pci_rt2800_ops, |
| e783619e | 417 | .hw = &rt2800pci_mac80211_ops, |
| a9b3a9f7 | 418 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS |
| 04d0362e | 419 | .debugfs = &rt2800_rt2x00debug, |
| a9b3a9f7 ID |
420 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ |
| 421 | }; | |
| 422 | ||
| 423 | /* | |
| 424 | * RT2800pci module information. | |
| 425 | */ | |
| a3aa1884 | 426 | static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = { |
| e01ae27f GW |
427 | { PCI_DEVICE(0x1814, 0x0601) }, |
| 428 | { PCI_DEVICE(0x1814, 0x0681) }, | |
| 429 | { PCI_DEVICE(0x1814, 0x0701) }, | |
| 430 | { PCI_DEVICE(0x1814, 0x0781) }, | |
| 431 | { PCI_DEVICE(0x1814, 0x3090) }, | |
| 432 | { PCI_DEVICE(0x1814, 0x3091) }, | |
| 433 | { PCI_DEVICE(0x1814, 0x3092) }, | |
| 434 | { PCI_DEVICE(0x1432, 0x7708) }, | |
| 435 | { PCI_DEVICE(0x1432, 0x7727) }, | |
| 436 | { PCI_DEVICE(0x1432, 0x7728) }, | |
| 437 | { PCI_DEVICE(0x1432, 0x7738) }, | |
| 438 | { PCI_DEVICE(0x1432, 0x7748) }, | |
| 439 | { PCI_DEVICE(0x1432, 0x7758) }, | |
| 440 | { PCI_DEVICE(0x1432, 0x7768) }, | |
| 441 | { PCI_DEVICE(0x1462, 0x891a) }, | |
| 442 | { PCI_DEVICE(0x1a3b, 0x1059) }, | |
| a89534ed WH |
443 | #ifdef CONFIG_RT2800PCI_RT3290 |
| 444 | { PCI_DEVICE(0x1814, 0x3290) }, | |
| 445 | #endif | |
| f93bc9b3 | 446 | #ifdef CONFIG_RT2800PCI_RT33XX |
| e01ae27f | 447 | { PCI_DEVICE(0x1814, 0x3390) }, |
| f93bc9b3 | 448 | #endif |
| de1ebdce | 449 | #ifdef CONFIG_RT2800PCI_RT35XX |
| e01ae27f GW |
450 | { PCI_DEVICE(0x1432, 0x7711) }, |
| 451 | { PCI_DEVICE(0x1432, 0x7722) }, | |
| 452 | { PCI_DEVICE(0x1814, 0x3060) }, | |
| 453 | { PCI_DEVICE(0x1814, 0x3062) }, | |
| 454 | { PCI_DEVICE(0x1814, 0x3562) }, | |
| 455 | { PCI_DEVICE(0x1814, 0x3592) }, | |
| 456 | { PCI_DEVICE(0x1814, 0x3593) }, | |
| c4806014 | 457 | { PCI_DEVICE(0x1814, 0x359f) }, |
| 60687ba7 RST |
458 | #endif |
| 459 | #ifdef CONFIG_RT2800PCI_RT53XX | |
| ccf91bd6 | 460 | { PCI_DEVICE(0x1814, 0x5360) }, |
| f57d7b6c | 461 | { PCI_DEVICE(0x1814, 0x5362) }, |
| e01ae27f | 462 | { PCI_DEVICE(0x1814, 0x5390) }, |
| f57d7b6c | 463 | { PCI_DEVICE(0x1814, 0x5392) }, |
| 5126d97e | 464 | { PCI_DEVICE(0x1814, 0x539a) }, |
| 2aed6915 | 465 | { PCI_DEVICE(0x1814, 0x539b) }, |
| 71e0b38c | 466 | { PCI_DEVICE(0x1814, 0x539f) }, |
| de1ebdce | 467 | #endif |
| a9b3a9f7 ID |
468 | { 0, } |
| 469 | }; | |
| 72c7296e | 470 | #endif /* CONFIG_PCI */ |
| a9b3a9f7 ID |
471 | |
| 472 | MODULE_AUTHOR(DRV_PROJECT); | |
| 473 | MODULE_VERSION(DRV_VERSION); | |
| 474 | MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver."); | |
| 475 | MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards"); | |
| 72c7296e | 476 | #ifdef CONFIG_PCI |
| a9b3a9f7 ID |
477 | MODULE_FIRMWARE(FIRMWARE_RT2860); |
| 478 | MODULE_DEVICE_TABLE(pci, rt2800pci_device_table); | |
| 72c7296e | 479 | #endif /* CONFIG_PCI */ |
| a9b3a9f7 ID |
480 | MODULE_LICENSE("GPL"); |
| 481 | ||
| 5818a46a | 482 | #if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X) |
| 68597ea8 GJ |
483 | static int rt2800soc_read_eeprom(struct rt2x00_dev *rt2x00dev) |
| 484 | { | |
| 485 | void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE); | |
| 486 | ||
| 487 | if (!base_addr) | |
| 488 | return -ENOMEM; | |
| 489 | ||
| 490 | memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE); | |
| 491 | ||
| 492 | iounmap(base_addr); | |
| 493 | return 0; | |
| 494 | } | |
| 495 | ||
| eeea863e GJ |
496 | static const struct ieee80211_ops rt2800soc_mac80211_ops = { |
| 497 | .tx = rt2x00mac_tx, | |
| 498 | .start = rt2x00mac_start, | |
| 499 | .stop = rt2x00mac_stop, | |
| 500 | .add_interface = rt2x00mac_add_interface, | |
| 501 | .remove_interface = rt2x00mac_remove_interface, | |
| 502 | .config = rt2x00mac_config, | |
| 503 | .configure_filter = rt2x00mac_configure_filter, | |
| 504 | .set_key = rt2x00mac_set_key, | |
| 505 | .sw_scan_start = rt2x00mac_sw_scan_start, | |
| 506 | .sw_scan_complete = rt2x00mac_sw_scan_complete, | |
| 507 | .get_stats = rt2x00mac_get_stats, | |
| 508 | .get_tkip_seq = rt2800_get_tkip_seq, | |
| 509 | .set_rts_threshold = rt2800_set_rts_threshold, | |
| 510 | .sta_add = rt2x00mac_sta_add, | |
| 511 | .sta_remove = rt2x00mac_sta_remove, | |
| 512 | .bss_info_changed = rt2x00mac_bss_info_changed, | |
| 513 | .conf_tx = rt2800_conf_tx, | |
| 514 | .get_tsf = rt2800_get_tsf, | |
| 515 | .rfkill_poll = rt2x00mac_rfkill_poll, | |
| 516 | .ampdu_action = rt2800_ampdu_action, | |
| 517 | .flush = rt2x00mac_flush, | |
| 518 | .get_survey = rt2800_get_survey, | |
| 519 | .get_ringparam = rt2x00mac_get_ringparam, | |
| 520 | .tx_frames_pending = rt2x00mac_tx_frames_pending, | |
| 521 | }; | |
| 522 | ||
| 523 | static const struct rt2800_ops rt2800soc_rt2800_ops = { | |
| 524 | .register_read = rt2x00mmio_register_read, | |
| 525 | .register_read_lock = rt2x00mmio_register_read, /* same for SoCs */ | |
| 526 | .register_write = rt2x00mmio_register_write, | |
| 527 | .register_write_lock = rt2x00mmio_register_write, /* same for SoCs */ | |
| 528 | .register_multiread = rt2x00mmio_register_multiread, | |
| 529 | .register_multiwrite = rt2x00mmio_register_multiwrite, | |
| 530 | .regbusy_read = rt2x00mmio_regbusy_read, | |
| 68597ea8 | 531 | .read_eeprom = rt2800soc_read_eeprom, |
| eeea863e GJ |
532 | .hwcrypt_disabled = rt2800pci_hwcrypt_disabled, |
| 533 | .drv_write_firmware = rt2800pci_write_firmware, | |
| 534 | .drv_init_registers = rt2800mmio_init_registers, | |
| 535 | .drv_get_txwi = rt2800mmio_get_txwi, | |
| 536 | }; | |
| 537 | ||
| 538 | static const struct rt2x00lib_ops rt2800soc_rt2x00_ops = { | |
| 539 | .irq_handler = rt2800mmio_interrupt, | |
| 540 | .txstatus_tasklet = rt2800mmio_txstatus_tasklet, | |
| 541 | .pretbtt_tasklet = rt2800mmio_pretbtt_tasklet, | |
| 542 | .tbtt_tasklet = rt2800mmio_tbtt_tasklet, | |
| 543 | .rxdone_tasklet = rt2800mmio_rxdone_tasklet, | |
| 544 | .autowake_tasklet = rt2800mmio_autowake_tasklet, | |
| 545 | .probe_hw = rt2800_probe_hw, | |
| 546 | .get_firmware_name = rt2800pci_get_firmware_name, | |
| 547 | .check_firmware = rt2800_check_firmware, | |
| 548 | .load_firmware = rt2800_load_firmware, | |
| 549 | .initialize = rt2x00mmio_initialize, | |
| 550 | .uninitialize = rt2x00mmio_uninitialize, | |
| 551 | .get_entry_state = rt2800mmio_get_entry_state, | |
| 552 | .clear_entry = rt2800mmio_clear_entry, | |
| 553 | .set_device_state = rt2800pci_set_device_state, | |
| 554 | .rfkill_poll = rt2800_rfkill_poll, | |
| 555 | .link_stats = rt2800_link_stats, | |
| 556 | .reset_tuner = rt2800_reset_tuner, | |
| 557 | .link_tuner = rt2800_link_tuner, | |
| 558 | .gain_calibration = rt2800_gain_calibration, | |
| 559 | .vco_calibration = rt2800_vco_calibration, | |
| 560 | .start_queue = rt2800mmio_start_queue, | |
| 561 | .kick_queue = rt2800mmio_kick_queue, | |
| 562 | .stop_queue = rt2800mmio_stop_queue, | |
| 563 | .flush_queue = rt2x00mmio_flush_queue, | |
| 564 | .write_tx_desc = rt2800mmio_write_tx_desc, | |
| 565 | .write_tx_data = rt2800_write_tx_data, | |
| 566 | .write_beacon = rt2800_write_beacon, | |
| 567 | .clear_beacon = rt2800_clear_beacon, | |
| 568 | .fill_rxdone = rt2800mmio_fill_rxdone, | |
| 569 | .config_shared_key = rt2800_config_shared_key, | |
| 570 | .config_pairwise_key = rt2800_config_pairwise_key, | |
| 571 | .config_filter = rt2800_config_filter, | |
| 572 | .config_intf = rt2800_config_intf, | |
| 573 | .config_erp = rt2800_config_erp, | |
| 574 | .config_ant = rt2800_config_ant, | |
| 575 | .config = rt2800_config, | |
| 576 | .sta_add = rt2800_sta_add, | |
| 577 | .sta_remove = rt2800_sta_remove, | |
| 578 | }; | |
| 579 | ||
| 580 | static const struct rt2x00_ops rt2800soc_ops = { | |
| 581 | .name = KBUILD_MODNAME, | |
| 582 | .drv_data_size = sizeof(struct rt2800_drv_data), | |
| 583 | .max_ap_intf = 8, | |
| 584 | .eeprom_size = EEPROM_SIZE, | |
| 585 | .rf_size = RF_SIZE, | |
| 586 | .tx_queues = NUM_TX_QUEUES, | |
| 587 | .queue_init = rt2800mmio_queue_init, | |
| 588 | .lib = &rt2800soc_rt2x00_ops, | |
| 589 | .drv = &rt2800soc_rt2800_ops, | |
| 590 | .hw = &rt2800soc_mac80211_ops, | |
| 591 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS | |
| 592 | .debugfs = &rt2800_rt2x00debug, | |
| 593 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ | |
| 594 | }; | |
| 595 | ||
| 714fa663 GW |
596 | static int rt2800soc_probe(struct platform_device *pdev) |
| 597 | { | |
| eeea863e | 598 | return rt2x00soc_probe(pdev, &rt2800soc_ops); |
| 714fa663 | 599 | } |
| a9b3a9f7 ID |
600 | |
| 601 | static struct platform_driver rt2800soc_driver = { | |
| 602 | .driver = { | |
| 603 | .name = "rt2800_wmac", | |
| 604 | .owner = THIS_MODULE, | |
| 605 | .mod_name = KBUILD_MODNAME, | |
| 606 | }, | |
| 714fa663 | 607 | .probe = rt2800soc_probe, |
| 69202359 | 608 | .remove = rt2x00soc_remove, |
| a9b3a9f7 ID |
609 | .suspend = rt2x00soc_suspend, |
| 610 | .resume = rt2x00soc_resume, | |
| 611 | }; | |
| 5818a46a | 612 | #endif /* CONFIG_SOC_RT288X || CONFIG_SOC_RT305X */ |
| a9b3a9f7 | 613 | |
| 72c7296e | 614 | #ifdef CONFIG_PCI |
| e01ae27f GW |
615 | static int rt2800pci_probe(struct pci_dev *pci_dev, |
| 616 | const struct pci_device_id *id) | |
| 617 | { | |
| 618 | return rt2x00pci_probe(pci_dev, &rt2800pci_ops); | |
| 619 | } | |
| 620 | ||
| a9b3a9f7 ID |
621 | static struct pci_driver rt2800pci_driver = { |
| 622 | .name = KBUILD_MODNAME, | |
| 623 | .id_table = rt2800pci_device_table, | |
| e01ae27f | 624 | .probe = rt2800pci_probe, |
| 69202359 | 625 | .remove = rt2x00pci_remove, |
| a9b3a9f7 ID |
626 | .suspend = rt2x00pci_suspend, |
| 627 | .resume = rt2x00pci_resume, | |
| 628 | }; | |
| 72c7296e | 629 | #endif /* CONFIG_PCI */ |
| a9b3a9f7 ID |
630 | |
| 631 | static int __init rt2800pci_init(void) | |
| 632 | { | |
| 633 | int ret = 0; | |
| 634 | ||
| 5818a46a | 635 | #if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X) |
| a9b3a9f7 ID |
636 | ret = platform_driver_register(&rt2800soc_driver); |
| 637 | if (ret) | |
| 638 | return ret; | |
| 639 | #endif | |
| 72c7296e | 640 | #ifdef CONFIG_PCI |
| a9b3a9f7 ID |
641 | ret = pci_register_driver(&rt2800pci_driver); |
| 642 | if (ret) { | |
| 5818a46a | 643 | #if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X) |
| a9b3a9f7 ID |
644 | platform_driver_unregister(&rt2800soc_driver); |
| 645 | #endif | |
| 646 | return ret; | |
| 647 | } | |
| 648 | #endif | |
| 649 | ||
| 650 | return ret; | |
| 651 | } | |
| 652 | ||
| 653 | static void __exit rt2800pci_exit(void) | |
| 654 | { | |
| 72c7296e | 655 | #ifdef CONFIG_PCI |
| a9b3a9f7 ID |
656 | pci_unregister_driver(&rt2800pci_driver); |
| 657 | #endif | |
| 5818a46a | 658 | #if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X) |
| a9b3a9f7 ID |
659 | platform_driver_unregister(&rt2800soc_driver); |
| 660 | #endif | |
| 661 | } | |
| 662 | ||
| 663 | module_init(rt2800pci_init); | |
| 664 | module_exit(rt2800pci_exit); |