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rt2500usb: remove dead link tuning code
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2800pci.c
CommitLineData
a9b3a9f7
ID		 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2800pci
23 Abstract: rt2800pci device specific routines.
24 Supported chipsets: RT2800E & RT2800ED.
25 */
26
27#include <linux/crc-ccitt.h>
28#include <linux/delay.h>
29#include <linux/etherdevice.h>
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/pci.h>
34#include <linux/platform_device.h>
35#include <linux/eeprom_93cx6.h>
36
37#include "rt2x00.h"
38#include "rt2x00pci.h"
39#include "rt2x00soc.h"
7ef5cc92 40#include "rt2800lib.h"
b54f78a8 41#include "rt2800.h"
a9b3a9f7
ID		 42#include "rt2800pci.h"
43
44#ifdef CONFIG_RT2800PCI_PCI_MODULE
45#define CONFIG_RT2800PCI_PCI
46#endif
47
48#ifdef CONFIG_RT2800PCI_WISOC_MODULE
49#define CONFIG_RT2800PCI_WISOC
50#endif
51
52/*
53 * Allow hardware encryption to be disabled.
54 */
55static int modparam_nohwcrypt = 1;
56module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
57MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
58
a9b3a9f7
ID		 59static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
60{
61 unsigned int i;
62 u32 reg;
63
64 for (i = 0; i < 200; i++) {
9ca21eb7 65 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
a9b3a9f7
ID		 66
67 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
68 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
69 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
70 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
71 break;
72
73 udelay(REGISTER_BUSY_DELAY);
74 }
75
76 if (i == 200)
77 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
78
9ca21eb7
BZ		 79 rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
80 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
a9b3a9f7
ID		 81}
82
83#ifdef CONFIG_RT2800PCI_WISOC
84static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
85{
86 u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */
87
88 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
89}
90#else
91static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
92{
93}
94#endif /* CONFIG_RT2800PCI_WISOC */
95
96#ifdef CONFIG_RT2800PCI_PCI
97static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
98{
99 struct rt2x00_dev *rt2x00dev = eeprom->data;
100 u32 reg;
101
9ca21eb7 102 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 103
104 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
105 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
106 eeprom->reg_data_clock =
107 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
108 eeprom->reg_chip_select =
109 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
110}
111
112static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
113{
114 struct rt2x00_dev *rt2x00dev = eeprom->data;
115 u32 reg = 0;
116
117 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
118 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
119 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
120 !!eeprom->reg_data_clock);
121 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
122 !!eeprom->reg_chip_select);
123
9ca21eb7 124 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
a9b3a9f7
ID		 125}
126
127static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
128{
129 struct eeprom_93cx6 eeprom;
130 u32 reg;
131
9ca21eb7 132 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 133
134 eeprom.data = rt2x00dev;
135 eeprom.register_read = rt2800pci_eepromregister_read;
136 eeprom.register_write = rt2800pci_eepromregister_write;
137 eeprom.width = !rt2x00_get_field32(reg, E2PROM_CSR_TYPE) ?
138 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
139 eeprom.reg_data_in = 0;
140 eeprom.reg_data_out = 0;
141 eeprom.reg_data_clock = 0;
142 eeprom.reg_chip_select = 0;
143
144 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
145 EEPROM_SIZE / sizeof(u16));
146}
147
a6598682
GW		 148static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
149{
30e84034 150 return rt2800_efuse_detect(rt2x00dev);
a9b3a9f7
ID		 151}
152
30e84034 153static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 154{
30e84034 155 rt2800_read_eeprom_efuse(rt2x00dev);
a9b3a9f7
ID		 156}
157#else
158static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
159{
160}
161
a6598682
GW		 162static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
163{
164 return 0;
165}
166
a9b3a9f7
ID		 167static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
168{
169}
170#endif /* CONFIG_RT2800PCI_PCI */
171
a9b3a9f7
ID		 172/*
173 * Firmware functions
174 */
175static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
176{
177 return FIRMWARE_RT2860;
178}
179
180static int rt2800pci_check_firmware(struct rt2x00_dev *rt2x00dev,
181 const u8 *data, const size_t len)
182{
183 u16 fw_crc;
184 u16 crc;
185
186 /*
187 * Only support 8kb firmware files.
188 */
189 if (len != 8192)
190 return FW_BAD_LENGTH;
191
192 /*
193 * The last 2 bytes in the firmware array are the crc checksum itself,
194 * this means that we should never pass those 2 bytes to the crc
195 * algorithm.
196 */
197 fw_crc = (data[len - 2] << 8 | data[len - 1]);
198
199 /*
200 * Use the crc ccitt algorithm.
201 * This will return the same value as the legacy driver which
202 * used bit ordering reversion on the both the firmware bytes
203 * before input input as well as on the final output.
204 * Obviously using crc ccitt directly is much more efficient.
205 */
206 crc = crc_ccitt(~0, data, len - 2);
207
208 /*
209 * There is a small difference between the crc-itu-t + bitrev and
210 * the crc-ccitt crc calculation. In the latter method the 2 bytes
211 * will be swapped, use swab16 to convert the crc to the correct
212 * value.
213 */
214 crc = swab16(crc);
215
216 return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
217}
218
219static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
220 const u8 *data, const size_t len)
221{
222 unsigned int i;
223 u32 reg;
224
225 /*
226 * Wait for stable hardware.
227 */
228 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9ca21eb7 229 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
a9b3a9f7
ID		 230 if (reg && reg != ~0)
231 break;
232 msleep(1);
233 }
234
235 if (i == REGISTER_BUSY_COUNT) {
236 ERROR(rt2x00dev, "Unstable hardware.\n");
237 return -EBUSY;
238 }
239
9ca21eb7
BZ		 240 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
241 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
a9b3a9f7
ID		 242
243 /*
244 * Disable DMA, will be reenabled later when enabling
245 * the radio.
246 */
9ca21eb7 247 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 248 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
249 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
250 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
251 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
252 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 253 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7
ID		 254
255 /*
256 * enable Host program ram write selection
257 */
258 reg = 0;
259 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
9ca21eb7 260 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
a9b3a9f7
ID		 261
262 /*
263 * Write firmware to device.
264 */
4f2732ce 265 rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
a9b3a9f7
ID		 266 data, len);
267
9ca21eb7
BZ		 268 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
269 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
a9b3a9f7
ID		 270
271 /*
272 * Wait for device to stabilize.
273 */
274 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9ca21eb7 275 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
a9b3a9f7
ID		 276 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
277 break;
278 msleep(1);
279 }
280
281 if (i == REGISTER_BUSY_COUNT) {
282 ERROR(rt2x00dev, "PBF system register not ready.\n");
283 return -EBUSY;
284 }
285
286 /*
287 * Disable interrupts
288 */
289 rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_OFF);
290
291 /*
292 * Initialize BBP R/W access agent
293 */
9ca21eb7
BZ		 294 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
295 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
a9b3a9f7
ID		 296
297 return 0;
298}
299
300/*
301 * Initialization functions.
302 */
303static bool rt2800pci_get_entry_state(struct queue_entry *entry)
304{
305 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
306 u32 word;
307
308 if (entry->queue->qid == QID_RX) {
309 rt2x00_desc_read(entry_priv->desc, 1, &word);
310
311 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
312 } else {
313 rt2x00_desc_read(entry_priv->desc, 1, &word);
314
315 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
316 }
317}
318
319static void rt2800pci_clear_entry(struct queue_entry *entry)
320{
321 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
322 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
323 u32 word;
324
325 if (entry->queue->qid == QID_RX) {
326 rt2x00_desc_read(entry_priv->desc, 0, &word);
327 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
328 rt2x00_desc_write(entry_priv->desc, 0, word);
329
330 rt2x00_desc_read(entry_priv->desc, 1, &word);
331 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
332 rt2x00_desc_write(entry_priv->desc, 1, word);
333 } else {
334 rt2x00_desc_read(entry_priv->desc, 1, &word);
335 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
336 rt2x00_desc_write(entry_priv->desc, 1, word);
337 }
338}
339
340static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
341{
342 struct queue_entry_priv_pci *entry_priv;
343 u32 reg;
344
9ca21eb7 345 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
a9b3a9f7
ID		 346 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
347 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
348 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
349 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
350 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
351 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
352 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
9ca21eb7 353 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
a9b3a9f7 354
9ca21eb7
BZ		 355 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
356 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
a9b3a9f7
ID		 357
358 /*
359 * Initialize registers.
360 */
361 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
9ca21eb7
BZ		 362 rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
363 rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
364 rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
365 rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
a9b3a9f7
ID		 366
367 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
9ca21eb7
BZ		 368 rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
369 rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
370 rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
371 rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
a9b3a9f7
ID		 372
373 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
9ca21eb7
BZ		 374 rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
375 rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
376 rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
377 rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
a9b3a9f7
ID		 378
379 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
9ca21eb7
BZ		 380 rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
381 rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
382 rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
383 rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
a9b3a9f7
ID		 384
385 entry_priv = rt2x00dev->rx->entries[0].priv_data;
9ca21eb7
BZ		 386 rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
387 rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
388 rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
389 rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
a9b3a9f7
ID		 390
391 /*
392 * Enable global DMA configuration
393 */
9ca21eb7 394 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 395 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
396 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
397 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 398 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7 399
9ca21eb7 400 rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
a9b3a9f7
ID		 401
402 return 0;
403}
404
a9b3a9f7
ID		 405/*
406 * Device state switch handlers.
407 */
408static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
409 enum dev_state state)
410{
411 u32 reg;
412
9ca21eb7 413 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
a9b3a9f7
ID		 414 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
415 (state == STATE_RADIO_RX_ON) ||
416 (state == STATE_RADIO_RX_ON_LINK));
9ca21eb7 417 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
a9b3a9f7
ID		 418}
419
420static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
421 enum dev_state state)
422{
423 int mask = (state == STATE_RADIO_IRQ_ON);
424 u32 reg;
425
426 /*
427 * When interrupts are being enabled, the interrupt registers
428 * should clear the register to assure a clean state.
429 */
430 if (state == STATE_RADIO_IRQ_ON) {
9ca21eb7
BZ		 431 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
432 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
a9b3a9f7
ID		 433 }
434
9ca21eb7 435 rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
a9b3a9f7
ID		 436 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
437 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
438 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
439 rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
440 rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
441 rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
442 rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
443 rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
444 rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
445 rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
446 rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, mask);
447 rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
448 rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
449 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
450 rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
451 rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
452 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
453 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
9ca21eb7 454 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
a9b3a9f7
ID		 455}
456
457static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
458{
459 unsigned int i;
460 u32 reg;
461
462 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9ca21eb7 463 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 464 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
465 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
466 return 0;
467
468 msleep(1);
469 }
470
471 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
472 return -EACCES;
473}
474
475static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
476{
477 u32 reg;
478 u16 word;
479
480 /*
481 * Initialize all registers.
482 */
483 if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) ||
484 rt2800pci_init_queues(rt2x00dev) ||
fcf51541 485 rt2800_init_registers(rt2x00dev) ||
a9b3a9f7 486 rt2800pci_wait_wpdma_ready(rt2x00dev) ||
fcf51541
BZ		 487 rt2800_init_bbp(rt2x00dev) ||
488 rt2800_init_rfcsr(rt2x00dev)))
a9b3a9f7
ID		 489 return -EIO;
490
491 /*
492 * Send signal to firmware during boot time.
493 */
3a9e5b0f 494 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
a9b3a9f7
ID		 495
496 /*
497 * Enable RX.
498 */
9ca21eb7 499 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
a9b3a9f7
ID		 500 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
501 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
9ca21eb7 502 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
a9b3a9f7 503
9ca21eb7 504 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 505 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
506 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
507 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
508 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 509 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7 510
9ca21eb7 511 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
a9b3a9f7
ID		 512 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
513 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
9ca21eb7 514 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
a9b3a9f7
ID		 515
516 /*
517 * Initialize LED control
518 */
519 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
3a9e5b0f 520 rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
a9b3a9f7
ID		 521 word & 0xff, (word >> 8) & 0xff);
522
523 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
3a9e5b0f 524 rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
a9b3a9f7
ID		 525 word & 0xff, (word >> 8) & 0xff);
526
527 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
3a9e5b0f 528 rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
a9b3a9f7
ID		 529 word & 0xff, (word >> 8) & 0xff);
530
531 return 0;
532}
533
534static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
535{
536 u32 reg;
537
9ca21eb7 538 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 539 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
540 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
541 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
542 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
543 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 544 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7 545
9ca21eb7
BZ		 546 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
547 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
548 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
a9b3a9f7 549
9ca21eb7 550 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
a9b3a9f7 551
9ca21eb7 552 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
a9b3a9f7
ID		 553 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
554 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
555 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
556 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
557 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
558 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
559 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
9ca21eb7 560 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
a9b3a9f7 561
9ca21eb7
BZ		 562 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
563 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
a9b3a9f7
ID		 564
565 /* Wait for DMA, ignore error */
566 rt2800pci_wait_wpdma_ready(rt2x00dev);
567}
568
569static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
570 enum dev_state state)
571{
572 /*
573 * Always put the device to sleep (even when we intend to wakeup!)
574 * if the device is booting and wasn't asleep it will return
575 * failure when attempting to wakeup.
576 */
3a9e5b0f 577 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
a9b3a9f7
ID		 578
579 if (state == STATE_AWAKE) {
3a9e5b0f 580 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
a9b3a9f7
ID		 581 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
582 }
583
584 return 0;
585}
586
587static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
588 enum dev_state state)
589{
590 int retval = 0;
591
592 switch (state) {
593 case STATE_RADIO_ON:
594 /*
595 * Before the radio can be enabled, the device first has
596 * to be woken up. After that it needs a bit of time
597 * to be fully awake and then the radio can be enabled.
598 */
599 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
600 msleep(1);
601 retval = rt2800pci_enable_radio(rt2x00dev);
602 break;
603 case STATE_RADIO_OFF:
604 /*
605 * After the radio has been disabled, the device should
606 * be put to sleep for powersaving.
607 */
608 rt2800pci_disable_radio(rt2x00dev);
609 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
610 break;
611 case STATE_RADIO_RX_ON:
612 case STATE_RADIO_RX_ON_LINK:
613 case STATE_RADIO_RX_OFF:
614 case STATE_RADIO_RX_OFF_LINK:
615 rt2800pci_toggle_rx(rt2x00dev, state);
616 break;
617 case STATE_RADIO_IRQ_ON:
618 case STATE_RADIO_IRQ_OFF:
619 rt2800pci_toggle_irq(rt2x00dev, state);
620 break;
621 case STATE_DEEP_SLEEP:
622 case STATE_SLEEP:
623 case STATE_STANDBY:
624 case STATE_AWAKE:
625 retval = rt2800pci_set_state(rt2x00dev, state);
626 break;
627 default:
628 retval = -ENOTSUPP;
629 break;
630 }
631
632 if (unlikely(retval))
633 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
634 state, retval);
635
636 return retval;
637}
638
639/*
640 * TX descriptor initialization
641 */
642static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
643 struct sk_buff *skb,
644 struct txentry_desc *txdesc)
645{
646 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
647 __le32 *txd = skbdesc->desc;
648 __le32 *txwi = (__le32 *)(skb->data - rt2x00dev->hw->extra_tx_headroom);
649 u32 word;
650
651 /*
652 * Initialize TX Info descriptor
653 */
654 rt2x00_desc_read(txwi, 0, &word);
655 rt2x00_set_field32(&word, TXWI_W0_FRAG,
656 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
657 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
658 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
659 rt2x00_set_field32(&word, TXWI_W0_TS,
660 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
661 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
662 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
663 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
664 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
665 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
666 rt2x00_set_field32(&word, TXWI_W0_BW,
667 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
668 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
669 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
670 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
671 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
672 rt2x00_desc_write(txwi, 0, word);
673
674 rt2x00_desc_read(txwi, 1, &word);
675 rt2x00_set_field32(&word, TXWI_W1_ACK,
676 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
677 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
678 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
679 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
680 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
681 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
f644fea1 682 txdesc->key_idx : 0xff);
a9b3a9f7
ID		 683 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
684 skb->len - txdesc->l2pad);
685 rt2x00_set_field32(&word, TXWI_W1_PACKETID,
686 skbdesc->entry->queue->qid + 1);
687 rt2x00_desc_write(txwi, 1, word);
688
689 /*
690 * Always write 0 to IV/EIV fields, hardware will insert the IV
77dba493
BZ		 691 * from the IVEIV register when TXD_W3_WIV is set to 0.
692 * When TXD_W3_WIV is set to 1 it will use the IV data
a9b3a9f7
ID		 693 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
694 * crypto entry in the registers should be used to encrypt the frame.
695 */
696 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
697 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
698
699 /*
700 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
701 * must contains a TXWI structure + 802.11 header + padding + 802.11
702 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
703 * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
704 * data. It means that LAST_SEC0 is always 0.
705 */
706
707 /*
708 * Initialize TX descriptor
709 */
710 rt2x00_desc_read(txd, 0, &word);
711 rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
712 rt2x00_desc_write(txd, 0, word);
713
714 rt2x00_desc_read(txd, 1, &word);
715 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
716 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
717 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
718 rt2x00_set_field32(&word, TXD_W1_BURST,
719 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
720 rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
721 rt2x00dev->hw->extra_tx_headroom);
722 rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
723 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
724 rt2x00_desc_write(txd, 1, word);
725
726 rt2x00_desc_read(txd, 2, &word);
727 rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
728 skbdesc->skb_dma + rt2x00dev->hw->extra_tx_headroom);
729 rt2x00_desc_write(txd, 2, word);
730
731 rt2x00_desc_read(txd, 3, &word);
732 rt2x00_set_field32(&word, TXD_W3_WIV,
733 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
734 rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
735 rt2x00_desc_write(txd, 3, word);
736}
737
738/*
739 * TX data initialization
740 */
741static void rt2800pci_write_beacon(struct queue_entry *entry)
742{
743 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
744 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
745 unsigned int beacon_base;
746 u32 reg;
747
748 /*
749 * Disable beaconing while we are reloading the beacon data,
750 * otherwise we might be sending out invalid data.
751 */
9ca21eb7 752 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
a9b3a9f7 753 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
9ca21eb7 754 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
a9b3a9f7
ID		 755
756 /*
757 * Write entire beacon with descriptor to register.
758 */
759 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
4f2732ce 760 rt2800_register_multiwrite(rt2x00dev,
a9b3a9f7
ID		 761 beacon_base,
762 skbdesc->desc, skbdesc->desc_len);
4f2732ce 763 rt2800_register_multiwrite(rt2x00dev,
a9b3a9f7
ID		 764 beacon_base + skbdesc->desc_len,
765 entry->skb->data, entry->skb->len);
766
767 /*
768 * Clean up beacon skb.
769 */
770 dev_kfree_skb_any(entry->skb);
771 entry->skb = NULL;
772}
773
774static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
775 const enum data_queue_qid queue_idx)
776{
777 struct data_queue *queue;
778 unsigned int idx, qidx = 0;
779 u32 reg;
780
781 if (queue_idx == QID_BEACON) {
9ca21eb7 782 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
a9b3a9f7
ID		 783 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
784 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
785 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
786 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
9ca21eb7 787 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
a9b3a9f7
ID		 788 }
789 return;
790 }
791
792 if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
793 return;
794
795 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
796 idx = queue->index[Q_INDEX];
797
798 if (queue_idx == QID_MGMT)
799 qidx = 5;
800 else
801 qidx = queue_idx;
802
9ca21eb7 803 rt2800_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
a9b3a9f7
ID		 804}
805
806static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
807 const enum data_queue_qid qid)
808{
809 u32 reg;
810
811 if (qid == QID_BEACON) {
9ca21eb7 812 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, 0);
a9b3a9f7
ID		 813 return;
814 }
815
9ca21eb7 816 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
a9b3a9f7
ID		 817 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
818 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
819 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
820 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
9ca21eb7 821 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
a9b3a9f7
ID		 822}
823
824/*
825 * RX control handlers
826 */
827static void rt2800pci_fill_rxdone(struct queue_entry *entry,
828 struct rxdone_entry_desc *rxdesc)
829{
830 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
831 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
832 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
833 __le32 *rxd = entry_priv->desc;
834 __le32 *rxwi = (__le32 *)entry->skb->data;
835 u32 rxd3;
836 u32 rxwi0;
837 u32 rxwi1;
838 u32 rxwi2;
839 u32 rxwi3;
840
841 rt2x00_desc_read(rxd, 3, &rxd3);
842 rt2x00_desc_read(rxwi, 0, &rxwi0);
843 rt2x00_desc_read(rxwi, 1, &rxwi1);
844 rt2x00_desc_read(rxwi, 2, &rxwi2);
845 rt2x00_desc_read(rxwi, 3, &rxwi3);
846
847 if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR))
848 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
849
850 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
851 /*
852 * Unfortunately we don't know the cipher type used during
853 * decryption. This prevents us from correct providing
854 * correct statistics through debugfs.
855 */
856 rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
857 rxdesc->cipher_status =
858 rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);
859 }
860
861 if (rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED)) {
862 /*
863 * Hardware has stripped IV/EIV data from 802.11 frame during
864 * decryption. Unfortunately the descriptor doesn't contain
865 * any fields with the EIV/IV data either, so they can't
866 * be restored by rt2x00lib.
867 */
868 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
869
870 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
871 rxdesc->flags |= RX_FLAG_DECRYPTED;
872 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
873 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
874 }
875
876 if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS))
877 rxdesc->dev_flags |= RXDONE_MY_BSS;
878
879 if (rt2x00_get_field32(rxd3, RXD_W3_L2PAD)) {
880 rxdesc->dev_flags |= RXDONE_L2PAD;
881 skbdesc->flags |= SKBDESC_L2_PADDED;
882 }
883
884 if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
885 rxdesc->flags |= RX_FLAG_SHORT_GI;
886
887 if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
888 rxdesc->flags |= RX_FLAG_40MHZ;
889
890 /*
891 * Detect RX rate, always use MCS as signal type.
892 */
893 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
894 rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
895 rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
896
897 /*
898 * Mask of 0x8 bit to remove the short preamble flag.
899 */
900 if (rxdesc->rate_mode == RATE_MODE_CCK)
901 rxdesc->signal &= ~0x8;
902
903 rxdesc->rssi =
904 (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
905 rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
906
907 rxdesc->noise =
908 (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
909 rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
910
911 rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
912
913 /*
914 * Set RX IDX in register to inform hardware that we have handled
915 * this entry and it is available for reuse again.
916 */
9ca21eb7 917 rt2800_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
a9b3a9f7
ID		 918
919 /*
920 * Remove TXWI descriptor from start of buffer.
921 */
922 skb_pull(entry->skb, RXWI_DESC_SIZE);
923 skb_trim(entry->skb, rxdesc->size);
924}
925
926/*
927 * Interrupt functions.
928 */
929static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
930{
931 struct data_queue *queue;
932 struct queue_entry *entry;
933 struct queue_entry *entry_done;
934 struct queue_entry_priv_pci *entry_priv;
935 struct txdone_entry_desc txdesc;
936 u32 word;
937 u32 reg;
938 u32 old_reg;
939 unsigned int type;
940 unsigned int index;
941 u16 mcs, real_mcs;
942
943 /*
944 * During each loop we will compare the freshly read
945 * TX_STA_FIFO register value with the value read from
946 * the previous loop. If the 2 values are equal then
947 * we should stop processing because the chance it
948 * quite big that the device has been unplugged and
949 * we risk going into an endless loop.
950 */
951 old_reg = 0;
952
953 while (1) {
9ca21eb7 954 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
a9b3a9f7
ID		 955 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
956 break;
957
958 if (old_reg == reg)
959 break;
960 old_reg = reg;
961
962 /*
963 * Skip this entry when it contains an invalid
964 * queue identication number.
965 */
966 type = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE) - 1;
967 if (type >= QID_RX)
968 continue;
969
970 queue = rt2x00queue_get_queue(rt2x00dev, type);
971 if (unlikely(!queue))
972 continue;
973
974 /*
975 * Skip this entry when it contains an invalid
976 * index number.
977 */
978 index = rt2x00_get_field32(reg, TX_STA_FIFO_WCID) - 1;
979 if (unlikely(index >= queue->limit))
980 continue;
981
982 entry = &queue->entries[index];
983 entry_priv = entry->priv_data;
984 rt2x00_desc_read((__le32 *)entry->skb->data, 0, &word);
985
986 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
987 while (entry != entry_done) {
988 /*
989 * Catch up.
990 * Just report any entries we missed as failed.
991 */
992 WARNING(rt2x00dev,
993 "TX status report missed for entry %d\n",
994 entry_done->entry_idx);
995
996 txdesc.flags = 0;
997 __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
998 txdesc.retry = 0;
999
1000 rt2x00lib_txdone(entry_done, &txdesc);
1001 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1002 }
1003
1004 /*
1005 * Obtain the status about this packet.
1006 */
1007 txdesc.flags = 0;
1008 if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS))
1009 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1010 else
1011 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1012
1013 /*
1014 * Ralink has a retry mechanism using a global fallback
1015 * table. We setup this fallback table to try immediate
1016 * lower rate for all rates. In the TX_STA_FIFO,
1017 * the MCS field contains the MCS used for the successfull
1018 * transmission. If the first transmission succeed,
1019 * we have mcs == tx_mcs. On the second transmission,
1020 * we have mcs = tx_mcs - 1. So the number of
1021 * retry is (tx_mcs - mcs).
1022 */
1023 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
1024 real_mcs = rt2x00_get_field32(reg, TX_STA_FIFO_MCS);
1025 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
1026 txdesc.retry = mcs - min(mcs, real_mcs);
1027
1028 rt2x00lib_txdone(entry, &txdesc);
1029 }
1030}
1031
1032static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
1033{
1034 struct rt2x00_dev *rt2x00dev = dev_instance;
1035 u32 reg;
1036
1037 /* Read status and ACK all interrupts */
9ca21eb7
BZ		 1038 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1039 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
a9b3a9f7
ID		 1040
1041 if (!reg)
1042 return IRQ_NONE;
1043
1044 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1045 return IRQ_HANDLED;
1046
1047 /*
1048 * 1 - Rx ring done interrupt.
1049 */
1050 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
1051 rt2x00pci_rxdone(rt2x00dev);
1052
1053 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
1054 rt2800pci_txdone(rt2x00dev);
1055
1056 return IRQ_HANDLED;
1057}
1058
1059/*
1060 * Device probe functions.
1061 */
7ab71325
BZ		 1062static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1063{
1064 /*
1065 * Read EEPROM into buffer
1066 */
1067 switch (rt2x00dev->chip.rt) {
1068 case RT2880:
1069 case RT3052:
1070 rt2800pci_read_eeprom_soc(rt2x00dev);
1071 break;
1072 default:
1073 if (rt2800pci_efuse_detect(rt2x00dev))
1074 rt2800pci_read_eeprom_efuse(rt2x00dev);
1075 else
1076 rt2800pci_read_eeprom_pci(rt2x00dev);
1077 break;
1078 }
1079
1080 return rt2800_validate_eeprom(rt2x00dev);
1081}
1082
b0a1edab
BZ		 1083static const struct rt2800_ops rt2800pci_rt2800_ops = {
1084 .register_read = rt2x00pci_register_read,
1085 .register_write = rt2x00pci_register_write,
1086 .register_write_lock = rt2x00pci_register_write, /* same for PCI */
1087
1088 .register_multiread = rt2x00pci_register_multiread,
1089 .register_multiwrite = rt2x00pci_register_multiwrite,
1090
1091 .regbusy_read = rt2x00pci_regbusy_read,
1092};
1093
a9b3a9f7
ID		 1094static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1095{
1096 int retval;
1097
b0a1edab
BZ		 1098 rt2x00dev->priv = (void *)&rt2800pci_rt2800_ops;
1099
a9b3a9f7
ID		 1100 /*
1101 * Allocate eeprom data.
1102 */
1103 retval = rt2800pci_validate_eeprom(rt2x00dev);
1104 if (retval)
1105 return retval;
1106
38bd7b8a 1107 retval = rt2800_init_eeprom(rt2x00dev);
a9b3a9f7
ID		 1108 if (retval)
1109 return retval;
1110
1111 /*
1112 * Initialize hw specifications.
1113 */
4da2933f 1114 retval = rt2800_probe_hw_mode(rt2x00dev);
a9b3a9f7
ID		 1115 if (retval)
1116 return retval;
1117
1118 /*
1119 * This device has multiple filters for control frames
1120 * and has a separate filter for PS Poll frames.
1121 */
1122 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
1123 __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
1124
1125 /*
1126 * This device requires firmware.
1127 */
1128 if (!rt2x00_rt(&rt2x00dev->chip, RT2880) &&
1129 !rt2x00_rt(&rt2x00dev->chip, RT3052))
1130 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
1131 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1132 __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
1133 if (!modparam_nohwcrypt)
1134 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
1135
1136 /*
1137 * Set the rssi offset.
1138 */
1139 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1140
1141 return 0;
1142}
1143
a9b3a9f7
ID		 1144static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1145 .irq_handler = rt2800pci_interrupt,
1146 .probe_hw = rt2800pci_probe_hw,
1147 .get_firmware_name = rt2800pci_get_firmware_name,
1148 .check_firmware = rt2800pci_check_firmware,
1149 .load_firmware = rt2800pci_load_firmware,
1150 .initialize = rt2x00pci_initialize,
1151 .uninitialize = rt2x00pci_uninitialize,
1152 .get_entry_state = rt2800pci_get_entry_state,
1153 .clear_entry = rt2800pci_clear_entry,
1154 .set_device_state = rt2800pci_set_device_state,
f4450616
BZ		 1155 .rfkill_poll = rt2800_rfkill_poll,
1156 .link_stats = rt2800_link_stats,
1157 .reset_tuner = rt2800_reset_tuner,
1158 .link_tuner = rt2800_link_tuner,
a9b3a9f7
ID		 1159 .write_tx_desc = rt2800pci_write_tx_desc,
1160 .write_tx_data = rt2x00pci_write_tx_data,
1161 .write_beacon = rt2800pci_write_beacon,
1162 .kick_tx_queue = rt2800pci_kick_tx_queue,
1163 .kill_tx_queue = rt2800pci_kill_tx_queue,
1164 .fill_rxdone = rt2800pci_fill_rxdone,
f4450616
BZ		 1165 .config_shared_key = rt2800_config_shared_key,
1166 .config_pairwise_key = rt2800_config_pairwise_key,
1167 .config_filter = rt2800_config_filter,
1168 .config_intf = rt2800_config_intf,
1169 .config_erp = rt2800_config_erp,
1170 .config_ant = rt2800_config_ant,
1171 .config = rt2800_config,
a9b3a9f7
ID		 1172};
1173
1174static const struct data_queue_desc rt2800pci_queue_rx = {
1175 .entry_num = RX_ENTRIES,
1176 .data_size = AGGREGATION_SIZE,
1177 .desc_size = RXD_DESC_SIZE,
1178 .priv_size = sizeof(struct queue_entry_priv_pci),
1179};
1180
1181static const struct data_queue_desc rt2800pci_queue_tx = {
1182 .entry_num = TX_ENTRIES,
1183 .data_size = AGGREGATION_SIZE,
1184 .desc_size = TXD_DESC_SIZE,
1185 .priv_size = sizeof(struct queue_entry_priv_pci),
1186};
1187
1188static const struct data_queue_desc rt2800pci_queue_bcn = {
1189 .entry_num = 8 * BEACON_ENTRIES,
1190 .data_size = 0, /* No DMA required for beacons */
1191 .desc_size = TXWI_DESC_SIZE,
1192 .priv_size = sizeof(struct queue_entry_priv_pci),
1193};
1194
1195static const struct rt2x00_ops rt2800pci_ops = {
1196 .name = KBUILD_MODNAME,
1197 .max_sta_intf = 1,
1198 .max_ap_intf = 8,
1199 .eeprom_size = EEPROM_SIZE,
1200 .rf_size = RF_SIZE,
1201 .tx_queues = NUM_TX_QUEUES,
1202 .rx = &rt2800pci_queue_rx,
1203 .tx = &rt2800pci_queue_tx,
1204 .bcn = &rt2800pci_queue_bcn,
1205 .lib = &rt2800pci_rt2x00_ops,
2ce33995 1206 .hw = &rt2800_mac80211_ops,
a9b3a9f7 1207#ifdef CONFIG_RT2X00_LIB_DEBUGFS
f4450616 1208 .debugfs = &rt2800_rt2x00debug,
a9b3a9f7
ID		 1209#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1210};
1211
1212/*
1213 * RT2800pci module information.
1214 */
1215static struct pci_device_id rt2800pci_device_table[] = {
1216 { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
1217 { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
1218 { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
1219 { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
1220 { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
1221 { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
1222 { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
1223 { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
1224 { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
1225 { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
1226 { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
1227 { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
1228 { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
1229 { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
1230 { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
1231 { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
1232 { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
1233 { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
1234 { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
1235 { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
1236 { 0, }
1237};
1238
1239MODULE_AUTHOR(DRV_PROJECT);
1240MODULE_VERSION(DRV_VERSION);
1241MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1242MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1243#ifdef CONFIG_RT2800PCI_PCI
1244MODULE_FIRMWARE(FIRMWARE_RT2860);
1245MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1246#endif /* CONFIG_RT2800PCI_PCI */
1247MODULE_LICENSE("GPL");
1248
1249#ifdef CONFIG_RT2800PCI_WISOC
1250#if defined(CONFIG_RALINK_RT288X)
1251__rt2x00soc_probe(RT2880, &rt2800pci_ops);
1252#elif defined(CONFIG_RALINK_RT305X)
1253__rt2x00soc_probe(RT3052, &rt2800pci_ops);
1254#endif
1255
1256static struct platform_driver rt2800soc_driver = {
1257 .driver = {
1258 .name = "rt2800_wmac",
1259 .owner = THIS_MODULE,
1260 .mod_name = KBUILD_MODNAME,
1261 },
1262 .probe = __rt2x00soc_probe,
1263 .remove = __devexit_p(rt2x00soc_remove),
1264 .suspend = rt2x00soc_suspend,
1265 .resume = rt2x00soc_resume,
1266};
1267#endif /* CONFIG_RT2800PCI_WISOC */
1268
1269#ifdef CONFIG_RT2800PCI_PCI
1270static struct pci_driver rt2800pci_driver = {
1271 .name = KBUILD_MODNAME,
1272 .id_table = rt2800pci_device_table,
1273 .probe = rt2x00pci_probe,
1274 .remove = __devexit_p(rt2x00pci_remove),
1275 .suspend = rt2x00pci_suspend,
1276 .resume = rt2x00pci_resume,
1277};
1278#endif /* CONFIG_RT2800PCI_PCI */
1279
1280static int __init rt2800pci_init(void)
1281{
1282 int ret = 0;
1283
1284#ifdef CONFIG_RT2800PCI_WISOC
1285 ret = platform_driver_register(&rt2800soc_driver);
1286 if (ret)
1287 return ret;
1288#endif
1289#ifdef CONFIG_RT2800PCI_PCI
1290 ret = pci_register_driver(&rt2800pci_driver);
1291 if (ret) {
1292#ifdef CONFIG_RT2800PCI_WISOC
1293 platform_driver_unregister(&rt2800soc_driver);
1294#endif
1295 return ret;
1296 }
1297#endif
1298
1299 return ret;
1300}
1301
1302static void __exit rt2800pci_exit(void)
1303{
1304#ifdef CONFIG_RT2800PCI_PCI
1305 pci_unregister_driver(&rt2800pci_driver);
1306#endif
1307#ifdef CONFIG_RT2800PCI_WISOC
1308 platform_driver_unregister(&rt2800soc_driver);
1309#endif
1310}
1311
1312module_init(rt2800pci_init);
1313module_exit(rt2800pci_exit);
Linux kernel - Deliverables
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