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rt2800: prepare for unification of EEPROM support code
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2800pci.c
CommitLineData
a9b3a9f7
ID		 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2800pci
23 Abstract: rt2800pci device specific routines.
24 Supported chipsets: RT2800E & RT2800ED.
25 */
26
27#include <linux/crc-ccitt.h>
28#include <linux/delay.h>
29#include <linux/etherdevice.h>
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/pci.h>
34#include <linux/platform_device.h>
35#include <linux/eeprom_93cx6.h>
36
37#include "rt2x00.h"
38#include "rt2x00pci.h"
39#include "rt2x00soc.h"
7ef5cc92 40#include "rt2800lib.h"
b54f78a8 41#include "rt2800.h"
a9b3a9f7
ID		 42#include "rt2800pci.h"
43
44#ifdef CONFIG_RT2800PCI_PCI_MODULE
45#define CONFIG_RT2800PCI_PCI
46#endif
47
48#ifdef CONFIG_RT2800PCI_WISOC_MODULE
49#define CONFIG_RT2800PCI_WISOC
50#endif
51
52/*
53 * Allow hardware encryption to be disabled.
54 */
55static int modparam_nohwcrypt = 1;
56module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
57MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
58
a9b3a9f7
ID		 59static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
60{
61 unsigned int i;
62 u32 reg;
63
64 for (i = 0; i < 200; i++) {
9ca21eb7 65 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
a9b3a9f7
ID		 66
67 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
68 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
69 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
70 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
71 break;
72
73 udelay(REGISTER_BUSY_DELAY);
74 }
75
76 if (i == 200)
77 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
78
9ca21eb7
BZ		 79 rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
80 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
a9b3a9f7
ID		 81}
82
83#ifdef CONFIG_RT2800PCI_WISOC
84static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
85{
86 u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */
87
88 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
89}
90#else
91static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
92{
93}
94#endif /* CONFIG_RT2800PCI_WISOC */
95
96#ifdef CONFIG_RT2800PCI_PCI
97static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
98{
99 struct rt2x00_dev *rt2x00dev = eeprom->data;
100 u32 reg;
101
9ca21eb7 102 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 103
104 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
105 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
106 eeprom->reg_data_clock =
107 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
108 eeprom->reg_chip_select =
109 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
110}
111
112static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
113{
114 struct rt2x00_dev *rt2x00dev = eeprom->data;
115 u32 reg = 0;
116
117 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
118 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
119 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
120 !!eeprom->reg_data_clock);
121 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
122 !!eeprom->reg_chip_select);
123
9ca21eb7 124 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
a9b3a9f7
ID		 125}
126
127static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
128{
129 struct eeprom_93cx6 eeprom;
130 u32 reg;
131
9ca21eb7 132 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 133
134 eeprom.data = rt2x00dev;
135 eeprom.register_read = rt2800pci_eepromregister_read;
136 eeprom.register_write = rt2800pci_eepromregister_write;
137 eeprom.width = !rt2x00_get_field32(reg, E2PROM_CSR_TYPE) ?
138 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
139 eeprom.reg_data_in = 0;
140 eeprom.reg_data_out = 0;
141 eeprom.reg_data_clock = 0;
142 eeprom.reg_chip_select = 0;
143
144 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
145 EEPROM_SIZE / sizeof(u16));
146}
147
a6598682
GW		 148static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
149{
150 u32 reg;
151
152 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
153
154 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
155}
156
a9b3a9f7
ID		 157static void rt2800pci_efuse_read(struct rt2x00_dev *rt2x00dev,
158 unsigned int i)
159{
160 u32 reg;
161
9ca21eb7 162 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
a9b3a9f7
ID		 163 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
164 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
165 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
9ca21eb7 166 rt2800_register_write(rt2x00dev, EFUSE_CTRL, reg);
a9b3a9f7
ID		 167
168 /* Wait until the EEPROM has been loaded */
b4a77d0d 169 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
a9b3a9f7
ID		 170
171 /* Apparently the data is read from end to start */
9ca21eb7 172 rt2800_register_read(rt2x00dev, EFUSE_DATA3,
a9b3a9f7 173 (u32 *)&rt2x00dev->eeprom[i]);
9ca21eb7 174 rt2800_register_read(rt2x00dev, EFUSE_DATA2,
a9b3a9f7 175 (u32 *)&rt2x00dev->eeprom[i + 2]);
9ca21eb7 176 rt2800_register_read(rt2x00dev, EFUSE_DATA1,
a9b3a9f7 177 (u32 *)&rt2x00dev->eeprom[i + 4]);
9ca21eb7 178 rt2800_register_read(rt2x00dev, EFUSE_DATA0,
a9b3a9f7
ID		 179 (u32 *)&rt2x00dev->eeprom[i + 6]);
180}
181
182static void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
183{
184 unsigned int i;
185
186 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
187 rt2800pci_efuse_read(rt2x00dev, i);
188}
189#else
190static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
191{
192}
193
a6598682
GW		 194static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
195{
196 return 0;
197}
198
a9b3a9f7
ID		 199static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
200{
201}
202#endif /* CONFIG_RT2800PCI_PCI */
203
a9b3a9f7
ID		 204/*
205 * Firmware functions
206 */
207static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
208{
209 return FIRMWARE_RT2860;
210}
211
212static int rt2800pci_check_firmware(struct rt2x00_dev *rt2x00dev,
213 const u8 *data, const size_t len)
214{
215 u16 fw_crc;
216 u16 crc;
217
218 /*
219 * Only support 8kb firmware files.
220 */
221 if (len != 8192)
222 return FW_BAD_LENGTH;
223
224 /*
225 * The last 2 bytes in the firmware array are the crc checksum itself,
226 * this means that we should never pass those 2 bytes to the crc
227 * algorithm.
228 */
229 fw_crc = (data[len - 2] << 8 | data[len - 1]);
230
231 /*
232 * Use the crc ccitt algorithm.
233 * This will return the same value as the legacy driver which
234 * used bit ordering reversion on the both the firmware bytes
235 * before input input as well as on the final output.
236 * Obviously using crc ccitt directly is much more efficient.
237 */
238 crc = crc_ccitt(~0, data, len - 2);
239
240 /*
241 * There is a small difference between the crc-itu-t + bitrev and
242 * the crc-ccitt crc calculation. In the latter method the 2 bytes
243 * will be swapped, use swab16 to convert the crc to the correct
244 * value.
245 */
246 crc = swab16(crc);
247
248 return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
249}
250
251static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
252 const u8 *data, const size_t len)
253{
254 unsigned int i;
255 u32 reg;
256
257 /*
258 * Wait for stable hardware.
259 */
260 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9ca21eb7 261 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
a9b3a9f7
ID		 262 if (reg && reg != ~0)
263 break;
264 msleep(1);
265 }
266
267 if (i == REGISTER_BUSY_COUNT) {
268 ERROR(rt2x00dev, "Unstable hardware.\n");
269 return -EBUSY;
270 }
271
9ca21eb7
BZ		 272 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
273 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
a9b3a9f7
ID		 274
275 /*
276 * Disable DMA, will be reenabled later when enabling
277 * the radio.
278 */
9ca21eb7 279 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 280 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
281 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
282 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
283 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
284 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 285 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7
ID		 286
287 /*
288 * enable Host program ram write selection
289 */
290 reg = 0;
291 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
9ca21eb7 292 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
a9b3a9f7
ID		 293
294 /*
295 * Write firmware to device.
296 */
4f2732ce 297 rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
a9b3a9f7
ID		 298 data, len);
299
9ca21eb7
BZ		 300 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
301 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
a9b3a9f7
ID		 302
303 /*
304 * Wait for device to stabilize.
305 */
306 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9ca21eb7 307 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
a9b3a9f7
ID		 308 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
309 break;
310 msleep(1);
311 }
312
313 if (i == REGISTER_BUSY_COUNT) {
314 ERROR(rt2x00dev, "PBF system register not ready.\n");
315 return -EBUSY;
316 }
317
318 /*
319 * Disable interrupts
320 */
321 rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_OFF);
322
323 /*
324 * Initialize BBP R/W access agent
325 */
9ca21eb7
BZ		 326 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
327 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
a9b3a9f7
ID		 328
329 return 0;
330}
331
332/*
333 * Initialization functions.
334 */
335static bool rt2800pci_get_entry_state(struct queue_entry *entry)
336{
337 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
338 u32 word;
339
340 if (entry->queue->qid == QID_RX) {
341 rt2x00_desc_read(entry_priv->desc, 1, &word);
342
343 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
344 } else {
345 rt2x00_desc_read(entry_priv->desc, 1, &word);
346
347 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
348 }
349}
350
351static void rt2800pci_clear_entry(struct queue_entry *entry)
352{
353 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
354 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
355 u32 word;
356
357 if (entry->queue->qid == QID_RX) {
358 rt2x00_desc_read(entry_priv->desc, 0, &word);
359 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
360 rt2x00_desc_write(entry_priv->desc, 0, word);
361
362 rt2x00_desc_read(entry_priv->desc, 1, &word);
363 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
364 rt2x00_desc_write(entry_priv->desc, 1, word);
365 } else {
366 rt2x00_desc_read(entry_priv->desc, 1, &word);
367 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
368 rt2x00_desc_write(entry_priv->desc, 1, word);
369 }
370}
371
372static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
373{
374 struct queue_entry_priv_pci *entry_priv;
375 u32 reg;
376
9ca21eb7 377 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
a9b3a9f7
ID		 378 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
379 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
380 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
381 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
382 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
383 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
384 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
9ca21eb7 385 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
a9b3a9f7 386
9ca21eb7
BZ		 387 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
388 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
a9b3a9f7
ID		 389
390 /*
391 * Initialize registers.
392 */
393 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
9ca21eb7
BZ		 394 rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
395 rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
396 rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
397 rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
a9b3a9f7
ID		 398
399 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
9ca21eb7
BZ		 400 rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
401 rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
402 rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
403 rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
a9b3a9f7
ID		 404
405 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
9ca21eb7
BZ		 406 rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
407 rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
408 rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
409 rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
a9b3a9f7
ID		 410
411 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
9ca21eb7
BZ		 412 rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
413 rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
414 rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
415 rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
a9b3a9f7
ID		 416
417 entry_priv = rt2x00dev->rx->entries[0].priv_data;
9ca21eb7
BZ		 418 rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
419 rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
420 rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
421 rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
a9b3a9f7
ID		 422
423 /*
424 * Enable global DMA configuration
425 */
9ca21eb7 426 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 427 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
428 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
429 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 430 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7 431
9ca21eb7 432 rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
a9b3a9f7
ID		 433
434 return 0;
435}
436
a9b3a9f7
ID		 437/*
438 * Device state switch handlers.
439 */
440static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
441 enum dev_state state)
442{
443 u32 reg;
444
9ca21eb7 445 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
a9b3a9f7
ID		 446 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
447 (state == STATE_RADIO_RX_ON) ||
448 (state == STATE_RADIO_RX_ON_LINK));
9ca21eb7 449 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
a9b3a9f7
ID		 450}
451
452static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
453 enum dev_state state)
454{
455 int mask = (state == STATE_RADIO_IRQ_ON);
456 u32 reg;
457
458 /*
459 * When interrupts are being enabled, the interrupt registers
460 * should clear the register to assure a clean state.
461 */
462 if (state == STATE_RADIO_IRQ_ON) {
9ca21eb7
BZ		 463 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
464 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
a9b3a9f7
ID		 465 }
466
9ca21eb7 467 rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
a9b3a9f7
ID		 468 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
469 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
470 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
471 rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
472 rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
473 rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
474 rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
475 rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
476 rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
477 rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
478 rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, mask);
479 rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
480 rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
481 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
482 rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
483 rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
484 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
485 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
9ca21eb7 486 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
a9b3a9f7
ID		 487}
488
489static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
490{
491 unsigned int i;
492 u32 reg;
493
494 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9ca21eb7 495 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 496 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
497 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
498 return 0;
499
500 msleep(1);
501 }
502
503 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
504 return -EACCES;
505}
506
507static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
508{
509 u32 reg;
510 u16 word;
511
512 /*
513 * Initialize all registers.
514 */
515 if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) ||
516 rt2800pci_init_queues(rt2x00dev) ||
fcf51541 517 rt2800_init_registers(rt2x00dev) ||
a9b3a9f7 518 rt2800pci_wait_wpdma_ready(rt2x00dev) ||
fcf51541
BZ		 519 rt2800_init_bbp(rt2x00dev) ||
520 rt2800_init_rfcsr(rt2x00dev)))
a9b3a9f7
ID		 521 return -EIO;
522
523 /*
524 * Send signal to firmware during boot time.
525 */
3a9e5b0f 526 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
a9b3a9f7
ID		 527
528 /*
529 * Enable RX.
530 */
9ca21eb7 531 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
a9b3a9f7
ID		 532 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
533 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
9ca21eb7 534 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
a9b3a9f7 535
9ca21eb7 536 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 537 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
538 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
539 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
540 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 541 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7 542
9ca21eb7 543 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
a9b3a9f7
ID		 544 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
545 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
9ca21eb7 546 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
a9b3a9f7
ID		 547
548 /*
549 * Initialize LED control
550 */
551 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
3a9e5b0f 552 rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
a9b3a9f7
ID		 553 word & 0xff, (word >> 8) & 0xff);
554
555 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
3a9e5b0f 556 rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
a9b3a9f7
ID		 557 word & 0xff, (word >> 8) & 0xff);
558
559 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
3a9e5b0f 560 rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
a9b3a9f7
ID		 561 word & 0xff, (word >> 8) & 0xff);
562
563 return 0;
564}
565
566static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
567{
568 u32 reg;
569
9ca21eb7 570 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 571 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
572 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
573 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
574 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
575 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 576 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7 577
9ca21eb7
BZ		 578 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
579 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
580 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
a9b3a9f7 581
9ca21eb7 582 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
a9b3a9f7 583
9ca21eb7 584 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
a9b3a9f7
ID		 585 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
586 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
587 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
588 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
589 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
590 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
591 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
9ca21eb7 592 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
a9b3a9f7 593
9ca21eb7
BZ		 594 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
595 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
a9b3a9f7
ID		 596
597 /* Wait for DMA, ignore error */
598 rt2800pci_wait_wpdma_ready(rt2x00dev);
599}
600
601static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
602 enum dev_state state)
603{
604 /*
605 * Always put the device to sleep (even when we intend to wakeup!)
606 * if the device is booting and wasn't asleep it will return
607 * failure when attempting to wakeup.
608 */
3a9e5b0f 609 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
a9b3a9f7
ID		 610
611 if (state == STATE_AWAKE) {
3a9e5b0f 612 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
a9b3a9f7
ID		 613 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
614 }
615
616 return 0;
617}
618
619static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
620 enum dev_state state)
621{
622 int retval = 0;
623
624 switch (state) {
625 case STATE_RADIO_ON:
626 /*
627 * Before the radio can be enabled, the device first has
628 * to be woken up. After that it needs a bit of time
629 * to be fully awake and then the radio can be enabled.
630 */
631 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
632 msleep(1);
633 retval = rt2800pci_enable_radio(rt2x00dev);
634 break;
635 case STATE_RADIO_OFF:
636 /*
637 * After the radio has been disabled, the device should
638 * be put to sleep for powersaving.
639 */
640 rt2800pci_disable_radio(rt2x00dev);
641 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
642 break;
643 case STATE_RADIO_RX_ON:
644 case STATE_RADIO_RX_ON_LINK:
645 case STATE_RADIO_RX_OFF:
646 case STATE_RADIO_RX_OFF_LINK:
647 rt2800pci_toggle_rx(rt2x00dev, state);
648 break;
649 case STATE_RADIO_IRQ_ON:
650 case STATE_RADIO_IRQ_OFF:
651 rt2800pci_toggle_irq(rt2x00dev, state);
652 break;
653 case STATE_DEEP_SLEEP:
654 case STATE_SLEEP:
655 case STATE_STANDBY:
656 case STATE_AWAKE:
657 retval = rt2800pci_set_state(rt2x00dev, state);
658 break;
659 default:
660 retval = -ENOTSUPP;
661 break;
662 }
663
664 if (unlikely(retval))
665 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
666 state, retval);
667
668 return retval;
669}
670
671/*
672 * TX descriptor initialization
673 */
674static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
675 struct sk_buff *skb,
676 struct txentry_desc *txdesc)
677{
678 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
679 __le32 *txd = skbdesc->desc;
680 __le32 *txwi = (__le32 *)(skb->data - rt2x00dev->hw->extra_tx_headroom);
681 u32 word;
682
683 /*
684 * Initialize TX Info descriptor
685 */
686 rt2x00_desc_read(txwi, 0, &word);
687 rt2x00_set_field32(&word, TXWI_W0_FRAG,
688 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
689 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
690 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
691 rt2x00_set_field32(&word, TXWI_W0_TS,
692 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
693 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
694 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
695 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
696 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
697 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
698 rt2x00_set_field32(&word, TXWI_W0_BW,
699 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
700 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
701 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
702 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
703 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
704 rt2x00_desc_write(txwi, 0, word);
705
706 rt2x00_desc_read(txwi, 1, &word);
707 rt2x00_set_field32(&word, TXWI_W1_ACK,
708 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
709 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
710 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
711 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
712 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
713 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
f644fea1 714 txdesc->key_idx : 0xff);
a9b3a9f7
ID		 715 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
716 skb->len - txdesc->l2pad);
717 rt2x00_set_field32(&word, TXWI_W1_PACKETID,
718 skbdesc->entry->queue->qid + 1);
719 rt2x00_desc_write(txwi, 1, word);
720
721 /*
722 * Always write 0 to IV/EIV fields, hardware will insert the IV
77dba493
BZ		 723 * from the IVEIV register when TXD_W3_WIV is set to 0.
724 * When TXD_W3_WIV is set to 1 it will use the IV data
a9b3a9f7
ID		 725 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
726 * crypto entry in the registers should be used to encrypt the frame.
727 */
728 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
729 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
730
731 /*
732 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
733 * must contains a TXWI structure + 802.11 header + padding + 802.11
734 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
735 * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
736 * data. It means that LAST_SEC0 is always 0.
737 */
738
739 /*
740 * Initialize TX descriptor
741 */
742 rt2x00_desc_read(txd, 0, &word);
743 rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
744 rt2x00_desc_write(txd, 0, word);
745
746 rt2x00_desc_read(txd, 1, &word);
747 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
748 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
749 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
750 rt2x00_set_field32(&word, TXD_W1_BURST,
751 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
752 rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
753 rt2x00dev->hw->extra_tx_headroom);
754 rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
755 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
756 rt2x00_desc_write(txd, 1, word);
757
758 rt2x00_desc_read(txd, 2, &word);
759 rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
760 skbdesc->skb_dma + rt2x00dev->hw->extra_tx_headroom);
761 rt2x00_desc_write(txd, 2, word);
762
763 rt2x00_desc_read(txd, 3, &word);
764 rt2x00_set_field32(&word, TXD_W3_WIV,
765 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
766 rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
767 rt2x00_desc_write(txd, 3, word);
768}
769
770/*
771 * TX data initialization
772 */
773static void rt2800pci_write_beacon(struct queue_entry *entry)
774{
775 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
776 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
777 unsigned int beacon_base;
778 u32 reg;
779
780 /*
781 * Disable beaconing while we are reloading the beacon data,
782 * otherwise we might be sending out invalid data.
783 */
9ca21eb7 784 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
a9b3a9f7 785 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
9ca21eb7 786 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
a9b3a9f7
ID		 787
788 /*
789 * Write entire beacon with descriptor to register.
790 */
791 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
4f2732ce 792 rt2800_register_multiwrite(rt2x00dev,
a9b3a9f7
ID		 793 beacon_base,
794 skbdesc->desc, skbdesc->desc_len);
4f2732ce 795 rt2800_register_multiwrite(rt2x00dev,
a9b3a9f7
ID		 796 beacon_base + skbdesc->desc_len,
797 entry->skb->data, entry->skb->len);
798
799 /*
800 * Clean up beacon skb.
801 */
802 dev_kfree_skb_any(entry->skb);
803 entry->skb = NULL;
804}
805
806static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
807 const enum data_queue_qid queue_idx)
808{
809 struct data_queue *queue;
810 unsigned int idx, qidx = 0;
811 u32 reg;
812
813 if (queue_idx == QID_BEACON) {
9ca21eb7 814 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
a9b3a9f7
ID		 815 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
816 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
817 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
818 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
9ca21eb7 819 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
a9b3a9f7
ID		 820 }
821 return;
822 }
823
824 if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
825 return;
826
827 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
828 idx = queue->index[Q_INDEX];
829
830 if (queue_idx == QID_MGMT)
831 qidx = 5;
832 else
833 qidx = queue_idx;
834
9ca21eb7 835 rt2800_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
a9b3a9f7
ID		 836}
837
838static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
839 const enum data_queue_qid qid)
840{
841 u32 reg;
842
843 if (qid == QID_BEACON) {
9ca21eb7 844 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, 0);
a9b3a9f7
ID		 845 return;
846 }
847
9ca21eb7 848 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
a9b3a9f7
ID		 849 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
850 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
851 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
852 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
9ca21eb7 853 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
a9b3a9f7
ID		 854}
855
856/*
857 * RX control handlers
858 */
859static void rt2800pci_fill_rxdone(struct queue_entry *entry,
860 struct rxdone_entry_desc *rxdesc)
861{
862 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
863 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
864 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
865 __le32 *rxd = entry_priv->desc;
866 __le32 *rxwi = (__le32 *)entry->skb->data;
867 u32 rxd3;
868 u32 rxwi0;
869 u32 rxwi1;
870 u32 rxwi2;
871 u32 rxwi3;
872
873 rt2x00_desc_read(rxd, 3, &rxd3);
874 rt2x00_desc_read(rxwi, 0, &rxwi0);
875 rt2x00_desc_read(rxwi, 1, &rxwi1);
876 rt2x00_desc_read(rxwi, 2, &rxwi2);
877 rt2x00_desc_read(rxwi, 3, &rxwi3);
878
879 if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR))
880 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
881
882 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
883 /*
884 * Unfortunately we don't know the cipher type used during
885 * decryption. This prevents us from correct providing
886 * correct statistics through debugfs.
887 */
888 rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
889 rxdesc->cipher_status =
890 rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);
891 }
892
893 if (rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED)) {
894 /*
895 * Hardware has stripped IV/EIV data from 802.11 frame during
896 * decryption. Unfortunately the descriptor doesn't contain
897 * any fields with the EIV/IV data either, so they can't
898 * be restored by rt2x00lib.
899 */
900 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
901
902 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
903 rxdesc->flags |= RX_FLAG_DECRYPTED;
904 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
905 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
906 }
907
908 if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS))
909 rxdesc->dev_flags |= RXDONE_MY_BSS;
910
911 if (rt2x00_get_field32(rxd3, RXD_W3_L2PAD)) {
912 rxdesc->dev_flags |= RXDONE_L2PAD;
913 skbdesc->flags |= SKBDESC_L2_PADDED;
914 }
915
916 if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
917 rxdesc->flags |= RX_FLAG_SHORT_GI;
918
919 if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
920 rxdesc->flags |= RX_FLAG_40MHZ;
921
922 /*
923 * Detect RX rate, always use MCS as signal type.
924 */
925 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
926 rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
927 rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
928
929 /*
930 * Mask of 0x8 bit to remove the short preamble flag.
931 */
932 if (rxdesc->rate_mode == RATE_MODE_CCK)
933 rxdesc->signal &= ~0x8;
934
935 rxdesc->rssi =
936 (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
937 rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
938
939 rxdesc->noise =
940 (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
941 rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
942
943 rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
944
945 /*
946 * Set RX IDX in register to inform hardware that we have handled
947 * this entry and it is available for reuse again.
948 */
9ca21eb7 949 rt2800_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
a9b3a9f7
ID		 950
951 /*
952 * Remove TXWI descriptor from start of buffer.
953 */
954 skb_pull(entry->skb, RXWI_DESC_SIZE);
955 skb_trim(entry->skb, rxdesc->size);
956}
957
958/*
959 * Interrupt functions.
960 */
961static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
962{
963 struct data_queue *queue;
964 struct queue_entry *entry;
965 struct queue_entry *entry_done;
966 struct queue_entry_priv_pci *entry_priv;
967 struct txdone_entry_desc txdesc;
968 u32 word;
969 u32 reg;
970 u32 old_reg;
971 unsigned int type;
972 unsigned int index;
973 u16 mcs, real_mcs;
974
975 /*
976 * During each loop we will compare the freshly read
977 * TX_STA_FIFO register value with the value read from
978 * the previous loop. If the 2 values are equal then
979 * we should stop processing because the chance it
980 * quite big that the device has been unplugged and
981 * we risk going into an endless loop.
982 */
983 old_reg = 0;
984
985 while (1) {
9ca21eb7 986 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
a9b3a9f7
ID		 987 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
988 break;
989
990 if (old_reg == reg)
991 break;
992 old_reg = reg;
993
994 /*
995 * Skip this entry when it contains an invalid
996 * queue identication number.
997 */
998 type = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE) - 1;
999 if (type >= QID_RX)
1000 continue;
1001
1002 queue = rt2x00queue_get_queue(rt2x00dev, type);
1003 if (unlikely(!queue))
1004 continue;
1005
1006 /*
1007 * Skip this entry when it contains an invalid
1008 * index number.
1009 */
1010 index = rt2x00_get_field32(reg, TX_STA_FIFO_WCID) - 1;
1011 if (unlikely(index >= queue->limit))
1012 continue;
1013
1014 entry = &queue->entries[index];
1015 entry_priv = entry->priv_data;
1016 rt2x00_desc_read((__le32 *)entry->skb->data, 0, &word);
1017
1018 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1019 while (entry != entry_done) {
1020 /*
1021 * Catch up.
1022 * Just report any entries we missed as failed.
1023 */
1024 WARNING(rt2x00dev,
1025 "TX status report missed for entry %d\n",
1026 entry_done->entry_idx);
1027
1028 txdesc.flags = 0;
1029 __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
1030 txdesc.retry = 0;
1031
1032 rt2x00lib_txdone(entry_done, &txdesc);
1033 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1034 }
1035
1036 /*
1037 * Obtain the status about this packet.
1038 */
1039 txdesc.flags = 0;
1040 if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS))
1041 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1042 else
1043 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1044
1045 /*
1046 * Ralink has a retry mechanism using a global fallback
1047 * table. We setup this fallback table to try immediate
1048 * lower rate for all rates. In the TX_STA_FIFO,
1049 * the MCS field contains the MCS used for the successfull
1050 * transmission. If the first transmission succeed,
1051 * we have mcs == tx_mcs. On the second transmission,
1052 * we have mcs = tx_mcs - 1. So the number of
1053 * retry is (tx_mcs - mcs).
1054 */
1055 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
1056 real_mcs = rt2x00_get_field32(reg, TX_STA_FIFO_MCS);
1057 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
1058 txdesc.retry = mcs - min(mcs, real_mcs);
1059
1060 rt2x00lib_txdone(entry, &txdesc);
1061 }
1062}
1063
1064static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
1065{
1066 struct rt2x00_dev *rt2x00dev = dev_instance;
1067 u32 reg;
1068
1069 /* Read status and ACK all interrupts */
9ca21eb7
BZ		 1070 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1071 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
a9b3a9f7
ID		 1072
1073 if (!reg)
1074 return IRQ_NONE;
1075
1076 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1077 return IRQ_HANDLED;
1078
1079 /*
1080 * 1 - Rx ring done interrupt.
1081 */
1082 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
1083 rt2x00pci_rxdone(rt2x00dev);
1084
1085 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
1086 rt2800pci_txdone(rt2x00dev);
1087
1088 return IRQ_HANDLED;
1089}
1090
1091/*
1092 * Device probe functions.
1093 */
7ab71325 1094static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
a9b3a9f7
ID		 1095{
1096 u16 word;
1097 u8 *mac;
1098 u8 default_lna_gain;
1099
a9b3a9f7
ID		 1100 /*
1101 * Start validation of the data that has been read.
1102 */
1103 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1104 if (!is_valid_ether_addr(mac)) {
1105 random_ether_addr(mac);
1106 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1107 }
1108
1109 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1110 if (word == 0xffff) {
1111 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
1112 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
1113 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
1114 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1115 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1116 } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) {
1117 /*
7ab71325 1118 * There is a max of 2 RX streams for RT28x0 series
a9b3a9f7
ID		 1119 */
1120 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
1121 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
1122 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1123 }
1124
1125 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1126 if (word == 0xffff) {
1127 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
1128 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
1129 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1130 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1131 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1132 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
1133 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
1134 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
1135 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
1136 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
1137 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1138 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1139 }
1140
1141 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1142 if ((word & 0x00ff) == 0x00ff) {
1143 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1144 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
1145 LED_MODE_TXRX_ACTIVITY);
1146 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
1147 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1148 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
1149 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
1150 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
1151 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1152 }
1153
1154 /*
1155 * During the LNA validation we are going to use
1156 * lna0 as correct value. Note that EEPROM_LNA
1157 * is never validated.
1158 */
1159 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
1160 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
1161
1162 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
1163 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
1164 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
1165 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
1166 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
1167 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
1168
1169 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
1170 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
1171 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
1172 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
1173 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
1174 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
1175 default_lna_gain);
1176 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
1177
1178 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
1179 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
1180 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
1181 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
1182 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
1183 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
1184
1185 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
1186 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
1187 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
1188 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
1189 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
1190 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
1191 default_lna_gain);
1192 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
1193
1194 return 0;
1195}
1196
7ab71325
BZ		 1197static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1198{
1199 /*
1200 * Read EEPROM into buffer
1201 */
1202 switch (rt2x00dev->chip.rt) {
1203 case RT2880:
1204 case RT3052:
1205 rt2800pci_read_eeprom_soc(rt2x00dev);
1206 break;
1207 default:
1208 if (rt2800pci_efuse_detect(rt2x00dev))
1209 rt2800pci_read_eeprom_efuse(rt2x00dev);
1210 else
1211 rt2800pci_read_eeprom_pci(rt2x00dev);
1212 break;
1213 }
1214
1215 return rt2800_validate_eeprom(rt2x00dev);
1216}
1217
a9b3a9f7
ID		 1218static int rt2800pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1219{
1220 u32 reg;
1221 u16 value;
1222 u16 eeprom;
1223
1224 /*
1225 * Read EEPROM word for configuration.
1226 */
1227 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1228
1229 /*
1230 * Identify RF chipset.
1231 */
1232 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
9ca21eb7 1233 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
7ab71325
BZ		 1234
1235 if (rt2x00_intf_is_pci(rt2x00dev))
1236 rt2x00_set_chip_rf(rt2x00dev, value, reg);
a9b3a9f7
ID		 1237
1238 if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
1239 !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
1240 !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
1241 !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
1242 !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
1243 !rt2x00_rf(&rt2x00dev->chip, RF2020) &&
7ab71325
BZ		 1244 (rt2x00_intf_is_usb(rt2x00dev) ||
1245 (rt2x00_intf_is_pci(rt2x00dev) &&
1246 !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
1247 !rt2x00_rf(&rt2x00dev->chip, RF3022)))) {
a9b3a9f7
ID		 1248 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1249 return -ENODEV;
1250 }
1251
1252 /*
1253 * Identify default antenna configuration.
1254 */
1255 rt2x00dev->default_ant.tx =
1256 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
1257 rt2x00dev->default_ant.rx =
1258 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
1259
1260 /*
1261 * Read frequency offset and RF programming sequence.
1262 */
1263 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1264 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1265
1266 /*
1267 * Read external LNA informations.
1268 */
1269 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1270
1271 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
1272 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1273 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
1274 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1275
1276 /*
1277 * Detect if this device has an hardware controlled radio.
1278 */
1279 if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
1280 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1281
1282 /*
1283 * Store led settings, for correct led behaviour.
1284 */
1285#ifdef CONFIG_RT2X00_LIB_LEDS
f4450616
BZ		 1286 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1287 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1288 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
a9b3a9f7
ID		 1289
1290 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
1291#endif /* CONFIG_RT2X00_LIB_LEDS */
1292
1293 return 0;
1294}
1295
1296/*
1297 * RF value list for rt2860
1298 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
1299 */
1300static const struct rf_channel rf_vals[] = {
1301 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
1302 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
1303 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
1304 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
1305 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
1306 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
1307 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
1308 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
1309 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
1310 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
1311 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
1312 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
1313 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
1314 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
1315
1316 /* 802.11 UNI / HyperLan 2 */
1317 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
1318 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
1319 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
1320 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
1321 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
1322 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
1323 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
1324 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
1325 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
1326 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
1327 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
1328 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
1329
1330 /* 802.11 HyperLan 2 */
1331 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
1332 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
1333 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
1334 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
1335 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
1336 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
1337 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
1338 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
1339 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
1340 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
1341 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
1342 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
1343 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
1344 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
1345 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
1346 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
1347
1348 /* 802.11 UNII */
1349 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
1350 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
1351 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
1352 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
1353 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
1354 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
1355 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
1356
1357 /* 802.11 Japan */
1358 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
1359 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
1360 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
1361 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
1362 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
1363 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
1364 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
1365};
1366
1367static int rt2800pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1368{
1369 struct hw_mode_spec *spec = &rt2x00dev->spec;
1370 struct channel_info *info;
1371 char *tx_power1;
1372 char *tx_power2;
1373 unsigned int i;
1374 u16 eeprom;
1375
1376 /*
1377 * Initialize all hw fields.
1378 */
1379 rt2x00dev->hw->flags =
1380 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1381 IEEE80211_HW_SIGNAL_DBM |
1382 IEEE80211_HW_SUPPORTS_PS |
1383 IEEE80211_HW_PS_NULLFUNC_STACK;
1384 rt2x00dev->hw->extra_tx_headroom = TXWI_DESC_SIZE;
1385
1386 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1387 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1388 rt2x00_eeprom_addr(rt2x00dev,
1389 EEPROM_MAC_ADDR_0));
1390
1391 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1392
1393 /*
1394 * Initialize hw_mode information.
1395 */
1396 spec->supported_bands = SUPPORT_BAND_2GHZ;
1397 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1398
1399 if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
1400 rt2x00_rf(&rt2x00dev->chip, RF2720) ||
1401 rt2x00_rf(&rt2x00dev->chip, RF3020) ||
1402 rt2x00_rf(&rt2x00dev->chip, RF3021) ||
1403 rt2x00_rf(&rt2x00dev->chip, RF3022) ||
1404 rt2x00_rf(&rt2x00dev->chip, RF2020) ||
1405 rt2x00_rf(&rt2x00dev->chip, RF3052)) {
1406 spec->num_channels = 14;
1407 spec->channels = rf_vals;
1408 } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
1409 rt2x00_rf(&rt2x00dev->chip, RF2750)) {
1410 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1411 spec->num_channels = ARRAY_SIZE(rf_vals);
1412 spec->channels = rf_vals;
1413 }
1414
1415 /*
1416 * Initialize HT information.
1417 */
1418 spec->ht.ht_supported = true;
1419 spec->ht.cap =
1420 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
1421 IEEE80211_HT_CAP_GRN_FLD |
1422 IEEE80211_HT_CAP_SGI_20 |
1423 IEEE80211_HT_CAP_SGI_40 |
1424 IEEE80211_HT_CAP_TX_STBC |
1425 IEEE80211_HT_CAP_RX_STBC |
1426 IEEE80211_HT_CAP_PSMP_SUPPORT;
1427 spec->ht.ampdu_factor = 3;
1428 spec->ht.ampdu_density = 4;
1429 spec->ht.mcs.tx_params =
1430 IEEE80211_HT_MCS_TX_DEFINED |
1431 IEEE80211_HT_MCS_TX_RX_DIFF |
1432 ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
1433 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
1434
1435 switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
1436 case 3:
1437 spec->ht.mcs.rx_mask[2] = 0xff;
1438 case 2:
1439 spec->ht.mcs.rx_mask[1] = 0xff;
1440 case 1:
1441 spec->ht.mcs.rx_mask[0] = 0xff;
1442 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
1443 break;
1444 }
1445
1446 /*
1447 * Create channel information array
1448 */
1449 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1450 if (!info)
1451 return -ENOMEM;
1452
1453 spec->channels_info = info;
1454
1455 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
1456 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
1457
1458 for (i = 0; i < 14; i++) {
1459 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
1460 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
1461 }
1462
1463 if (spec->num_channels > 14) {
1464 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
1465 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
1466
1467 for (i = 14; i < spec->num_channels; i++) {
1468 info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
1469 info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
1470 }
1471 }
1472
1473 return 0;
1474}
1475
b0a1edab
BZ		 1476static const struct rt2800_ops rt2800pci_rt2800_ops = {
1477 .register_read = rt2x00pci_register_read,
1478 .register_write = rt2x00pci_register_write,
1479 .register_write_lock = rt2x00pci_register_write, /* same for PCI */
1480
1481 .register_multiread = rt2x00pci_register_multiread,
1482 .register_multiwrite = rt2x00pci_register_multiwrite,
1483
1484 .regbusy_read = rt2x00pci_regbusy_read,
1485};
1486
a9b3a9f7
ID		 1487static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1488{
1489 int retval;
1490
b0a1edab
BZ		 1491 rt2x00dev->priv = (void *)&rt2800pci_rt2800_ops;
1492
a9b3a9f7
ID		 1493 /*
1494 * Allocate eeprom data.
1495 */
1496 retval = rt2800pci_validate_eeprom(rt2x00dev);
1497 if (retval)
1498 return retval;
1499
1500 retval = rt2800pci_init_eeprom(rt2x00dev);
1501 if (retval)
1502 return retval;
1503
1504 /*
1505 * Initialize hw specifications.
1506 */
1507 retval = rt2800pci_probe_hw_mode(rt2x00dev);
1508 if (retval)
1509 return retval;
1510
1511 /*
1512 * This device has multiple filters for control frames
1513 * and has a separate filter for PS Poll frames.
1514 */
1515 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
1516 __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
1517
1518 /*
1519 * This device requires firmware.
1520 */
1521 if (!rt2x00_rt(&rt2x00dev->chip, RT2880) &&
1522 !rt2x00_rt(&rt2x00dev->chip, RT3052))
1523 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
1524 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1525 __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
1526 if (!modparam_nohwcrypt)
1527 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
1528
1529 /*
1530 * Set the rssi offset.
1531 */
1532 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1533
1534 return 0;
1535}
1536
a9b3a9f7
ID		 1537static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1538 .irq_handler = rt2800pci_interrupt,
1539 .probe_hw = rt2800pci_probe_hw,
1540 .get_firmware_name = rt2800pci_get_firmware_name,
1541 .check_firmware = rt2800pci_check_firmware,
1542 .load_firmware = rt2800pci_load_firmware,
1543 .initialize = rt2x00pci_initialize,
1544 .uninitialize = rt2x00pci_uninitialize,
1545 .get_entry_state = rt2800pci_get_entry_state,
1546 .clear_entry = rt2800pci_clear_entry,
1547 .set_device_state = rt2800pci_set_device_state,
f4450616
BZ		 1548 .rfkill_poll = rt2800_rfkill_poll,
1549 .link_stats = rt2800_link_stats,
1550 .reset_tuner = rt2800_reset_tuner,
1551 .link_tuner = rt2800_link_tuner,
a9b3a9f7
ID		 1552 .write_tx_desc = rt2800pci_write_tx_desc,
1553 .write_tx_data = rt2x00pci_write_tx_data,
1554 .write_beacon = rt2800pci_write_beacon,
1555 .kick_tx_queue = rt2800pci_kick_tx_queue,
1556 .kill_tx_queue = rt2800pci_kill_tx_queue,
1557 .fill_rxdone = rt2800pci_fill_rxdone,
f4450616
BZ		 1558 .config_shared_key = rt2800_config_shared_key,
1559 .config_pairwise_key = rt2800_config_pairwise_key,
1560 .config_filter = rt2800_config_filter,
1561 .config_intf = rt2800_config_intf,
1562 .config_erp = rt2800_config_erp,
1563 .config_ant = rt2800_config_ant,
1564 .config = rt2800_config,
a9b3a9f7
ID		 1565};
1566
1567static const struct data_queue_desc rt2800pci_queue_rx = {
1568 .entry_num = RX_ENTRIES,
1569 .data_size = AGGREGATION_SIZE,
1570 .desc_size = RXD_DESC_SIZE,
1571 .priv_size = sizeof(struct queue_entry_priv_pci),
1572};
1573
1574static const struct data_queue_desc rt2800pci_queue_tx = {
1575 .entry_num = TX_ENTRIES,
1576 .data_size = AGGREGATION_SIZE,
1577 .desc_size = TXD_DESC_SIZE,
1578 .priv_size = sizeof(struct queue_entry_priv_pci),
1579};
1580
1581static const struct data_queue_desc rt2800pci_queue_bcn = {
1582 .entry_num = 8 * BEACON_ENTRIES,
1583 .data_size = 0, /* No DMA required for beacons */
1584 .desc_size = TXWI_DESC_SIZE,
1585 .priv_size = sizeof(struct queue_entry_priv_pci),
1586};
1587
1588static const struct rt2x00_ops rt2800pci_ops = {
1589 .name = KBUILD_MODNAME,
1590 .max_sta_intf = 1,
1591 .max_ap_intf = 8,
1592 .eeprom_size = EEPROM_SIZE,
1593 .rf_size = RF_SIZE,
1594 .tx_queues = NUM_TX_QUEUES,
1595 .rx = &rt2800pci_queue_rx,
1596 .tx = &rt2800pci_queue_tx,
1597 .bcn = &rt2800pci_queue_bcn,
1598 .lib = &rt2800pci_rt2x00_ops,
2ce33995 1599 .hw = &rt2800_mac80211_ops,
a9b3a9f7 1600#ifdef CONFIG_RT2X00_LIB_DEBUGFS
f4450616 1601 .debugfs = &rt2800_rt2x00debug,
a9b3a9f7
ID		 1602#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1603};
1604
1605/*
1606 * RT2800pci module information.
1607 */
1608static struct pci_device_id rt2800pci_device_table[] = {
1609 { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
1610 { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
1611 { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
1612 { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
1613 { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
1614 { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
1615 { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
1616 { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
1617 { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
1618 { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
1619 { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
1620 { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
1621 { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
1622 { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
1623 { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
1624 { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
1625 { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
1626 { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
1627 { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
1628 { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
1629 { 0, }
1630};
1631
1632MODULE_AUTHOR(DRV_PROJECT);
1633MODULE_VERSION(DRV_VERSION);
1634MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1635MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1636#ifdef CONFIG_RT2800PCI_PCI
1637MODULE_FIRMWARE(FIRMWARE_RT2860);
1638MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1639#endif /* CONFIG_RT2800PCI_PCI */
1640MODULE_LICENSE("GPL");
1641
1642#ifdef CONFIG_RT2800PCI_WISOC
1643#if defined(CONFIG_RALINK_RT288X)
1644__rt2x00soc_probe(RT2880, &rt2800pci_ops);
1645#elif defined(CONFIG_RALINK_RT305X)
1646__rt2x00soc_probe(RT3052, &rt2800pci_ops);
1647#endif
1648
1649static struct platform_driver rt2800soc_driver = {
1650 .driver = {
1651 .name = "rt2800_wmac",
1652 .owner = THIS_MODULE,
1653 .mod_name = KBUILD_MODNAME,
1654 },
1655 .probe = __rt2x00soc_probe,
1656 .remove = __devexit_p(rt2x00soc_remove),
1657 .suspend = rt2x00soc_suspend,
1658 .resume = rt2x00soc_resume,
1659};
1660#endif /* CONFIG_RT2800PCI_WISOC */
1661
1662#ifdef CONFIG_RT2800PCI_PCI
1663static struct pci_driver rt2800pci_driver = {
1664 .name = KBUILD_MODNAME,
1665 .id_table = rt2800pci_device_table,
1666 .probe = rt2x00pci_probe,
1667 .remove = __devexit_p(rt2x00pci_remove),
1668 .suspend = rt2x00pci_suspend,
1669 .resume = rt2x00pci_resume,
1670};
1671#endif /* CONFIG_RT2800PCI_PCI */
1672
1673static int __init rt2800pci_init(void)
1674{
1675 int ret = 0;
1676
1677#ifdef CONFIG_RT2800PCI_WISOC
1678 ret = platform_driver_register(&rt2800soc_driver);
1679 if (ret)
1680 return ret;
1681#endif
1682#ifdef CONFIG_RT2800PCI_PCI
1683 ret = pci_register_driver(&rt2800pci_driver);
1684 if (ret) {
1685#ifdef CONFIG_RT2800PCI_WISOC
1686 platform_driver_unregister(&rt2800soc_driver);
1687#endif
1688 return ret;
1689 }
1690#endif
1691
1692 return ret;
1693}
1694
1695static void __exit rt2800pci_exit(void)
1696{
1697#ifdef CONFIG_RT2800PCI_PCI
1698 pci_unregister_driver(&rt2800pci_driver);
1699#endif
1700#ifdef CONFIG_RT2800PCI_WISOC
1701 platform_driver_unregister(&rt2800soc_driver);
1702#endif
1703}
1704
1705module_init(rt2800pci_init);
1706module_exit(rt2800pci_exit);
Linux kernel - Deliverables
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