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rt2x00: rt2x00pci_regbusy_read() - only print register access failure once
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2800pci.c
CommitLineData
a9b3a9f7 1/*
96481b20 2 Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14
GW		 3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
a9b3a9f7
ID		 10 <http://rt2x00.serialmonkey.com>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 */
27
28/*
29 Module: rt2800pci
30 Abstract: rt2800pci device specific routines.
31 Supported chipsets: RT2800E & RT2800ED.
32 */
33
a9b3a9f7
ID		 34#include <linux/delay.h>
35#include <linux/etherdevice.h>
36#include <linux/init.h>
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/pci.h>
40#include <linux/platform_device.h>
41#include <linux/eeprom_93cx6.h>
42
43#include "rt2x00.h"
44#include "rt2x00pci.h"
45#include "rt2x00soc.h"
7ef5cc92 46#include "rt2800lib.h"
b54f78a8 47#include "rt2800.h"
a9b3a9f7
ID		 48#include "rt2800pci.h"
49
a9b3a9f7
ID		 50/*
51 * Allow hardware encryption to be disabled.
52 */
eb939922 53static bool modparam_nohwcrypt = false;
a9b3a9f7
ID		 54module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
55MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
56
ad417a53
GW		 57static bool rt2800pci_hwcrypt_disabled(struct rt2x00_dev *rt2x00dev)
58{
59 return modparam_nohwcrypt;
60}
61
a9b3a9f7
ID		 62static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
63{
64 unsigned int i;
65 u32 reg;
66
f18d4463
LC		 67 /*
68 * SOC devices don't support MCU requests.
69 */
70 if (rt2x00_is_soc(rt2x00dev))
71 return;
72
a9b3a9f7 73 for (i = 0; i < 200; i++) {
9a819996 74 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
a9b3a9f7
ID		 75
76 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
77 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
78 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
79 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
80 break;
81
82 udelay(REGISTER_BUSY_DELAY);
83 }
84
85 if (i == 200)
86 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
87
9a819996
HS		 88 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
89 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
a9b3a9f7
ID		 90}
91
5818a46a 92#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
a02308e9 93static int rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 94{
ef8397cf 95 void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
a9b3a9f7 96
a02308e9
GJ		 97 if (!base_addr)
98 return -ENOMEM;
99
a9b3a9f7 100 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
ef8397cf
GW		 101
102 iounmap(base_addr);
a02308e9 103 return 0;
a9b3a9f7
ID		 104}
105#else
a02308e9 106static inline int rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 107{
a02308e9 108 return -ENOMEM;
a9b3a9f7 109}
5818a46a 110#endif /* CONFIG_SOC_RT288X || CONFIG_SOC_RT305X */
a9b3a9f7 111
72c7296e 112#ifdef CONFIG_PCI
a9b3a9f7
ID		 113static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
114{
115 struct rt2x00_dev *rt2x00dev = eeprom->data;
116 u32 reg;
117
9a819996 118 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 119
120 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
121 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
122 eeprom->reg_data_clock =
123 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
124 eeprom->reg_chip_select =
125 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
126}
127
128static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
129{
130 struct rt2x00_dev *rt2x00dev = eeprom->data;
131 u32 reg = 0;
132
133 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
134 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
135 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
136 !!eeprom->reg_data_clock);
137 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
138 !!eeprom->reg_chip_select);
139
9a819996 140 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
a9b3a9f7
ID		 141}
142
a02308e9 143static int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
a9b3a9f7
ID		 144{
145 struct eeprom_93cx6 eeprom;
146 u32 reg;
147
9a819996 148 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 149
150 eeprom.data = rt2x00dev;
151 eeprom.register_read = rt2800pci_eepromregister_read;
152 eeprom.register_write = rt2800pci_eepromregister_write;
20f8b139
GW		 153 switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
154 {
155 case 0:
156 eeprom.width = PCI_EEPROM_WIDTH_93C46;
157 break;
158 case 1:
159 eeprom.width = PCI_EEPROM_WIDTH_93C66;
160 break;
161 default:
162 eeprom.width = PCI_EEPROM_WIDTH_93C86;
163 break;
164 }
a9b3a9f7
ID		 165 eeprom.reg_data_in = 0;
166 eeprom.reg_data_out = 0;
167 eeprom.reg_data_clock = 0;
168 eeprom.reg_chip_select = 0;
169
170 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
171 EEPROM_SIZE / sizeof(u16));
a02308e9
GJ		 172
173 return 0;
a9b3a9f7
ID		 174}
175
a6598682
GW		 176static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
177{
30e84034 178 return rt2800_efuse_detect(rt2x00dev);
a9b3a9f7
ID		 179}
180
a02308e9 181static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 182{
a02308e9 183 return rt2800_read_eeprom_efuse(rt2x00dev);
a9b3a9f7
ID		 184}
185#else
a02308e9 186static inline int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 187{
a02308e9 188 return -EOPNOTSUPP;
a9b3a9f7
ID		 189}
190
a6598682
GW		 191static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
192{
193 return 0;
194}
195
a02308e9 196static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 197{
a02308e9 198 return -EOPNOTSUPP;
a9b3a9f7 199}
72c7296e 200#endif /* CONFIG_PCI */
a9b3a9f7 201
5450b7e2
ID		 202/*
203 * Queue handlers.
204 */
205static void rt2800pci_start_queue(struct data_queue *queue)
206{
207 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
208 u32 reg;
209
210 switch (queue->qid) {
211 case QID_RX:
9a819996 212 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5450b7e2 213 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
9a819996 214 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5450b7e2
ID		 215 break;
216 case QID_BEACON:
9a819996 217 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
5450b7e2
ID		 218 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
219 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
220 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
9a819996 221 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
69cf36a4 222
9a819996 223 rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, &reg);
69cf36a4 224 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 1);
9a819996 225 rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
5450b7e2
ID		 226 break;
227 default:
228 break;
6403eab1 229 }
5450b7e2
ID		 230}
231
232static void rt2800pci_kick_queue(struct data_queue *queue)
233{
234 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
235 struct queue_entry *entry;
236
237 switch (queue->qid) {
f615e9a3
ID		 238 case QID_AC_VO:
239 case QID_AC_VI:
5450b7e2
ID		 240 case QID_AC_BE:
241 case QID_AC_BK:
5450b7e2 242 entry = rt2x00queue_get_entry(queue, Q_INDEX);
9a819996
HS		 243 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(queue->qid),
244 entry->entry_idx);
5450b7e2
ID		 245 break;
246 case QID_MGMT:
247 entry = rt2x00queue_get_entry(queue, Q_INDEX);
9a819996
HS		 248 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(5),
249 entry->entry_idx);
5450b7e2
ID		 250 break;
251 default:
252 break;
253 }
254}
255
256static void rt2800pci_stop_queue(struct data_queue *queue)
257{
258 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
259 u32 reg;
260
261 switch (queue->qid) {
262 case QID_RX:
9a819996 263 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5450b7e2 264 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
9a819996 265 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5450b7e2
ID		 266 break;
267 case QID_BEACON:
9a819996 268 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
5450b7e2
ID		 269 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
270 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
271 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
9a819996 272 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
69cf36a4 273
9a819996 274 rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, &reg);
69cf36a4 275 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 0);
9a819996 276 rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
a9d61e9e
HS		 277
278 /*
abc11994
HS		 279 * Wait for current invocation to finish. The tasklet
280 * won't be scheduled anymore afterwards since we disabled
281 * the TBTT and PRE TBTT timer.
a9d61e9e 282 */
abc11994
HS		 283 tasklet_kill(&rt2x00dev->tbtt_tasklet);
284 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
285
5450b7e2
ID		 286 break;
287 default:
288 break;
289 }
290}
291
a9b3a9f7
ID		 292/*
293 * Firmware functions
294 */
295static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
296{
a89534ed
WH		 297 /*
298 * Chip rt3290 use specific 4KB firmware named rt3290.bin.
299 */
300 if (rt2x00_rt(rt2x00dev, RT3290))
301 return FIRMWARE_RT3290;
302 else
303 return FIRMWARE_RT2860;
a9b3a9f7
ID		 304}
305
f31c9a8c 306static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
a9b3a9f7
ID		 307 const u8 *data, const size_t len)
308{
a9b3a9f7
ID		 309 u32 reg;
310
a9b3a9f7
ID		 311 /*
312 * enable Host program ram write selection
313 */
314 reg = 0;
315 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
9a819996 316 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
a9b3a9f7
ID		 317
318 /*
319 * Write firmware to device.
320 */
d4c838ef
ID		 321 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
322 data, len);
a9b3a9f7 323
9a819996
HS		 324 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
325 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
a9b3a9f7 326
9a819996
HS		 327 rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
328 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
a9b3a9f7
ID		 329
330 return 0;
331}
332
333/*
334 * Initialization functions.
335 */
336static bool rt2800pci_get_entry_state(struct queue_entry *entry)
337{
338 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
339 u32 word;
340
341 if (entry->queue->qid == QID_RX) {
342 rt2x00_desc_read(entry_priv->desc, 1, &word);
343
344 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
345 } else {
346 rt2x00_desc_read(entry_priv->desc, 1, &word);
347
348 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
349 }
350}
351
352static void rt2800pci_clear_entry(struct queue_entry *entry)
353{
354 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
355 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95192339 356 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
a9b3a9f7
ID		 357 u32 word;
358
359 if (entry->queue->qid == QID_RX) {
360 rt2x00_desc_read(entry_priv->desc, 0, &word);
361 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
362 rt2x00_desc_write(entry_priv->desc, 0, word);
363
364 rt2x00_desc_read(entry_priv->desc, 1, &word);
365 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
366 rt2x00_desc_write(entry_priv->desc, 1, word);
95192339
HS		 367
368 /*
369 * Set RX IDX in register to inform hardware that we have
370 * handled this entry and it is available for reuse again.
371 */
9a819996 372 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
95192339 373 entry->entry_idx);
a9b3a9f7
ID		 374 } else {
375 rt2x00_desc_read(entry_priv->desc, 1, &word);
376 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
377 rt2x00_desc_write(entry_priv->desc, 1, word);
378 }
379}
380
381static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
382{
383 struct queue_entry_priv_pci *entry_priv;
a9b3a9f7 384
a9b3a9f7
ID		 385 /*
386 * Initialize registers.
387 */
388 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
9a819996
HS		 389 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
390 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0,
391 rt2x00dev->tx[0].limit);
392 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
393 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX0, 0);
a9b3a9f7
ID		 394
395 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
9a819996
HS		 396 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
397 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1,
398 rt2x00dev->tx[1].limit);
399 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
400 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX1, 0);
a9b3a9f7
ID		 401
402 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
9a819996
HS		 403 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
404 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2,
405 rt2x00dev->tx[2].limit);
406 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
407 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX2, 0);
a9b3a9f7
ID		 408
409 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
9a819996
HS		 410 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
411 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3,
412 rt2x00dev->tx[3].limit);
413 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
414 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX3, 0);
a9b3a9f7 415
3a4b43fd
JK		 416 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR4, 0);
417 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT4, 0);
418 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX4, 0);
419 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX4, 0);
420
421 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR5, 0);
422 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT5, 0);
423 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX5, 0);
424 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX5, 0);
425
a9b3a9f7 426 entry_priv = rt2x00dev->rx->entries[0].priv_data;
9a819996
HS		 427 rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
428 rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT,
429 rt2x00dev->rx[0].limit);
430 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
431 rt2x00dev->rx[0].limit - 1);
432 rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0);
a9b3a9f7 433
f7b395e9 434 rt2800_disable_wpdma(rt2x00dev);
a9b3a9f7 435
9a819996 436 rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
a9b3a9f7
ID		 437
438 return 0;
439}
440
a9b3a9f7
ID		 441/*
442 * Device state switch handlers.
443 */
a9b3a9f7
ID		 444static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
445 enum dev_state state)
446{
a9b3a9f7 447 u32 reg;
a9d61e9e 448 unsigned long flags;
a9b3a9f7
ID		 449
450 /*
451 * When interrupts are being enabled, the interrupt registers
452 * should clear the register to assure a clean state.
453 */
454 if (state == STATE_RADIO_IRQ_ON) {
9a819996
HS		 455 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
456 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
a9d61e9e 457 }
a9b3a9f7 458
a9d61e9e 459 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
dfd00c4c
SG		 460 reg = 0;
461 if (state == STATE_RADIO_IRQ_ON) {
462 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, 1);
463 rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, 1);
464 rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, 1);
465 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, 1);
466 rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, 1);
467 }
9a819996 468 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
a9d61e9e
HS		 469 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
470
471 if (state == STATE_RADIO_IRQ_OFF) {
472 /*
abc11994 473 * Wait for possibly running tasklets to finish.
a9d61e9e 474 */
abc11994
HS		 475 tasklet_kill(&rt2x00dev->txstatus_tasklet);
476 tasklet_kill(&rt2x00dev->rxdone_tasklet);
477 tasklet_kill(&rt2x00dev->autowake_tasklet);
478 tasklet_kill(&rt2x00dev->tbtt_tasklet);
479 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
a9d61e9e 480 }
a9b3a9f7
ID		 481}
482
e3a896b9
GW		 483static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
484{
485 u32 reg;
486
487 /*
488 * Reset DMA indexes
489 */
9a819996 490 rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
e3a896b9
GW		 491 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
492 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
493 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
494 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
495 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
496 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
497 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
9a819996 498 rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
e3a896b9 499
9a819996
HS		 500 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
501 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
e3a896b9 502
872834df
GW		 503 if (rt2x00_is_pcie(rt2x00dev) &&
504 (rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884
JL		 505 rt2x00_rt(rt2x00dev, RT5390) ||
506 rt2x00_rt(rt2x00dev, RT5392))) {
9a819996 507 rt2x00pci_register_read(rt2x00dev, AUX_CTRL, &reg);
adde5882
GJ		 508 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
509 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
9a819996 510 rt2x00pci_register_write(rt2x00dev, AUX_CTRL, reg);
adde5882 511 }
60687ba7 512
9a819996 513 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
e3a896b9 514
2a48e8ae 515 reg = 0;
e3a896b9
GW		 516 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
517 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
9a819996 518 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
e3a896b9 519
9a819996 520 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
e3a896b9
GW		 521
522 return 0;
523}
524
a9b3a9f7
ID		 525static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
526{
e8b461c3
JK		 527 int retval;
528
52b8243b
JK		 529 /* Wait for DMA, ignore error until we initialize queues. */
530 rt2800_wait_wpdma_ready(rt2x00dev);
531
532 if (unlikely(rt2800pci_init_queues(rt2x00dev)))
a9b3a9f7
ID		 533 return -EIO;
534
e8b461c3
JK		 535 retval = rt2800_enable_radio(rt2x00dev);
536 if (retval)
537 return retval;
538
539 /* After resume MCU_BOOT_SIGNAL will trash these. */
540 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
541 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
542
543 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_RADIO_OFF, 0xff, 0x02);
544 rt2800pci_mcu_status(rt2x00dev, TOKEN_RADIO_OFF);
545
546 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP, 0, 0);
547 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
548
549 return retval;
a9b3a9f7
ID		 550}
551
552static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
553{
7f6e144f
RJH		 554 if (rt2x00_is_soc(rt2x00dev)) {
555 rt2800_disable_radio(rt2x00dev);
9a819996
HS		 556 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
557 rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
7f6e144f 558 }
a9b3a9f7
ID		 559}
560
561static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
562 enum dev_state state)
563{
a9b3a9f7 564 if (state == STATE_AWAKE) {
09a3311c
JK		 565 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP,
566 0, 0x02);
567 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
7f6e144f 568 } else if (state == STATE_SLEEP) {
9a819996
HS		 569 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
570 0xffffffff);
571 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID,
572 0xffffffff);
09a3311c
JK		 573 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_SLEEP,
574 0xff, 0x01);
a9b3a9f7
ID		 575 }
576
577 return 0;
578}
579
580static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
581 enum dev_state state)
582{
583 int retval = 0;
584
585 switch (state) {
586 case STATE_RADIO_ON:
a9b3a9f7
ID		 587 retval = rt2800pci_enable_radio(rt2x00dev);
588 break;
589 case STATE_RADIO_OFF:
590 /*
591 * After the radio has been disabled, the device should
592 * be put to sleep for powersaving.
593 */
594 rt2800pci_disable_radio(rt2x00dev);
595 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
596 break;
a9b3a9f7
ID		 597 case STATE_RADIO_IRQ_ON:
598 case STATE_RADIO_IRQ_OFF:
599 rt2800pci_toggle_irq(rt2x00dev, state);
600 break;
601 case STATE_DEEP_SLEEP:
602 case STATE_SLEEP:
603 case STATE_STANDBY:
604 case STATE_AWAKE:
605 retval = rt2800pci_set_state(rt2x00dev, state);
606 break;
607 default:
608 retval = -ENOTSUPP;
609 break;
610 }
611
612 if (unlikely(retval))
613 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
614 state, retval);
615
616 return retval;
617}
618
619/*
620 * TX descriptor initialization
621 */
0c5879bc 622static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)
a9b3a9f7 623{
0c5879bc 624 return (__le32 *) entry->skb->data;
745b1ae3
HS		 625}
626
93331458 627static void rt2800pci_write_tx_desc(struct queue_entry *entry,
745b1ae3
HS		 628 struct txentry_desc *txdesc)
629{
93331458
ID		 630 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
631 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
85b7a8b3 632 __le32 *txd = entry_priv->desc;
745b1ae3
HS		 633 u32 word;
634
a9b3a9f7
ID		 635 /*
636 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
637 * must contains a TXWI structure + 802.11 header + padding + 802.11
638 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
639 * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
640 * data. It means that LAST_SEC0 is always 0.
641 */
642
643 /*
644 * Initialize TX descriptor
645 */
3de3d966 646 word = 0;
a9b3a9f7
ID		 647 rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
648 rt2x00_desc_write(txd, 0, word);
649
3de3d966 650 word = 0;
93331458 651 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);
a9b3a9f7
ID		 652 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
653 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
654 rt2x00_set_field32(&word, TXD_W1_BURST,
655 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
85b7a8b3 656 rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
a9b3a9f7
ID		 657 rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
658 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
659 rt2x00_desc_write(txd, 1, word);
660
3de3d966 661 word = 0;
a9b3a9f7 662 rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
85b7a8b3 663 skbdesc->skb_dma + TXWI_DESC_SIZE);
a9b3a9f7
ID		 664 rt2x00_desc_write(txd, 2, word);
665
3de3d966 666 word = 0;
a9b3a9f7
ID		 667 rt2x00_set_field32(&word, TXD_W3_WIV,
668 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
669 rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
670 rt2x00_desc_write(txd, 3, word);
85b7a8b3
GW		 671
672 /*
673 * Register descriptor details in skb frame descriptor.
674 */
675 skbdesc->desc = txd;
676 skbdesc->desc_len = TXD_DESC_SIZE;
a9b3a9f7
ID		 677}
678
a9b3a9f7
ID		 679/*
680 * RX control handlers
681 */
682static void rt2800pci_fill_rxdone(struct queue_entry *entry,
683 struct rxdone_entry_desc *rxdesc)
684{
a9b3a9f7
ID		 685 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
686 __le32 *rxd = entry_priv->desc;
2de64dd2
GW		 687 u32 word;
688
689 rt2x00_desc_read(rxd, 3, &word);
690
691 if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
a9b3a9f7
ID		 692 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
693
78b8f3b0
GW		 694 /*
695 * Unfortunately we don't know the cipher type used during
696 * decryption. This prevents us from correct providing
697 * correct statistics through debugfs.
698 */
2de64dd2 699 rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
a9b3a9f7 700
2de64dd2 701 if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
a9b3a9f7
ID		 702 /*
703 * Hardware has stripped IV/EIV data from 802.11 frame during
704 * decryption. Unfortunately the descriptor doesn't contain
705 * any fields with the EIV/IV data either, so they can't
706 * be restored by rt2x00lib.
707 */
708 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
709
a45f369d
GW		 710 /*
711 * The hardware has already checked the Michael Mic and has
712 * stripped it from the frame. Signal this to mac80211.
713 */
714 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
715
a9b3a9f7
ID		 716 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
717 rxdesc->flags |= RX_FLAG_DECRYPTED;
718 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
719 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
720 }
721
2de64dd2 722 if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
a9b3a9f7
ID		 723 rxdesc->dev_flags |= RXDONE_MY_BSS;
724
2de64dd2 725 if (rt2x00_get_field32(word, RXD_W3_L2PAD))
a9b3a9f7 726 rxdesc->dev_flags |= RXDONE_L2PAD;
a9b3a9f7 727
a9b3a9f7 728 /*
2de64dd2 729 * Process the RXWI structure that is at the start of the buffer.
a9b3a9f7 730 */
74861922 731 rt2800_process_rxwi(entry, rxdesc);
a9b3a9f7
ID		 732}
733
734/*
735 * Interrupt functions.
736 */
4d66edc8
GW		 737static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
738{
739 struct ieee80211_conf conf = { .flags = 0 };
740 struct rt2x00lib_conf libconf = { .conf = &conf };
741
742 rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
743}
744
2e7798b7 745static bool rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
96c3da7d
HS		 746{
747 struct data_queue *queue;
748 struct queue_entry *entry;
749 u32 status;
750 u8 qid;
2e7798b7 751 int max_tx_done = 16;
96c3da7d 752
c4d63244 753 while (kfifo_get(&rt2x00dev->txstatus_fifo, &status)) {
12eec2cc 754 qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
87443e87 755 if (unlikely(qid >= QID_RX)) {
96c3da7d
HS		 756 /*
757 * Unknown queue, this shouldn't happen. Just drop
758 * this tx status.
759 */
760 WARNING(rt2x00dev, "Got TX status report with "
094a1d92 761 "unexpected pid %u, dropping\n", qid);
96c3da7d
HS		 762 break;
763 }
764
11f818e0 765 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
96c3da7d
HS		 766 if (unlikely(queue == NULL)) {
767 /*
768 * The queue is NULL, this shouldn't happen. Stop
769 * processing here and drop the tx status
770 */
771 WARNING(rt2x00dev, "Got TX status for an unavailable "
094a1d92 772 "queue %u, dropping\n", qid);
96c3da7d
HS		 773 break;
774 }
775
87443e87 776 if (unlikely(rt2x00queue_empty(queue))) {
96c3da7d
HS		 777 /*
778 * The queue is empty. Stop processing here
779 * and drop the tx status.
780 */
781 WARNING(rt2x00dev, "Got TX status for an empty "
094a1d92 782 "queue %u, dropping\n", qid);
96c3da7d
HS		 783 break;
784 }
785
786 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
31937c42 787 rt2800_txdone_entry(entry, status, rt2800pci_get_txwi(entry));
2e7798b7
HS		 788
789 if (--max_tx_done == 0)
790 break;
96c3da7d 791 }
2e7798b7
HS		 792
793 return !max_tx_done;
96c3da7d
HS		 794}
795
7a5a681a
HS		 796static inline void rt2800pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
797 struct rt2x00_field32 irq_field)
a9b3a9f7 798{
a9d61e9e 799 u32 reg;
a9b3a9f7
ID		 800
801 /*
a9d61e9e
HS		 802 * Enable a single interrupt. The interrupt mask register
803 * access needs locking.
9f926fb5 804 */
0aa13b2e 805 spin_lock_irq(&rt2x00dev->irqmask_lock);
9a819996 806 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
a9d61e9e 807 rt2x00_set_field32(&reg, irq_field, 1);
9a819996 808 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
0aa13b2e 809 spin_unlock_irq(&rt2x00dev->irqmask_lock);
a9d61e9e 810}
9f926fb5 811
a9d61e9e
HS		 812static void rt2800pci_txstatus_tasklet(unsigned long data)
813{
2e7798b7
HS		 814 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
815 if (rt2800pci_txdone(rt2x00dev))
816 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
9f926fb5
HS		 817
818 /*
a9d61e9e
HS		 819 * No need to enable the tx status interrupt here as we always
820 * leave it enabled to minimize the possibility of a tx status
821 * register overflow. See comment in interrupt handler.
a9b3a9f7 822 */
a9d61e9e 823}
a9b3a9f7 824
a9d61e9e
HS		 825static void rt2800pci_pretbtt_tasklet(unsigned long data)
826{
827 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
828 rt2x00lib_pretbtt(rt2x00dev);
abc11994
HS		 829 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
830 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_PRE_TBTT);
a9d61e9e 831}
4d66edc8 832
a9d61e9e
HS		 833static void rt2800pci_tbtt_tasklet(unsigned long data)
834{
835 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
290d6089
HS		 836 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
837 u32 reg;
838
a9d61e9e 839 rt2x00lib_beacondone(rt2x00dev);
290d6089
HS		 840
841 if (rt2x00dev->intf_ap_count) {
842 /*
843 * The rt2800pci hardware tbtt timer is off by 1us per tbtt
844 * causing beacon skew and as a result causing problems with
845 * some powersaving clients over time. Shorten the beacon
846 * interval every 64 beacons by 64us to mitigate this effect.
847 */
848 if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 2)) {
849 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
850 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
851 (rt2x00dev->beacon_int * 16) - 1);
852 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
853 } else if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 1)) {
854 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
855 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
856 (rt2x00dev->beacon_int * 16));
857 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
858 }
859 drv_data->tbtt_tick++;
860 drv_data->tbtt_tick %= BCN_TBTT_OFFSET;
861 }
862
abc11994
HS		 863 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
864 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TBTT);
a9d61e9e 865}
78e256c9 866
a9d61e9e
HS		 867static void rt2800pci_rxdone_tasklet(unsigned long data)
868{
869 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
16638937
HS		 870 if (rt2x00pci_rxdone(rt2x00dev))
871 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
abc11994 872 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
16638937 873 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RX_DONE);
a9d61e9e
HS		 874}
875
876static void rt2800pci_autowake_tasklet(unsigned long data)
877{
878 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
879 rt2800pci_wakeup(rt2x00dev);
abc11994
HS		 880 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
881 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_AUTO_WAKEUP);
a9b3a9f7
ID		 882}
883
96c3da7d
HS		 884static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
885{
886 u32 status;
887 int i;
888
889 /*
890 * The TX_FIFO_STATUS interrupt needs special care. We should
891 * read TX_STA_FIFO but we should do it immediately as otherwise
892 * the register can overflow and we would lose status reports.
893 *
894 * Hence, read the TX_STA_FIFO register and copy all tx status
895 * reports into a kernel FIFO which is handled in the txstatus
896 * tasklet. We use a tasklet to process the tx status reports
897 * because we can schedule the tasklet multiple times (when the
898 * interrupt fires again during tx status processing).
899 *
900 * Furthermore we don't disable the TX_FIFO_STATUS
901 * interrupt here but leave it enabled so that the TX_STA_FIFO
3736fe58 902 * can also be read while the tx status tasklet gets executed.
96c3da7d
HS		 903 *
904 * Since we have only one producer and one consumer we don't
905 * need to lock the kfifo.
906 */
efd2f271 907 for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
9a819996 908 rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &status);
96c3da7d
HS		 909
910 if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
911 break;
912
c4d63244 913 if (!kfifo_put(&rt2x00dev->txstatus_fifo, &status)) {
96c3da7d
HS		 914 WARNING(rt2x00dev, "TX status FIFO overrun,"
915 "drop tx status report.\n");
916 break;
917 }
918 }
919
920 /* Schedule the tasklet for processing the tx status. */
921 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
922}
923
78e256c9
HS		 924static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
925{
926 struct rt2x00_dev *rt2x00dev = dev_instance;
a9d61e9e 927 u32 reg, mask;
78e256c9
HS		 928
929 /* Read status and ACK all interrupts */
9a819996
HS		 930 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
931 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
78e256c9
HS		 932
933 if (!reg)
934 return IRQ_NONE;
935
936 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
937 return IRQ_HANDLED;
938
a9d61e9e
HS		 939 /*
940 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
941 * for interrupts and interrupt masks we can just use the value of
942 * INT_SOURCE_CSR to create the interrupt mask.
943 */
944 mask = ~reg;
78e256c9 945
a9d61e9e
HS		 946 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) {
947 rt2800pci_txstatus_interrupt(rt2x00dev);
96c3da7d 948 /*
a9d61e9e 949 * Never disable the TX_FIFO_STATUS interrupt.
96c3da7d 950 */
a9d61e9e
HS		 951 rt2x00_set_field32(&mask, INT_MASK_CSR_TX_FIFO_STATUS, 1);
952 }
96c3da7d 953
a9d61e9e
HS		 954 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
955 tasklet_hi_schedule(&rt2x00dev->pretbtt_tasklet);
78e256c9 956
a9d61e9e
HS		 957 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
958 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
96c3da7d 959
a9d61e9e
HS		 960 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
961 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
78e256c9 962
a9d61e9e
HS		 963 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
964 tasklet_schedule(&rt2x00dev->autowake_tasklet);
965
966 /*
967 * Disable all interrupts for which a tasklet was scheduled right now,
968 * the tasklet will reenable the appropriate interrupts.
969 */
0aa13b2e 970 spin_lock(&rt2x00dev->irqmask_lock);
9a819996 971 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
a9d61e9e 972 reg &= mask;
9a819996 973 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
0aa13b2e 974 spin_unlock(&rt2x00dev->irqmask_lock);
a9d61e9e
HS		 975
976 return IRQ_HANDLED;
78e256c9
HS		 977}
978
a9b3a9f7
ID		 979/*
980 * Device probe functions.
981 */
a02308e9 982static int rt2800pci_read_eeprom(struct rt2x00_dev *rt2x00dev)
7ab71325 983{
a02308e9
GJ		 984 int retval;
985
cea90e55 986 if (rt2x00_is_soc(rt2x00dev))
a02308e9 987 retval = rt2800pci_read_eeprom_soc(rt2x00dev);
cea90e55 988 else if (rt2800pci_efuse_detect(rt2x00dev))
a02308e9 989 retval = rt2800pci_read_eeprom_efuse(rt2x00dev);
cea90e55 990 else
a02308e9
GJ		 991 retval = rt2800pci_read_eeprom_pci(rt2x00dev);
992
993 return retval;
a9b3a9f7
ID		 994}
995
e783619e
HS		 996static const struct ieee80211_ops rt2800pci_mac80211_ops = {
997 .tx = rt2x00mac_tx,
998 .start = rt2x00mac_start,
999 .stop = rt2x00mac_stop,
1000 .add_interface = rt2x00mac_add_interface,
1001 .remove_interface = rt2x00mac_remove_interface,
1002 .config = rt2x00mac_config,
1003 .configure_filter = rt2x00mac_configure_filter,
e783619e
HS		 1004 .set_key = rt2x00mac_set_key,
1005 .sw_scan_start = rt2x00mac_sw_scan_start,
1006 .sw_scan_complete = rt2x00mac_sw_scan_complete,
1007 .get_stats = rt2x00mac_get_stats,
1008 .get_tkip_seq = rt2800_get_tkip_seq,
1009 .set_rts_threshold = rt2800_set_rts_threshold,
a2b1328a
HS		 1010 .sta_add = rt2x00mac_sta_add,
1011 .sta_remove = rt2x00mac_sta_remove,
e783619e
HS		 1012 .bss_info_changed = rt2x00mac_bss_info_changed,
1013 .conf_tx = rt2800_conf_tx,
1014 .get_tsf = rt2800_get_tsf,
1015 .rfkill_poll = rt2x00mac_rfkill_poll,
1016 .ampdu_action = rt2800_ampdu_action,
f44df18c 1017 .flush = rt2x00mac_flush,
977206d7 1018 .get_survey = rt2800_get_survey,
e7dee444 1019 .get_ringparam = rt2x00mac_get_ringparam,
5f0dd296 1020 .tx_frames_pending = rt2x00mac_tx_frames_pending,
e783619e
HS		 1021};
1022
e796643e
ID		 1023static const struct rt2800_ops rt2800pci_rt2800_ops = {
1024 .register_read = rt2x00pci_register_read,
1025 .register_read_lock = rt2x00pci_register_read, /* same for PCI */
1026 .register_write = rt2x00pci_register_write,
1027 .register_write_lock = rt2x00pci_register_write, /* same for PCI */
1028 .register_multiread = rt2x00pci_register_multiread,
1029 .register_multiwrite = rt2x00pci_register_multiwrite,
1030 .regbusy_read = rt2x00pci_regbusy_read,
ad417a53
GW		 1031 .read_eeprom = rt2800pci_read_eeprom,
1032 .hwcrypt_disabled = rt2800pci_hwcrypt_disabled,
e796643e
ID		 1033 .drv_write_firmware = rt2800pci_write_firmware,
1034 .drv_init_registers = rt2800pci_init_registers,
0c5879bc 1035 .drv_get_txwi = rt2800pci_get_txwi,
e796643e
ID		 1036};
1037
a9b3a9f7
ID		 1038static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1039 .irq_handler = rt2800pci_interrupt,
a9d61e9e
HS		 1040 .txstatus_tasklet = rt2800pci_txstatus_tasklet,
1041 .pretbtt_tasklet = rt2800pci_pretbtt_tasklet,
1042 .tbtt_tasklet = rt2800pci_tbtt_tasklet,
1043 .rxdone_tasklet = rt2800pci_rxdone_tasklet,
1044 .autowake_tasklet = rt2800pci_autowake_tasklet,
ad417a53 1045 .probe_hw = rt2800_probe_hw,
a9b3a9f7 1046 .get_firmware_name = rt2800pci_get_firmware_name,
f31c9a8c
ID		 1047 .check_firmware = rt2800_check_firmware,
1048 .load_firmware = rt2800_load_firmware,
a9b3a9f7
ID		 1049 .initialize = rt2x00pci_initialize,
1050 .uninitialize = rt2x00pci_uninitialize,
1051 .get_entry_state = rt2800pci_get_entry_state,
1052 .clear_entry = rt2800pci_clear_entry,
1053 .set_device_state = rt2800pci_set_device_state,
f4450616
BZ		 1054 .rfkill_poll = rt2800_rfkill_poll,
1055 .link_stats = rt2800_link_stats,
1056 .reset_tuner = rt2800_reset_tuner,
1057 .link_tuner = rt2800_link_tuner,
9e33a355 1058 .gain_calibration = rt2800_gain_calibration,
2e9c43dd 1059 .vco_calibration = rt2800_vco_calibration,
dbba306f
ID		 1060 .start_queue = rt2800pci_start_queue,
1061 .kick_queue = rt2800pci_kick_queue,
1062 .stop_queue = rt2800pci_stop_queue,
152a5992 1063 .flush_queue = rt2x00pci_flush_queue,
a9b3a9f7 1064 .write_tx_desc = rt2800pci_write_tx_desc,
0c5879bc 1065 .write_tx_data = rt2800_write_tx_data,
f0194b2d 1066 .write_beacon = rt2800_write_beacon,
69cf36a4 1067 .clear_beacon = rt2800_clear_beacon,
a9b3a9f7 1068 .fill_rxdone = rt2800pci_fill_rxdone,
f4450616
BZ		 1069 .config_shared_key = rt2800_config_shared_key,
1070 .config_pairwise_key = rt2800_config_pairwise_key,
1071 .config_filter = rt2800_config_filter,
1072 .config_intf = rt2800_config_intf,
1073 .config_erp = rt2800_config_erp,
1074 .config_ant = rt2800_config_ant,
1075 .config = rt2800_config,
a2b1328a
HS		 1076 .sta_add = rt2800_sta_add,
1077 .sta_remove = rt2800_sta_remove,
a9b3a9f7
ID		 1078};
1079
1080static const struct data_queue_desc rt2800pci_queue_rx = {
efd2f271 1081 .entry_num = 128,
a9b3a9f7
ID		 1082 .data_size = AGGREGATION_SIZE,
1083 .desc_size = RXD_DESC_SIZE,
1084 .priv_size = sizeof(struct queue_entry_priv_pci),
1085};
1086
1087static const struct data_queue_desc rt2800pci_queue_tx = {
efd2f271 1088 .entry_num = 64,
a9b3a9f7
ID		 1089 .data_size = AGGREGATION_SIZE,
1090 .desc_size = TXD_DESC_SIZE,
1091 .priv_size = sizeof(struct queue_entry_priv_pci),
1092};
1093
1094static const struct data_queue_desc rt2800pci_queue_bcn = {
efd2f271 1095 .entry_num = 8,
a9b3a9f7
ID		 1096 .data_size = 0, /* No DMA required for beacons */
1097 .desc_size = TXWI_DESC_SIZE,
1098 .priv_size = sizeof(struct queue_entry_priv_pci),
1099};
1100
1101static const struct rt2x00_ops rt2800pci_ops = {
04d0362e 1102 .name = KBUILD_MODNAME,
3a1c0128 1103 .drv_data_size = sizeof(struct rt2800_drv_data),
04d0362e
GW		 1104 .max_ap_intf = 8,
1105 .eeprom_size = EEPROM_SIZE,
1106 .rf_size = RF_SIZE,
1107 .tx_queues = NUM_TX_QUEUES,
e6218cc4 1108 .extra_tx_headroom = TXWI_DESC_SIZE,
04d0362e
GW		 1109 .rx = &rt2800pci_queue_rx,
1110 .tx = &rt2800pci_queue_tx,
1111 .bcn = &rt2800pci_queue_bcn,
1112 .lib = &rt2800pci_rt2x00_ops,
e796643e 1113 .drv = &rt2800pci_rt2800_ops,
e783619e 1114 .hw = &rt2800pci_mac80211_ops,
a9b3a9f7 1115#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 1116 .debugfs = &rt2800_rt2x00debug,
a9b3a9f7
ID		 1117#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1118};
1119
1120/*
1121 * RT2800pci module information.
1122 */
72c7296e 1123#ifdef CONFIG_PCI
a3aa1884 1124static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
e01ae27f
GW		 1125 { PCI_DEVICE(0x1814, 0x0601) },
1126 { PCI_DEVICE(0x1814, 0x0681) },
1127 { PCI_DEVICE(0x1814, 0x0701) },
1128 { PCI_DEVICE(0x1814, 0x0781) },
1129 { PCI_DEVICE(0x1814, 0x3090) },
1130 { PCI_DEVICE(0x1814, 0x3091) },
1131 { PCI_DEVICE(0x1814, 0x3092) },
1132 { PCI_DEVICE(0x1432, 0x7708) },
1133 { PCI_DEVICE(0x1432, 0x7727) },
1134 { PCI_DEVICE(0x1432, 0x7728) },
1135 { PCI_DEVICE(0x1432, 0x7738) },
1136 { PCI_DEVICE(0x1432, 0x7748) },
1137 { PCI_DEVICE(0x1432, 0x7758) },
1138 { PCI_DEVICE(0x1432, 0x7768) },
1139 { PCI_DEVICE(0x1462, 0x891a) },
1140 { PCI_DEVICE(0x1a3b, 0x1059) },
a89534ed
WH		 1141#ifdef CONFIG_RT2800PCI_RT3290
1142 { PCI_DEVICE(0x1814, 0x3290) },
1143#endif
f93bc9b3 1144#ifdef CONFIG_RT2800PCI_RT33XX
e01ae27f 1145 { PCI_DEVICE(0x1814, 0x3390) },
f93bc9b3 1146#endif
de1ebdce 1147#ifdef CONFIG_RT2800PCI_RT35XX
e01ae27f
GW		 1148 { PCI_DEVICE(0x1432, 0x7711) },
1149 { PCI_DEVICE(0x1432, 0x7722) },
1150 { PCI_DEVICE(0x1814, 0x3060) },
1151 { PCI_DEVICE(0x1814, 0x3062) },
1152 { PCI_DEVICE(0x1814, 0x3562) },
1153 { PCI_DEVICE(0x1814, 0x3592) },
1154 { PCI_DEVICE(0x1814, 0x3593) },
c4806014 1155 { PCI_DEVICE(0x1814, 0x359f) },
60687ba7
RST		 1156#endif
1157#ifdef CONFIG_RT2800PCI_RT53XX
ccf91bd6 1158 { PCI_DEVICE(0x1814, 0x5360) },
f57d7b6c 1159 { PCI_DEVICE(0x1814, 0x5362) },
e01ae27f 1160 { PCI_DEVICE(0x1814, 0x5390) },
f57d7b6c 1161 { PCI_DEVICE(0x1814, 0x5392) },
5126d97e 1162 { PCI_DEVICE(0x1814, 0x539a) },
2aed6915 1163 { PCI_DEVICE(0x1814, 0x539b) },
71e0b38c 1164 { PCI_DEVICE(0x1814, 0x539f) },
de1ebdce 1165#endif
a9b3a9f7
ID		 1166 { 0, }
1167};
72c7296e 1168#endif /* CONFIG_PCI */
a9b3a9f7
ID		 1169
1170MODULE_AUTHOR(DRV_PROJECT);
1171MODULE_VERSION(DRV_VERSION);
1172MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1173MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
72c7296e 1174#ifdef CONFIG_PCI
a9b3a9f7
ID		 1175MODULE_FIRMWARE(FIRMWARE_RT2860);
1176MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
72c7296e 1177#endif /* CONFIG_PCI */
a9b3a9f7
ID		 1178MODULE_LICENSE("GPL");
1179
5818a46a 1180#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
714fa663
GW		 1181static int rt2800soc_probe(struct platform_device *pdev)
1182{
6e93d719 1183 return rt2x00soc_probe(pdev, &rt2800pci_ops);
714fa663 1184}
a9b3a9f7
ID		 1185
1186static struct platform_driver rt2800soc_driver = {
1187 .driver = {
1188 .name = "rt2800_wmac",
1189 .owner = THIS_MODULE,
1190 .mod_name = KBUILD_MODNAME,
1191 },
714fa663 1192 .probe = rt2800soc_probe,
69202359 1193 .remove = rt2x00soc_remove,
a9b3a9f7
ID		 1194 .suspend = rt2x00soc_suspend,
1195 .resume = rt2x00soc_resume,
1196};
5818a46a 1197#endif /* CONFIG_SOC_RT288X || CONFIG_SOC_RT305X */
a9b3a9f7 1198
72c7296e 1199#ifdef CONFIG_PCI
e01ae27f
GW		 1200static int rt2800pci_probe(struct pci_dev *pci_dev,
1201 const struct pci_device_id *id)
1202{
1203 return rt2x00pci_probe(pci_dev, &rt2800pci_ops);
1204}
1205
a9b3a9f7
ID		 1206static struct pci_driver rt2800pci_driver = {
1207 .name = KBUILD_MODNAME,
1208 .id_table = rt2800pci_device_table,
e01ae27f 1209 .probe = rt2800pci_probe,
69202359 1210 .remove = rt2x00pci_remove,
a9b3a9f7
ID		 1211 .suspend = rt2x00pci_suspend,
1212 .resume = rt2x00pci_resume,
1213};
72c7296e 1214#endif /* CONFIG_PCI */
a9b3a9f7
ID		 1215
1216static int __init rt2800pci_init(void)
1217{
1218 int ret = 0;
1219
5818a46a 1220#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
a9b3a9f7
ID		 1221 ret = platform_driver_register(&rt2800soc_driver);
1222 if (ret)
1223 return ret;
1224#endif
72c7296e 1225#ifdef CONFIG_PCI
a9b3a9f7
ID		 1226 ret = pci_register_driver(&rt2800pci_driver);
1227 if (ret) {
5818a46a 1228#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
a9b3a9f7
ID		 1229 platform_driver_unregister(&rt2800soc_driver);
1230#endif
1231 return ret;
1232 }
1233#endif
1234
1235 return ret;
1236}
1237
1238static void __exit rt2800pci_exit(void)
1239{
72c7296e 1240#ifdef CONFIG_PCI
a9b3a9f7
ID		 1241 pci_unregister_driver(&rt2800pci_driver);
1242#endif
5818a46a 1243#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
a9b3a9f7
ID		 1244 platform_driver_unregister(&rt2800soc_driver);
1245#endif
1246}
1247
1248module_init(rt2800pci_init);
1249module_exit(rt2800pci_exit);
Linux kernel - Deliverables
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