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rt2x00: rt2800pci: move interrupt functions to the rt2800mmio module
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2800pci.c
CommitLineData
a9b3a9f7 1/*
96481b20 2 Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14
GW		 3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
a9b3a9f7
ID		 10 <http://rt2x00.serialmonkey.com>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 */
27
28/*
29 Module: rt2800pci
30 Abstract: rt2800pci device specific routines.
31 Supported chipsets: RT2800E & RT2800ED.
32 */
33
a9b3a9f7
ID		 34#include <linux/delay.h>
35#include <linux/etherdevice.h>
36#include <linux/init.h>
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/pci.h>
40#include <linux/platform_device.h>
41#include <linux/eeprom_93cx6.h>
42
43#include "rt2x00.h"
69a2bac8 44#include "rt2x00mmio.h"
a9b3a9f7
ID		 45#include "rt2x00pci.h"
46#include "rt2x00soc.h"
7ef5cc92 47#include "rt2800lib.h"
0bc202b3 48#include "rt2800mmio.h"
b54f78a8 49#include "rt2800.h"
a9b3a9f7
ID		 50#include "rt2800pci.h"
51
a9b3a9f7
ID		 52/*
53 * Allow hardware encryption to be disabled.
54 */
eb939922 55static bool modparam_nohwcrypt = false;
a9b3a9f7
ID		 56module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
57MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
58
ad417a53
GW		 59static bool rt2800pci_hwcrypt_disabled(struct rt2x00_dev *rt2x00dev)
60{
61 return modparam_nohwcrypt;
62}
63
a9b3a9f7
ID		 64static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
65{
66 unsigned int i;
67 u32 reg;
68
f18d4463
LC		 69 /*
70 * SOC devices don't support MCU requests.
71 */
72 if (rt2x00_is_soc(rt2x00dev))
73 return;
74
a9b3a9f7 75 for (i = 0; i < 200; i++) {
b9570b66 76 rt2x00mmio_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
a9b3a9f7
ID		 77
78 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
79 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
80 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
81 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
82 break;
83
84 udelay(REGISTER_BUSY_DELAY);
85 }
86
87 if (i == 200)
ec9c4989 88 rt2x00_err(rt2x00dev, "MCU request failed, no response from hardware\n");
a9b3a9f7 89
b9570b66
GJ		 90 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
91 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
a9b3a9f7
ID		 92}
93
5818a46a 94#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
a02308e9 95static int rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 96{
ef8397cf 97 void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
a9b3a9f7 98
a02308e9
GJ		 99 if (!base_addr)
100 return -ENOMEM;
101
a9b3a9f7 102 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
ef8397cf
GW		 103
104 iounmap(base_addr);
a02308e9 105 return 0;
a9b3a9f7
ID		 106}
107#else
a02308e9 108static inline int rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 109{
a02308e9 110 return -ENOMEM;
a9b3a9f7 111}
5818a46a 112#endif /* CONFIG_SOC_RT288X || CONFIG_SOC_RT305X */
a9b3a9f7 113
72c7296e 114#ifdef CONFIG_PCI
a9b3a9f7
ID		 115static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
116{
117 struct rt2x00_dev *rt2x00dev = eeprom->data;
118 u32 reg;
119
b9570b66 120 rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 121
122 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
123 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
124 eeprom->reg_data_clock =
125 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
126 eeprom->reg_chip_select =
127 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
128}
129
130static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
131{
132 struct rt2x00_dev *rt2x00dev = eeprom->data;
133 u32 reg = 0;
134
135 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
136 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
137 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
138 !!eeprom->reg_data_clock);
139 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
140 !!eeprom->reg_chip_select);
141
b9570b66 142 rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg);
a9b3a9f7
ID		 143}
144
a02308e9 145static int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
a9b3a9f7
ID		 146{
147 struct eeprom_93cx6 eeprom;
148 u32 reg;
149
b9570b66 150 rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 151
152 eeprom.data = rt2x00dev;
153 eeprom.register_read = rt2800pci_eepromregister_read;
154 eeprom.register_write = rt2800pci_eepromregister_write;
20f8b139
GW		 155 switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
156 {
157 case 0:
158 eeprom.width = PCI_EEPROM_WIDTH_93C46;
159 break;
160 case 1:
161 eeprom.width = PCI_EEPROM_WIDTH_93C66;
162 break;
163 default:
164 eeprom.width = PCI_EEPROM_WIDTH_93C86;
165 break;
166 }
a9b3a9f7
ID		 167 eeprom.reg_data_in = 0;
168 eeprom.reg_data_out = 0;
169 eeprom.reg_data_clock = 0;
170 eeprom.reg_chip_select = 0;
171
172 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
173 EEPROM_SIZE / sizeof(u16));
a02308e9
GJ		 174
175 return 0;
a9b3a9f7
ID		 176}
177
a6598682
GW		 178static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
179{
30e84034 180 return rt2800_efuse_detect(rt2x00dev);
a9b3a9f7
ID		 181}
182
a02308e9 183static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 184{
a02308e9 185 return rt2800_read_eeprom_efuse(rt2x00dev);
a9b3a9f7
ID		 186}
187#else
a02308e9 188static inline int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 189{
a02308e9 190 return -EOPNOTSUPP;
a9b3a9f7
ID		 191}
192
a6598682
GW		 193static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
194{
195 return 0;
196}
197
a02308e9 198static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 199{
a02308e9 200 return -EOPNOTSUPP;
a9b3a9f7 201}
72c7296e 202#endif /* CONFIG_PCI */
a9b3a9f7 203
5450b7e2
ID		 204/*
205 * Queue handlers.
206 */
207static void rt2800pci_start_queue(struct data_queue *queue)
208{
209 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
210 u32 reg;
211
212 switch (queue->qid) {
213 case QID_RX:
b9570b66 214 rt2x00mmio_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5450b7e2 215 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
b9570b66 216 rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5450b7e2
ID		 217 break;
218 case QID_BEACON:
b9570b66 219 rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
5450b7e2
ID		 220 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
221 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
222 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
b9570b66 223 rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
69cf36a4 224
b9570b66 225 rt2x00mmio_register_read(rt2x00dev, INT_TIMER_EN, &reg);
69cf36a4 226 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 1);
b9570b66 227 rt2x00mmio_register_write(rt2x00dev, INT_TIMER_EN, reg);
5450b7e2
ID		 228 break;
229 default:
230 break;
6403eab1 231 }
5450b7e2
ID		 232}
233
234static void rt2800pci_kick_queue(struct data_queue *queue)
235{
236 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
237 struct queue_entry *entry;
238
239 switch (queue->qid) {
f615e9a3
ID		 240 case QID_AC_VO:
241 case QID_AC_VI:
5450b7e2
ID		 242 case QID_AC_BE:
243 case QID_AC_BK:
5450b7e2 244 entry = rt2x00queue_get_entry(queue, Q_INDEX);
b9570b66
GJ		 245 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX(queue->qid),
246 entry->entry_idx);
5450b7e2
ID		 247 break;
248 case QID_MGMT:
249 entry = rt2x00queue_get_entry(queue, Q_INDEX);
b9570b66
GJ		 250 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX(5),
251 entry->entry_idx);
5450b7e2
ID		 252 break;
253 default:
254 break;
255 }
256}
257
258static void rt2800pci_stop_queue(struct data_queue *queue)
259{
260 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
261 u32 reg;
262
263 switch (queue->qid) {
264 case QID_RX:
b9570b66 265 rt2x00mmio_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5450b7e2 266 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
b9570b66 267 rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5450b7e2
ID		 268 break;
269 case QID_BEACON:
b9570b66 270 rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
5450b7e2
ID		 271 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
272 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
273 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
b9570b66 274 rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
69cf36a4 275
b9570b66 276 rt2x00mmio_register_read(rt2x00dev, INT_TIMER_EN, &reg);
69cf36a4 277 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 0);
b9570b66 278 rt2x00mmio_register_write(rt2x00dev, INT_TIMER_EN, reg);
a9d61e9e
HS		 279
280 /*
abc11994
HS		 281 * Wait for current invocation to finish. The tasklet
282 * won't be scheduled anymore afterwards since we disabled
283 * the TBTT and PRE TBTT timer.
a9d61e9e 284 */
abc11994
HS		 285 tasklet_kill(&rt2x00dev->tbtt_tasklet);
286 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
287
5450b7e2
ID		 288 break;
289 default:
290 break;
291 }
292}
293
a9b3a9f7
ID		 294/*
295 * Firmware functions
296 */
297static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
298{
a89534ed
WH		 299 /*
300 * Chip rt3290 use specific 4KB firmware named rt3290.bin.
301 */
302 if (rt2x00_rt(rt2x00dev, RT3290))
303 return FIRMWARE_RT3290;
304 else
305 return FIRMWARE_RT2860;
a9b3a9f7
ID		 306}
307
f31c9a8c 308static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
a9b3a9f7
ID		 309 const u8 *data, const size_t len)
310{
a9b3a9f7
ID		 311 u32 reg;
312
a9b3a9f7
ID		 313 /*
314 * enable Host program ram write selection
315 */
316 reg = 0;
317 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
b9570b66 318 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
a9b3a9f7
ID		 319
320 /*
321 * Write firmware to device.
322 */
b9570b66
GJ		 323 rt2x00mmio_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
324 data, len);
a9b3a9f7 325
b9570b66
GJ		 326 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
327 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
a9b3a9f7 328
b9570b66
GJ		 329 rt2x00mmio_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
330 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
a9b3a9f7
ID		 331
332 return 0;
333}
334
335/*
336 * Initialization functions.
337 */
338static bool rt2800pci_get_entry_state(struct queue_entry *entry)
339{
b9570b66 340 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
a9b3a9f7
ID		 341 u32 word;
342
343 if (entry->queue->qid == QID_RX) {
344 rt2x00_desc_read(entry_priv->desc, 1, &word);
345
346 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
347 } else {
348 rt2x00_desc_read(entry_priv->desc, 1, &word);
349
350 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
351 }
352}
353
354static void rt2800pci_clear_entry(struct queue_entry *entry)
355{
b9570b66 356 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
a9b3a9f7 357 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95192339 358 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
a9b3a9f7
ID		 359 u32 word;
360
361 if (entry->queue->qid == QID_RX) {
362 rt2x00_desc_read(entry_priv->desc, 0, &word);
363 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
364 rt2x00_desc_write(entry_priv->desc, 0, word);
365
366 rt2x00_desc_read(entry_priv->desc, 1, &word);
367 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
368 rt2x00_desc_write(entry_priv->desc, 1, word);
95192339
HS		 369
370 /*
371 * Set RX IDX in register to inform hardware that we have
372 * handled this entry and it is available for reuse again.
373 */
b9570b66
GJ		 374 rt2x00mmio_register_write(rt2x00dev, RX_CRX_IDX,
375 entry->entry_idx);
a9b3a9f7
ID		 376 } else {
377 rt2x00_desc_read(entry_priv->desc, 1, &word);
378 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
379 rt2x00_desc_write(entry_priv->desc, 1, word);
380 }
381}
382
383static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
384{
b9570b66 385 struct queue_entry_priv_mmio *entry_priv;
a9b3a9f7 386
a9b3a9f7
ID		 387 /*
388 * Initialize registers.
389 */
390 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
b9570b66
GJ		 391 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR0,
392 entry_priv->desc_dma);
393 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT0,
394 rt2x00dev->tx[0].limit);
395 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX0, 0);
396 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX0, 0);
a9b3a9f7
ID		 397
398 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
b9570b66
GJ		 399 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR1,
400 entry_priv->desc_dma);
401 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT1,
402 rt2x00dev->tx[1].limit);
403 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX1, 0);
404 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX1, 0);
a9b3a9f7
ID		 405
406 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
b9570b66
GJ		 407 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR2,
408 entry_priv->desc_dma);
409 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT2,
410 rt2x00dev->tx[2].limit);
411 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX2, 0);
412 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX2, 0);
a9b3a9f7
ID		 413
414 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
b9570b66
GJ		 415 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR3,
416 entry_priv->desc_dma);
417 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT3,
418 rt2x00dev->tx[3].limit);
419 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX3, 0);
420 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX3, 0);
421
422 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR4, 0);
423 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT4, 0);
424 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX4, 0);
425 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX4, 0);
426
427 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR5, 0);
428 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT5, 0);
429 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX5, 0);
430 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX5, 0);
3a4b43fd 431
a9b3a9f7 432 entry_priv = rt2x00dev->rx->entries[0].priv_data;
b9570b66
GJ		 433 rt2x00mmio_register_write(rt2x00dev, RX_BASE_PTR,
434 entry_priv->desc_dma);
435 rt2x00mmio_register_write(rt2x00dev, RX_MAX_CNT,
436 rt2x00dev->rx[0].limit);
437 rt2x00mmio_register_write(rt2x00dev, RX_CRX_IDX,
438 rt2x00dev->rx[0].limit - 1);
439 rt2x00mmio_register_write(rt2x00dev, RX_DRX_IDX, 0);
a9b3a9f7 440
f7b395e9 441 rt2800_disable_wpdma(rt2x00dev);
a9b3a9f7 442
b9570b66 443 rt2x00mmio_register_write(rt2x00dev, DELAY_INT_CFG, 0);
a9b3a9f7
ID		 444
445 return 0;
446}
447
a9b3a9f7
ID		 448/*
449 * Device state switch handlers.
450 */
e3a896b9
GW		 451static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
452{
453 u32 reg;
454
455 /*
456 * Reset DMA indexes
457 */
b9570b66 458 rt2x00mmio_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
e3a896b9
GW		 459 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
460 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
461 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
462 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
463 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
464 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
465 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
b9570b66 466 rt2x00mmio_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
e3a896b9 467
b9570b66
GJ		 468 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
469 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
e3a896b9 470
872834df 471 if (rt2x00_is_pcie(rt2x00dev) &&
41caa760
GJ		 472 (rt2x00_rt(rt2x00dev, RT3090) ||
473 rt2x00_rt(rt2x00dev, RT3390) ||
474 rt2x00_rt(rt2x00dev, RT3572) ||
475 rt2x00_rt(rt2x00dev, RT3593) ||
2ed71884 476 rt2x00_rt(rt2x00dev, RT5390) ||
41caa760
GJ		 477 rt2x00_rt(rt2x00dev, RT5392) ||
478 rt2x00_rt(rt2x00dev, RT5592))) {
b9570b66 479 rt2x00mmio_register_read(rt2x00dev, AUX_CTRL, &reg);
adde5882
GJ		 480 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
481 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
b9570b66 482 rt2x00mmio_register_write(rt2x00dev, AUX_CTRL, reg);
adde5882 483 }
60687ba7 484
b9570b66 485 rt2x00mmio_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
e3a896b9 486
2a48e8ae 487 reg = 0;
e3a896b9
GW		 488 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
489 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
b9570b66 490 rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
e3a896b9 491
b9570b66 492 rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
e3a896b9
GW		 493
494 return 0;
495}
496
a9b3a9f7
ID		 497static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
498{
e8b461c3
JK		 499 int retval;
500
52b8243b
JK		 501 /* Wait for DMA, ignore error until we initialize queues. */
502 rt2800_wait_wpdma_ready(rt2x00dev);
503
504 if (unlikely(rt2800pci_init_queues(rt2x00dev)))
a9b3a9f7
ID		 505 return -EIO;
506
e8b461c3
JK		 507 retval = rt2800_enable_radio(rt2x00dev);
508 if (retval)
509 return retval;
510
511 /* After resume MCU_BOOT_SIGNAL will trash these. */
b9570b66
GJ		 512 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
513 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
e8b461c3
JK		 514
515 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_RADIO_OFF, 0xff, 0x02);
516 rt2800pci_mcu_status(rt2x00dev, TOKEN_RADIO_OFF);
517
518 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP, 0, 0);
519 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
520
521 return retval;
a9b3a9f7
ID		 522}
523
524static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
525{
7f6e144f
RJH		 526 if (rt2x00_is_soc(rt2x00dev)) {
527 rt2800_disable_radio(rt2x00dev);
b9570b66
GJ		 528 rt2x00mmio_register_write(rt2x00dev, PWR_PIN_CFG, 0);
529 rt2x00mmio_register_write(rt2x00dev, TX_PIN_CFG, 0);
7f6e144f 530 }
a9b3a9f7
ID		 531}
532
533static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
534 enum dev_state state)
535{
a9b3a9f7 536 if (state == STATE_AWAKE) {
09a3311c
JK		 537 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP,
538 0, 0x02);
539 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
7f6e144f 540 } else if (state == STATE_SLEEP) {
b9570b66
GJ		 541 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
542 0xffffffff);
543 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID,
544 0xffffffff);
09a3311c
JK		 545 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_SLEEP,
546 0xff, 0x01);
a9b3a9f7
ID		 547 }
548
549 return 0;
550}
551
552static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
553 enum dev_state state)
554{
555 int retval = 0;
556
557 switch (state) {
558 case STATE_RADIO_ON:
a9b3a9f7
ID		 559 retval = rt2800pci_enable_radio(rt2x00dev);
560 break;
561 case STATE_RADIO_OFF:
562 /*
563 * After the radio has been disabled, the device should
564 * be put to sleep for powersaving.
565 */
566 rt2800pci_disable_radio(rt2x00dev);
567 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
568 break;
a9b3a9f7
ID		 569 case STATE_RADIO_IRQ_ON:
570 case STATE_RADIO_IRQ_OFF:
b5cfde3f 571 rt2800mmio_toggle_irq(rt2x00dev, state);
a9b3a9f7
ID		 572 break;
573 case STATE_DEEP_SLEEP:
574 case STATE_SLEEP:
575 case STATE_STANDBY:
576 case STATE_AWAKE:
577 retval = rt2800pci_set_state(rt2x00dev, state);
578 break;
579 default:
580 retval = -ENOTSUPP;
581 break;
582 }
583
584 if (unlikely(retval))
ec9c4989
JP		 585 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
586 state, retval);
a9b3a9f7
ID		 587
588 return retval;
589}
590
a9b3a9f7
ID		 591/*
592 * Device probe functions.
593 */
a02308e9 594static int rt2800pci_read_eeprom(struct rt2x00_dev *rt2x00dev)
7ab71325 595{
a02308e9
GJ		 596 int retval;
597
cea90e55 598 if (rt2x00_is_soc(rt2x00dev))
a02308e9 599 retval = rt2800pci_read_eeprom_soc(rt2x00dev);
cea90e55 600 else if (rt2800pci_efuse_detect(rt2x00dev))
a02308e9 601 retval = rt2800pci_read_eeprom_efuse(rt2x00dev);
cea90e55 602 else
a02308e9
GJ		 603 retval = rt2800pci_read_eeprom_pci(rt2x00dev);
604
605 return retval;
a9b3a9f7
ID		 606}
607
e783619e
HS		 608static const struct ieee80211_ops rt2800pci_mac80211_ops = {
609 .tx = rt2x00mac_tx,
610 .start = rt2x00mac_start,
611 .stop = rt2x00mac_stop,
612 .add_interface = rt2x00mac_add_interface,
613 .remove_interface = rt2x00mac_remove_interface,
614 .config = rt2x00mac_config,
615 .configure_filter = rt2x00mac_configure_filter,
e783619e
HS		 616 .set_key = rt2x00mac_set_key,
617 .sw_scan_start = rt2x00mac_sw_scan_start,
618 .sw_scan_complete = rt2x00mac_sw_scan_complete,
619 .get_stats = rt2x00mac_get_stats,
620 .get_tkip_seq = rt2800_get_tkip_seq,
621 .set_rts_threshold = rt2800_set_rts_threshold,
a2b1328a
HS		 622 .sta_add = rt2x00mac_sta_add,
623 .sta_remove = rt2x00mac_sta_remove,
e783619e
HS		 624 .bss_info_changed = rt2x00mac_bss_info_changed,
625 .conf_tx = rt2800_conf_tx,
626 .get_tsf = rt2800_get_tsf,
627 .rfkill_poll = rt2x00mac_rfkill_poll,
628 .ampdu_action = rt2800_ampdu_action,
f44df18c 629 .flush = rt2x00mac_flush,
977206d7 630 .get_survey = rt2800_get_survey,
e7dee444 631 .get_ringparam = rt2x00mac_get_ringparam,
5f0dd296 632 .tx_frames_pending = rt2x00mac_tx_frames_pending,
e783619e
HS		 633};
634
e796643e 635static const struct rt2800_ops rt2800pci_rt2800_ops = {
b9570b66
GJ		 636 .register_read = rt2x00mmio_register_read,
637 .register_read_lock = rt2x00mmio_register_read, /* same for PCI */
638 .register_write = rt2x00mmio_register_write,
639 .register_write_lock = rt2x00mmio_register_write, /* same for PCI */
640 .register_multiread = rt2x00mmio_register_multiread,
641 .register_multiwrite = rt2x00mmio_register_multiwrite,
642 .regbusy_read = rt2x00mmio_regbusy_read,
ad417a53
GW		 643 .read_eeprom = rt2800pci_read_eeprom,
644 .hwcrypt_disabled = rt2800pci_hwcrypt_disabled,
e796643e
ID		 645 .drv_write_firmware = rt2800pci_write_firmware,
646 .drv_init_registers = rt2800pci_init_registers,
45c67550 647 .drv_get_txwi = rt2800mmio_get_txwi,
e796643e
ID		 648};
649
a9b3a9f7 650static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
b5cfde3f
GJ		 651 .irq_handler = rt2800mmio_interrupt,
652 .txstatus_tasklet = rt2800mmio_txstatus_tasklet,
653 .pretbtt_tasklet = rt2800mmio_pretbtt_tasklet,
654 .tbtt_tasklet = rt2800mmio_tbtt_tasklet,
655 .rxdone_tasklet = rt2800mmio_rxdone_tasklet,
656 .autowake_tasklet = rt2800mmio_autowake_tasklet,
ad417a53 657 .probe_hw = rt2800_probe_hw,
a9b3a9f7 658 .get_firmware_name = rt2800pci_get_firmware_name,
f31c9a8c
ID		 659 .check_firmware = rt2800_check_firmware,
660 .load_firmware = rt2800_load_firmware,
b9570b66
GJ		 661 .initialize = rt2x00mmio_initialize,
662 .uninitialize = rt2x00mmio_uninitialize,
a9b3a9f7
ID		 663 .get_entry_state = rt2800pci_get_entry_state,
664 .clear_entry = rt2800pci_clear_entry,
665 .set_device_state = rt2800pci_set_device_state,
f4450616
BZ		 666 .rfkill_poll = rt2800_rfkill_poll,
667 .link_stats = rt2800_link_stats,
668 .reset_tuner = rt2800_reset_tuner,
669 .link_tuner = rt2800_link_tuner,
9e33a355 670 .gain_calibration = rt2800_gain_calibration,
2e9c43dd 671 .vco_calibration = rt2800_vco_calibration,
dbba306f
ID		 672 .start_queue = rt2800pci_start_queue,
673 .kick_queue = rt2800pci_kick_queue,
674 .stop_queue = rt2800pci_stop_queue,
b9570b66 675 .flush_queue = rt2x00mmio_flush_queue,
45c67550 676 .write_tx_desc = rt2800mmio_write_tx_desc,
0c5879bc 677 .write_tx_data = rt2800_write_tx_data,
f0194b2d 678 .write_beacon = rt2800_write_beacon,
69cf36a4 679 .clear_beacon = rt2800_clear_beacon,
d10b7547 680 .fill_rxdone = rt2800mmio_fill_rxdone,
f4450616
BZ		 681 .config_shared_key = rt2800_config_shared_key,
682 .config_pairwise_key = rt2800_config_pairwise_key,
683 .config_filter = rt2800_config_filter,
684 .config_intf = rt2800_config_intf,
685 .config_erp = rt2800_config_erp,
686 .config_ant = rt2800_config_ant,
687 .config = rt2800_config,
a2b1328a
HS		 688 .sta_add = rt2800_sta_add,
689 .sta_remove = rt2800_sta_remove,
a9b3a9f7
ID		 690};
691
1896b760
GJ		 692static void rt2800pci_queue_init(struct data_queue *queue)
693{
ae1b1c5d
GJ		 694 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
695 unsigned short txwi_size, rxwi_size;
696
697 rt2800_get_txwi_rxwi_size(rt2x00dev, &txwi_size, &rxwi_size);
698
1896b760
GJ		 699 switch (queue->qid) {
700 case QID_RX:
701 queue->limit = 128;
702 queue->data_size = AGGREGATION_SIZE;
703 queue->desc_size = RXD_DESC_SIZE;
ae1b1c5d 704 queue->winfo_size = rxwi_size;
1896b760
GJ		 705 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
706 break;
a9b3a9f7 707
1896b760
GJ		 708 case QID_AC_VO:
709 case QID_AC_VI:
710 case QID_AC_BE:
711 case QID_AC_BK:
712 queue->limit = 64;
713 queue->data_size = AGGREGATION_SIZE;
714 queue->desc_size = TXD_DESC_SIZE;
ae1b1c5d 715 queue->winfo_size = txwi_size;
1896b760
GJ		 716 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
717 break;
a9b3a9f7 718
1896b760
GJ		 719 case QID_BEACON:
720 queue->limit = 8;
721 queue->data_size = 0; /* No DMA required for beacons */
722 queue->desc_size = TXD_DESC_SIZE;
ae1b1c5d 723 queue->winfo_size = txwi_size;
1896b760
GJ		 724 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
725 break;
726
727 case QID_ATIM:
728 /* fallthrough */
729 default:
730 BUG();
731 break;
732 }
733}
a9b3a9f7
ID		 734
735static const struct rt2x00_ops rt2800pci_ops = {
04d0362e 736 .name = KBUILD_MODNAME,
3a1c0128 737 .drv_data_size = sizeof(struct rt2800_drv_data),
04d0362e
GW		 738 .max_ap_intf = 8,
739 .eeprom_size = EEPROM_SIZE,
740 .rf_size = RF_SIZE,
741 .tx_queues = NUM_TX_QUEUES,
1896b760 742 .queue_init = rt2800pci_queue_init,
04d0362e 743 .lib = &rt2800pci_rt2x00_ops,
e796643e 744 .drv = &rt2800pci_rt2800_ops,
e783619e 745 .hw = &rt2800pci_mac80211_ops,
a9b3a9f7 746#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 747 .debugfs = &rt2800_rt2x00debug,
a9b3a9f7
ID		 748#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
749};
750
751/*
752 * RT2800pci module information.
753 */
72c7296e 754#ifdef CONFIG_PCI
a3aa1884 755static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
e01ae27f
GW		 756 { PCI_DEVICE(0x1814, 0x0601) },
757 { PCI_DEVICE(0x1814, 0x0681) },
758 { PCI_DEVICE(0x1814, 0x0701) },
759 { PCI_DEVICE(0x1814, 0x0781) },
760 { PCI_DEVICE(0x1814, 0x3090) },
761 { PCI_DEVICE(0x1814, 0x3091) },
762 { PCI_DEVICE(0x1814, 0x3092) },
763 { PCI_DEVICE(0x1432, 0x7708) },
764 { PCI_DEVICE(0x1432, 0x7727) },
765 { PCI_DEVICE(0x1432, 0x7728) },
766 { PCI_DEVICE(0x1432, 0x7738) },
767 { PCI_DEVICE(0x1432, 0x7748) },
768 { PCI_DEVICE(0x1432, 0x7758) },
769 { PCI_DEVICE(0x1432, 0x7768) },
770 { PCI_DEVICE(0x1462, 0x891a) },
771 { PCI_DEVICE(0x1a3b, 0x1059) },
a89534ed
WH		 772#ifdef CONFIG_RT2800PCI_RT3290
773 { PCI_DEVICE(0x1814, 0x3290) },
774#endif
f93bc9b3 775#ifdef CONFIG_RT2800PCI_RT33XX
e01ae27f 776 { PCI_DEVICE(0x1814, 0x3390) },
f93bc9b3 777#endif
de1ebdce 778#ifdef CONFIG_RT2800PCI_RT35XX
e01ae27f
GW		 779 { PCI_DEVICE(0x1432, 0x7711) },
780 { PCI_DEVICE(0x1432, 0x7722) },
781 { PCI_DEVICE(0x1814, 0x3060) },
782 { PCI_DEVICE(0x1814, 0x3062) },
783 { PCI_DEVICE(0x1814, 0x3562) },
784 { PCI_DEVICE(0x1814, 0x3592) },
785 { PCI_DEVICE(0x1814, 0x3593) },
c4806014 786 { PCI_DEVICE(0x1814, 0x359f) },
60687ba7
RST		 787#endif
788#ifdef CONFIG_RT2800PCI_RT53XX
ccf91bd6 789 { PCI_DEVICE(0x1814, 0x5360) },
f57d7b6c 790 { PCI_DEVICE(0x1814, 0x5362) },
e01ae27f 791 { PCI_DEVICE(0x1814, 0x5390) },
f57d7b6c 792 { PCI_DEVICE(0x1814, 0x5392) },
5126d97e 793 { PCI_DEVICE(0x1814, 0x539a) },
2aed6915 794 { PCI_DEVICE(0x1814, 0x539b) },
71e0b38c 795 { PCI_DEVICE(0x1814, 0x539f) },
de1ebdce 796#endif
a9b3a9f7
ID		 797 { 0, }
798};
72c7296e 799#endif /* CONFIG_PCI */
a9b3a9f7
ID		 800
801MODULE_AUTHOR(DRV_PROJECT);
802MODULE_VERSION(DRV_VERSION);
803MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
804MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
72c7296e 805#ifdef CONFIG_PCI
a9b3a9f7
ID		 806MODULE_FIRMWARE(FIRMWARE_RT2860);
807MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
72c7296e 808#endif /* CONFIG_PCI */
a9b3a9f7
ID		 809MODULE_LICENSE("GPL");
810
5818a46a 811#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
714fa663
GW		 812static int rt2800soc_probe(struct platform_device *pdev)
813{
6e93d719 814 return rt2x00soc_probe(pdev, &rt2800pci_ops);
714fa663 815}
a9b3a9f7
ID		 816
817static struct platform_driver rt2800soc_driver = {
818 .driver = {
819 .name = "rt2800_wmac",
820 .owner = THIS_MODULE,
821 .mod_name = KBUILD_MODNAME,
822 },
714fa663 823 .probe = rt2800soc_probe,
69202359 824 .remove = rt2x00soc_remove,
a9b3a9f7
ID		 825 .suspend = rt2x00soc_suspend,
826 .resume = rt2x00soc_resume,
827};
5818a46a 828#endif /* CONFIG_SOC_RT288X || CONFIG_SOC_RT305X */
a9b3a9f7 829
72c7296e 830#ifdef CONFIG_PCI
e01ae27f
GW		 831static int rt2800pci_probe(struct pci_dev *pci_dev,
832 const struct pci_device_id *id)
833{
834 return rt2x00pci_probe(pci_dev, &rt2800pci_ops);
835}
836
a9b3a9f7
ID		 837static struct pci_driver rt2800pci_driver = {
838 .name = KBUILD_MODNAME,
839 .id_table = rt2800pci_device_table,
e01ae27f 840 .probe = rt2800pci_probe,
69202359 841 .remove = rt2x00pci_remove,
a9b3a9f7
ID		 842 .suspend = rt2x00pci_suspend,
843 .resume = rt2x00pci_resume,
844};
72c7296e 845#endif /* CONFIG_PCI */
a9b3a9f7
ID		 846
847static int __init rt2800pci_init(void)
848{
849 int ret = 0;
850
5818a46a 851#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
a9b3a9f7
ID		 852 ret = platform_driver_register(&rt2800soc_driver);
853 if (ret)
854 return ret;
855#endif
72c7296e 856#ifdef CONFIG_PCI
a9b3a9f7
ID		 857 ret = pci_register_driver(&rt2800pci_driver);
858 if (ret) {
5818a46a 859#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
a9b3a9f7
ID		 860 platform_driver_unregister(&rt2800soc_driver);
861#endif
862 return ret;
863 }
864#endif
865
866 return ret;
867}
868
869static void __exit rt2800pci_exit(void)
870{
72c7296e 871#ifdef CONFIG_PCI
a9b3a9f7
ID		 872 pci_unregister_driver(&rt2800pci_driver);
873#endif
5818a46a 874#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
a9b3a9f7
ID		 875 platform_driver_unregister(&rt2800soc_driver);
876#endif
877}
878
879module_init(rt2800pci_init);
880module_exit(rt2800pci_exit);
Linux kernel - Deliverables
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