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rt2x00: Add missing TSF sync mode for AP operation
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2800pci.c
CommitLineData
a9b3a9f7 1/*
9c9a0d14
GW		 2 Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
a9b3a9f7
ID		 10 <http://rt2x00.serialmonkey.com>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 */
27
28/*
29 Module: rt2800pci
30 Abstract: rt2800pci device specific routines.
31 Supported chipsets: RT2800E & RT2800ED.
32 */
33
34#include <linux/crc-ccitt.h>
35#include <linux/delay.h>
36#include <linux/etherdevice.h>
37#include <linux/init.h>
38#include <linux/kernel.h>
39#include <linux/module.h>
40#include <linux/pci.h>
41#include <linux/platform_device.h>
42#include <linux/eeprom_93cx6.h>
43
44#include "rt2x00.h"
45#include "rt2x00pci.h"
46#include "rt2x00soc.h"
7ef5cc92 47#include "rt2800lib.h"
b54f78a8 48#include "rt2800.h"
a9b3a9f7
ID		 49#include "rt2800pci.h"
50
a9b3a9f7
ID		 51/*
52 * Allow hardware encryption to be disabled.
53 */
04f1e34d 54static int modparam_nohwcrypt = 0;
a9b3a9f7
ID		 55module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
56MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
57
a9b3a9f7
ID		 58static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
59{
60 unsigned int i;
61 u32 reg;
62
f18d4463
LC		 63 /*
64 * SOC devices don't support MCU requests.
65 */
66 if (rt2x00_is_soc(rt2x00dev))
67 return;
68
a9b3a9f7 69 for (i = 0; i < 200; i++) {
9ca21eb7 70 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
a9b3a9f7
ID		 71
72 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
73 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
74 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
75 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
76 break;
77
78 udelay(REGISTER_BUSY_DELAY);
79 }
80
81 if (i == 200)
82 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
83
9ca21eb7
BZ		 84 rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
85 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
a9b3a9f7
ID		 86}
87
00e23ce2 88#ifdef CONFIG_RT2800PCI_SOC
a9b3a9f7
ID		 89static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
90{
91 u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */
92
93 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
94}
95#else
96static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
97{
98}
00e23ce2 99#endif /* CONFIG_RT2800PCI_SOC */
a9b3a9f7
ID		 100
101#ifdef CONFIG_RT2800PCI_PCI
102static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
103{
104 struct rt2x00_dev *rt2x00dev = eeprom->data;
105 u32 reg;
106
9ca21eb7 107 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 108
109 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
110 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
111 eeprom->reg_data_clock =
112 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
113 eeprom->reg_chip_select =
114 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
115}
116
117static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
118{
119 struct rt2x00_dev *rt2x00dev = eeprom->data;
120 u32 reg = 0;
121
122 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
123 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
124 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
125 !!eeprom->reg_data_clock);
126 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
127 !!eeprom->reg_chip_select);
128
9ca21eb7 129 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
a9b3a9f7
ID		 130}
131
132static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
133{
134 struct eeprom_93cx6 eeprom;
135 u32 reg;
136
9ca21eb7 137 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 138
139 eeprom.data = rt2x00dev;
140 eeprom.register_read = rt2800pci_eepromregister_read;
141 eeprom.register_write = rt2800pci_eepromregister_write;
20f8b139
GW		 142 switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
143 {
144 case 0:
145 eeprom.width = PCI_EEPROM_WIDTH_93C46;
146 break;
147 case 1:
148 eeprom.width = PCI_EEPROM_WIDTH_93C66;
149 break;
150 default:
151 eeprom.width = PCI_EEPROM_WIDTH_93C86;
152 break;
153 }
a9b3a9f7
ID		 154 eeprom.reg_data_in = 0;
155 eeprom.reg_data_out = 0;
156 eeprom.reg_data_clock = 0;
157 eeprom.reg_chip_select = 0;
158
159 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
160 EEPROM_SIZE / sizeof(u16));
161}
162
a6598682
GW		 163static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
164{
30e84034 165 return rt2800_efuse_detect(rt2x00dev);
a9b3a9f7
ID		 166}
167
30e84034 168static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 169{
30e84034 170 rt2800_read_eeprom_efuse(rt2x00dev);
a9b3a9f7
ID		 171}
172#else
173static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
174{
175}
176
a6598682
GW		 177static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
178{
179 return 0;
180}
181
a9b3a9f7
ID		 182static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
183{
184}
185#endif /* CONFIG_RT2800PCI_PCI */
186
a9b3a9f7
ID		 187/*
188 * Firmware functions
189 */
190static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
191{
192 return FIRMWARE_RT2860;
193}
194
195static int rt2800pci_check_firmware(struct rt2x00_dev *rt2x00dev,
196 const u8 *data, const size_t len)
197{
198 u16 fw_crc;
199 u16 crc;
200
201 /*
202 * Only support 8kb firmware files.
203 */
204 if (len != 8192)
205 return FW_BAD_LENGTH;
206
207 /*
208 * The last 2 bytes in the firmware array are the crc checksum itself,
209 * this means that we should never pass those 2 bytes to the crc
210 * algorithm.
211 */
212 fw_crc = (data[len - 2] << 8 | data[len - 1]);
213
214 /*
215 * Use the crc ccitt algorithm.
216 * This will return the same value as the legacy driver which
217 * used bit ordering reversion on the both the firmware bytes
218 * before input input as well as on the final output.
219 * Obviously using crc ccitt directly is much more efficient.
220 */
221 crc = crc_ccitt(~0, data, len - 2);
222
223 /*
224 * There is a small difference between the crc-itu-t + bitrev and
225 * the crc-ccitt crc calculation. In the latter method the 2 bytes
226 * will be swapped, use swab16 to convert the crc to the correct
227 * value.
228 */
229 crc = swab16(crc);
230
231 return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
232}
233
234static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
235 const u8 *data, const size_t len)
236{
237 unsigned int i;
238 u32 reg;
239
240 /*
241 * Wait for stable hardware.
242 */
243 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9ca21eb7 244 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
a9b3a9f7
ID		 245 if (reg && reg != ~0)
246 break;
247 msleep(1);
248 }
249
250 if (i == REGISTER_BUSY_COUNT) {
251 ERROR(rt2x00dev, "Unstable hardware.\n");
252 return -EBUSY;
253 }
254
9ca21eb7
BZ		 255 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
256 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
a9b3a9f7
ID		 257
258 /*
259 * Disable DMA, will be reenabled later when enabling
260 * the radio.
261 */
9ca21eb7 262 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 263 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
264 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
265 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
266 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
267 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 268 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7
ID		 269
270 /*
271 * enable Host program ram write selection
272 */
273 reg = 0;
274 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
9ca21eb7 275 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
a9b3a9f7
ID		 276
277 /*
278 * Write firmware to device.
279 */
4f2732ce 280 rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
a9b3a9f7
ID		 281 data, len);
282
9ca21eb7
BZ		 283 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
284 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
a9b3a9f7
ID		 285
286 /*
287 * Wait for device to stabilize.
288 */
289 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9ca21eb7 290 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
a9b3a9f7
ID		 291 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
292 break;
293 msleep(1);
294 }
295
296 if (i == REGISTER_BUSY_COUNT) {
297 ERROR(rt2x00dev, "PBF system register not ready.\n");
298 return -EBUSY;
299 }
300
301 /*
302 * Disable interrupts
303 */
304 rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_OFF);
305
306 /*
307 * Initialize BBP R/W access agent
308 */
9ca21eb7
BZ		 309 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
310 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
a9b3a9f7
ID		 311
312 return 0;
313}
314
315/*
316 * Initialization functions.
317 */
318static bool rt2800pci_get_entry_state(struct queue_entry *entry)
319{
320 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
321 u32 word;
322
323 if (entry->queue->qid == QID_RX) {
324 rt2x00_desc_read(entry_priv->desc, 1, &word);
325
326 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
327 } else {
328 rt2x00_desc_read(entry_priv->desc, 1, &word);
329
330 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
331 }
332}
333
334static void rt2800pci_clear_entry(struct queue_entry *entry)
335{
336 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
337 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
338 u32 word;
339
340 if (entry->queue->qid == QID_RX) {
341 rt2x00_desc_read(entry_priv->desc, 0, &word);
342 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
343 rt2x00_desc_write(entry_priv->desc, 0, word);
344
345 rt2x00_desc_read(entry_priv->desc, 1, &word);
346 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
347 rt2x00_desc_write(entry_priv->desc, 1, word);
348 } else {
349 rt2x00_desc_read(entry_priv->desc, 1, &word);
350 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
351 rt2x00_desc_write(entry_priv->desc, 1, word);
352 }
353}
354
355static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
356{
357 struct queue_entry_priv_pci *entry_priv;
358 u32 reg;
359
a9b3a9f7
ID		 360 /*
361 * Initialize registers.
362 */
363 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
9ca21eb7
BZ		 364 rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
365 rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
366 rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
367 rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
a9b3a9f7
ID		 368
369 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
9ca21eb7
BZ		 370 rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
371 rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
372 rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
373 rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
a9b3a9f7
ID		 374
375 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
9ca21eb7
BZ		 376 rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
377 rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
378 rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
379 rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
a9b3a9f7
ID		 380
381 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
9ca21eb7
BZ		 382 rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
383 rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
384 rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
385 rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
a9b3a9f7
ID		 386
387 entry_priv = rt2x00dev->rx->entries[0].priv_data;
9ca21eb7
BZ		 388 rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
389 rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
390 rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
391 rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
a9b3a9f7
ID		 392
393 /*
394 * Enable global DMA configuration
395 */
9ca21eb7 396 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 397 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
398 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
399 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 400 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7 401
9ca21eb7 402 rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
a9b3a9f7
ID		 403
404 return 0;
405}
406
a9b3a9f7
ID		 407/*
408 * Device state switch handlers.
409 */
410static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
411 enum dev_state state)
412{
413 u32 reg;
414
9ca21eb7 415 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
a9b3a9f7
ID		 416 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
417 (state == STATE_RADIO_RX_ON) ||
418 (state == STATE_RADIO_RX_ON_LINK));
9ca21eb7 419 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
a9b3a9f7
ID		 420}
421
422static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
423 enum dev_state state)
424{
78e256c9
HS		 425 int mask = (state == STATE_RADIO_IRQ_ON) ||
426 (state == STATE_RADIO_IRQ_ON_ISR);
a9b3a9f7
ID		 427 u32 reg;
428
429 /*
430 * When interrupts are being enabled, the interrupt registers
431 * should clear the register to assure a clean state.
432 */
433 if (state == STATE_RADIO_IRQ_ON) {
9ca21eb7
BZ		 434 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
435 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
a9b3a9f7
ID		 436 }
437
9ca21eb7 438 rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
a9b3a9f7
ID		 439 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
440 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
441 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
442 rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
443 rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
444 rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
445 rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
446 rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
447 rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
448 rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
449 rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, mask);
450 rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
451 rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
452 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
453 rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
454 rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
455 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
456 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
9ca21eb7 457 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
a9b3a9f7
ID		 458}
459
e3a896b9
GW		 460static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
461{
462 u32 reg;
463
464 /*
465 * Reset DMA indexes
466 */
467 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
468 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
469 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
470 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
471 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
472 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
473 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
474 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
475 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
476
477 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
478 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
479
480 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
481
482 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
483 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
484 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
485 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
486
487 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
488
489 return 0;
490}
491
a9b3a9f7
ID		 492static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
493{
494 u32 reg;
495 u16 word;
496
497 /*
498 * Initialize all registers.
499 */
67a4c1e2 500 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
a9b3a9f7 501 rt2800pci_init_queues(rt2x00dev) ||
fcf51541 502 rt2800_init_registers(rt2x00dev) ||
67a4c1e2 503 rt2800_wait_wpdma_ready(rt2x00dev) ||
fcf51541
BZ		 504 rt2800_init_bbp(rt2x00dev) ||
505 rt2800_init_rfcsr(rt2x00dev)))
a9b3a9f7
ID		 506 return -EIO;
507
508 /*
509 * Send signal to firmware during boot time.
510 */
532bc2d5 511 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
a9b3a9f7
ID		 512
513 /*
514 * Enable RX.
515 */
9ca21eb7 516 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
a9b3a9f7
ID		 517 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
518 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
9ca21eb7 519 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
a9b3a9f7 520
9ca21eb7 521 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 522 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
523 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
524 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
525 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 526 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7 527
9ca21eb7 528 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
a9b3a9f7
ID		 529 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
530 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
9ca21eb7 531 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
a9b3a9f7
ID		 532
533 /*
534 * Initialize LED control
535 */
536 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
3a9e5b0f 537 rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
a9b3a9f7
ID		 538 word & 0xff, (word >> 8) & 0xff);
539
540 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
3a9e5b0f 541 rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
a9b3a9f7
ID		 542 word & 0xff, (word >> 8) & 0xff);
543
544 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
3a9e5b0f 545 rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
a9b3a9f7
ID		 546 word & 0xff, (word >> 8) & 0xff);
547
548 return 0;
549}
550
551static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
552{
553 u32 reg;
554
9ca21eb7 555 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 556 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
557 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
558 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
559 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
560 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 561 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7 562
9ca21eb7
BZ		 563 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
564 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
565 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
a9b3a9f7 566
9ca21eb7 567 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
a9b3a9f7 568
9ca21eb7 569 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
a9b3a9f7
ID		 570 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
571 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
572 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
573 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
574 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
575 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
576 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
9ca21eb7 577 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
a9b3a9f7 578
9ca21eb7
BZ		 579 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
580 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
a9b3a9f7
ID		 581
582 /* Wait for DMA, ignore error */
67a4c1e2 583 rt2800_wait_wpdma_ready(rt2x00dev);
a9b3a9f7
ID		 584}
585
586static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
587 enum dev_state state)
588{
589 /*
590 * Always put the device to sleep (even when we intend to wakeup!)
591 * if the device is booting and wasn't asleep it will return
592 * failure when attempting to wakeup.
593 */
3a9e5b0f 594 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
a9b3a9f7
ID		 595
596 if (state == STATE_AWAKE) {
3a9e5b0f 597 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
a9b3a9f7
ID		 598 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
599 }
600
601 return 0;
602}
603
604static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
605 enum dev_state state)
606{
607 int retval = 0;
608
609 switch (state) {
610 case STATE_RADIO_ON:
611 /*
612 * Before the radio can be enabled, the device first has
613 * to be woken up. After that it needs a bit of time
614 * to be fully awake and then the radio can be enabled.
615 */
616 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
617 msleep(1);
618 retval = rt2800pci_enable_radio(rt2x00dev);
619 break;
620 case STATE_RADIO_OFF:
621 /*
622 * After the radio has been disabled, the device should
623 * be put to sleep for powersaving.
624 */
625 rt2800pci_disable_radio(rt2x00dev);
626 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
627 break;
628 case STATE_RADIO_RX_ON:
629 case STATE_RADIO_RX_ON_LINK:
630 case STATE_RADIO_RX_OFF:
631 case STATE_RADIO_RX_OFF_LINK:
632 rt2800pci_toggle_rx(rt2x00dev, state);
633 break;
634 case STATE_RADIO_IRQ_ON:
78e256c9 635 case STATE_RADIO_IRQ_ON_ISR:
a9b3a9f7 636 case STATE_RADIO_IRQ_OFF:
78e256c9 637 case STATE_RADIO_IRQ_OFF_ISR:
a9b3a9f7
ID		 638 rt2800pci_toggle_irq(rt2x00dev, state);
639 break;
640 case STATE_DEEP_SLEEP:
641 case STATE_SLEEP:
642 case STATE_STANDBY:
643 case STATE_AWAKE:
644 retval = rt2800pci_set_state(rt2x00dev, state);
645 break;
646 default:
647 retval = -ENOTSUPP;
648 break;
649 }
650
651 if (unlikely(retval))
652 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
653 state, retval);
654
655 return retval;
656}
657
658/*
659 * TX descriptor initialization
660 */
76dd5ddf
GW		 661static void rt2800pci_write_tx_data(struct queue_entry* entry,
662 struct txentry_desc *txdesc)
a9b3a9f7 663{
9cf4cb05
GW		 664 __le32 *txwi = (__le32 *) entry->skb->data;
665
666 rt2800_write_txwi(txwi, txdesc);
745b1ae3
HS		 667}
668
669
670static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
671 struct sk_buff *skb,
672 struct txentry_desc *txdesc)
673{
674 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
85b7a8b3
GW		 675 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
676 __le32 *txd = entry_priv->desc;
745b1ae3
HS		 677 u32 word;
678
a9b3a9f7
ID		 679 /*
680 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
681 * must contains a TXWI structure + 802.11 header + padding + 802.11
682 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
683 * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
684 * data. It means that LAST_SEC0 is always 0.
685 */
686
687 /*
688 * Initialize TX descriptor
689 */
690 rt2x00_desc_read(txd, 0, &word);
691 rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
692 rt2x00_desc_write(txd, 0, word);
693
694 rt2x00_desc_read(txd, 1, &word);
695 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
696 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
697 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
698 rt2x00_set_field32(&word, TXD_W1_BURST,
699 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
85b7a8b3 700 rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
a9b3a9f7
ID		 701 rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
702 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
703 rt2x00_desc_write(txd, 1, word);
704
705 rt2x00_desc_read(txd, 2, &word);
706 rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
85b7a8b3 707 skbdesc->skb_dma + TXWI_DESC_SIZE);
a9b3a9f7
ID		 708 rt2x00_desc_write(txd, 2, word);
709
710 rt2x00_desc_read(txd, 3, &word);
711 rt2x00_set_field32(&word, TXD_W3_WIV,
712 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
713 rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
714 rt2x00_desc_write(txd, 3, word);
85b7a8b3
GW		 715
716 /*
717 * Register descriptor details in skb frame descriptor.
718 */
719 skbdesc->desc = txd;
720 skbdesc->desc_len = TXD_DESC_SIZE;
a9b3a9f7
ID		 721}
722
723/*
724 * TX data initialization
725 */
a9b3a9f7
ID		 726static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
727 const enum data_queue_qid queue_idx)
728{
729 struct data_queue *queue;
730 unsigned int idx, qidx = 0;
a9b3a9f7
ID		 731
732 if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
733 return;
734
735 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
736 idx = queue->index[Q_INDEX];
737
738 if (queue_idx == QID_MGMT)
739 qidx = 5;
740 else
741 qidx = queue_idx;
742
9ca21eb7 743 rt2800_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
a9b3a9f7
ID		 744}
745
746static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
747 const enum data_queue_qid qid)
748{
749 u32 reg;
750
751 if (qid == QID_BEACON) {
9ca21eb7 752 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, 0);
a9b3a9f7
ID		 753 return;
754 }
755
9ca21eb7 756 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
a9b3a9f7
ID		 757 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
758 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
759 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
760 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
9ca21eb7 761 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
a9b3a9f7
ID		 762}
763
764/*
765 * RX control handlers
766 */
767static void rt2800pci_fill_rxdone(struct queue_entry *entry,
768 struct rxdone_entry_desc *rxdesc)
769{
770 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
a9b3a9f7
ID		 771 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
772 __le32 *rxd = entry_priv->desc;
2de64dd2
GW		 773 u32 word;
774
775 rt2x00_desc_read(rxd, 3, &word);
776
777 if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
a9b3a9f7
ID		 778 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
779
78b8f3b0
GW		 780 /*
781 * Unfortunately we don't know the cipher type used during
782 * decryption. This prevents us from correct providing
783 * correct statistics through debugfs.
784 */
2de64dd2 785 rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
a9b3a9f7 786
2de64dd2 787 if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
a9b3a9f7
ID		 788 /*
789 * Hardware has stripped IV/EIV data from 802.11 frame during
790 * decryption. Unfortunately the descriptor doesn't contain
791 * any fields with the EIV/IV data either, so they can't
792 * be restored by rt2x00lib.
793 */
794 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
795
796 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
797 rxdesc->flags |= RX_FLAG_DECRYPTED;
798 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
799 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
800 }
801
2de64dd2 802 if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
a9b3a9f7
ID		 803 rxdesc->dev_flags |= RXDONE_MY_BSS;
804
2de64dd2 805 if (rt2x00_get_field32(word, RXD_W3_L2PAD))
a9b3a9f7 806 rxdesc->dev_flags |= RXDONE_L2PAD;
a9b3a9f7 807
a9b3a9f7 808 /*
2de64dd2 809 * Process the RXWI structure that is at the start of the buffer.
a9b3a9f7 810 */
74861922 811 rt2800_process_rxwi(entry, rxdesc);
a9b3a9f7
ID		 812
813 /*
814 * Set RX IDX in register to inform hardware that we have handled
815 * this entry and it is available for reuse again.
816 */
9ca21eb7 817 rt2800_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
a9b3a9f7
ID		 818}
819
820/*
821 * Interrupt functions.
822 */
823static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
824{
825 struct data_queue *queue;
826 struct queue_entry *entry;
632dd959 827 __le32 *txwi;
a9b3a9f7
ID		 828 struct txdone_entry_desc txdesc;
829 u32 word;
830 u32 reg;
632dd959 831 int wcid, ack, pid, tx_wcid, tx_ack, tx_pid;
a9b3a9f7 832 u16 mcs, real_mcs;
3afa626a 833 int i;
a9b3a9f7
ID		 834
835 /*
3afa626a
HS		 836 * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
837 * at most X times and also stop processing once the TX_STA_FIFO_VALID
838 * flag is not set anymore.
839 *
840 * The legacy drivers use X=TX_RING_SIZE but state in a comment
841 * that the TX_STA_FIFO stack has a size of 16. We stick to our
842 * tx ring size for now.
a9b3a9f7 843 */
3afa626a 844 for (i = 0; i < TX_ENTRIES; i++) {
9ca21eb7 845 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
a9b3a9f7
ID		 846 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
847 break;
848
632dd959
AB		 849 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
850 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
851 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
852
a9b3a9f7
ID		 853 /*
854 * Skip this entry when it contains an invalid
855 * queue identication number.
856 */
632dd959 857 if (pid <= 0 || pid > QID_RX)
a9b3a9f7
ID		 858 continue;
859
632dd959 860 queue = rt2x00queue_get_queue(rt2x00dev, pid - 1);
a9b3a9f7
ID		 861 if (unlikely(!queue))
862 continue;
863
864 /*
632dd959
AB		 865 * Inside each queue, we process each entry in a chronological
866 * order. We first check that the queue is not empty.
a9b3a9f7 867 */
632dd959 868 if (rt2x00queue_empty(queue))
a9b3a9f7 869 continue;
632dd959 870 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
a9b3a9f7 871
632dd959
AB		 872 /* Check if we got a match by looking at WCID/ACK/PID
873 * fields */
0b8004aa 874 txwi = (__le32 *) entry->skb->data;
632dd959
AB		 875
876 rt2x00_desc_read(txwi, 1, &word);
877 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
878 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK);
879 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID);
880
881 if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid))
882 WARNING(rt2x00dev, "invalid TX_STA_FIFO content\n");
a9b3a9f7
ID		 883
884 /*
885 * Obtain the status about this packet.
886 */
887 txdesc.flags = 0;
bf18723d
AB		 888 rt2x00_desc_read(txwi, 0, &word);
889 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
890 real_mcs = rt2x00_get_field32(reg, TX_STA_FIFO_MCS);
a9b3a9f7
ID		 891
892 /*
893 * Ralink has a retry mechanism using a global fallback
bf18723d
AB		 894 * table. We setup this fallback table to try the immediate
895 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
896 * always contains the MCS used for the last transmission, be
897 * it successful or not.
a9b3a9f7 898 */
bf18723d
AB		 899 if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS)) {
900 /*
901 * Transmission succeeded. The number of retries is
902 * mcs - real_mcs
903 */
904 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
905 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
906 } else {
907 /*
908 * Transmission failed. The number of retries is
909 * always 7 in this case (for a total number of 8
910 * frames sent).
911 */
912 __set_bit(TXDONE_FAILURE, &txdesc.flags);
913 txdesc.retry = 7;
914 }
915
ecb7cab5
HS		 916 /*
917 * the frame was retried at least once
918 * -> hw used fallback rates
919 */
920 if (txdesc.retry)
921 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
a9b3a9f7 922
e513a0b6 923 rt2x00lib_txdone(entry, &txdesc);
a9b3a9f7
ID		 924 }
925}
926
4d66edc8
GW		 927static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
928{
929 struct ieee80211_conf conf = { .flags = 0 };
930 struct rt2x00lib_conf libconf = { .conf = &conf };
931
932 rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
933}
934
78e256c9 935static irqreturn_t rt2800pci_interrupt_thread(int irq, void *dev_instance)
a9b3a9f7
ID		 936{
937 struct rt2x00_dev *rt2x00dev = dev_instance;
78e256c9 938 u32 reg = rt2x00dev->irqvalue[0];
a9b3a9f7
ID		 939
940 /*
9f926fb5
HS		 941 * 1 - Pre TBTT interrupt.
942 */
943 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
944 rt2x00lib_pretbtt(rt2x00dev);
945
946 /*
947 * 2 - Beacondone interrupt.
948 */
949 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
950 rt2x00lib_beacondone(rt2x00dev);
951
952 /*
953 * 3 - Rx ring done interrupt.
a9b3a9f7
ID		 954 */
955 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
956 rt2x00pci_rxdone(rt2x00dev);
957
9f926fb5
HS		 958 /*
959 * 4 - Tx done interrupt.
960 */
a9b3a9f7
ID		 961 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
962 rt2800pci_txdone(rt2x00dev);
963
ad90319b 964 /*
9f926fb5 965 * 5 - Auto wakeup interrupt.
ad90319b 966 */
4d66edc8
GW		 967 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
968 rt2800pci_wakeup(rt2x00dev);
969
78e256c9
HS		 970 /* Enable interrupts again. */
971 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
972 STATE_RADIO_IRQ_ON_ISR);
973
a9b3a9f7
ID		 974 return IRQ_HANDLED;
975}
976
78e256c9
HS		 977static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
978{
979 struct rt2x00_dev *rt2x00dev = dev_instance;
980 u32 reg;
981
982 /* Read status and ACK all interrupts */
983 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
984 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
985
986 if (!reg)
987 return IRQ_NONE;
988
989 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
990 return IRQ_HANDLED;
991
992 /* Store irqvalue for use in the interrupt thread. */
993 rt2x00dev->irqvalue[0] = reg;
994
995 /* Disable interrupts, will be enabled again in the interrupt thread. */
996 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
997 STATE_RADIO_IRQ_OFF_ISR);
998
999
1000 return IRQ_WAKE_THREAD;
1001}
1002
a9b3a9f7
ID		 1003/*
1004 * Device probe functions.
1005 */
7ab71325
BZ		 1006static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1007{
1008 /*
1009 * Read EEPROM into buffer
1010 */
cea90e55 1011 if (rt2x00_is_soc(rt2x00dev))
7ab71325 1012 rt2800pci_read_eeprom_soc(rt2x00dev);
cea90e55
GW		 1013 else if (rt2800pci_efuse_detect(rt2x00dev))
1014 rt2800pci_read_eeprom_efuse(rt2x00dev);
1015 else
1016 rt2800pci_read_eeprom_pci(rt2x00dev);
7ab71325
BZ		 1017
1018 return rt2800_validate_eeprom(rt2x00dev);
1019}
1020
b0a1edab
BZ		 1021static const struct rt2800_ops rt2800pci_rt2800_ops = {
1022 .register_read = rt2x00pci_register_read,
31a4cf1f 1023 .register_read_lock = rt2x00pci_register_read, /* same for PCI */
b0a1edab
BZ		 1024 .register_write = rt2x00pci_register_write,
1025 .register_write_lock = rt2x00pci_register_write, /* same for PCI */
1026
1027 .register_multiread = rt2x00pci_register_multiread,
1028 .register_multiwrite = rt2x00pci_register_multiwrite,
1029
1030 .regbusy_read = rt2x00pci_regbusy_read,
e3a896b9
GW		 1031
1032 .drv_init_registers = rt2800pci_init_registers,
b0a1edab
BZ		 1033};
1034
a9b3a9f7
ID		 1035static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1036{
1037 int retval;
1038
b0a1edab
BZ		 1039 rt2x00dev->priv = (void *)&rt2800pci_rt2800_ops;
1040
a9b3a9f7
ID		 1041 /*
1042 * Allocate eeprom data.
1043 */
1044 retval = rt2800pci_validate_eeprom(rt2x00dev);
1045 if (retval)
1046 return retval;
1047
38bd7b8a 1048 retval = rt2800_init_eeprom(rt2x00dev);
a9b3a9f7
ID		 1049 if (retval)
1050 return retval;
1051
1052 /*
1053 * Initialize hw specifications.
1054 */
4da2933f 1055 retval = rt2800_probe_hw_mode(rt2x00dev);
a9b3a9f7
ID		 1056 if (retval)
1057 return retval;
1058
1059 /*
1060 * This device has multiple filters for control frames
1061 * and has a separate filter for PS Poll frames.
1062 */
1063 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
1064 __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
1065
9f926fb5
HS		 1066 /*
1067 * This device has a pre tbtt interrupt and thus fetches
1068 * a new beacon directly prior to transmission.
1069 */
1070 __set_bit(DRIVER_SUPPORT_PRE_TBTT_INTERRUPT, &rt2x00dev->flags);
1071
a9b3a9f7
ID		 1072 /*
1073 * This device requires firmware.
1074 */
cea90e55 1075 if (!rt2x00_is_soc(rt2x00dev))
a9b3a9f7
ID		 1076 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
1077 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1078 __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
1079 if (!modparam_nohwcrypt)
1080 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
27df2a9c 1081 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
a9b3a9f7
ID		 1082
1083 /*
1084 * Set the rssi offset.
1085 */
1086 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1087
1088 return 0;
1089}
1090
e783619e
HS		 1091static const struct ieee80211_ops rt2800pci_mac80211_ops = {
1092 .tx = rt2x00mac_tx,
1093 .start = rt2x00mac_start,
1094 .stop = rt2x00mac_stop,
1095 .add_interface = rt2x00mac_add_interface,
1096 .remove_interface = rt2x00mac_remove_interface,
1097 .config = rt2x00mac_config,
1098 .configure_filter = rt2x00mac_configure_filter,
e783619e
HS		 1099 .set_key = rt2x00mac_set_key,
1100 .sw_scan_start = rt2x00mac_sw_scan_start,
1101 .sw_scan_complete = rt2x00mac_sw_scan_complete,
1102 .get_stats = rt2x00mac_get_stats,
1103 .get_tkip_seq = rt2800_get_tkip_seq,
1104 .set_rts_threshold = rt2800_set_rts_threshold,
1105 .bss_info_changed = rt2x00mac_bss_info_changed,
1106 .conf_tx = rt2800_conf_tx,
1107 .get_tsf = rt2800_get_tsf,
1108 .rfkill_poll = rt2x00mac_rfkill_poll,
1109 .ampdu_action = rt2800_ampdu_action,
1110};
1111
a9b3a9f7
ID		 1112static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1113 .irq_handler = rt2800pci_interrupt,
78e256c9 1114 .irq_handler_thread = rt2800pci_interrupt_thread,
a9b3a9f7
ID		 1115 .probe_hw = rt2800pci_probe_hw,
1116 .get_firmware_name = rt2800pci_get_firmware_name,
1117 .check_firmware = rt2800pci_check_firmware,
1118 .load_firmware = rt2800pci_load_firmware,
1119 .initialize = rt2x00pci_initialize,
1120 .uninitialize = rt2x00pci_uninitialize,
1121 .get_entry_state = rt2800pci_get_entry_state,
1122 .clear_entry = rt2800pci_clear_entry,
1123 .set_device_state = rt2800pci_set_device_state,
f4450616
BZ		 1124 .rfkill_poll = rt2800_rfkill_poll,
1125 .link_stats = rt2800_link_stats,
1126 .reset_tuner = rt2800_reset_tuner,
1127 .link_tuner = rt2800_link_tuner,
a9b3a9f7 1128 .write_tx_desc = rt2800pci_write_tx_desc,
76dd5ddf 1129 .write_tx_data = rt2800pci_write_tx_data,
f0194b2d 1130 .write_beacon = rt2800_write_beacon,
a9b3a9f7
ID		 1131 .kick_tx_queue = rt2800pci_kick_tx_queue,
1132 .kill_tx_queue = rt2800pci_kill_tx_queue,
1133 .fill_rxdone = rt2800pci_fill_rxdone,
f4450616
BZ		 1134 .config_shared_key = rt2800_config_shared_key,
1135 .config_pairwise_key = rt2800_config_pairwise_key,
1136 .config_filter = rt2800_config_filter,
1137 .config_intf = rt2800_config_intf,
1138 .config_erp = rt2800_config_erp,
1139 .config_ant = rt2800_config_ant,
1140 .config = rt2800_config,
a9b3a9f7
ID		 1141};
1142
1143static const struct data_queue_desc rt2800pci_queue_rx = {
1144 .entry_num = RX_ENTRIES,
1145 .data_size = AGGREGATION_SIZE,
1146 .desc_size = RXD_DESC_SIZE,
1147 .priv_size = sizeof(struct queue_entry_priv_pci),
1148};
1149
1150static const struct data_queue_desc rt2800pci_queue_tx = {
1151 .entry_num = TX_ENTRIES,
1152 .data_size = AGGREGATION_SIZE,
1153 .desc_size = TXD_DESC_SIZE,
1154 .priv_size = sizeof(struct queue_entry_priv_pci),
1155};
1156
1157static const struct data_queue_desc rt2800pci_queue_bcn = {
1158 .entry_num = 8 * BEACON_ENTRIES,
1159 .data_size = 0, /* No DMA required for beacons */
1160 .desc_size = TXWI_DESC_SIZE,
1161 .priv_size = sizeof(struct queue_entry_priv_pci),
1162};
1163
1164static const struct rt2x00_ops rt2800pci_ops = {
04d0362e
GW		 1165 .name = KBUILD_MODNAME,
1166 .max_sta_intf = 1,
1167 .max_ap_intf = 8,
1168 .eeprom_size = EEPROM_SIZE,
1169 .rf_size = RF_SIZE,
1170 .tx_queues = NUM_TX_QUEUES,
e6218cc4 1171 .extra_tx_headroom = TXWI_DESC_SIZE,
04d0362e
GW		 1172 .rx = &rt2800pci_queue_rx,
1173 .tx = &rt2800pci_queue_tx,
1174 .bcn = &rt2800pci_queue_bcn,
1175 .lib = &rt2800pci_rt2x00_ops,
e783619e 1176 .hw = &rt2800pci_mac80211_ops,
a9b3a9f7 1177#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 1178 .debugfs = &rt2800_rt2x00debug,
a9b3a9f7
ID		 1179#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1180};
1181
1182/*
1183 * RT2800pci module information.
1184 */
d6e36ec1 1185#ifdef CONFIG_RT2800PCI_PCI
a3aa1884 1186static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
de1ebdce
GW		 1187 { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
1188 { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
1189 { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
1190 { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
a9b3a9f7
ID		 1191 { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
1192 { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
1193 { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
1194 { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
1195 { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
1196 { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
1197 { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
de1ebdce
GW		 1198 { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
1199#ifdef CONFIG_RT2800PCI_RT30XX
a9b3a9f7
ID		 1200 { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
1201 { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
1202 { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
de1ebdce
GW		 1203 { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
1204#endif
1205#ifdef CONFIG_RT2800PCI_RT35XX
1206 { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
1207 { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
a9b3a9f7
ID		 1208 { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
1209 { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
6424bf70 1210 { PCI_DEVICE(0x1814, 0x3593), PCI_DEVICE_DATA(&rt2800pci_ops) },
de1ebdce 1211#endif
a9b3a9f7
ID		 1212 { 0, }
1213};
d6e36ec1 1214#endif /* CONFIG_RT2800PCI_PCI */
a9b3a9f7
ID		 1215
1216MODULE_AUTHOR(DRV_PROJECT);
1217MODULE_VERSION(DRV_VERSION);
1218MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1219MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1220#ifdef CONFIG_RT2800PCI_PCI
1221MODULE_FIRMWARE(FIRMWARE_RT2860);
1222MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1223#endif /* CONFIG_RT2800PCI_PCI */
1224MODULE_LICENSE("GPL");
1225
00e23ce2 1226#ifdef CONFIG_RT2800PCI_SOC
714fa663
GW		 1227static int rt2800soc_probe(struct platform_device *pdev)
1228{
6e93d719 1229 return rt2x00soc_probe(pdev, &rt2800pci_ops);
714fa663 1230}
a9b3a9f7
ID		 1231
1232static struct platform_driver rt2800soc_driver = {
1233 .driver = {
1234 .name = "rt2800_wmac",
1235 .owner = THIS_MODULE,
1236 .mod_name = KBUILD_MODNAME,
1237 },
714fa663 1238 .probe = rt2800soc_probe,
a9b3a9f7
ID		 1239 .remove = __devexit_p(rt2x00soc_remove),
1240 .suspend = rt2x00soc_suspend,
1241 .resume = rt2x00soc_resume,
1242};
00e23ce2 1243#endif /* CONFIG_RT2800PCI_SOC */
a9b3a9f7
ID		 1244
1245#ifdef CONFIG_RT2800PCI_PCI
1246static struct pci_driver rt2800pci_driver = {
1247 .name = KBUILD_MODNAME,
1248 .id_table = rt2800pci_device_table,
1249 .probe = rt2x00pci_probe,
1250 .remove = __devexit_p(rt2x00pci_remove),
1251 .suspend = rt2x00pci_suspend,
1252 .resume = rt2x00pci_resume,
1253};
1254#endif /* CONFIG_RT2800PCI_PCI */
1255
1256static int __init rt2800pci_init(void)
1257{
1258 int ret = 0;
1259
00e23ce2 1260#ifdef CONFIG_RT2800PCI_SOC
a9b3a9f7
ID		 1261 ret = platform_driver_register(&rt2800soc_driver);
1262 if (ret)
1263 return ret;
1264#endif
1265#ifdef CONFIG_RT2800PCI_PCI
1266 ret = pci_register_driver(&rt2800pci_driver);
1267 if (ret) {
00e23ce2 1268#ifdef CONFIG_RT2800PCI_SOC
a9b3a9f7
ID		 1269 platform_driver_unregister(&rt2800soc_driver);
1270#endif
1271 return ret;
1272 }
1273#endif
1274
1275 return ret;
1276}
1277
1278static void __exit rt2800pci_exit(void)
1279{
1280#ifdef CONFIG_RT2800PCI_PCI
1281 pci_unregister_driver(&rt2800pci_driver);
1282#endif
00e23ce2 1283#ifdef CONFIG_RT2800PCI_SOC
a9b3a9f7
ID		 1284 platform_driver_unregister(&rt2800soc_driver);
1285#endif
1286}
1287
1288module_init(rt2800pci_init);
1289module_exit(rt2800pci_exit);
Linux kernel - Deliverables
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