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rt2x00: Properly identify rt2800usb devices.
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2800pci.c
CommitLineData
a9b3a9f7 1/*
96481b20 2 Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14
GW		 3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
a9b3a9f7
ID		 10 <http://rt2x00.serialmonkey.com>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 */
27
28/*
29 Module: rt2800pci
30 Abstract: rt2800pci device specific routines.
31 Supported chipsets: RT2800E & RT2800ED.
32 */
33
a9b3a9f7
ID		 34#include <linux/delay.h>
35#include <linux/etherdevice.h>
36#include <linux/init.h>
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/pci.h>
40#include <linux/platform_device.h>
41#include <linux/eeprom_93cx6.h>
42
43#include "rt2x00.h"
44#include "rt2x00pci.h"
45#include "rt2x00soc.h"
7ef5cc92 46#include "rt2800lib.h"
b54f78a8 47#include "rt2800.h"
a9b3a9f7
ID		 48#include "rt2800pci.h"
49
a9b3a9f7
ID		 50/*
51 * Allow hardware encryption to be disabled.
52 */
04f1e34d 53static int modparam_nohwcrypt = 0;
a9b3a9f7
ID		 54module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
55MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
56
a9b3a9f7
ID		 57static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
58{
59 unsigned int i;
60 u32 reg;
61
f18d4463
LC		 62 /*
63 * SOC devices don't support MCU requests.
64 */
65 if (rt2x00_is_soc(rt2x00dev))
66 return;
67
a9b3a9f7 68 for (i = 0; i < 200; i++) {
9a819996 69 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
a9b3a9f7
ID		 70
71 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
72 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
73 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
74 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
75 break;
76
77 udelay(REGISTER_BUSY_DELAY);
78 }
79
80 if (i == 200)
81 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
82
9a819996
HS		 83 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
84 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
a9b3a9f7
ID		 85}
86
72c7296e 87#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
a9b3a9f7
ID		 88static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
89{
ef8397cf 90 void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
a9b3a9f7
ID		 91
92 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
ef8397cf
GW		 93
94 iounmap(base_addr);
a9b3a9f7
ID		 95}
96#else
97static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
98{
99}
72c7296e 100#endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
a9b3a9f7 101
72c7296e 102#ifdef CONFIG_PCI
a9b3a9f7
ID		 103static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
104{
105 struct rt2x00_dev *rt2x00dev = eeprom->data;
106 u32 reg;
107
9a819996 108 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 109
110 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
111 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
112 eeprom->reg_data_clock =
113 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
114 eeprom->reg_chip_select =
115 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
116}
117
118static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
119{
120 struct rt2x00_dev *rt2x00dev = eeprom->data;
121 u32 reg = 0;
122
123 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
124 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
125 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
126 !!eeprom->reg_data_clock);
127 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
128 !!eeprom->reg_chip_select);
129
9a819996 130 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
a9b3a9f7
ID		 131}
132
133static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
134{
135 struct eeprom_93cx6 eeprom;
136 u32 reg;
137
9a819996 138 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 139
140 eeprom.data = rt2x00dev;
141 eeprom.register_read = rt2800pci_eepromregister_read;
142 eeprom.register_write = rt2800pci_eepromregister_write;
20f8b139
GW		 143 switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
144 {
145 case 0:
146 eeprom.width = PCI_EEPROM_WIDTH_93C46;
147 break;
148 case 1:
149 eeprom.width = PCI_EEPROM_WIDTH_93C66;
150 break;
151 default:
152 eeprom.width = PCI_EEPROM_WIDTH_93C86;
153 break;
154 }
a9b3a9f7
ID		 155 eeprom.reg_data_in = 0;
156 eeprom.reg_data_out = 0;
157 eeprom.reg_data_clock = 0;
158 eeprom.reg_chip_select = 0;
159
160 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
161 EEPROM_SIZE / sizeof(u16));
162}
163
a6598682
GW		 164static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
165{
30e84034 166 return rt2800_efuse_detect(rt2x00dev);
a9b3a9f7
ID		 167}
168
30e84034 169static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 170{
30e84034 171 rt2800_read_eeprom_efuse(rt2x00dev);
a9b3a9f7
ID		 172}
173#else
174static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
175{
176}
177
a6598682
GW		 178static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
179{
180 return 0;
181}
182
a9b3a9f7
ID		 183static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
184{
185}
72c7296e 186#endif /* CONFIG_PCI */
a9b3a9f7 187
5450b7e2
ID		 188/*
189 * Queue handlers.
190 */
191static void rt2800pci_start_queue(struct data_queue *queue)
192{
193 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
194 u32 reg;
195
196 switch (queue->qid) {
197 case QID_RX:
9a819996 198 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5450b7e2 199 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
9a819996 200 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5450b7e2
ID		 201 break;
202 case QID_BEACON:
a9d61e9e
HS		 203 /*
204 * Allow beacon tasklets to be scheduled for periodic
205 * beacon updates.
206 */
207 tasklet_enable(&rt2x00dev->tbtt_tasklet);
208 tasklet_enable(&rt2x00dev->pretbtt_tasklet);
209
9a819996 210 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
5450b7e2
ID		 211 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
212 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
213 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
9a819996 214 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
69cf36a4 215
9a819996 216 rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, &reg);
69cf36a4 217 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 1);
9a819996 218 rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
5450b7e2
ID		 219 break;
220 default:
221 break;
222 };
223}
224
225static void rt2800pci_kick_queue(struct data_queue *queue)
226{
227 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
228 struct queue_entry *entry;
229
230 switch (queue->qid) {
f615e9a3
ID		 231 case QID_AC_VO:
232 case QID_AC_VI:
5450b7e2
ID		 233 case QID_AC_BE:
234 case QID_AC_BK:
5450b7e2 235 entry = rt2x00queue_get_entry(queue, Q_INDEX);
9a819996
HS		 236 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(queue->qid),
237 entry->entry_idx);
5450b7e2
ID		 238 break;
239 case QID_MGMT:
240 entry = rt2x00queue_get_entry(queue, Q_INDEX);
9a819996
HS		 241 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(5),
242 entry->entry_idx);
5450b7e2
ID		 243 break;
244 default:
245 break;
246 }
247}
248
249static void rt2800pci_stop_queue(struct data_queue *queue)
250{
251 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
252 u32 reg;
253
254 switch (queue->qid) {
255 case QID_RX:
9a819996 256 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5450b7e2 257 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
9a819996 258 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5450b7e2
ID		 259 break;
260 case QID_BEACON:
9a819996 261 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
5450b7e2
ID		 262 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
263 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
264 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
9a819996 265 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
69cf36a4 266
9a819996 267 rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, &reg);
69cf36a4 268 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 0);
9a819996 269 rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
a9d61e9e
HS		 270
271 /*
272 * Wait for tbtt tasklets to finish.
273 */
274 tasklet_disable(&rt2x00dev->tbtt_tasklet);
275 tasklet_disable(&rt2x00dev->pretbtt_tasklet);
5450b7e2
ID		 276 break;
277 default:
278 break;
279 }
280}
281
a9b3a9f7
ID		 282/*
283 * Firmware functions
284 */
285static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
286{
287 return FIRMWARE_RT2860;
288}
289
f31c9a8c 290static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
a9b3a9f7
ID		 291 const u8 *data, const size_t len)
292{
a9b3a9f7
ID		 293 u32 reg;
294
a9b3a9f7
ID		 295 /*
296 * enable Host program ram write selection
297 */
298 reg = 0;
299 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
9a819996 300 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
a9b3a9f7
ID		 301
302 /*
303 * Write firmware to device.
304 */
d4c838ef
ID		 305 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
306 data, len);
a9b3a9f7 307
9a819996
HS		 308 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
309 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
a9b3a9f7 310
9a819996
HS		 311 rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
312 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
a9b3a9f7
ID		 313
314 return 0;
315}
316
317/*
318 * Initialization functions.
319 */
320static bool rt2800pci_get_entry_state(struct queue_entry *entry)
321{
322 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
323 u32 word;
324
325 if (entry->queue->qid == QID_RX) {
326 rt2x00_desc_read(entry_priv->desc, 1, &word);
327
328 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
329 } else {
330 rt2x00_desc_read(entry_priv->desc, 1, &word);
331
332 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
333 }
334}
335
336static void rt2800pci_clear_entry(struct queue_entry *entry)
337{
338 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
339 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95192339 340 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
a9b3a9f7
ID		 341 u32 word;
342
343 if (entry->queue->qid == QID_RX) {
344 rt2x00_desc_read(entry_priv->desc, 0, &word);
345 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
346 rt2x00_desc_write(entry_priv->desc, 0, word);
347
348 rt2x00_desc_read(entry_priv->desc, 1, &word);
349 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
350 rt2x00_desc_write(entry_priv->desc, 1, word);
95192339
HS		 351
352 /*
353 * Set RX IDX in register to inform hardware that we have
354 * handled this entry and it is available for reuse again.
355 */
9a819996 356 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
95192339 357 entry->entry_idx);
a9b3a9f7
ID		 358 } else {
359 rt2x00_desc_read(entry_priv->desc, 1, &word);
360 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
361 rt2x00_desc_write(entry_priv->desc, 1, word);
362 }
363}
364
365static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
366{
367 struct queue_entry_priv_pci *entry_priv;
368 u32 reg;
369
a9b3a9f7
ID		 370 /*
371 * Initialize registers.
372 */
373 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
9a819996
HS		 374 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
375 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0,
376 rt2x00dev->tx[0].limit);
377 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
378 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX0, 0);
a9b3a9f7
ID		 379
380 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
9a819996
HS		 381 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
382 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1,
383 rt2x00dev->tx[1].limit);
384 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
385 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX1, 0);
a9b3a9f7
ID		 386
387 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
9a819996
HS		 388 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
389 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2,
390 rt2x00dev->tx[2].limit);
391 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
392 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX2, 0);
a9b3a9f7
ID		 393
394 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
9a819996
HS		 395 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
396 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3,
397 rt2x00dev->tx[3].limit);
398 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
399 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX3, 0);
a9b3a9f7
ID		 400
401 entry_priv = rt2x00dev->rx->entries[0].priv_data;
9a819996
HS		 402 rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
403 rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT,
404 rt2x00dev->rx[0].limit);
405 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
406 rt2x00dev->rx[0].limit - 1);
407 rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0);
a9b3a9f7
ID		 408
409 /*
410 * Enable global DMA configuration
411 */
9a819996 412 rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 413 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
414 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
415 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9a819996 416 rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7 417
9a819996 418 rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
a9b3a9f7
ID		 419
420 return 0;
421}
422
a9b3a9f7
ID		 423/*
424 * Device state switch handlers.
425 */
a9b3a9f7
ID		 426static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
427 enum dev_state state)
428{
b550911a 429 int mask = (state == STATE_RADIO_IRQ_ON);
a9b3a9f7 430 u32 reg;
a9d61e9e 431 unsigned long flags;
a9b3a9f7
ID		 432
433 /*
434 * When interrupts are being enabled, the interrupt registers
435 * should clear the register to assure a clean state.
436 */
437 if (state == STATE_RADIO_IRQ_ON) {
9a819996
HS		 438 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
439 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
c8e15a1e 440
a9d61e9e
HS		 441 /*
442 * Enable tasklets. The beacon related tasklets are
443 * enabled when the beacon queue is started.
444 */
c8e15a1e 445 tasklet_enable(&rt2x00dev->txstatus_tasklet);
a9d61e9e
HS		 446 tasklet_enable(&rt2x00dev->rxdone_tasklet);
447 tasklet_enable(&rt2x00dev->autowake_tasklet);
448 }
a9b3a9f7 449
a9d61e9e 450 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
9a819996 451 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
93149cf8
HS		 452 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, 0);
453 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, 0);
a9b3a9f7 454 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
93149cf8
HS		 455 rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, 0);
456 rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, 0);
457 rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, 0);
458 rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, 0);
459 rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, 0);
460 rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, 0);
461 rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, 0);
462 rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, 0);
a9b3a9f7
ID		 463 rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
464 rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
465 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
466 rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
93149cf8
HS		 467 rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, 0);
468 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, 0);
469 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, 0);
9a819996 470 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
a9d61e9e
HS		 471 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
472
473 if (state == STATE_RADIO_IRQ_OFF) {
474 /*
475 * Ensure that all tasklets are finished before
476 * disabling the interrupts.
477 */
478 tasklet_disable(&rt2x00dev->txstatus_tasklet);
479 tasklet_disable(&rt2x00dev->rxdone_tasklet);
480 tasklet_disable(&rt2x00dev->autowake_tasklet);
481 }
a9b3a9f7
ID		 482}
483
e3a896b9
GW		 484static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
485{
486 u32 reg;
487
488 /*
489 * Reset DMA indexes
490 */
9a819996 491 rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
e3a896b9
GW		 492 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
493 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
494 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
495 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
496 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
497 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
498 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
9a819996 499 rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
e3a896b9 500
9a819996
HS		 501 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
502 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
e3a896b9 503
872834df
GW		 504 if (rt2x00_is_pcie(rt2x00dev) &&
505 (rt2x00_rt(rt2x00dev, RT3572) ||
506 rt2x00_rt(rt2x00dev, RT5390))) {
9a819996 507 rt2x00pci_register_read(rt2x00dev, AUX_CTRL, &reg);
adde5882
GJ		 508 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
509 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
9a819996 510 rt2x00pci_register_write(rt2x00dev, AUX_CTRL, reg);
adde5882 511 }
60687ba7 512
9a819996 513 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
e3a896b9 514
9a819996 515 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
e3a896b9
GW		 516 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
517 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
9a819996 518 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
e3a896b9 519
9a819996 520 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
e3a896b9
GW		 521
522 return 0;
523}
524
a9b3a9f7
ID		 525static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
526{
67a4c1e2 527 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
b9a07ae9 528 rt2800pci_init_queues(rt2x00dev)))
a9b3a9f7
ID		 529 return -EIO;
530
b9a07ae9 531 return rt2800_enable_radio(rt2x00dev);
a9b3a9f7
ID		 532}
533
534static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
535{
7f6e144f
RJH		 536 if (rt2x00_is_soc(rt2x00dev)) {
537 rt2800_disable_radio(rt2x00dev);
9a819996
HS		 538 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
539 rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
7f6e144f 540 }
a9b3a9f7
ID		 541}
542
543static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
544 enum dev_state state)
545{
a9b3a9f7 546 if (state == STATE_AWAKE) {
7f6e144f 547 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0x02);
a9b3a9f7 548 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
7f6e144f 549 } else if (state == STATE_SLEEP) {
9a819996
HS		 550 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
551 0xffffffff);
552 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID,
553 0xffffffff);
7f6e144f 554 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0x01, 0xff, 0x01);
a9b3a9f7
ID		 555 }
556
557 return 0;
558}
559
560static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
561 enum dev_state state)
562{
563 int retval = 0;
564
565 switch (state) {
566 case STATE_RADIO_ON:
567 /*
568 * Before the radio can be enabled, the device first has
569 * to be woken up. After that it needs a bit of time
570 * to be fully awake and then the radio can be enabled.
571 */
572 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
573 msleep(1);
574 retval = rt2800pci_enable_radio(rt2x00dev);
575 break;
576 case STATE_RADIO_OFF:
577 /*
578 * After the radio has been disabled, the device should
579 * be put to sleep for powersaving.
580 */
581 rt2800pci_disable_radio(rt2x00dev);
582 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
583 break;
a9b3a9f7
ID		 584 case STATE_RADIO_IRQ_ON:
585 case STATE_RADIO_IRQ_OFF:
586 rt2800pci_toggle_irq(rt2x00dev, state);
587 break;
588 case STATE_DEEP_SLEEP:
589 case STATE_SLEEP:
590 case STATE_STANDBY:
591 case STATE_AWAKE:
592 retval = rt2800pci_set_state(rt2x00dev, state);
593 break;
594 default:
595 retval = -ENOTSUPP;
596 break;
597 }
598
599 if (unlikely(retval))
600 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
601 state, retval);
602
603 return retval;
604}
605
606/*
607 * TX descriptor initialization
608 */
0c5879bc 609static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)
a9b3a9f7 610{
0c5879bc 611 return (__le32 *) entry->skb->data;
745b1ae3
HS		 612}
613
93331458 614static void rt2800pci_write_tx_desc(struct queue_entry *entry,
745b1ae3
HS		 615 struct txentry_desc *txdesc)
616{
93331458
ID		 617 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
618 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
85b7a8b3 619 __le32 *txd = entry_priv->desc;
745b1ae3
HS		 620 u32 word;
621
a9b3a9f7
ID		 622 /*
623 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
624 * must contains a TXWI structure + 802.11 header + padding + 802.11
625 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
626 * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
627 * data. It means that LAST_SEC0 is always 0.
628 */
629
630 /*
631 * Initialize TX descriptor
632 */
633 rt2x00_desc_read(txd, 0, &word);
634 rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
635 rt2x00_desc_write(txd, 0, word);
636
637 rt2x00_desc_read(txd, 1, &word);
93331458 638 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);
a9b3a9f7
ID		 639 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
640 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
641 rt2x00_set_field32(&word, TXD_W1_BURST,
642 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
85b7a8b3 643 rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
a9b3a9f7
ID		 644 rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
645 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
646 rt2x00_desc_write(txd, 1, word);
647
648 rt2x00_desc_read(txd, 2, &word);
649 rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
85b7a8b3 650 skbdesc->skb_dma + TXWI_DESC_SIZE);
a9b3a9f7
ID		 651 rt2x00_desc_write(txd, 2, word);
652
653 rt2x00_desc_read(txd, 3, &word);
654 rt2x00_set_field32(&word, TXD_W3_WIV,
655 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
656 rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
657 rt2x00_desc_write(txd, 3, word);
85b7a8b3
GW		 658
659 /*
660 * Register descriptor details in skb frame descriptor.
661 */
662 skbdesc->desc = txd;
663 skbdesc->desc_len = TXD_DESC_SIZE;
a9b3a9f7
ID		 664}
665
a9b3a9f7
ID		 666/*
667 * RX control handlers
668 */
669static void rt2800pci_fill_rxdone(struct queue_entry *entry,
670 struct rxdone_entry_desc *rxdesc)
671{
a9b3a9f7
ID		 672 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
673 __le32 *rxd = entry_priv->desc;
2de64dd2
GW		 674 u32 word;
675
676 rt2x00_desc_read(rxd, 3, &word);
677
678 if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
a9b3a9f7
ID		 679 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
680
78b8f3b0
GW		 681 /*
682 * Unfortunately we don't know the cipher type used during
683 * decryption. This prevents us from correct providing
684 * correct statistics through debugfs.
685 */
2de64dd2 686 rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
a9b3a9f7 687
2de64dd2 688 if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
a9b3a9f7
ID		 689 /*
690 * Hardware has stripped IV/EIV data from 802.11 frame during
691 * decryption. Unfortunately the descriptor doesn't contain
692 * any fields with the EIV/IV data either, so they can't
693 * be restored by rt2x00lib.
694 */
695 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
696
a45f369d
GW		 697 /*
698 * The hardware has already checked the Michael Mic and has
699 * stripped it from the frame. Signal this to mac80211.
700 */
701 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
702
a9b3a9f7
ID		 703 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
704 rxdesc->flags |= RX_FLAG_DECRYPTED;
705 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
706 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
707 }
708
2de64dd2 709 if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
a9b3a9f7
ID		 710 rxdesc->dev_flags |= RXDONE_MY_BSS;
711
2de64dd2 712 if (rt2x00_get_field32(word, RXD_W3_L2PAD))
a9b3a9f7 713 rxdesc->dev_flags |= RXDONE_L2PAD;
a9b3a9f7 714
a9b3a9f7 715 /*
2de64dd2 716 * Process the RXWI structure that is at the start of the buffer.
a9b3a9f7 717 */
74861922 718 rt2800_process_rxwi(entry, rxdesc);
a9b3a9f7
ID		 719}
720
721/*
722 * Interrupt functions.
723 */
4d66edc8
GW		 724static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
725{
726 struct ieee80211_conf conf = { .flags = 0 };
727 struct rt2x00lib_conf libconf = { .conf = &conf };
728
729 rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
730}
731
2e7798b7 732static bool rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
96c3da7d
HS		 733{
734 struct data_queue *queue;
735 struct queue_entry *entry;
736 u32 status;
737 u8 qid;
2e7798b7 738 int max_tx_done = 16;
96c3da7d 739
c4d63244 740 while (kfifo_get(&rt2x00dev->txstatus_fifo, &status)) {
12eec2cc 741 qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
87443e87 742 if (unlikely(qid >= QID_RX)) {
96c3da7d
HS		 743 /*
744 * Unknown queue, this shouldn't happen. Just drop
745 * this tx status.
746 */
747 WARNING(rt2x00dev, "Got TX status report with "
094a1d92 748 "unexpected pid %u, dropping\n", qid);
96c3da7d
HS		 749 break;
750 }
751
11f818e0 752 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
96c3da7d
HS		 753 if (unlikely(queue == NULL)) {
754 /*
755 * The queue is NULL, this shouldn't happen. Stop
756 * processing here and drop the tx status
757 */
758 WARNING(rt2x00dev, "Got TX status for an unavailable "
094a1d92 759 "queue %u, dropping\n", qid);
96c3da7d
HS		 760 break;
761 }
762
87443e87 763 if (unlikely(rt2x00queue_empty(queue))) {
96c3da7d
HS		 764 /*
765 * The queue is empty. Stop processing here
766 * and drop the tx status.
767 */
768 WARNING(rt2x00dev, "Got TX status for an empty "
094a1d92 769 "queue %u, dropping\n", qid);
96c3da7d
HS		 770 break;
771 }
772
773 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
774 rt2800_txdone_entry(entry, status);
2e7798b7
HS		 775
776 if (--max_tx_done == 0)
777 break;
96c3da7d 778 }
2e7798b7
HS		 779
780 return !max_tx_done;
96c3da7d
HS		 781}
782
7a5a681a
HS		 783static inline void rt2800pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
784 struct rt2x00_field32 irq_field)
a9b3a9f7 785{
a9d61e9e 786 u32 reg;
a9b3a9f7
ID		 787
788 /*
a9d61e9e
HS		 789 * Enable a single interrupt. The interrupt mask register
790 * access needs locking.
9f926fb5 791 */
0aa13b2e 792 spin_lock_irq(&rt2x00dev->irqmask_lock);
9a819996 793 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
a9d61e9e 794 rt2x00_set_field32(&reg, irq_field, 1);
9a819996 795 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
0aa13b2e 796 spin_unlock_irq(&rt2x00dev->irqmask_lock);
a9d61e9e 797}
9f926fb5 798
a9d61e9e
HS		 799static void rt2800pci_txstatus_tasklet(unsigned long data)
800{
2e7798b7
HS		 801 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
802 if (rt2800pci_txdone(rt2x00dev))
803 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
9f926fb5
HS		 804
805 /*
a9d61e9e
HS		 806 * No need to enable the tx status interrupt here as we always
807 * leave it enabled to minimize the possibility of a tx status
808 * register overflow. See comment in interrupt handler.
a9b3a9f7 809 */
a9d61e9e 810}
a9b3a9f7 811
a9d61e9e
HS		 812static void rt2800pci_pretbtt_tasklet(unsigned long data)
813{
814 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
815 rt2x00lib_pretbtt(rt2x00dev);
816 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_PRE_TBTT);
817}
4d66edc8 818
a9d61e9e
HS		 819static void rt2800pci_tbtt_tasklet(unsigned long data)
820{
821 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
822 rt2x00lib_beacondone(rt2x00dev);
823 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TBTT);
824}
78e256c9 825
a9d61e9e
HS		 826static void rt2800pci_rxdone_tasklet(unsigned long data)
827{
828 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
16638937
HS		 829 if (rt2x00pci_rxdone(rt2x00dev))
830 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
831 else
832 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RX_DONE);
a9d61e9e
HS		 833}
834
835static void rt2800pci_autowake_tasklet(unsigned long data)
836{
837 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
838 rt2800pci_wakeup(rt2x00dev);
839 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_AUTO_WAKEUP);
a9b3a9f7
ID		 840}
841
96c3da7d
HS		 842static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
843{
844 u32 status;
845 int i;
846
847 /*
848 * The TX_FIFO_STATUS interrupt needs special care. We should
849 * read TX_STA_FIFO but we should do it immediately as otherwise
850 * the register can overflow and we would lose status reports.
851 *
852 * Hence, read the TX_STA_FIFO register and copy all tx status
853 * reports into a kernel FIFO which is handled in the txstatus
854 * tasklet. We use a tasklet to process the tx status reports
855 * because we can schedule the tasklet multiple times (when the
856 * interrupt fires again during tx status processing).
857 *
858 * Furthermore we don't disable the TX_FIFO_STATUS
859 * interrupt here but leave it enabled so that the TX_STA_FIFO
3736fe58 860 * can also be read while the tx status tasklet gets executed.
96c3da7d
HS		 861 *
862 * Since we have only one producer and one consumer we don't
863 * need to lock the kfifo.
864 */
efd2f271 865 for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
9a819996 866 rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &status);
96c3da7d
HS		 867
868 if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
869 break;
870
c4d63244 871 if (!kfifo_put(&rt2x00dev->txstatus_fifo, &status)) {
96c3da7d
HS		 872 WARNING(rt2x00dev, "TX status FIFO overrun,"
873 "drop tx status report.\n");
874 break;
875 }
876 }
877
878 /* Schedule the tasklet for processing the tx status. */
879 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
880}
881
78e256c9
HS		 882static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
883{
884 struct rt2x00_dev *rt2x00dev = dev_instance;
a9d61e9e 885 u32 reg, mask;
78e256c9
HS		 886
887 /* Read status and ACK all interrupts */
9a819996
HS		 888 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
889 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
78e256c9
HS		 890
891 if (!reg)
892 return IRQ_NONE;
893
894 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
895 return IRQ_HANDLED;
896
a9d61e9e
HS		 897 /*
898 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
899 * for interrupts and interrupt masks we can just use the value of
900 * INT_SOURCE_CSR to create the interrupt mask.
901 */
902 mask = ~reg;
78e256c9 903
a9d61e9e
HS		 904 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) {
905 rt2800pci_txstatus_interrupt(rt2x00dev);
96c3da7d 906 /*
a9d61e9e 907 * Never disable the TX_FIFO_STATUS interrupt.
96c3da7d 908 */
a9d61e9e
HS		 909 rt2x00_set_field32(&mask, INT_MASK_CSR_TX_FIFO_STATUS, 1);
910 }
96c3da7d 911
a9d61e9e
HS		 912 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
913 tasklet_hi_schedule(&rt2x00dev->pretbtt_tasklet);
78e256c9 914
a9d61e9e
HS		 915 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
916 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
96c3da7d 917
a9d61e9e
HS		 918 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
919 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
78e256c9 920
a9d61e9e
HS		 921 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
922 tasklet_schedule(&rt2x00dev->autowake_tasklet);
923
924 /*
925 * Disable all interrupts for which a tasklet was scheduled right now,
926 * the tasklet will reenable the appropriate interrupts.
927 */
0aa13b2e 928 spin_lock(&rt2x00dev->irqmask_lock);
9a819996 929 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
a9d61e9e 930 reg &= mask;
9a819996 931 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
0aa13b2e 932 spin_unlock(&rt2x00dev->irqmask_lock);
a9d61e9e
HS		 933
934 return IRQ_HANDLED;
78e256c9
HS		 935}
936
a9b3a9f7
ID		 937/*
938 * Device probe functions.
939 */
7ab71325
BZ		 940static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
941{
942 /*
943 * Read EEPROM into buffer
944 */
cea90e55 945 if (rt2x00_is_soc(rt2x00dev))
7ab71325 946 rt2800pci_read_eeprom_soc(rt2x00dev);
cea90e55
GW		 947 else if (rt2800pci_efuse_detect(rt2x00dev))
948 rt2800pci_read_eeprom_efuse(rt2x00dev);
949 else
950 rt2800pci_read_eeprom_pci(rt2x00dev);
7ab71325
BZ		 951
952 return rt2800_validate_eeprom(rt2x00dev);
953}
954
a9b3a9f7
ID		 955static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
956{
957 int retval;
958
959 /*
960 * Allocate eeprom data.
961 */
962 retval = rt2800pci_validate_eeprom(rt2x00dev);
963 if (retval)
964 return retval;
965
38bd7b8a 966 retval = rt2800_init_eeprom(rt2x00dev);
a9b3a9f7
ID		 967 if (retval)
968 return retval;
969
970 /*
971 * Initialize hw specifications.
972 */
4da2933f 973 retval = rt2800_probe_hw_mode(rt2x00dev);
a9b3a9f7
ID		 974 if (retval)
975 return retval;
976
977 /*
978 * This device has multiple filters for control frames
979 * and has a separate filter for PS Poll frames.
980 */
7dab73b3
ID		 981 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
982 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
a9b3a9f7 983
9f926fb5
HS		 984 /*
985 * This device has a pre tbtt interrupt and thus fetches
986 * a new beacon directly prior to transmission.
987 */
7dab73b3 988 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
9f926fb5 989
a9b3a9f7
ID		 990 /*
991 * This device requires firmware.
992 */
cea90e55 993 if (!rt2x00_is_soc(rt2x00dev))
7dab73b3
ID		 994 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
995 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
996 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
997 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
998 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
a9b3a9f7 999 if (!modparam_nohwcrypt)
7dab73b3
ID		 1000 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
1001 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
1002 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
a9b3a9f7
ID		 1003
1004 /*
1005 * Set the rssi offset.
1006 */
1007 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1008
1009 return 0;
1010}
1011
e783619e
HS		 1012static const struct ieee80211_ops rt2800pci_mac80211_ops = {
1013 .tx = rt2x00mac_tx,
1014 .start = rt2x00mac_start,
1015 .stop = rt2x00mac_stop,
1016 .add_interface = rt2x00mac_add_interface,
1017 .remove_interface = rt2x00mac_remove_interface,
1018 .config = rt2x00mac_config,
1019 .configure_filter = rt2x00mac_configure_filter,
e783619e
HS		 1020 .set_key = rt2x00mac_set_key,
1021 .sw_scan_start = rt2x00mac_sw_scan_start,
1022 .sw_scan_complete = rt2x00mac_sw_scan_complete,
1023 .get_stats = rt2x00mac_get_stats,
1024 .get_tkip_seq = rt2800_get_tkip_seq,
1025 .set_rts_threshold = rt2800_set_rts_threshold,
1026 .bss_info_changed = rt2x00mac_bss_info_changed,
1027 .conf_tx = rt2800_conf_tx,
1028 .get_tsf = rt2800_get_tsf,
1029 .rfkill_poll = rt2x00mac_rfkill_poll,
1030 .ampdu_action = rt2800_ampdu_action,
f44df18c 1031 .flush = rt2x00mac_flush,
977206d7 1032 .get_survey = rt2800_get_survey,
e7dee444 1033 .get_ringparam = rt2x00mac_get_ringparam,
e783619e
HS		 1034};
1035
e796643e
ID		 1036static const struct rt2800_ops rt2800pci_rt2800_ops = {
1037 .register_read = rt2x00pci_register_read,
1038 .register_read_lock = rt2x00pci_register_read, /* same for PCI */
1039 .register_write = rt2x00pci_register_write,
1040 .register_write_lock = rt2x00pci_register_write, /* same for PCI */
1041 .register_multiread = rt2x00pci_register_multiread,
1042 .register_multiwrite = rt2x00pci_register_multiwrite,
1043 .regbusy_read = rt2x00pci_regbusy_read,
1044 .drv_write_firmware = rt2800pci_write_firmware,
1045 .drv_init_registers = rt2800pci_init_registers,
0c5879bc 1046 .drv_get_txwi = rt2800pci_get_txwi,
e796643e
ID		 1047};
1048
a9b3a9f7
ID		 1049static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1050 .irq_handler = rt2800pci_interrupt,
a9d61e9e
HS		 1051 .txstatus_tasklet = rt2800pci_txstatus_tasklet,
1052 .pretbtt_tasklet = rt2800pci_pretbtt_tasklet,
1053 .tbtt_tasklet = rt2800pci_tbtt_tasklet,
1054 .rxdone_tasklet = rt2800pci_rxdone_tasklet,
1055 .autowake_tasklet = rt2800pci_autowake_tasklet,
a9b3a9f7
ID		 1056 .probe_hw = rt2800pci_probe_hw,
1057 .get_firmware_name = rt2800pci_get_firmware_name,
f31c9a8c
ID		 1058 .check_firmware = rt2800_check_firmware,
1059 .load_firmware = rt2800_load_firmware,
a9b3a9f7
ID		 1060 .initialize = rt2x00pci_initialize,
1061 .uninitialize = rt2x00pci_uninitialize,
1062 .get_entry_state = rt2800pci_get_entry_state,
1063 .clear_entry = rt2800pci_clear_entry,
1064 .set_device_state = rt2800pci_set_device_state,
f4450616
BZ		 1065 .rfkill_poll = rt2800_rfkill_poll,
1066 .link_stats = rt2800_link_stats,
1067 .reset_tuner = rt2800_reset_tuner,
1068 .link_tuner = rt2800_link_tuner,
9e33a355 1069 .gain_calibration = rt2800_gain_calibration,
dbba306f
ID		 1070 .start_queue = rt2800pci_start_queue,
1071 .kick_queue = rt2800pci_kick_queue,
1072 .stop_queue = rt2800pci_stop_queue,
152a5992 1073 .flush_queue = rt2x00pci_flush_queue,
a9b3a9f7 1074 .write_tx_desc = rt2800pci_write_tx_desc,
0c5879bc 1075 .write_tx_data = rt2800_write_tx_data,
f0194b2d 1076 .write_beacon = rt2800_write_beacon,
69cf36a4 1077 .clear_beacon = rt2800_clear_beacon,
a9b3a9f7 1078 .fill_rxdone = rt2800pci_fill_rxdone,
f4450616
BZ		 1079 .config_shared_key = rt2800_config_shared_key,
1080 .config_pairwise_key = rt2800_config_pairwise_key,
1081 .config_filter = rt2800_config_filter,
1082 .config_intf = rt2800_config_intf,
1083 .config_erp = rt2800_config_erp,
1084 .config_ant = rt2800_config_ant,
1085 .config = rt2800_config,
a9b3a9f7
ID		 1086};
1087
1088static const struct data_queue_desc rt2800pci_queue_rx = {
efd2f271 1089 .entry_num = 128,
a9b3a9f7
ID		 1090 .data_size = AGGREGATION_SIZE,
1091 .desc_size = RXD_DESC_SIZE,
1092 .priv_size = sizeof(struct queue_entry_priv_pci),
1093};
1094
1095static const struct data_queue_desc rt2800pci_queue_tx = {
efd2f271 1096 .entry_num = 64,
a9b3a9f7
ID		 1097 .data_size = AGGREGATION_SIZE,
1098 .desc_size = TXD_DESC_SIZE,
1099 .priv_size = sizeof(struct queue_entry_priv_pci),
1100};
1101
1102static const struct data_queue_desc rt2800pci_queue_bcn = {
efd2f271 1103 .entry_num = 8,
a9b3a9f7
ID		 1104 .data_size = 0, /* No DMA required for beacons */
1105 .desc_size = TXWI_DESC_SIZE,
1106 .priv_size = sizeof(struct queue_entry_priv_pci),
1107};
1108
1109static const struct rt2x00_ops rt2800pci_ops = {
04d0362e
GW		 1110 .name = KBUILD_MODNAME,
1111 .max_sta_intf = 1,
1112 .max_ap_intf = 8,
1113 .eeprom_size = EEPROM_SIZE,
1114 .rf_size = RF_SIZE,
1115 .tx_queues = NUM_TX_QUEUES,
e6218cc4 1116 .extra_tx_headroom = TXWI_DESC_SIZE,
04d0362e
GW		 1117 .rx = &rt2800pci_queue_rx,
1118 .tx = &rt2800pci_queue_tx,
1119 .bcn = &rt2800pci_queue_bcn,
1120 .lib = &rt2800pci_rt2x00_ops,
e796643e 1121 .drv = &rt2800pci_rt2800_ops,
e783619e 1122 .hw = &rt2800pci_mac80211_ops,
a9b3a9f7 1123#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 1124 .debugfs = &rt2800_rt2x00debug,
a9b3a9f7
ID		 1125#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1126};
1127
1128/*
1129 * RT2800pci module information.
1130 */
72c7296e 1131#ifdef CONFIG_PCI
a3aa1884 1132static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
e01ae27f
GW		 1133 { PCI_DEVICE(0x1814, 0x0601) },
1134 { PCI_DEVICE(0x1814, 0x0681) },
1135 { PCI_DEVICE(0x1814, 0x0701) },
1136 { PCI_DEVICE(0x1814, 0x0781) },
1137 { PCI_DEVICE(0x1814, 0x3090) },
1138 { PCI_DEVICE(0x1814, 0x3091) },
1139 { PCI_DEVICE(0x1814, 0x3092) },
1140 { PCI_DEVICE(0x1432, 0x7708) },
1141 { PCI_DEVICE(0x1432, 0x7727) },
1142 { PCI_DEVICE(0x1432, 0x7728) },
1143 { PCI_DEVICE(0x1432, 0x7738) },
1144 { PCI_DEVICE(0x1432, 0x7748) },
1145 { PCI_DEVICE(0x1432, 0x7758) },
1146 { PCI_DEVICE(0x1432, 0x7768) },
1147 { PCI_DEVICE(0x1462, 0x891a) },
1148 { PCI_DEVICE(0x1a3b, 0x1059) },
f93bc9b3 1149#ifdef CONFIG_RT2800PCI_RT33XX
e01ae27f 1150 { PCI_DEVICE(0x1814, 0x3390) },
f93bc9b3 1151#endif
de1ebdce 1152#ifdef CONFIG_RT2800PCI_RT35XX
e01ae27f
GW		 1153 { PCI_DEVICE(0x1432, 0x7711) },
1154 { PCI_DEVICE(0x1432, 0x7722) },
1155 { PCI_DEVICE(0x1814, 0x3060) },
1156 { PCI_DEVICE(0x1814, 0x3062) },
1157 { PCI_DEVICE(0x1814, 0x3562) },
1158 { PCI_DEVICE(0x1814, 0x3592) },
1159 { PCI_DEVICE(0x1814, 0x3593) },
60687ba7
RST		 1160#endif
1161#ifdef CONFIG_RT2800PCI_RT53XX
e01ae27f 1162 { PCI_DEVICE(0x1814, 0x5390) },
71e0b38c 1163 { PCI_DEVICE(0x1814, 0x539f) },
de1ebdce 1164#endif
a9b3a9f7
ID		 1165 { 0, }
1166};
72c7296e 1167#endif /* CONFIG_PCI */
a9b3a9f7
ID		 1168
1169MODULE_AUTHOR(DRV_PROJECT);
1170MODULE_VERSION(DRV_VERSION);
1171MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1172MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
72c7296e 1173#ifdef CONFIG_PCI
a9b3a9f7
ID		 1174MODULE_FIRMWARE(FIRMWARE_RT2860);
1175MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
72c7296e 1176#endif /* CONFIG_PCI */
a9b3a9f7
ID		 1177MODULE_LICENSE("GPL");
1178
72c7296e 1179#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
714fa663
GW		 1180static int rt2800soc_probe(struct platform_device *pdev)
1181{
6e93d719 1182 return rt2x00soc_probe(pdev, &rt2800pci_ops);
714fa663 1183}
a9b3a9f7
ID		 1184
1185static struct platform_driver rt2800soc_driver = {
1186 .driver = {
1187 .name = "rt2800_wmac",
1188 .owner = THIS_MODULE,
1189 .mod_name = KBUILD_MODNAME,
1190 },
714fa663 1191 .probe = rt2800soc_probe,
a9b3a9f7
ID		 1192 .remove = __devexit_p(rt2x00soc_remove),
1193 .suspend = rt2x00soc_suspend,
1194 .resume = rt2x00soc_resume,
1195};
72c7296e 1196#endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
a9b3a9f7 1197
72c7296e 1198#ifdef CONFIG_PCI
e01ae27f
GW		 1199static int rt2800pci_probe(struct pci_dev *pci_dev,
1200 const struct pci_device_id *id)
1201{
1202 return rt2x00pci_probe(pci_dev, &rt2800pci_ops);
1203}
1204
a9b3a9f7
ID		 1205static struct pci_driver rt2800pci_driver = {
1206 .name = KBUILD_MODNAME,
1207 .id_table = rt2800pci_device_table,
e01ae27f 1208 .probe = rt2800pci_probe,
a9b3a9f7
ID		 1209 .remove = __devexit_p(rt2x00pci_remove),
1210 .suspend = rt2x00pci_suspend,
1211 .resume = rt2x00pci_resume,
1212};
72c7296e 1213#endif /* CONFIG_PCI */
a9b3a9f7
ID		 1214
1215static int __init rt2800pci_init(void)
1216{
1217 int ret = 0;
1218
72c7296e 1219#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
a9b3a9f7
ID		 1220 ret = platform_driver_register(&rt2800soc_driver);
1221 if (ret)
1222 return ret;
1223#endif
72c7296e 1224#ifdef CONFIG_PCI
a9b3a9f7
ID		 1225 ret = pci_register_driver(&rt2800pci_driver);
1226 if (ret) {
72c7296e 1227#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
a9b3a9f7
ID		 1228 platform_driver_unregister(&rt2800soc_driver);
1229#endif
1230 return ret;
1231 }
1232#endif
1233
1234 return ret;
1235}
1236
1237static void __exit rt2800pci_exit(void)
1238{
72c7296e 1239#ifdef CONFIG_PCI
a9b3a9f7
ID		 1240 pci_unregister_driver(&rt2800pci_driver);
1241#endif
72c7296e 1242#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
a9b3a9f7
ID		 1243 platform_driver_unregister(&rt2800soc_driver);
1244#endif
1245}
1246
1247module_init(rt2800pci_init);
1248module_exit(rt2800pci_exit);
Linux kernel - Deliverables
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