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rt2x00: Disable txstatus tasklet by default
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2800pci.c
CommitLineData
a9b3a9f7 1/*
96481b20 2 Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14
GW		 3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
a9b3a9f7
ID		 10 <http://rt2x00.serialmonkey.com>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 */
27
28/*
29 Module: rt2800pci
30 Abstract: rt2800pci device specific routines.
31 Supported chipsets: RT2800E & RT2800ED.
32 */
33
a9b3a9f7
ID		 34#include <linux/delay.h>
35#include <linux/etherdevice.h>
36#include <linux/init.h>
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/pci.h>
40#include <linux/platform_device.h>
41#include <linux/eeprom_93cx6.h>
42
43#include "rt2x00.h"
44#include "rt2x00pci.h"
45#include "rt2x00soc.h"
7ef5cc92 46#include "rt2800lib.h"
b54f78a8 47#include "rt2800.h"
a9b3a9f7
ID		 48#include "rt2800pci.h"
49
a9b3a9f7
ID		 50/*
51 * Allow hardware encryption to be disabled.
52 */
04f1e34d 53static int modparam_nohwcrypt = 0;
a9b3a9f7
ID		 54module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
55MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
56
a9b3a9f7
ID		 57static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
58{
59 unsigned int i;
60 u32 reg;
61
f18d4463
LC		 62 /*
63 * SOC devices don't support MCU requests.
64 */
65 if (rt2x00_is_soc(rt2x00dev))
66 return;
67
a9b3a9f7 68 for (i = 0; i < 200; i++) {
9ca21eb7 69 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
a9b3a9f7
ID		 70
71 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
72 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
73 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
74 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
75 break;
76
77 udelay(REGISTER_BUSY_DELAY);
78 }
79
80 if (i == 200)
81 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
82
9ca21eb7
BZ		 83 rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
84 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
a9b3a9f7
ID		 85}
86
72c7296e 87#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
a9b3a9f7
ID		 88static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
89{
ef8397cf 90 void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
a9b3a9f7
ID		 91
92 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
ef8397cf
GW		 93
94 iounmap(base_addr);
a9b3a9f7
ID		 95}
96#else
97static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
98{
99}
72c7296e 100#endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
a9b3a9f7 101
72c7296e 102#ifdef CONFIG_PCI
a9b3a9f7
ID		 103static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
104{
105 struct rt2x00_dev *rt2x00dev = eeprom->data;
106 u32 reg;
107
9ca21eb7 108 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 109
110 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
111 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
112 eeprom->reg_data_clock =
113 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
114 eeprom->reg_chip_select =
115 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
116}
117
118static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
119{
120 struct rt2x00_dev *rt2x00dev = eeprom->data;
121 u32 reg = 0;
122
123 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
124 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
125 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
126 !!eeprom->reg_data_clock);
127 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
128 !!eeprom->reg_chip_select);
129
9ca21eb7 130 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
a9b3a9f7
ID		 131}
132
133static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
134{
135 struct eeprom_93cx6 eeprom;
136 u32 reg;
137
9ca21eb7 138 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 139
140 eeprom.data = rt2x00dev;
141 eeprom.register_read = rt2800pci_eepromregister_read;
142 eeprom.register_write = rt2800pci_eepromregister_write;
20f8b139
GW		 143 switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
144 {
145 case 0:
146 eeprom.width = PCI_EEPROM_WIDTH_93C46;
147 break;
148 case 1:
149 eeprom.width = PCI_EEPROM_WIDTH_93C66;
150 break;
151 default:
152 eeprom.width = PCI_EEPROM_WIDTH_93C86;
153 break;
154 }
a9b3a9f7
ID		 155 eeprom.reg_data_in = 0;
156 eeprom.reg_data_out = 0;
157 eeprom.reg_data_clock = 0;
158 eeprom.reg_chip_select = 0;
159
160 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
161 EEPROM_SIZE / sizeof(u16));
162}
163
a6598682
GW		 164static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
165{
30e84034 166 return rt2800_efuse_detect(rt2x00dev);
a9b3a9f7
ID		 167}
168
30e84034 169static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 170{
30e84034 171 rt2800_read_eeprom_efuse(rt2x00dev);
a9b3a9f7
ID		 172}
173#else
174static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
175{
176}
177
a6598682
GW		 178static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
179{
180 return 0;
181}
182
a9b3a9f7
ID		 183static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
184{
185}
72c7296e 186#endif /* CONFIG_PCI */
a9b3a9f7 187
5450b7e2
ID		 188/*
189 * Queue handlers.
190 */
191static void rt2800pci_start_queue(struct data_queue *queue)
192{
193 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
194 u32 reg;
195
196 switch (queue->qid) {
197 case QID_RX:
198 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
199 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
200 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
201 break;
202 case QID_BEACON:
203 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
204 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
205 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
206 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
207 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
69cf36a4
HS		 208
209 rt2800_register_read(rt2x00dev, INT_TIMER_EN, &reg);
210 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 1);
211 rt2800_register_write(rt2x00dev, INT_TIMER_EN, reg);
5450b7e2
ID		 212 break;
213 default:
214 break;
215 };
216}
217
218static void rt2800pci_kick_queue(struct data_queue *queue)
219{
220 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
221 struct queue_entry *entry;
222
223 switch (queue->qid) {
f615e9a3
ID		 224 case QID_AC_VO:
225 case QID_AC_VI:
5450b7e2
ID		 226 case QID_AC_BE:
227 case QID_AC_BK:
5450b7e2
ID		 228 entry = rt2x00queue_get_entry(queue, Q_INDEX);
229 rt2800_register_write(rt2x00dev, TX_CTX_IDX(queue->qid), entry->entry_idx);
230 break;
231 case QID_MGMT:
232 entry = rt2x00queue_get_entry(queue, Q_INDEX);
233 rt2800_register_write(rt2x00dev, TX_CTX_IDX(5), entry->entry_idx);
234 break;
235 default:
236 break;
237 }
238}
239
240static void rt2800pci_stop_queue(struct data_queue *queue)
241{
242 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
243 u32 reg;
244
245 switch (queue->qid) {
246 case QID_RX:
247 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
248 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
249 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
250 break;
251 case QID_BEACON:
252 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
253 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
254 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
255 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
256 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
69cf36a4
HS		 257
258 rt2800_register_read(rt2x00dev, INT_TIMER_EN, &reg);
259 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 0);
260 rt2800_register_write(rt2x00dev, INT_TIMER_EN, reg);
5450b7e2
ID		 261 break;
262 default:
263 break;
264 }
265}
266
a9b3a9f7
ID		 267/*
268 * Firmware functions
269 */
270static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
271{
272 return FIRMWARE_RT2860;
273}
274
f31c9a8c 275static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
a9b3a9f7
ID		 276 const u8 *data, const size_t len)
277{
a9b3a9f7
ID		 278 u32 reg;
279
a9b3a9f7
ID		 280 /*
281 * enable Host program ram write selection
282 */
283 reg = 0;
284 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
9ca21eb7 285 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
a9b3a9f7
ID		 286
287 /*
288 * Write firmware to device.
289 */
4f2732ce 290 rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
f31c9a8c 291 data, len);
a9b3a9f7 292
9ca21eb7
BZ		 293 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
294 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
a9b3a9f7 295
9ca21eb7
BZ		 296 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
297 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
a9b3a9f7
ID		 298
299 return 0;
300}
301
302/*
303 * Initialization functions.
304 */
305static bool rt2800pci_get_entry_state(struct queue_entry *entry)
306{
307 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
308 u32 word;
309
310 if (entry->queue->qid == QID_RX) {
311 rt2x00_desc_read(entry_priv->desc, 1, &word);
312
313 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
314 } else {
315 rt2x00_desc_read(entry_priv->desc, 1, &word);
316
317 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
318 }
319}
320
321static void rt2800pci_clear_entry(struct queue_entry *entry)
322{
323 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
324 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95192339 325 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
a9b3a9f7
ID		 326 u32 word;
327
328 if (entry->queue->qid == QID_RX) {
329 rt2x00_desc_read(entry_priv->desc, 0, &word);
330 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
331 rt2x00_desc_write(entry_priv->desc, 0, word);
332
333 rt2x00_desc_read(entry_priv->desc, 1, &word);
334 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
335 rt2x00_desc_write(entry_priv->desc, 1, word);
95192339
HS		 336
337 /*
338 * Set RX IDX in register to inform hardware that we have
339 * handled this entry and it is available for reuse again.
340 */
341 rt2800_register_write(rt2x00dev, RX_CRX_IDX,
342 entry->entry_idx);
a9b3a9f7
ID		 343 } else {
344 rt2x00_desc_read(entry_priv->desc, 1, &word);
345 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
346 rt2x00_desc_write(entry_priv->desc, 1, word);
347 }
348}
349
350static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
351{
352 struct queue_entry_priv_pci *entry_priv;
353 u32 reg;
354
a9b3a9f7
ID		 355 /*
356 * Initialize registers.
357 */
358 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
9ca21eb7
BZ		 359 rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
360 rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
361 rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
362 rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
a9b3a9f7
ID		 363
364 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
9ca21eb7
BZ		 365 rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
366 rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
367 rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
368 rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
a9b3a9f7
ID		 369
370 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
9ca21eb7
BZ		 371 rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
372 rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
373 rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
374 rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
a9b3a9f7
ID		 375
376 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
9ca21eb7
BZ		 377 rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
378 rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
379 rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
380 rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
a9b3a9f7
ID		 381
382 entry_priv = rt2x00dev->rx->entries[0].priv_data;
9ca21eb7
BZ		 383 rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
384 rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
385 rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
386 rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
a9b3a9f7
ID		 387
388 /*
389 * Enable global DMA configuration
390 */
9ca21eb7 391 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 392 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
393 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
394 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 395 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7 396
9ca21eb7 397 rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
a9b3a9f7
ID		 398
399 return 0;
400}
401
a9b3a9f7
ID		 402/*
403 * Device state switch handlers.
404 */
a9b3a9f7
ID		 405static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
406 enum dev_state state)
407{
78e256c9
HS		 408 int mask = (state == STATE_RADIO_IRQ_ON) ||
409 (state == STATE_RADIO_IRQ_ON_ISR);
a9b3a9f7
ID		 410 u32 reg;
411
412 /*
413 * When interrupts are being enabled, the interrupt registers
414 * should clear the register to assure a clean state.
415 */
416 if (state == STATE_RADIO_IRQ_ON) {
9ca21eb7
BZ		 417 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
418 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
c8e15a1e
HS		 419
420 tasklet_enable(&rt2x00dev->txstatus_tasklet);
421 } else if (state == STATE_RADIO_IRQ_OFF)
422 tasklet_disable(&rt2x00dev->txstatus_tasklet);
a9b3a9f7 423
9ca21eb7 424 rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
93149cf8
HS		 425 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, 0);
426 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, 0);
a9b3a9f7 427 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
93149cf8
HS		 428 rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, 0);
429 rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, 0);
430 rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, 0);
431 rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, 0);
432 rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, 0);
433 rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, 0);
434 rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, 0);
435 rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, 0);
a9b3a9f7
ID		 436 rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
437 rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
438 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
439 rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
93149cf8
HS		 440 rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, 0);
441 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, 0);
442 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, 0);
9ca21eb7 443 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
a9b3a9f7
ID		 444}
445
e3a896b9
GW		 446static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
447{
448 u32 reg;
449
450 /*
451 * Reset DMA indexes
452 */
453 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
454 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
455 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
456 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
457 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
458 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
459 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
460 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
461 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
462
463 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
464 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
465
466 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
467
468 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
469 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
470 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
471 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
472
473 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
474
475 return 0;
476}
477
a9b3a9f7
ID		 478static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
479{
67a4c1e2 480 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
b9a07ae9 481 rt2800pci_init_queues(rt2x00dev)))
a9b3a9f7
ID		 482 return -EIO;
483
b9a07ae9 484 return rt2800_enable_radio(rt2x00dev);
a9b3a9f7
ID		 485}
486
487static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
488{
7f6e144f
RJH		 489 if (rt2x00_is_soc(rt2x00dev)) {
490 rt2800_disable_radio(rt2x00dev);
491 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
492 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
493 }
a9b3a9f7
ID		 494}
495
496static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
497 enum dev_state state)
498{
a9b3a9f7 499 if (state == STATE_AWAKE) {
7f6e144f 500 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0x02);
a9b3a9f7 501 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
7f6e144f
RJH		 502 } else if (state == STATE_SLEEP) {
503 rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, 0xffffffff);
504 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, 0xffffffff);
505 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0x01, 0xff, 0x01);
a9b3a9f7
ID		 506 }
507
508 return 0;
509}
510
511static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
512 enum dev_state state)
513{
514 int retval = 0;
515
516 switch (state) {
517 case STATE_RADIO_ON:
518 /*
519 * Before the radio can be enabled, the device first has
520 * to be woken up. After that it needs a bit of time
521 * to be fully awake and then the radio can be enabled.
522 */
523 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
524 msleep(1);
525 retval = rt2800pci_enable_radio(rt2x00dev);
526 break;
527 case STATE_RADIO_OFF:
528 /*
529 * After the radio has been disabled, the device should
530 * be put to sleep for powersaving.
531 */
532 rt2800pci_disable_radio(rt2x00dev);
533 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
534 break;
a9b3a9f7 535 case STATE_RADIO_IRQ_ON:
78e256c9 536 case STATE_RADIO_IRQ_ON_ISR:
a9b3a9f7 537 case STATE_RADIO_IRQ_OFF:
78e256c9 538 case STATE_RADIO_IRQ_OFF_ISR:
a9b3a9f7
ID		 539 rt2800pci_toggle_irq(rt2x00dev, state);
540 break;
541 case STATE_DEEP_SLEEP:
542 case STATE_SLEEP:
543 case STATE_STANDBY:
544 case STATE_AWAKE:
545 retval = rt2800pci_set_state(rt2x00dev, state);
546 break;
547 default:
548 retval = -ENOTSUPP;
549 break;
550 }
551
552 if (unlikely(retval))
553 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
554 state, retval);
555
556 return retval;
557}
558
559/*
560 * TX descriptor initialization
561 */
0c5879bc 562static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)
a9b3a9f7 563{
0c5879bc 564 return (__le32 *) entry->skb->data;
745b1ae3
HS		 565}
566
93331458 567static void rt2800pci_write_tx_desc(struct queue_entry *entry,
745b1ae3
HS		 568 struct txentry_desc *txdesc)
569{
93331458
ID		 570 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
571 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
85b7a8b3 572 __le32 *txd = entry_priv->desc;
745b1ae3
HS		 573 u32 word;
574
a9b3a9f7
ID		 575 /*
576 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
577 * must contains a TXWI structure + 802.11 header + padding + 802.11
578 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
579 * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
580 * data. It means that LAST_SEC0 is always 0.
581 */
582
583 /*
584 * Initialize TX descriptor
585 */
586 rt2x00_desc_read(txd, 0, &word);
587 rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
588 rt2x00_desc_write(txd, 0, word);
589
590 rt2x00_desc_read(txd, 1, &word);
93331458 591 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);
a9b3a9f7
ID		 592 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
593 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
594 rt2x00_set_field32(&word, TXD_W1_BURST,
595 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
85b7a8b3 596 rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
a9b3a9f7
ID		 597 rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
598 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
599 rt2x00_desc_write(txd, 1, word);
600
601 rt2x00_desc_read(txd, 2, &word);
602 rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
85b7a8b3 603 skbdesc->skb_dma + TXWI_DESC_SIZE);
a9b3a9f7
ID		 604 rt2x00_desc_write(txd, 2, word);
605
606 rt2x00_desc_read(txd, 3, &word);
607 rt2x00_set_field32(&word, TXD_W3_WIV,
608 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
609 rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
610 rt2x00_desc_write(txd, 3, word);
85b7a8b3
GW		 611
612 /*
613 * Register descriptor details in skb frame descriptor.
614 */
615 skbdesc->desc = txd;
616 skbdesc->desc_len = TXD_DESC_SIZE;
a9b3a9f7
ID		 617}
618
a9b3a9f7
ID		 619/*
620 * RX control handlers
621 */
622static void rt2800pci_fill_rxdone(struct queue_entry *entry,
623 struct rxdone_entry_desc *rxdesc)
624{
a9b3a9f7
ID		 625 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
626 __le32 *rxd = entry_priv->desc;
2de64dd2
GW		 627 u32 word;
628
629 rt2x00_desc_read(rxd, 3, &word);
630
631 if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
a9b3a9f7
ID		 632 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
633
78b8f3b0
GW		 634 /*
635 * Unfortunately we don't know the cipher type used during
636 * decryption. This prevents us from correct providing
637 * correct statistics through debugfs.
638 */
2de64dd2 639 rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
a9b3a9f7 640
2de64dd2 641 if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
a9b3a9f7
ID		 642 /*
643 * Hardware has stripped IV/EIV data from 802.11 frame during
644 * decryption. Unfortunately the descriptor doesn't contain
645 * any fields with the EIV/IV data either, so they can't
646 * be restored by rt2x00lib.
647 */
648 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
649
650 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
651 rxdesc->flags |= RX_FLAG_DECRYPTED;
652 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
653 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
654 }
655
2de64dd2 656 if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
a9b3a9f7
ID		 657 rxdesc->dev_flags |= RXDONE_MY_BSS;
658
2de64dd2 659 if (rt2x00_get_field32(word, RXD_W3_L2PAD))
a9b3a9f7 660 rxdesc->dev_flags |= RXDONE_L2PAD;
a9b3a9f7 661
a9b3a9f7 662 /*
2de64dd2 663 * Process the RXWI structure that is at the start of the buffer.
a9b3a9f7 664 */
74861922 665 rt2800_process_rxwi(entry, rxdesc);
a9b3a9f7
ID		 666}
667
668/*
669 * Interrupt functions.
670 */
4d66edc8
GW		 671static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
672{
673 struct ieee80211_conf conf = { .flags = 0 };
674 struct rt2x00lib_conf libconf = { .conf = &conf };
675
676 rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
677}
678
96c3da7d
HS		 679static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
680{
681 struct data_queue *queue;
682 struct queue_entry *entry;
683 u32 status;
684 u8 qid;
685
c4d63244 686 while (kfifo_get(&rt2x00dev->txstatus_fifo, &status)) {
12eec2cc 687 qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
96c3da7d
HS		 688 if (qid >= QID_RX) {
689 /*
690 * Unknown queue, this shouldn't happen. Just drop
691 * this tx status.
692 */
693 WARNING(rt2x00dev, "Got TX status report with "
094a1d92 694 "unexpected pid %u, dropping\n", qid);
96c3da7d
HS		 695 break;
696 }
697
698 queue = rt2x00queue_get_queue(rt2x00dev, qid);
699 if (unlikely(queue == NULL)) {
700 /*
701 * The queue is NULL, this shouldn't happen. Stop
702 * processing here and drop the tx status
703 */
704 WARNING(rt2x00dev, "Got TX status for an unavailable "
094a1d92 705 "queue %u, dropping\n", qid);
96c3da7d
HS		 706 break;
707 }
708
709 if (rt2x00queue_empty(queue)) {
710 /*
711 * The queue is empty. Stop processing here
712 * and drop the tx status.
713 */
714 WARNING(rt2x00dev, "Got TX status for an empty "
094a1d92 715 "queue %u, dropping\n", qid);
96c3da7d
HS		 716 break;
717 }
718
719 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
720 rt2800_txdone_entry(entry, status);
721 }
722}
723
724static void rt2800pci_txstatus_tasklet(unsigned long data)
725{
726 rt2800pci_txdone((struct rt2x00_dev *)data);
727}
728
78e256c9 729static irqreturn_t rt2800pci_interrupt_thread(int irq, void *dev_instance)
a9b3a9f7
ID		 730{
731 struct rt2x00_dev *rt2x00dev = dev_instance;
78e256c9 732 u32 reg = rt2x00dev->irqvalue[0];
a9b3a9f7
ID		 733
734 /*
9f926fb5
HS		 735 * 1 - Pre TBTT interrupt.
736 */
737 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
738 rt2x00lib_pretbtt(rt2x00dev);
739
740 /*
741 * 2 - Beacondone interrupt.
742 */
743 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
744 rt2x00lib_beacondone(rt2x00dev);
745
746 /*
747 * 3 - Rx ring done interrupt.
a9b3a9f7
ID		 748 */
749 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
750 rt2x00pci_rxdone(rt2x00dev);
751
9f926fb5 752 /*
96c3da7d 753 * 4 - Auto wakeup interrupt.
ad90319b 754 */
4d66edc8
GW		 755 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
756 rt2800pci_wakeup(rt2x00dev);
757
78e256c9
HS		 758 /* Enable interrupts again. */
759 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
760 STATE_RADIO_IRQ_ON_ISR);
761
a9b3a9f7
ID		 762 return IRQ_HANDLED;
763}
764
96c3da7d
HS		 765static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
766{
767 u32 status;
768 int i;
769
770 /*
771 * The TX_FIFO_STATUS interrupt needs special care. We should
772 * read TX_STA_FIFO but we should do it immediately as otherwise
773 * the register can overflow and we would lose status reports.
774 *
775 * Hence, read the TX_STA_FIFO register and copy all tx status
776 * reports into a kernel FIFO which is handled in the txstatus
777 * tasklet. We use a tasklet to process the tx status reports
778 * because we can schedule the tasklet multiple times (when the
779 * interrupt fires again during tx status processing).
780 *
781 * Furthermore we don't disable the TX_FIFO_STATUS
782 * interrupt here but leave it enabled so that the TX_STA_FIFO
783 * can also be read while the interrupt thread gets executed.
784 *
785 * Since we have only one producer and one consumer we don't
786 * need to lock the kfifo.
787 */
efd2f271 788 for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
96c3da7d
HS		 789 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &status);
790
791 if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
792 break;
793
c4d63244 794 if (!kfifo_put(&rt2x00dev->txstatus_fifo, &status)) {
96c3da7d
HS		 795 WARNING(rt2x00dev, "TX status FIFO overrun,"
796 "drop tx status report.\n");
797 break;
798 }
799 }
800
801 /* Schedule the tasklet for processing the tx status. */
802 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
803}
804
78e256c9
HS		 805static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
806{
807 struct rt2x00_dev *rt2x00dev = dev_instance;
808 u32 reg;
96c3da7d 809 irqreturn_t ret = IRQ_HANDLED;
78e256c9
HS		 810
811 /* Read status and ACK all interrupts */
812 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
813 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
814
815 if (!reg)
816 return IRQ_NONE;
817
818 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
819 return IRQ_HANDLED;
820
96c3da7d
HS		 821 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
822 rt2800pci_txstatus_interrupt(rt2x00dev);
78e256c9 823
96c3da7d
HS		 824 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT) ||
825 rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT) ||
826 rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE) ||
827 rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP)) {
828 /*
829 * All other interrupts are handled in the interrupt thread.
830 * Store irqvalue for use in the interrupt thread.
831 */
832 rt2x00dev->irqvalue[0] = reg;
833
834 /*
835 * Disable interrupts, will be enabled again in the
836 * interrupt thread.
837 */
838 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
839 STATE_RADIO_IRQ_OFF_ISR);
78e256c9 840
96c3da7d
HS		 841 /*
842 * Leave the TX_FIFO_STATUS interrupt enabled to not lose any
843 * tx status reports.
844 */
845 rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
846 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, 1);
847 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
848
849 ret = IRQ_WAKE_THREAD;
850 }
78e256c9 851
96c3da7d 852 return ret;
78e256c9
HS		 853}
854
a9b3a9f7
ID		 855/*
856 * Device probe functions.
857 */
7ab71325
BZ		 858static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
859{
860 /*
861 * Read EEPROM into buffer
862 */
cea90e55 863 if (rt2x00_is_soc(rt2x00dev))
7ab71325 864 rt2800pci_read_eeprom_soc(rt2x00dev);
cea90e55
GW		 865 else if (rt2800pci_efuse_detect(rt2x00dev))
866 rt2800pci_read_eeprom_efuse(rt2x00dev);
867 else
868 rt2800pci_read_eeprom_pci(rt2x00dev);
7ab71325
BZ		 869
870 return rt2800_validate_eeprom(rt2x00dev);
871}
872
a9b3a9f7
ID		 873static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
874{
875 int retval;
876
877 /*
878 * Allocate eeprom data.
879 */
880 retval = rt2800pci_validate_eeprom(rt2x00dev);
881 if (retval)
882 return retval;
883
38bd7b8a 884 retval = rt2800_init_eeprom(rt2x00dev);
a9b3a9f7
ID		 885 if (retval)
886 return retval;
887
888 /*
889 * Initialize hw specifications.
890 */
4da2933f 891 retval = rt2800_probe_hw_mode(rt2x00dev);
a9b3a9f7
ID		 892 if (retval)
893 return retval;
894
895 /*
896 * This device has multiple filters for control frames
897 * and has a separate filter for PS Poll frames.
898 */
899 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
900 __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
901
9f926fb5
HS		 902 /*
903 * This device has a pre tbtt interrupt and thus fetches
904 * a new beacon directly prior to transmission.
905 */
906 __set_bit(DRIVER_SUPPORT_PRE_TBTT_INTERRUPT, &rt2x00dev->flags);
907
a9b3a9f7
ID		 908 /*
909 * This device requires firmware.
910 */
cea90e55 911 if (!rt2x00_is_soc(rt2x00dev))
a9b3a9f7
ID		 912 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
913 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
914 __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
96c3da7d 915 __set_bit(DRIVER_REQUIRE_TXSTATUS_FIFO, &rt2x00dev->flags);
20ed3166 916 __set_bit(DRIVER_REQUIRE_TASKLET_CONTEXT, &rt2x00dev->flags);
a9b3a9f7
ID		 917 if (!modparam_nohwcrypt)
918 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
27df2a9c 919 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
a9b3a9f7
ID		 920
921 /*
922 * Set the rssi offset.
923 */
924 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
925
926 return 0;
927}
928
e783619e
HS		 929static const struct ieee80211_ops rt2800pci_mac80211_ops = {
930 .tx = rt2x00mac_tx,
931 .start = rt2x00mac_start,
932 .stop = rt2x00mac_stop,
933 .add_interface = rt2x00mac_add_interface,
934 .remove_interface = rt2x00mac_remove_interface,
935 .config = rt2x00mac_config,
936 .configure_filter = rt2x00mac_configure_filter,
e783619e
HS		 937 .set_key = rt2x00mac_set_key,
938 .sw_scan_start = rt2x00mac_sw_scan_start,
939 .sw_scan_complete = rt2x00mac_sw_scan_complete,
940 .get_stats = rt2x00mac_get_stats,
941 .get_tkip_seq = rt2800_get_tkip_seq,
942 .set_rts_threshold = rt2800_set_rts_threshold,
943 .bss_info_changed = rt2x00mac_bss_info_changed,
944 .conf_tx = rt2800_conf_tx,
945 .get_tsf = rt2800_get_tsf,
946 .rfkill_poll = rt2x00mac_rfkill_poll,
947 .ampdu_action = rt2800_ampdu_action,
f44df18c 948 .flush = rt2x00mac_flush,
977206d7 949 .get_survey = rt2800_get_survey,
e783619e
HS		 950};
951
e796643e
ID		 952static const struct rt2800_ops rt2800pci_rt2800_ops = {
953 .register_read = rt2x00pci_register_read,
954 .register_read_lock = rt2x00pci_register_read, /* same for PCI */
955 .register_write = rt2x00pci_register_write,
956 .register_write_lock = rt2x00pci_register_write, /* same for PCI */
957 .register_multiread = rt2x00pci_register_multiread,
958 .register_multiwrite = rt2x00pci_register_multiwrite,
959 .regbusy_read = rt2x00pci_regbusy_read,
960 .drv_write_firmware = rt2800pci_write_firmware,
961 .drv_init_registers = rt2800pci_init_registers,
0c5879bc 962 .drv_get_txwi = rt2800pci_get_txwi,
e796643e
ID		 963};
964
a9b3a9f7
ID		 965static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
966 .irq_handler = rt2800pci_interrupt,
78e256c9 967 .irq_handler_thread = rt2800pci_interrupt_thread,
96c3da7d 968 .txstatus_tasklet = rt2800pci_txstatus_tasklet,
a9b3a9f7
ID		 969 .probe_hw = rt2800pci_probe_hw,
970 .get_firmware_name = rt2800pci_get_firmware_name,
f31c9a8c
ID		 971 .check_firmware = rt2800_check_firmware,
972 .load_firmware = rt2800_load_firmware,
a9b3a9f7
ID		 973 .initialize = rt2x00pci_initialize,
974 .uninitialize = rt2x00pci_uninitialize,
975 .get_entry_state = rt2800pci_get_entry_state,
976 .clear_entry = rt2800pci_clear_entry,
977 .set_device_state = rt2800pci_set_device_state,
f4450616
BZ		 978 .rfkill_poll = rt2800_rfkill_poll,
979 .link_stats = rt2800_link_stats,
980 .reset_tuner = rt2800_reset_tuner,
981 .link_tuner = rt2800_link_tuner,
dbba306f
ID		 982 .start_queue = rt2800pci_start_queue,
983 .kick_queue = rt2800pci_kick_queue,
984 .stop_queue = rt2800pci_stop_queue,
a9b3a9f7 985 .write_tx_desc = rt2800pci_write_tx_desc,
0c5879bc 986 .write_tx_data = rt2800_write_tx_data,
f0194b2d 987 .write_beacon = rt2800_write_beacon,
69cf36a4 988 .clear_beacon = rt2800_clear_beacon,
a9b3a9f7 989 .fill_rxdone = rt2800pci_fill_rxdone,
f4450616
BZ		 990 .config_shared_key = rt2800_config_shared_key,
991 .config_pairwise_key = rt2800_config_pairwise_key,
992 .config_filter = rt2800_config_filter,
993 .config_intf = rt2800_config_intf,
994 .config_erp = rt2800_config_erp,
995 .config_ant = rt2800_config_ant,
996 .config = rt2800_config,
a9b3a9f7
ID		 997};
998
999static const struct data_queue_desc rt2800pci_queue_rx = {
efd2f271 1000 .entry_num = 128,
a9b3a9f7
ID		 1001 .data_size = AGGREGATION_SIZE,
1002 .desc_size = RXD_DESC_SIZE,
1003 .priv_size = sizeof(struct queue_entry_priv_pci),
1004};
1005
1006static const struct data_queue_desc rt2800pci_queue_tx = {
efd2f271 1007 .entry_num = 64,
a9b3a9f7
ID		 1008 .data_size = AGGREGATION_SIZE,
1009 .desc_size = TXD_DESC_SIZE,
1010 .priv_size = sizeof(struct queue_entry_priv_pci),
1011};
1012
1013static const struct data_queue_desc rt2800pci_queue_bcn = {
efd2f271 1014 .entry_num = 8,
a9b3a9f7
ID		 1015 .data_size = 0, /* No DMA required for beacons */
1016 .desc_size = TXWI_DESC_SIZE,
1017 .priv_size = sizeof(struct queue_entry_priv_pci),
1018};
1019
1020static const struct rt2x00_ops rt2800pci_ops = {
04d0362e
GW		 1021 .name = KBUILD_MODNAME,
1022 .max_sta_intf = 1,
1023 .max_ap_intf = 8,
1024 .eeprom_size = EEPROM_SIZE,
1025 .rf_size = RF_SIZE,
1026 .tx_queues = NUM_TX_QUEUES,
e6218cc4 1027 .extra_tx_headroom = TXWI_DESC_SIZE,
04d0362e
GW		 1028 .rx = &rt2800pci_queue_rx,
1029 .tx = &rt2800pci_queue_tx,
1030 .bcn = &rt2800pci_queue_bcn,
1031 .lib = &rt2800pci_rt2x00_ops,
e796643e 1032 .drv = &rt2800pci_rt2800_ops,
e783619e 1033 .hw = &rt2800pci_mac80211_ops,
a9b3a9f7 1034#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 1035 .debugfs = &rt2800_rt2x00debug,
a9b3a9f7
ID		 1036#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1037};
1038
1039/*
1040 * RT2800pci module information.
1041 */
72c7296e 1042#ifdef CONFIG_PCI
a3aa1884 1043static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
de1ebdce
GW		 1044 { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
1045 { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
1046 { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
1047 { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
a6a8d66e
GW		 1048 { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
1049 { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
1050 { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
a9b3a9f7
ID		 1051 { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
1052 { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
1053 { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
1054 { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
1055 { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
1056 { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
1057 { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
de1ebdce 1058 { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
a6a8d66e 1059 { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
f93bc9b3
GW		 1060#ifdef CONFIG_RT2800PCI_RT33XX
1061 { PCI_DEVICE(0x1814, 0x3390), PCI_DEVICE_DATA(&rt2800pci_ops) },
1062#endif
de1ebdce
GW		 1063#ifdef CONFIG_RT2800PCI_RT35XX
1064 { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
1065 { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
a9b3a9f7
ID		 1066 { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
1067 { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
6424bf70 1068 { PCI_DEVICE(0x1814, 0x3593), PCI_DEVICE_DATA(&rt2800pci_ops) },
de1ebdce 1069#endif
a9b3a9f7
ID		 1070 { 0, }
1071};
72c7296e 1072#endif /* CONFIG_PCI */
a9b3a9f7
ID		 1073
1074MODULE_AUTHOR(DRV_PROJECT);
1075MODULE_VERSION(DRV_VERSION);
1076MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1077MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
72c7296e 1078#ifdef CONFIG_PCI
a9b3a9f7
ID		 1079MODULE_FIRMWARE(FIRMWARE_RT2860);
1080MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
72c7296e 1081#endif /* CONFIG_PCI */
a9b3a9f7
ID		 1082MODULE_LICENSE("GPL");
1083
72c7296e 1084#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
714fa663
GW		 1085static int rt2800soc_probe(struct platform_device *pdev)
1086{
6e93d719 1087 return rt2x00soc_probe(pdev, &rt2800pci_ops);
714fa663 1088}
a9b3a9f7
ID		 1089
1090static struct platform_driver rt2800soc_driver = {
1091 .driver = {
1092 .name = "rt2800_wmac",
1093 .owner = THIS_MODULE,
1094 .mod_name = KBUILD_MODNAME,
1095 },
714fa663 1096 .probe = rt2800soc_probe,
a9b3a9f7
ID		 1097 .remove = __devexit_p(rt2x00soc_remove),
1098 .suspend = rt2x00soc_suspend,
1099 .resume = rt2x00soc_resume,
1100};
72c7296e 1101#endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
a9b3a9f7 1102
72c7296e 1103#ifdef CONFIG_PCI
a9b3a9f7
ID		 1104static struct pci_driver rt2800pci_driver = {
1105 .name = KBUILD_MODNAME,
1106 .id_table = rt2800pci_device_table,
1107 .probe = rt2x00pci_probe,
1108 .remove = __devexit_p(rt2x00pci_remove),
1109 .suspend = rt2x00pci_suspend,
1110 .resume = rt2x00pci_resume,
1111};
72c7296e 1112#endif /* CONFIG_PCI */
a9b3a9f7
ID		 1113
1114static int __init rt2800pci_init(void)
1115{
1116 int ret = 0;
1117
72c7296e 1118#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
a9b3a9f7
ID		 1119 ret = platform_driver_register(&rt2800soc_driver);
1120 if (ret)
1121 return ret;
1122#endif
72c7296e 1123#ifdef CONFIG_PCI
a9b3a9f7
ID		 1124 ret = pci_register_driver(&rt2800pci_driver);
1125 if (ret) {
72c7296e 1126#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
a9b3a9f7
ID		 1127 platform_driver_unregister(&rt2800soc_driver);
1128#endif
1129 return ret;
1130 }
1131#endif
1132
1133 return ret;
1134}
1135
1136static void __exit rt2800pci_exit(void)
1137{
72c7296e 1138#ifdef CONFIG_PCI
a9b3a9f7
ID		 1139 pci_unregister_driver(&rt2800pci_driver);
1140#endif
72c7296e 1141#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
a9b3a9f7
ID		 1142 platform_driver_unregister(&rt2800soc_driver);
1143#endif
1144}
1145
1146module_init(rt2800pci_init);
1147module_exit(rt2800pci_exit);
Linux kernel - Deliverables
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