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rt2x00: Don't initialize MM40 HT protection to RTS/CTS on PCI devices
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2800pci.c
CommitLineData
a9b3a9f7 1/*
96481b20 2 Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14
GW		 3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
a9b3a9f7
ID		 10 <http://rt2x00.serialmonkey.com>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 */
27
28/*
29 Module: rt2800pci
30 Abstract: rt2800pci device specific routines.
31 Supported chipsets: RT2800E & RT2800ED.
32 */
33
a9b3a9f7
ID		 34#include <linux/delay.h>
35#include <linux/etherdevice.h>
36#include <linux/init.h>
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/pci.h>
40#include <linux/platform_device.h>
41#include <linux/eeprom_93cx6.h>
42
43#include "rt2x00.h"
44#include "rt2x00pci.h"
45#include "rt2x00soc.h"
7ef5cc92 46#include "rt2800lib.h"
b54f78a8 47#include "rt2800.h"
a9b3a9f7
ID		 48#include "rt2800pci.h"
49
a9b3a9f7
ID		 50/*
51 * Allow hardware encryption to be disabled.
52 */
04f1e34d 53static int modparam_nohwcrypt = 0;
a9b3a9f7
ID		 54module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
55MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
56
a9b3a9f7
ID		 57static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
58{
59 unsigned int i;
60 u32 reg;
61
f18d4463
LC		 62 /*
63 * SOC devices don't support MCU requests.
64 */
65 if (rt2x00_is_soc(rt2x00dev))
66 return;
67
a9b3a9f7 68 for (i = 0; i < 200; i++) {
9ca21eb7 69 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
a9b3a9f7
ID		 70
71 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
72 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
73 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
74 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
75 break;
76
77 udelay(REGISTER_BUSY_DELAY);
78 }
79
80 if (i == 200)
81 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
82
9ca21eb7
BZ		 83 rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
84 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
a9b3a9f7
ID		 85}
86
00e23ce2 87#ifdef CONFIG_RT2800PCI_SOC
a9b3a9f7
ID		 88static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
89{
90 u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */
91
92 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
93}
94#else
95static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
96{
97}
00e23ce2 98#endif /* CONFIG_RT2800PCI_SOC */
a9b3a9f7
ID		 99
100#ifdef CONFIG_RT2800PCI_PCI
101static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
102{
103 struct rt2x00_dev *rt2x00dev = eeprom->data;
104 u32 reg;
105
9ca21eb7 106 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 107
108 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
109 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
110 eeprom->reg_data_clock =
111 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
112 eeprom->reg_chip_select =
113 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
114}
115
116static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
117{
118 struct rt2x00_dev *rt2x00dev = eeprom->data;
119 u32 reg = 0;
120
121 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
122 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
123 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
124 !!eeprom->reg_data_clock);
125 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
126 !!eeprom->reg_chip_select);
127
9ca21eb7 128 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
a9b3a9f7
ID		 129}
130
131static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
132{
133 struct eeprom_93cx6 eeprom;
134 u32 reg;
135
9ca21eb7 136 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 137
138 eeprom.data = rt2x00dev;
139 eeprom.register_read = rt2800pci_eepromregister_read;
140 eeprom.register_write = rt2800pci_eepromregister_write;
20f8b139
GW		 141 switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
142 {
143 case 0:
144 eeprom.width = PCI_EEPROM_WIDTH_93C46;
145 break;
146 case 1:
147 eeprom.width = PCI_EEPROM_WIDTH_93C66;
148 break;
149 default:
150 eeprom.width = PCI_EEPROM_WIDTH_93C86;
151 break;
152 }
a9b3a9f7
ID		 153 eeprom.reg_data_in = 0;
154 eeprom.reg_data_out = 0;
155 eeprom.reg_data_clock = 0;
156 eeprom.reg_chip_select = 0;
157
158 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
159 EEPROM_SIZE / sizeof(u16));
160}
161
a6598682
GW		 162static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
163{
30e84034 164 return rt2800_efuse_detect(rt2x00dev);
a9b3a9f7
ID		 165}
166
30e84034 167static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 168{
30e84034 169 rt2800_read_eeprom_efuse(rt2x00dev);
a9b3a9f7
ID		 170}
171#else
172static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
173{
174}
175
a6598682
GW		 176static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
177{
178 return 0;
179}
180
a9b3a9f7
ID		 181static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
182{
183}
184#endif /* CONFIG_RT2800PCI_PCI */
185
a9b3a9f7
ID		 186/*
187 * Firmware functions
188 */
189static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
190{
191 return FIRMWARE_RT2860;
192}
193
f31c9a8c 194static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
a9b3a9f7
ID		 195 const u8 *data, const size_t len)
196{
a9b3a9f7
ID		 197 u32 reg;
198
a9b3a9f7
ID		 199 /*
200 * enable Host program ram write selection
201 */
202 reg = 0;
203 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
9ca21eb7 204 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
a9b3a9f7
ID		 205
206 /*
207 * Write firmware to device.
208 */
4f2732ce 209 rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
f31c9a8c 210 data, len);
a9b3a9f7 211
9ca21eb7
BZ		 212 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
213 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
a9b3a9f7 214
9ca21eb7
BZ		 215 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
216 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
a9b3a9f7
ID		 217
218 return 0;
219}
220
221/*
222 * Initialization functions.
223 */
224static bool rt2800pci_get_entry_state(struct queue_entry *entry)
225{
226 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
227 u32 word;
228
229 if (entry->queue->qid == QID_RX) {
230 rt2x00_desc_read(entry_priv->desc, 1, &word);
231
232 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
233 } else {
234 rt2x00_desc_read(entry_priv->desc, 1, &word);
235
236 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
237 }
238}
239
240static void rt2800pci_clear_entry(struct queue_entry *entry)
241{
242 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
243 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
244 u32 word;
245
246 if (entry->queue->qid == QID_RX) {
247 rt2x00_desc_read(entry_priv->desc, 0, &word);
248 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
249 rt2x00_desc_write(entry_priv->desc, 0, word);
250
251 rt2x00_desc_read(entry_priv->desc, 1, &word);
252 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
253 rt2x00_desc_write(entry_priv->desc, 1, word);
254 } else {
255 rt2x00_desc_read(entry_priv->desc, 1, &word);
256 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
257 rt2x00_desc_write(entry_priv->desc, 1, word);
258 }
259}
260
261static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
262{
263 struct queue_entry_priv_pci *entry_priv;
264 u32 reg;
265
a9b3a9f7
ID		 266 /*
267 * Initialize registers.
268 */
269 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
9ca21eb7
BZ		 270 rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
271 rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
272 rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
273 rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
a9b3a9f7
ID		 274
275 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
9ca21eb7
BZ		 276 rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
277 rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
278 rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
279 rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
a9b3a9f7
ID		 280
281 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
9ca21eb7
BZ		 282 rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
283 rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
284 rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
285 rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
a9b3a9f7
ID		 286
287 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
9ca21eb7
BZ		 288 rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
289 rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
290 rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
291 rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
a9b3a9f7
ID		 292
293 entry_priv = rt2x00dev->rx->entries[0].priv_data;
9ca21eb7
BZ		 294 rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
295 rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
296 rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
297 rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
a9b3a9f7
ID		 298
299 /*
300 * Enable global DMA configuration
301 */
9ca21eb7 302 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 303 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
304 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
305 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 306 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7 307
9ca21eb7 308 rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
a9b3a9f7
ID		 309
310 return 0;
311}
312
a9b3a9f7
ID		 313/*
314 * Device state switch handlers.
315 */
316static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
317 enum dev_state state)
318{
319 u32 reg;
320
9ca21eb7 321 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
a9b3a9f7
ID		 322 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
323 (state == STATE_RADIO_RX_ON) ||
324 (state == STATE_RADIO_RX_ON_LINK));
9ca21eb7 325 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
a9b3a9f7
ID		 326}
327
328static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
329 enum dev_state state)
330{
78e256c9
HS		 331 int mask = (state == STATE_RADIO_IRQ_ON) ||
332 (state == STATE_RADIO_IRQ_ON_ISR);
a9b3a9f7
ID		 333 u32 reg;
334
335 /*
336 * When interrupts are being enabled, the interrupt registers
337 * should clear the register to assure a clean state.
338 */
339 if (state == STATE_RADIO_IRQ_ON) {
9ca21eb7
BZ		 340 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
341 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
a9b3a9f7
ID		 342 }
343
9ca21eb7 344 rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
93149cf8
HS		 345 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, 0);
346 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, 0);
a9b3a9f7 347 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
93149cf8
HS		 348 rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, 0);
349 rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, 0);
350 rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, 0);
351 rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, 0);
352 rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, 0);
353 rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, 0);
354 rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, 0);
355 rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, 0);
a9b3a9f7
ID		 356 rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
357 rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
358 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
359 rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
93149cf8
HS		 360 rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, 0);
361 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, 0);
362 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, 0);
9ca21eb7 363 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
a9b3a9f7
ID		 364}
365
e3a896b9
GW		 366static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
367{
368 u32 reg;
369
370 /*
371 * Reset DMA indexes
372 */
373 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
374 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
375 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
376 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
377 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
378 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
379 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
380 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
381 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
382
383 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
384 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
385
386 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
387
388 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
389 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
390 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
391 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
392
393 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
394
395 return 0;
396}
397
a9b3a9f7
ID		 398static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
399{
67a4c1e2 400 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
b9a07ae9 401 rt2800pci_init_queues(rt2x00dev)))
a9b3a9f7
ID		 402 return -EIO;
403
b9a07ae9 404 return rt2800_enable_radio(rt2x00dev);
a9b3a9f7
ID		 405}
406
407static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
408{
409 u32 reg;
410
b9a07ae9 411 rt2800_disable_radio(rt2x00dev);
a9b3a9f7 412
9ca21eb7 413 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
a9b3a9f7 414
9ca21eb7 415 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
a9b3a9f7
ID		 416 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
417 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
418 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
419 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
420 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
421 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
422 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
9ca21eb7 423 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
a9b3a9f7 424
9ca21eb7
BZ		 425 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
426 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
a9b3a9f7
ID		 427}
428
429static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
430 enum dev_state state)
431{
432 /*
433 * Always put the device to sleep (even when we intend to wakeup!)
434 * if the device is booting and wasn't asleep it will return
435 * failure when attempting to wakeup.
436 */
3a9e5b0f 437 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
a9b3a9f7
ID		 438
439 if (state == STATE_AWAKE) {
3a9e5b0f 440 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
a9b3a9f7
ID		 441 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
442 }
443
444 return 0;
445}
446
447static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
448 enum dev_state state)
449{
450 int retval = 0;
451
452 switch (state) {
453 case STATE_RADIO_ON:
454 /*
455 * Before the radio can be enabled, the device first has
456 * to be woken up. After that it needs a bit of time
457 * to be fully awake and then the radio can be enabled.
458 */
459 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
460 msleep(1);
461 retval = rt2800pci_enable_radio(rt2x00dev);
462 break;
463 case STATE_RADIO_OFF:
464 /*
465 * After the radio has been disabled, the device should
466 * be put to sleep for powersaving.
467 */
468 rt2800pci_disable_radio(rt2x00dev);
469 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
470 break;
471 case STATE_RADIO_RX_ON:
472 case STATE_RADIO_RX_ON_LINK:
473 case STATE_RADIO_RX_OFF:
474 case STATE_RADIO_RX_OFF_LINK:
475 rt2800pci_toggle_rx(rt2x00dev, state);
476 break;
477 case STATE_RADIO_IRQ_ON:
78e256c9 478 case STATE_RADIO_IRQ_ON_ISR:
a9b3a9f7 479 case STATE_RADIO_IRQ_OFF:
78e256c9 480 case STATE_RADIO_IRQ_OFF_ISR:
a9b3a9f7
ID		 481 rt2800pci_toggle_irq(rt2x00dev, state);
482 break;
483 case STATE_DEEP_SLEEP:
484 case STATE_SLEEP:
485 case STATE_STANDBY:
486 case STATE_AWAKE:
487 retval = rt2800pci_set_state(rt2x00dev, state);
488 break;
489 default:
490 retval = -ENOTSUPP;
491 break;
492 }
493
494 if (unlikely(retval))
495 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
496 state, retval);
497
498 return retval;
499}
500
501/*
502 * TX descriptor initialization
503 */
0c5879bc 504static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)
a9b3a9f7 505{
0c5879bc 506 return (__le32 *) entry->skb->data;
745b1ae3
HS		 507}
508
93331458 509static void rt2800pci_write_tx_desc(struct queue_entry *entry,
745b1ae3
HS		 510 struct txentry_desc *txdesc)
511{
93331458
ID		 512 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
513 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
85b7a8b3 514 __le32 *txd = entry_priv->desc;
745b1ae3
HS		 515 u32 word;
516
a9b3a9f7
ID		 517 /*
518 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
519 * must contains a TXWI structure + 802.11 header + padding + 802.11
520 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
521 * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
522 * data. It means that LAST_SEC0 is always 0.
523 */
524
525 /*
526 * Initialize TX descriptor
527 */
528 rt2x00_desc_read(txd, 0, &word);
529 rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
530 rt2x00_desc_write(txd, 0, word);
531
532 rt2x00_desc_read(txd, 1, &word);
93331458 533 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);
a9b3a9f7
ID		 534 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
535 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
536 rt2x00_set_field32(&word, TXD_W1_BURST,
537 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
85b7a8b3 538 rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
a9b3a9f7
ID		 539 rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
540 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
541 rt2x00_desc_write(txd, 1, word);
542
543 rt2x00_desc_read(txd, 2, &word);
544 rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
85b7a8b3 545 skbdesc->skb_dma + TXWI_DESC_SIZE);
a9b3a9f7
ID		 546 rt2x00_desc_write(txd, 2, word);
547
548 rt2x00_desc_read(txd, 3, &word);
549 rt2x00_set_field32(&word, TXD_W3_WIV,
550 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
551 rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
552 rt2x00_desc_write(txd, 3, word);
85b7a8b3
GW		 553
554 /*
555 * Register descriptor details in skb frame descriptor.
556 */
557 skbdesc->desc = txd;
558 skbdesc->desc_len = TXD_DESC_SIZE;
a9b3a9f7
ID		 559}
560
561/*
562 * TX data initialization
563 */
93331458 564static void rt2800pci_kick_tx_queue(struct data_queue *queue)
a9b3a9f7 565{
93331458 566 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
5eb7efe8 567 struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX);
93331458 568 unsigned int qidx = 0;
a9b3a9f7 569
93331458 570 if (queue->qid == QID_MGMT)
a9b3a9f7
ID		 571 qidx = 5;
572 else
93331458 573 qidx = queue->qid;
a9b3a9f7 574
5eb7efe8 575 rt2800_register_write(rt2x00dev, TX_CTX_IDX(qidx), entry->entry_idx);
a9b3a9f7
ID		 576}
577
93331458 578static void rt2800pci_kill_tx_queue(struct data_queue *queue)
a9b3a9f7 579{
93331458 580 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
a9b3a9f7
ID		 581 u32 reg;
582
93331458 583 if (queue->qid == QID_BEACON) {
9ca21eb7 584 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, 0);
a9b3a9f7
ID		 585 return;
586 }
587
9ca21eb7 588 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
93331458
ID		 589 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (queue->qid == QID_AC_BE));
590 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (queue->qid == QID_AC_BK));
591 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (queue->qid == QID_AC_VI));
592 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (queue->qid == QID_AC_VO));
9ca21eb7 593 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
a9b3a9f7
ID		 594}
595
596/*
597 * RX control handlers
598 */
599static void rt2800pci_fill_rxdone(struct queue_entry *entry,
600 struct rxdone_entry_desc *rxdesc)
601{
602 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
a9b3a9f7
ID		 603 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
604 __le32 *rxd = entry_priv->desc;
2de64dd2
GW		 605 u32 word;
606
607 rt2x00_desc_read(rxd, 3, &word);
608
609 if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
a9b3a9f7
ID		 610 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
611
78b8f3b0
GW		 612 /*
613 * Unfortunately we don't know the cipher type used during
614 * decryption. This prevents us from correct providing
615 * correct statistics through debugfs.
616 */
2de64dd2 617 rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
a9b3a9f7 618
2de64dd2 619 if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
a9b3a9f7
ID		 620 /*
621 * Hardware has stripped IV/EIV data from 802.11 frame during
622 * decryption. Unfortunately the descriptor doesn't contain
623 * any fields with the EIV/IV data either, so they can't
624 * be restored by rt2x00lib.
625 */
626 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
627
628 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
629 rxdesc->flags |= RX_FLAG_DECRYPTED;
630 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
631 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
632 }
633
2de64dd2 634 if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
a9b3a9f7
ID		 635 rxdesc->dev_flags |= RXDONE_MY_BSS;
636
2de64dd2 637 if (rt2x00_get_field32(word, RXD_W3_L2PAD))
a9b3a9f7 638 rxdesc->dev_flags |= RXDONE_L2PAD;
a9b3a9f7 639
a9b3a9f7 640 /*
2de64dd2 641 * Process the RXWI structure that is at the start of the buffer.
a9b3a9f7 642 */
74861922 643 rt2800_process_rxwi(entry, rxdesc);
a9b3a9f7
ID		 644
645 /*
646 * Set RX IDX in register to inform hardware that we have handled
647 * this entry and it is available for reuse again.
648 */
9ca21eb7 649 rt2800_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
a9b3a9f7
ID		 650}
651
652/*
653 * Interrupt functions.
654 */
4d66edc8
GW		 655static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
656{
657 struct ieee80211_conf conf = { .flags = 0 };
658 struct rt2x00lib_conf libconf = { .conf = &conf };
659
660 rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
661}
662
96c3da7d
HS		 663static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
664{
665 struct data_queue *queue;
666 struct queue_entry *entry;
667 u32 status;
668 u8 qid;
669
670 while (!kfifo_is_empty(&rt2x00dev->txstatus_fifo)) {
671 /* Now remove the tx status from the FIFO */
672 if (kfifo_out(&rt2x00dev->txstatus_fifo, &status,
673 sizeof(status)) != sizeof(status)) {
674 WARN_ON(1);
675 break;
676 }
677
678 qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_TYPE) - 1;
679 if (qid >= QID_RX) {
680 /*
681 * Unknown queue, this shouldn't happen. Just drop
682 * this tx status.
683 */
684 WARNING(rt2x00dev, "Got TX status report with "
685 "unexpected pid %u, dropping", qid);
686 break;
687 }
688
689 queue = rt2x00queue_get_queue(rt2x00dev, qid);
690 if (unlikely(queue == NULL)) {
691 /*
692 * The queue is NULL, this shouldn't happen. Stop
693 * processing here and drop the tx status
694 */
695 WARNING(rt2x00dev, "Got TX status for an unavailable "
696 "queue %u, dropping", qid);
697 break;
698 }
699
700 if (rt2x00queue_empty(queue)) {
701 /*
702 * The queue is empty. Stop processing here
703 * and drop the tx status.
704 */
705 WARNING(rt2x00dev, "Got TX status for an empty "
706 "queue %u, dropping", qid);
707 break;
708 }
709
710 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
711 rt2800_txdone_entry(entry, status);
712 }
713}
714
715static void rt2800pci_txstatus_tasklet(unsigned long data)
716{
717 rt2800pci_txdone((struct rt2x00_dev *)data);
718}
719
78e256c9 720static irqreturn_t rt2800pci_interrupt_thread(int irq, void *dev_instance)
a9b3a9f7
ID		 721{
722 struct rt2x00_dev *rt2x00dev = dev_instance;
78e256c9 723 u32 reg = rt2x00dev->irqvalue[0];
a9b3a9f7
ID		 724
725 /*
9f926fb5
HS		 726 * 1 - Pre TBTT interrupt.
727 */
728 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
729 rt2x00lib_pretbtt(rt2x00dev);
730
731 /*
732 * 2 - Beacondone interrupt.
733 */
734 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
735 rt2x00lib_beacondone(rt2x00dev);
736
737 /*
738 * 3 - Rx ring done interrupt.
a9b3a9f7
ID		 739 */
740 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
741 rt2x00pci_rxdone(rt2x00dev);
742
9f926fb5 743 /*
96c3da7d 744 * 4 - Auto wakeup interrupt.
ad90319b 745 */
4d66edc8
GW		 746 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
747 rt2800pci_wakeup(rt2x00dev);
748
78e256c9
HS		 749 /* Enable interrupts again. */
750 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
751 STATE_RADIO_IRQ_ON_ISR);
752
a9b3a9f7
ID		 753 return IRQ_HANDLED;
754}
755
96c3da7d
HS		 756static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
757{
758 u32 status;
759 int i;
760
761 /*
762 * The TX_FIFO_STATUS interrupt needs special care. We should
763 * read TX_STA_FIFO but we should do it immediately as otherwise
764 * the register can overflow and we would lose status reports.
765 *
766 * Hence, read the TX_STA_FIFO register and copy all tx status
767 * reports into a kernel FIFO which is handled in the txstatus
768 * tasklet. We use a tasklet to process the tx status reports
769 * because we can schedule the tasklet multiple times (when the
770 * interrupt fires again during tx status processing).
771 *
772 * Furthermore we don't disable the TX_FIFO_STATUS
773 * interrupt here but leave it enabled so that the TX_STA_FIFO
774 * can also be read while the interrupt thread gets executed.
775 *
776 * Since we have only one producer and one consumer we don't
777 * need to lock the kfifo.
778 */
779 for (i = 0; i < TX_ENTRIES; i++) {
780 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &status);
781
782 if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
783 break;
784
785 if (kfifo_is_full(&rt2x00dev->txstatus_fifo)) {
786 WARNING(rt2x00dev, "TX status FIFO overrun,"
787 " drop tx status report.\n");
788 break;
789 }
790
791 if (kfifo_in(&rt2x00dev->txstatus_fifo, &status,
792 sizeof(status)) != sizeof(status)) {
793 WARNING(rt2x00dev, "TX status FIFO overrun,"
794 "drop tx status report.\n");
795 break;
796 }
797 }
798
799 /* Schedule the tasklet for processing the tx status. */
800 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
801}
802
78e256c9
HS		 803static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
804{
805 struct rt2x00_dev *rt2x00dev = dev_instance;
806 u32 reg;
96c3da7d 807 irqreturn_t ret = IRQ_HANDLED;
78e256c9
HS		 808
809 /* Read status and ACK all interrupts */
810 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
811 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
812
813 if (!reg)
814 return IRQ_NONE;
815
816 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
817 return IRQ_HANDLED;
818
96c3da7d
HS		 819 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
820 rt2800pci_txstatus_interrupt(rt2x00dev);
78e256c9 821
96c3da7d
HS		 822 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT) ||
823 rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT) ||
824 rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE) ||
825 rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP)) {
826 /*
827 * All other interrupts are handled in the interrupt thread.
828 * Store irqvalue for use in the interrupt thread.
829 */
830 rt2x00dev->irqvalue[0] = reg;
831
832 /*
833 * Disable interrupts, will be enabled again in the
834 * interrupt thread.
835 */
836 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
837 STATE_RADIO_IRQ_OFF_ISR);
78e256c9 838
96c3da7d
HS		 839 /*
840 * Leave the TX_FIFO_STATUS interrupt enabled to not lose any
841 * tx status reports.
842 */
843 rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
844 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, 1);
845 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
846
847 ret = IRQ_WAKE_THREAD;
848 }
78e256c9 849
96c3da7d 850 return ret;
78e256c9
HS		 851}
852
a9b3a9f7
ID		 853/*
854 * Device probe functions.
855 */
7ab71325
BZ		 856static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
857{
858 /*
859 * Read EEPROM into buffer
860 */
cea90e55 861 if (rt2x00_is_soc(rt2x00dev))
7ab71325 862 rt2800pci_read_eeprom_soc(rt2x00dev);
cea90e55
GW		 863 else if (rt2800pci_efuse_detect(rt2x00dev))
864 rt2800pci_read_eeprom_efuse(rt2x00dev);
865 else
866 rt2800pci_read_eeprom_pci(rt2x00dev);
7ab71325
BZ		 867
868 return rt2800_validate_eeprom(rt2x00dev);
869}
870
a9b3a9f7
ID		 871static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
872{
873 int retval;
874
875 /*
876 * Allocate eeprom data.
877 */
878 retval = rt2800pci_validate_eeprom(rt2x00dev);
879 if (retval)
880 return retval;
881
38bd7b8a 882 retval = rt2800_init_eeprom(rt2x00dev);
a9b3a9f7
ID		 883 if (retval)
884 return retval;
885
886 /*
887 * Initialize hw specifications.
888 */
4da2933f 889 retval = rt2800_probe_hw_mode(rt2x00dev);
a9b3a9f7
ID		 890 if (retval)
891 return retval;
892
893 /*
894 * This device has multiple filters for control frames
895 * and has a separate filter for PS Poll frames.
896 */
897 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
898 __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
899
9f926fb5
HS		 900 /*
901 * This device has a pre tbtt interrupt and thus fetches
902 * a new beacon directly prior to transmission.
903 */
904 __set_bit(DRIVER_SUPPORT_PRE_TBTT_INTERRUPT, &rt2x00dev->flags);
905
a9b3a9f7
ID		 906 /*
907 * This device requires firmware.
908 */
cea90e55 909 if (!rt2x00_is_soc(rt2x00dev))
a9b3a9f7
ID		 910 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
911 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
912 __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
96c3da7d 913 __set_bit(DRIVER_REQUIRE_TXSTATUS_FIFO, &rt2x00dev->flags);
a9b3a9f7
ID		 914 if (!modparam_nohwcrypt)
915 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
27df2a9c 916 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
a9b3a9f7
ID		 917
918 /*
919 * Set the rssi offset.
920 */
921 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
922
923 return 0;
924}
925
e783619e
HS		 926static const struct ieee80211_ops rt2800pci_mac80211_ops = {
927 .tx = rt2x00mac_tx,
928 .start = rt2x00mac_start,
929 .stop = rt2x00mac_stop,
930 .add_interface = rt2x00mac_add_interface,
931 .remove_interface = rt2x00mac_remove_interface,
932 .config = rt2x00mac_config,
933 .configure_filter = rt2x00mac_configure_filter,
e783619e
HS		 934 .set_key = rt2x00mac_set_key,
935 .sw_scan_start = rt2x00mac_sw_scan_start,
936 .sw_scan_complete = rt2x00mac_sw_scan_complete,
937 .get_stats = rt2x00mac_get_stats,
938 .get_tkip_seq = rt2800_get_tkip_seq,
939 .set_rts_threshold = rt2800_set_rts_threshold,
940 .bss_info_changed = rt2x00mac_bss_info_changed,
941 .conf_tx = rt2800_conf_tx,
942 .get_tsf = rt2800_get_tsf,
943 .rfkill_poll = rt2x00mac_rfkill_poll,
944 .ampdu_action = rt2800_ampdu_action,
945};
946
e796643e
ID		 947static const struct rt2800_ops rt2800pci_rt2800_ops = {
948 .register_read = rt2x00pci_register_read,
949 .register_read_lock = rt2x00pci_register_read, /* same for PCI */
950 .register_write = rt2x00pci_register_write,
951 .register_write_lock = rt2x00pci_register_write, /* same for PCI */
952 .register_multiread = rt2x00pci_register_multiread,
953 .register_multiwrite = rt2x00pci_register_multiwrite,
954 .regbusy_read = rt2x00pci_regbusy_read,
955 .drv_write_firmware = rt2800pci_write_firmware,
956 .drv_init_registers = rt2800pci_init_registers,
0c5879bc 957 .drv_get_txwi = rt2800pci_get_txwi,
e796643e
ID		 958};
959
a9b3a9f7
ID		 960static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
961 .irq_handler = rt2800pci_interrupt,
78e256c9 962 .irq_handler_thread = rt2800pci_interrupt_thread,
96c3da7d 963 .txstatus_tasklet = rt2800pci_txstatus_tasklet,
a9b3a9f7
ID		 964 .probe_hw = rt2800pci_probe_hw,
965 .get_firmware_name = rt2800pci_get_firmware_name,
f31c9a8c
ID		 966 .check_firmware = rt2800_check_firmware,
967 .load_firmware = rt2800_load_firmware,
a9b3a9f7
ID		 968 .initialize = rt2x00pci_initialize,
969 .uninitialize = rt2x00pci_uninitialize,
970 .get_entry_state = rt2800pci_get_entry_state,
971 .clear_entry = rt2800pci_clear_entry,
972 .set_device_state = rt2800pci_set_device_state,
f4450616
BZ		 973 .rfkill_poll = rt2800_rfkill_poll,
974 .link_stats = rt2800_link_stats,
975 .reset_tuner = rt2800_reset_tuner,
976 .link_tuner = rt2800_link_tuner,
a9b3a9f7 977 .write_tx_desc = rt2800pci_write_tx_desc,
0c5879bc 978 .write_tx_data = rt2800_write_tx_data,
f0194b2d 979 .write_beacon = rt2800_write_beacon,
a9b3a9f7
ID		 980 .kick_tx_queue = rt2800pci_kick_tx_queue,
981 .kill_tx_queue = rt2800pci_kill_tx_queue,
982 .fill_rxdone = rt2800pci_fill_rxdone,
f4450616
BZ		 983 .config_shared_key = rt2800_config_shared_key,
984 .config_pairwise_key = rt2800_config_pairwise_key,
985 .config_filter = rt2800_config_filter,
986 .config_intf = rt2800_config_intf,
987 .config_erp = rt2800_config_erp,
988 .config_ant = rt2800_config_ant,
989 .config = rt2800_config,
a9b3a9f7
ID		 990};
991
992static const struct data_queue_desc rt2800pci_queue_rx = {
993 .entry_num = RX_ENTRIES,
994 .data_size = AGGREGATION_SIZE,
995 .desc_size = RXD_DESC_SIZE,
996 .priv_size = sizeof(struct queue_entry_priv_pci),
997};
998
999static const struct data_queue_desc rt2800pci_queue_tx = {
1000 .entry_num = TX_ENTRIES,
1001 .data_size = AGGREGATION_SIZE,
1002 .desc_size = TXD_DESC_SIZE,
1003 .priv_size = sizeof(struct queue_entry_priv_pci),
1004};
1005
1006static const struct data_queue_desc rt2800pci_queue_bcn = {
1007 .entry_num = 8 * BEACON_ENTRIES,
1008 .data_size = 0, /* No DMA required for beacons */
1009 .desc_size = TXWI_DESC_SIZE,
1010 .priv_size = sizeof(struct queue_entry_priv_pci),
1011};
1012
1013static const struct rt2x00_ops rt2800pci_ops = {
04d0362e
GW		 1014 .name = KBUILD_MODNAME,
1015 .max_sta_intf = 1,
1016 .max_ap_intf = 8,
1017 .eeprom_size = EEPROM_SIZE,
1018 .rf_size = RF_SIZE,
1019 .tx_queues = NUM_TX_QUEUES,
e6218cc4 1020 .extra_tx_headroom = TXWI_DESC_SIZE,
04d0362e
GW		 1021 .rx = &rt2800pci_queue_rx,
1022 .tx = &rt2800pci_queue_tx,
1023 .bcn = &rt2800pci_queue_bcn,
1024 .lib = &rt2800pci_rt2x00_ops,
e796643e 1025 .drv = &rt2800pci_rt2800_ops,
e783619e 1026 .hw = &rt2800pci_mac80211_ops,
a9b3a9f7 1027#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 1028 .debugfs = &rt2800_rt2x00debug,
a9b3a9f7
ID		 1029#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1030};
1031
1032/*
1033 * RT2800pci module information.
1034 */
d6e36ec1 1035#ifdef CONFIG_RT2800PCI_PCI
a3aa1884 1036static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
de1ebdce
GW		 1037 { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
1038 { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
1039 { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
1040 { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
a9b3a9f7
ID		 1041 { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
1042 { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
1043 { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
1044 { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
1045 { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
1046 { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
1047 { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
de1ebdce
GW		 1048 { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
1049#ifdef CONFIG_RT2800PCI_RT30XX
a9b3a9f7
ID		 1050 { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
1051 { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
1052 { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
de1ebdce
GW		 1053 { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
1054#endif
1055#ifdef CONFIG_RT2800PCI_RT35XX
1056 { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
1057 { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
a9b3a9f7
ID		 1058 { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
1059 { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
6424bf70 1060 { PCI_DEVICE(0x1814, 0x3593), PCI_DEVICE_DATA(&rt2800pci_ops) },
de1ebdce 1061#endif
a9b3a9f7
ID		 1062 { 0, }
1063};
d6e36ec1 1064#endif /* CONFIG_RT2800PCI_PCI */
a9b3a9f7
ID		 1065
1066MODULE_AUTHOR(DRV_PROJECT);
1067MODULE_VERSION(DRV_VERSION);
1068MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1069MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1070#ifdef CONFIG_RT2800PCI_PCI
1071MODULE_FIRMWARE(FIRMWARE_RT2860);
1072MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1073#endif /* CONFIG_RT2800PCI_PCI */
1074MODULE_LICENSE("GPL");
1075
00e23ce2 1076#ifdef CONFIG_RT2800PCI_SOC
714fa663
GW		 1077static int rt2800soc_probe(struct platform_device *pdev)
1078{
6e93d719 1079 return rt2x00soc_probe(pdev, &rt2800pci_ops);
714fa663 1080}
a9b3a9f7
ID		 1081
1082static struct platform_driver rt2800soc_driver = {
1083 .driver = {
1084 .name = "rt2800_wmac",
1085 .owner = THIS_MODULE,
1086 .mod_name = KBUILD_MODNAME,
1087 },
714fa663 1088 .probe = rt2800soc_probe,
a9b3a9f7
ID		 1089 .remove = __devexit_p(rt2x00soc_remove),
1090 .suspend = rt2x00soc_suspend,
1091 .resume = rt2x00soc_resume,
1092};
00e23ce2 1093#endif /* CONFIG_RT2800PCI_SOC */
a9b3a9f7
ID		 1094
1095#ifdef CONFIG_RT2800PCI_PCI
1096static struct pci_driver rt2800pci_driver = {
1097 .name = KBUILD_MODNAME,
1098 .id_table = rt2800pci_device_table,
1099 .probe = rt2x00pci_probe,
1100 .remove = __devexit_p(rt2x00pci_remove),
1101 .suspend = rt2x00pci_suspend,
1102 .resume = rt2x00pci_resume,
1103};
1104#endif /* CONFIG_RT2800PCI_PCI */
1105
1106static int __init rt2800pci_init(void)
1107{
1108 int ret = 0;
1109
00e23ce2 1110#ifdef CONFIG_RT2800PCI_SOC
a9b3a9f7
ID		 1111 ret = platform_driver_register(&rt2800soc_driver);
1112 if (ret)
1113 return ret;
1114#endif
1115#ifdef CONFIG_RT2800PCI_PCI
1116 ret = pci_register_driver(&rt2800pci_driver);
1117 if (ret) {
00e23ce2 1118#ifdef CONFIG_RT2800PCI_SOC
a9b3a9f7
ID		 1119 platform_driver_unregister(&rt2800soc_driver);
1120#endif
1121 return ret;
1122 }
1123#endif
1124
1125 return ret;
1126}
1127
1128static void __exit rt2800pci_exit(void)
1129{
1130#ifdef CONFIG_RT2800PCI_PCI
1131 pci_unregister_driver(&rt2800pci_driver);
1132#endif
00e23ce2 1133#ifdef CONFIG_RT2800PCI_SOC
a9b3a9f7
ID		 1134 platform_driver_unregister(&rt2800soc_driver);
1135#endif
1136}
1137
1138module_init(rt2800pci_init);
1139module_exit(rt2800pci_exit);
Linux kernel - Deliverables
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