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rt2x00: rt2800pci: move queue functions to the rt2800mmio module
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2800pci.c
CommitLineData
a9b3a9f7 1/*
96481b20 2 Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14
GW		 3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
a9b3a9f7
ID		 10 <http://rt2x00.serialmonkey.com>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 */
27
28/*
29 Module: rt2800pci
30 Abstract: rt2800pci device specific routines.
31 Supported chipsets: RT2800E & RT2800ED.
32 */
33
a9b3a9f7
ID		 34#include <linux/delay.h>
35#include <linux/etherdevice.h>
36#include <linux/init.h>
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/pci.h>
40#include <linux/platform_device.h>
41#include <linux/eeprom_93cx6.h>
42
43#include "rt2x00.h"
69a2bac8 44#include "rt2x00mmio.h"
a9b3a9f7
ID		 45#include "rt2x00pci.h"
46#include "rt2x00soc.h"
7ef5cc92 47#include "rt2800lib.h"
0bc202b3 48#include "rt2800mmio.h"
b54f78a8 49#include "rt2800.h"
a9b3a9f7
ID		 50#include "rt2800pci.h"
51
a9b3a9f7
ID		 52/*
53 * Allow hardware encryption to be disabled.
54 */
eb939922 55static bool modparam_nohwcrypt = false;
a9b3a9f7
ID		 56module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
57MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
58
ad417a53
GW		 59static bool rt2800pci_hwcrypt_disabled(struct rt2x00_dev *rt2x00dev)
60{
61 return modparam_nohwcrypt;
62}
63
a9b3a9f7
ID		 64static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
65{
66 unsigned int i;
67 u32 reg;
68
f18d4463
LC		 69 /*
70 * SOC devices don't support MCU requests.
71 */
72 if (rt2x00_is_soc(rt2x00dev))
73 return;
74
a9b3a9f7 75 for (i = 0; i < 200; i++) {
b9570b66 76 rt2x00mmio_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
a9b3a9f7
ID		 77
78 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
79 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
80 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
81 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
82 break;
83
84 udelay(REGISTER_BUSY_DELAY);
85 }
86
87 if (i == 200)
ec9c4989 88 rt2x00_err(rt2x00dev, "MCU request failed, no response from hardware\n");
a9b3a9f7 89
b9570b66
GJ		 90 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
91 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
a9b3a9f7
ID		 92}
93
5818a46a 94#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
a02308e9 95static int rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 96{
ef8397cf 97 void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
a9b3a9f7 98
a02308e9
GJ		 99 if (!base_addr)
100 return -ENOMEM;
101
a9b3a9f7 102 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
ef8397cf
GW		 103
104 iounmap(base_addr);
a02308e9 105 return 0;
a9b3a9f7
ID		 106}
107#else
a02308e9 108static inline int rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 109{
a02308e9 110 return -ENOMEM;
a9b3a9f7 111}
5818a46a 112#endif /* CONFIG_SOC_RT288X || CONFIG_SOC_RT305X */
a9b3a9f7 113
72c7296e 114#ifdef CONFIG_PCI
a9b3a9f7
ID		 115static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
116{
117 struct rt2x00_dev *rt2x00dev = eeprom->data;
118 u32 reg;
119
b9570b66 120 rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 121
122 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
123 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
124 eeprom->reg_data_clock =
125 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
126 eeprom->reg_chip_select =
127 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
128}
129
130static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
131{
132 struct rt2x00_dev *rt2x00dev = eeprom->data;
133 u32 reg = 0;
134
135 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
136 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
137 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
138 !!eeprom->reg_data_clock);
139 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
140 !!eeprom->reg_chip_select);
141
b9570b66 142 rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg);
a9b3a9f7
ID		 143}
144
a02308e9 145static int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
a9b3a9f7
ID		 146{
147 struct eeprom_93cx6 eeprom;
148 u32 reg;
149
b9570b66 150 rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 151
152 eeprom.data = rt2x00dev;
153 eeprom.register_read = rt2800pci_eepromregister_read;
154 eeprom.register_write = rt2800pci_eepromregister_write;
20f8b139
GW		 155 switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
156 {
157 case 0:
158 eeprom.width = PCI_EEPROM_WIDTH_93C46;
159 break;
160 case 1:
161 eeprom.width = PCI_EEPROM_WIDTH_93C66;
162 break;
163 default:
164 eeprom.width = PCI_EEPROM_WIDTH_93C86;
165 break;
166 }
a9b3a9f7
ID		 167 eeprom.reg_data_in = 0;
168 eeprom.reg_data_out = 0;
169 eeprom.reg_data_clock = 0;
170 eeprom.reg_chip_select = 0;
171
172 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
173 EEPROM_SIZE / sizeof(u16));
a02308e9
GJ		 174
175 return 0;
a9b3a9f7
ID		 176}
177
a6598682
GW		 178static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
179{
30e84034 180 return rt2800_efuse_detect(rt2x00dev);
a9b3a9f7
ID		 181}
182
a02308e9 183static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 184{
a02308e9 185 return rt2800_read_eeprom_efuse(rt2x00dev);
a9b3a9f7
ID		 186}
187#else
a02308e9 188static inline int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 189{
a02308e9 190 return -EOPNOTSUPP;
a9b3a9f7
ID		 191}
192
a6598682
GW		 193static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
194{
195 return 0;
196}
197
a02308e9 198static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 199{
a02308e9 200 return -EOPNOTSUPP;
a9b3a9f7 201}
72c7296e 202#endif /* CONFIG_PCI */
a9b3a9f7 203
a9b3a9f7
ID		 204/*
205 * Firmware functions
206 */
207static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
208{
a89534ed
WH		 209 /*
210 * Chip rt3290 use specific 4KB firmware named rt3290.bin.
211 */
212 if (rt2x00_rt(rt2x00dev, RT3290))
213 return FIRMWARE_RT3290;
214 else
215 return FIRMWARE_RT2860;
a9b3a9f7
ID		 216}
217
f31c9a8c 218static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
a9b3a9f7
ID		 219 const u8 *data, const size_t len)
220{
a9b3a9f7
ID		 221 u32 reg;
222
a9b3a9f7
ID		 223 /*
224 * enable Host program ram write selection
225 */
226 reg = 0;
227 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
b9570b66 228 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
a9b3a9f7
ID		 229
230 /*
231 * Write firmware to device.
232 */
b9570b66
GJ		 233 rt2x00mmio_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
234 data, len);
a9b3a9f7 235
b9570b66
GJ		 236 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
237 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
a9b3a9f7 238
b9570b66
GJ		 239 rt2x00mmio_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
240 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
a9b3a9f7
ID		 241
242 return 0;
243}
244
245/*
246 * Initialization functions.
247 */
248static bool rt2800pci_get_entry_state(struct queue_entry *entry)
249{
b9570b66 250 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
a9b3a9f7
ID		 251 u32 word;
252
253 if (entry->queue->qid == QID_RX) {
254 rt2x00_desc_read(entry_priv->desc, 1, &word);
255
256 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
257 } else {
258 rt2x00_desc_read(entry_priv->desc, 1, &word);
259
260 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
261 }
262}
263
264static void rt2800pci_clear_entry(struct queue_entry *entry)
265{
b9570b66 266 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
a9b3a9f7 267 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95192339 268 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
a9b3a9f7
ID		 269 u32 word;
270
271 if (entry->queue->qid == QID_RX) {
272 rt2x00_desc_read(entry_priv->desc, 0, &word);
273 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
274 rt2x00_desc_write(entry_priv->desc, 0, word);
275
276 rt2x00_desc_read(entry_priv->desc, 1, &word);
277 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
278 rt2x00_desc_write(entry_priv->desc, 1, word);
95192339
HS		 279
280 /*
281 * Set RX IDX in register to inform hardware that we have
282 * handled this entry and it is available for reuse again.
283 */
b9570b66
GJ		 284 rt2x00mmio_register_write(rt2x00dev, RX_CRX_IDX,
285 entry->entry_idx);
a9b3a9f7
ID		 286 } else {
287 rt2x00_desc_read(entry_priv->desc, 1, &word);
288 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
289 rt2x00_desc_write(entry_priv->desc, 1, word);
290 }
291}
292
293static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
294{
b9570b66 295 struct queue_entry_priv_mmio *entry_priv;
a9b3a9f7 296
a9b3a9f7
ID		 297 /*
298 * Initialize registers.
299 */
300 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
b9570b66
GJ		 301 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR0,
302 entry_priv->desc_dma);
303 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT0,
304 rt2x00dev->tx[0].limit);
305 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX0, 0);
306 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX0, 0);
a9b3a9f7
ID		 307
308 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
b9570b66
GJ		 309 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR1,
310 entry_priv->desc_dma);
311 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT1,
312 rt2x00dev->tx[1].limit);
313 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX1, 0);
314 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX1, 0);
a9b3a9f7
ID		 315
316 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
b9570b66
GJ		 317 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR2,
318 entry_priv->desc_dma);
319 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT2,
320 rt2x00dev->tx[2].limit);
321 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX2, 0);
322 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX2, 0);
a9b3a9f7
ID		 323
324 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
b9570b66
GJ		 325 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR3,
326 entry_priv->desc_dma);
327 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT3,
328 rt2x00dev->tx[3].limit);
329 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX3, 0);
330 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX3, 0);
331
332 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR4, 0);
333 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT4, 0);
334 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX4, 0);
335 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX4, 0);
336
337 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR5, 0);
338 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT5, 0);
339 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX5, 0);
340 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX5, 0);
3a4b43fd 341
a9b3a9f7 342 entry_priv = rt2x00dev->rx->entries[0].priv_data;
b9570b66
GJ		 343 rt2x00mmio_register_write(rt2x00dev, RX_BASE_PTR,
344 entry_priv->desc_dma);
345 rt2x00mmio_register_write(rt2x00dev, RX_MAX_CNT,
346 rt2x00dev->rx[0].limit);
347 rt2x00mmio_register_write(rt2x00dev, RX_CRX_IDX,
348 rt2x00dev->rx[0].limit - 1);
349 rt2x00mmio_register_write(rt2x00dev, RX_DRX_IDX, 0);
a9b3a9f7 350
f7b395e9 351 rt2800_disable_wpdma(rt2x00dev);
a9b3a9f7 352
b9570b66 353 rt2x00mmio_register_write(rt2x00dev, DELAY_INT_CFG, 0);
a9b3a9f7
ID		 354
355 return 0;
356}
357
a9b3a9f7
ID		 358/*
359 * Device state switch handlers.
360 */
e3a896b9
GW		 361static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
362{
363 u32 reg;
364
365 /*
366 * Reset DMA indexes
367 */
b9570b66 368 rt2x00mmio_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
e3a896b9
GW		 369 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
370 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
371 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
372 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
373 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
374 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
375 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
b9570b66 376 rt2x00mmio_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
e3a896b9 377
b9570b66
GJ		 378 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
379 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
e3a896b9 380
872834df 381 if (rt2x00_is_pcie(rt2x00dev) &&
41caa760
GJ		 382 (rt2x00_rt(rt2x00dev, RT3090) ||
383 rt2x00_rt(rt2x00dev, RT3390) ||
384 rt2x00_rt(rt2x00dev, RT3572) ||
385 rt2x00_rt(rt2x00dev, RT3593) ||
2ed71884 386 rt2x00_rt(rt2x00dev, RT5390) ||
41caa760
GJ		 387 rt2x00_rt(rt2x00dev, RT5392) ||
388 rt2x00_rt(rt2x00dev, RT5592))) {
b9570b66 389 rt2x00mmio_register_read(rt2x00dev, AUX_CTRL, &reg);
adde5882
GJ		 390 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
391 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
b9570b66 392 rt2x00mmio_register_write(rt2x00dev, AUX_CTRL, reg);
adde5882 393 }
60687ba7 394
b9570b66 395 rt2x00mmio_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
e3a896b9 396
2a48e8ae 397 reg = 0;
e3a896b9
GW		 398 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
399 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
b9570b66 400 rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
e3a896b9 401
b9570b66 402 rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
e3a896b9
GW		 403
404 return 0;
405}
406
a9b3a9f7
ID		 407static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
408{
e8b461c3
JK		 409 int retval;
410
52b8243b
JK		 411 /* Wait for DMA, ignore error until we initialize queues. */
412 rt2800_wait_wpdma_ready(rt2x00dev);
413
414 if (unlikely(rt2800pci_init_queues(rt2x00dev)))
a9b3a9f7
ID		 415 return -EIO;
416
e8b461c3
JK		 417 retval = rt2800_enable_radio(rt2x00dev);
418 if (retval)
419 return retval;
420
421 /* After resume MCU_BOOT_SIGNAL will trash these. */
b9570b66
GJ		 422 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
423 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
e8b461c3
JK		 424
425 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_RADIO_OFF, 0xff, 0x02);
426 rt2800pci_mcu_status(rt2x00dev, TOKEN_RADIO_OFF);
427
428 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP, 0, 0);
429 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
430
431 return retval;
a9b3a9f7
ID		 432}
433
434static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
435{
7f6e144f
RJH		 436 if (rt2x00_is_soc(rt2x00dev)) {
437 rt2800_disable_radio(rt2x00dev);
b9570b66
GJ		 438 rt2x00mmio_register_write(rt2x00dev, PWR_PIN_CFG, 0);
439 rt2x00mmio_register_write(rt2x00dev, TX_PIN_CFG, 0);
7f6e144f 440 }
a9b3a9f7
ID		 441}
442
443static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
444 enum dev_state state)
445{
a9b3a9f7 446 if (state == STATE_AWAKE) {
09a3311c
JK		 447 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP,
448 0, 0x02);
449 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
7f6e144f 450 } else if (state == STATE_SLEEP) {
b9570b66
GJ		 451 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
452 0xffffffff);
453 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID,
454 0xffffffff);
09a3311c
JK		 455 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_SLEEP,
456 0xff, 0x01);
a9b3a9f7
ID		 457 }
458
459 return 0;
460}
461
462static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
463 enum dev_state state)
464{
465 int retval = 0;
466
467 switch (state) {
468 case STATE_RADIO_ON:
a9b3a9f7
ID		 469 retval = rt2800pci_enable_radio(rt2x00dev);
470 break;
471 case STATE_RADIO_OFF:
472 /*
473 * After the radio has been disabled, the device should
474 * be put to sleep for powersaving.
475 */
476 rt2800pci_disable_radio(rt2x00dev);
477 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
478 break;
a9b3a9f7
ID		 479 case STATE_RADIO_IRQ_ON:
480 case STATE_RADIO_IRQ_OFF:
b5cfde3f 481 rt2800mmio_toggle_irq(rt2x00dev, state);
a9b3a9f7
ID		 482 break;
483 case STATE_DEEP_SLEEP:
484 case STATE_SLEEP:
485 case STATE_STANDBY:
486 case STATE_AWAKE:
487 retval = rt2800pci_set_state(rt2x00dev, state);
488 break;
489 default:
490 retval = -ENOTSUPP;
491 break;
492 }
493
494 if (unlikely(retval))
ec9c4989
JP		 495 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
496 state, retval);
a9b3a9f7
ID		 497
498 return retval;
499}
500
a9b3a9f7
ID		 501/*
502 * Device probe functions.
503 */
a02308e9 504static int rt2800pci_read_eeprom(struct rt2x00_dev *rt2x00dev)
7ab71325 505{
a02308e9
GJ		 506 int retval;
507
cea90e55 508 if (rt2x00_is_soc(rt2x00dev))
a02308e9 509 retval = rt2800pci_read_eeprom_soc(rt2x00dev);
cea90e55 510 else if (rt2800pci_efuse_detect(rt2x00dev))
a02308e9 511 retval = rt2800pci_read_eeprom_efuse(rt2x00dev);
cea90e55 512 else
a02308e9
GJ		 513 retval = rt2800pci_read_eeprom_pci(rt2x00dev);
514
515 return retval;
a9b3a9f7
ID		 516}
517
e783619e
HS		 518static const struct ieee80211_ops rt2800pci_mac80211_ops = {
519 .tx = rt2x00mac_tx,
520 .start = rt2x00mac_start,
521 .stop = rt2x00mac_stop,
522 .add_interface = rt2x00mac_add_interface,
523 .remove_interface = rt2x00mac_remove_interface,
524 .config = rt2x00mac_config,
525 .configure_filter = rt2x00mac_configure_filter,
e783619e
HS		 526 .set_key = rt2x00mac_set_key,
527 .sw_scan_start = rt2x00mac_sw_scan_start,
528 .sw_scan_complete = rt2x00mac_sw_scan_complete,
529 .get_stats = rt2x00mac_get_stats,
530 .get_tkip_seq = rt2800_get_tkip_seq,
531 .set_rts_threshold = rt2800_set_rts_threshold,
a2b1328a
HS		 532 .sta_add = rt2x00mac_sta_add,
533 .sta_remove = rt2x00mac_sta_remove,
e783619e
HS		 534 .bss_info_changed = rt2x00mac_bss_info_changed,
535 .conf_tx = rt2800_conf_tx,
536 .get_tsf = rt2800_get_tsf,
537 .rfkill_poll = rt2x00mac_rfkill_poll,
538 .ampdu_action = rt2800_ampdu_action,
f44df18c 539 .flush = rt2x00mac_flush,
977206d7 540 .get_survey = rt2800_get_survey,
e7dee444 541 .get_ringparam = rt2x00mac_get_ringparam,
5f0dd296 542 .tx_frames_pending = rt2x00mac_tx_frames_pending,
e783619e
HS		 543};
544
e796643e 545static const struct rt2800_ops rt2800pci_rt2800_ops = {
b9570b66
GJ		 546 .register_read = rt2x00mmio_register_read,
547 .register_read_lock = rt2x00mmio_register_read, /* same for PCI */
548 .register_write = rt2x00mmio_register_write,
549 .register_write_lock = rt2x00mmio_register_write, /* same for PCI */
550 .register_multiread = rt2x00mmio_register_multiread,
551 .register_multiwrite = rt2x00mmio_register_multiwrite,
552 .regbusy_read = rt2x00mmio_regbusy_read,
ad417a53
GW		 553 .read_eeprom = rt2800pci_read_eeprom,
554 .hwcrypt_disabled = rt2800pci_hwcrypt_disabled,
e796643e
ID		 555 .drv_write_firmware = rt2800pci_write_firmware,
556 .drv_init_registers = rt2800pci_init_registers,
45c67550 557 .drv_get_txwi = rt2800mmio_get_txwi,
e796643e
ID		 558};
559
a9b3a9f7 560static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
b5cfde3f
GJ		 561 .irq_handler = rt2800mmio_interrupt,
562 .txstatus_tasklet = rt2800mmio_txstatus_tasklet,
563 .pretbtt_tasklet = rt2800mmio_pretbtt_tasklet,
564 .tbtt_tasklet = rt2800mmio_tbtt_tasklet,
565 .rxdone_tasklet = rt2800mmio_rxdone_tasklet,
566 .autowake_tasklet = rt2800mmio_autowake_tasklet,
ad417a53 567 .probe_hw = rt2800_probe_hw,
a9b3a9f7 568 .get_firmware_name = rt2800pci_get_firmware_name,
f31c9a8c
ID		 569 .check_firmware = rt2800_check_firmware,
570 .load_firmware = rt2800_load_firmware,
b9570b66
GJ		 571 .initialize = rt2x00mmio_initialize,
572 .uninitialize = rt2x00mmio_uninitialize,
a9b3a9f7
ID		 573 .get_entry_state = rt2800pci_get_entry_state,
574 .clear_entry = rt2800pci_clear_entry,
575 .set_device_state = rt2800pci_set_device_state,
f4450616
BZ		 576 .rfkill_poll = rt2800_rfkill_poll,
577 .link_stats = rt2800_link_stats,
578 .reset_tuner = rt2800_reset_tuner,
579 .link_tuner = rt2800_link_tuner,
9e33a355 580 .gain_calibration = rt2800_gain_calibration,
2e9c43dd 581 .vco_calibration = rt2800_vco_calibration,
51e62469
GJ		 582 .start_queue = rt2800mmio_start_queue,
583 .kick_queue = rt2800mmio_kick_queue,
584 .stop_queue = rt2800mmio_stop_queue,
b9570b66 585 .flush_queue = rt2x00mmio_flush_queue,
45c67550 586 .write_tx_desc = rt2800mmio_write_tx_desc,
0c5879bc 587 .write_tx_data = rt2800_write_tx_data,
f0194b2d 588 .write_beacon = rt2800_write_beacon,
69cf36a4 589 .clear_beacon = rt2800_clear_beacon,
d10b7547 590 .fill_rxdone = rt2800mmio_fill_rxdone,
f4450616
BZ		 591 .config_shared_key = rt2800_config_shared_key,
592 .config_pairwise_key = rt2800_config_pairwise_key,
593 .config_filter = rt2800_config_filter,
594 .config_intf = rt2800_config_intf,
595 .config_erp = rt2800_config_erp,
596 .config_ant = rt2800_config_ant,
597 .config = rt2800_config,
a2b1328a
HS		 598 .sta_add = rt2800_sta_add,
599 .sta_remove = rt2800_sta_remove,
a9b3a9f7
ID		 600};
601
a9b3a9f7 602static const struct rt2x00_ops rt2800pci_ops = {
04d0362e 603 .name = KBUILD_MODNAME,
3a1c0128 604 .drv_data_size = sizeof(struct rt2800_drv_data),
04d0362e
GW		 605 .max_ap_intf = 8,
606 .eeprom_size = EEPROM_SIZE,
607 .rf_size = RF_SIZE,
608 .tx_queues = NUM_TX_QUEUES,
51e62469 609 .queue_init = rt2800mmio_queue_init,
04d0362e 610 .lib = &rt2800pci_rt2x00_ops,
e796643e 611 .drv = &rt2800pci_rt2800_ops,
e783619e 612 .hw = &rt2800pci_mac80211_ops,
a9b3a9f7 613#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 614 .debugfs = &rt2800_rt2x00debug,
a9b3a9f7
ID		 615#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
616};
617
618/*
619 * RT2800pci module information.
620 */
72c7296e 621#ifdef CONFIG_PCI
a3aa1884 622static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
e01ae27f
GW		 623 { PCI_DEVICE(0x1814, 0x0601) },
624 { PCI_DEVICE(0x1814, 0x0681) },
625 { PCI_DEVICE(0x1814, 0x0701) },
626 { PCI_DEVICE(0x1814, 0x0781) },
627 { PCI_DEVICE(0x1814, 0x3090) },
628 { PCI_DEVICE(0x1814, 0x3091) },
629 { PCI_DEVICE(0x1814, 0x3092) },
630 { PCI_DEVICE(0x1432, 0x7708) },
631 { PCI_DEVICE(0x1432, 0x7727) },
632 { PCI_DEVICE(0x1432, 0x7728) },
633 { PCI_DEVICE(0x1432, 0x7738) },
634 { PCI_DEVICE(0x1432, 0x7748) },
635 { PCI_DEVICE(0x1432, 0x7758) },
636 { PCI_DEVICE(0x1432, 0x7768) },
637 { PCI_DEVICE(0x1462, 0x891a) },
638 { PCI_DEVICE(0x1a3b, 0x1059) },
a89534ed
WH		 639#ifdef CONFIG_RT2800PCI_RT3290
640 { PCI_DEVICE(0x1814, 0x3290) },
641#endif
f93bc9b3 642#ifdef CONFIG_RT2800PCI_RT33XX
e01ae27f 643 { PCI_DEVICE(0x1814, 0x3390) },
f93bc9b3 644#endif
de1ebdce 645#ifdef CONFIG_RT2800PCI_RT35XX
e01ae27f
GW		 646 { PCI_DEVICE(0x1432, 0x7711) },
647 { PCI_DEVICE(0x1432, 0x7722) },
648 { PCI_DEVICE(0x1814, 0x3060) },
649 { PCI_DEVICE(0x1814, 0x3062) },
650 { PCI_DEVICE(0x1814, 0x3562) },
651 { PCI_DEVICE(0x1814, 0x3592) },
652 { PCI_DEVICE(0x1814, 0x3593) },
c4806014 653 { PCI_DEVICE(0x1814, 0x359f) },
60687ba7
RST		 654#endif
655#ifdef CONFIG_RT2800PCI_RT53XX
ccf91bd6 656 { PCI_DEVICE(0x1814, 0x5360) },
f57d7b6c 657 { PCI_DEVICE(0x1814, 0x5362) },
e01ae27f 658 { PCI_DEVICE(0x1814, 0x5390) },
f57d7b6c 659 { PCI_DEVICE(0x1814, 0x5392) },
5126d97e 660 { PCI_DEVICE(0x1814, 0x539a) },
2aed6915 661 { PCI_DEVICE(0x1814, 0x539b) },
71e0b38c 662 { PCI_DEVICE(0x1814, 0x539f) },
de1ebdce 663#endif
a9b3a9f7
ID		 664 { 0, }
665};
72c7296e 666#endif /* CONFIG_PCI */
a9b3a9f7
ID		 667
668MODULE_AUTHOR(DRV_PROJECT);
669MODULE_VERSION(DRV_VERSION);
670MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
671MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
72c7296e 672#ifdef CONFIG_PCI
a9b3a9f7
ID		 673MODULE_FIRMWARE(FIRMWARE_RT2860);
674MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
72c7296e 675#endif /* CONFIG_PCI */
a9b3a9f7
ID		 676MODULE_LICENSE("GPL");
677
5818a46a 678#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
714fa663
GW		 679static int rt2800soc_probe(struct platform_device *pdev)
680{
6e93d719 681 return rt2x00soc_probe(pdev, &rt2800pci_ops);
714fa663 682}
a9b3a9f7
ID		 683
684static struct platform_driver rt2800soc_driver = {
685 .driver = {
686 .name = "rt2800_wmac",
687 .owner = THIS_MODULE,
688 .mod_name = KBUILD_MODNAME,
689 },
714fa663 690 .probe = rt2800soc_probe,
69202359 691 .remove = rt2x00soc_remove,
a9b3a9f7
ID		 692 .suspend = rt2x00soc_suspend,
693 .resume = rt2x00soc_resume,
694};
5818a46a 695#endif /* CONFIG_SOC_RT288X || CONFIG_SOC_RT305X */
a9b3a9f7 696
72c7296e 697#ifdef CONFIG_PCI
e01ae27f
GW		 698static int rt2800pci_probe(struct pci_dev *pci_dev,
699 const struct pci_device_id *id)
700{
701 return rt2x00pci_probe(pci_dev, &rt2800pci_ops);
702}
703
a9b3a9f7
ID		 704static struct pci_driver rt2800pci_driver = {
705 .name = KBUILD_MODNAME,
706 .id_table = rt2800pci_device_table,
e01ae27f 707 .probe = rt2800pci_probe,
69202359 708 .remove = rt2x00pci_remove,
a9b3a9f7
ID		 709 .suspend = rt2x00pci_suspend,
710 .resume = rt2x00pci_resume,
711};
72c7296e 712#endif /* CONFIG_PCI */
a9b3a9f7
ID		 713
714static int __init rt2800pci_init(void)
715{
716 int ret = 0;
717
5818a46a 718#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
a9b3a9f7
ID		 719 ret = platform_driver_register(&rt2800soc_driver);
720 if (ret)
721 return ret;
722#endif
72c7296e 723#ifdef CONFIG_PCI
a9b3a9f7
ID		 724 ret = pci_register_driver(&rt2800pci_driver);
725 if (ret) {
5818a46a 726#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
a9b3a9f7
ID		 727 platform_driver_unregister(&rt2800soc_driver);
728#endif
729 return ret;
730 }
731#endif
732
733 return ret;
734}
735
736static void __exit rt2800pci_exit(void)
737{
72c7296e 738#ifdef CONFIG_PCI
a9b3a9f7
ID		 739 pci_unregister_driver(&rt2800pci_driver);
740#endif
5818a46a 741#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
a9b3a9f7
ID		 742 platform_driver_unregister(&rt2800soc_driver);
743#endif
744}
745
746module_init(rt2800pci_init);
747module_exit(rt2800pci_exit);
Linux kernel - Deliverables
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