projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
rt2x00: rt2800pci: use separate ops for the SoC driver
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2800pci.c
CommitLineData
a9b3a9f7 1/*
96481b20 2 Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14
GW		 3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
a9b3a9f7
ID		 10 <http://rt2x00.serialmonkey.com>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 */
27
28/*
29 Module: rt2800pci
30 Abstract: rt2800pci device specific routines.
31 Supported chipsets: RT2800E & RT2800ED.
32 */
33
a9b3a9f7
ID		 34#include <linux/delay.h>
35#include <linux/etherdevice.h>
36#include <linux/init.h>
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/pci.h>
40#include <linux/platform_device.h>
41#include <linux/eeprom_93cx6.h>
42
43#include "rt2x00.h"
69a2bac8 44#include "rt2x00mmio.h"
a9b3a9f7
ID		 45#include "rt2x00pci.h"
46#include "rt2x00soc.h"
7ef5cc92 47#include "rt2800lib.h"
0bc202b3 48#include "rt2800mmio.h"
b54f78a8 49#include "rt2800.h"
a9b3a9f7
ID		 50#include "rt2800pci.h"
51
a9b3a9f7
ID		 52/*
53 * Allow hardware encryption to be disabled.
54 */
eb939922 55static bool modparam_nohwcrypt = false;
a9b3a9f7
ID		 56module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
57MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
58
ad417a53
GW		 59static bool rt2800pci_hwcrypt_disabled(struct rt2x00_dev *rt2x00dev)
60{
61 return modparam_nohwcrypt;
62}
63
a9b3a9f7
ID		 64static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
65{
66 unsigned int i;
67 u32 reg;
68
f18d4463
LC		 69 /*
70 * SOC devices don't support MCU requests.
71 */
72 if (rt2x00_is_soc(rt2x00dev))
73 return;
74
a9b3a9f7 75 for (i = 0; i < 200; i++) {
b9570b66 76 rt2x00mmio_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
a9b3a9f7
ID		 77
78 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
79 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
80 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
81 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
82 break;
83
84 udelay(REGISTER_BUSY_DELAY);
85 }
86
87 if (i == 200)
ec9c4989 88 rt2x00_err(rt2x00dev, "MCU request failed, no response from hardware\n");
a9b3a9f7 89
b9570b66
GJ		 90 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
91 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
a9b3a9f7
ID		 92}
93
5818a46a 94#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
a02308e9 95static int rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 96{
ef8397cf 97 void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
a9b3a9f7 98
a02308e9
GJ		 99 if (!base_addr)
100 return -ENOMEM;
101
a9b3a9f7 102 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
ef8397cf
GW		 103
104 iounmap(base_addr);
a02308e9 105 return 0;
a9b3a9f7
ID		 106}
107#else
a02308e9 108static inline int rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 109{
a02308e9 110 return -ENOMEM;
a9b3a9f7 111}
5818a46a 112#endif /* CONFIG_SOC_RT288X || CONFIG_SOC_RT305X */
a9b3a9f7 113
72c7296e 114#ifdef CONFIG_PCI
a9b3a9f7
ID		 115static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
116{
117 struct rt2x00_dev *rt2x00dev = eeprom->data;
118 u32 reg;
119
b9570b66 120 rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 121
122 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
123 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
124 eeprom->reg_data_clock =
125 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
126 eeprom->reg_chip_select =
127 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
128}
129
130static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
131{
132 struct rt2x00_dev *rt2x00dev = eeprom->data;
133 u32 reg = 0;
134
135 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
136 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
137 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
138 !!eeprom->reg_data_clock);
139 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
140 !!eeprom->reg_chip_select);
141
b9570b66 142 rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg);
a9b3a9f7
ID		 143}
144
a02308e9 145static int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
a9b3a9f7
ID		 146{
147 struct eeprom_93cx6 eeprom;
148 u32 reg;
149
b9570b66 150 rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 151
152 eeprom.data = rt2x00dev;
153 eeprom.register_read = rt2800pci_eepromregister_read;
154 eeprom.register_write = rt2800pci_eepromregister_write;
20f8b139
GW		 155 switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
156 {
157 case 0:
158 eeprom.width = PCI_EEPROM_WIDTH_93C46;
159 break;
160 case 1:
161 eeprom.width = PCI_EEPROM_WIDTH_93C66;
162 break;
163 default:
164 eeprom.width = PCI_EEPROM_WIDTH_93C86;
165 break;
166 }
a9b3a9f7
ID		 167 eeprom.reg_data_in = 0;
168 eeprom.reg_data_out = 0;
169 eeprom.reg_data_clock = 0;
170 eeprom.reg_chip_select = 0;
171
172 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
173 EEPROM_SIZE / sizeof(u16));
a02308e9
GJ		 174
175 return 0;
a9b3a9f7
ID		 176}
177
a6598682
GW		 178static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
179{
30e84034 180 return rt2800_efuse_detect(rt2x00dev);
a9b3a9f7
ID		 181}
182
a02308e9 183static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 184{
a02308e9 185 return rt2800_read_eeprom_efuse(rt2x00dev);
a9b3a9f7
ID		 186}
187#else
a02308e9 188static inline int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 189{
a02308e9 190 return -EOPNOTSUPP;
a9b3a9f7
ID		 191}
192
a6598682
GW		 193static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
194{
195 return 0;
196}
197
a02308e9 198static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 199{
a02308e9 200 return -EOPNOTSUPP;
a9b3a9f7 201}
72c7296e 202#endif /* CONFIG_PCI */
a9b3a9f7 203
a9b3a9f7
ID		 204/*
205 * Firmware functions
206 */
207static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
208{
a89534ed
WH		 209 /*
210 * Chip rt3290 use specific 4KB firmware named rt3290.bin.
211 */
212 if (rt2x00_rt(rt2x00dev, RT3290))
213 return FIRMWARE_RT3290;
214 else
215 return FIRMWARE_RT2860;
a9b3a9f7
ID		 216}
217
f31c9a8c 218static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
a9b3a9f7
ID		 219 const u8 *data, const size_t len)
220{
a9b3a9f7
ID		 221 u32 reg;
222
a9b3a9f7
ID		 223 /*
224 * enable Host program ram write selection
225 */
226 reg = 0;
227 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
b9570b66 228 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
a9b3a9f7
ID		 229
230 /*
231 * Write firmware to device.
232 */
b9570b66
GJ		 233 rt2x00mmio_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
234 data, len);
a9b3a9f7 235
b9570b66
GJ		 236 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
237 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
a9b3a9f7 238
b9570b66
GJ		 239 rt2x00mmio_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
240 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
a9b3a9f7
ID		 241
242 return 0;
243}
244
a9b3a9f7
ID		 245/*
246 * Device state switch handlers.
247 */
a9b3a9f7
ID		 248static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
249{
e8b461c3
JK		 250 int retval;
251
52b8243b
JK		 252 /* Wait for DMA, ignore error until we initialize queues. */
253 rt2800_wait_wpdma_ready(rt2x00dev);
254
7573afdf 255 if (unlikely(rt2800mmio_init_queues(rt2x00dev)))
a9b3a9f7
ID		 256 return -EIO;
257
e8b461c3
JK		 258 retval = rt2800_enable_radio(rt2x00dev);
259 if (retval)
260 return retval;
261
262 /* After resume MCU_BOOT_SIGNAL will trash these. */
b9570b66
GJ		 263 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
264 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
e8b461c3
JK		 265
266 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_RADIO_OFF, 0xff, 0x02);
267 rt2800pci_mcu_status(rt2x00dev, TOKEN_RADIO_OFF);
268
269 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP, 0, 0);
270 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
271
272 return retval;
a9b3a9f7
ID		 273}
274
275static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
276{
7f6e144f
RJH		 277 if (rt2x00_is_soc(rt2x00dev)) {
278 rt2800_disable_radio(rt2x00dev);
b9570b66
GJ		 279 rt2x00mmio_register_write(rt2x00dev, PWR_PIN_CFG, 0);
280 rt2x00mmio_register_write(rt2x00dev, TX_PIN_CFG, 0);
7f6e144f 281 }
a9b3a9f7
ID		 282}
283
284static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
285 enum dev_state state)
286{
a9b3a9f7 287 if (state == STATE_AWAKE) {
09a3311c
JK		 288 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP,
289 0, 0x02);
290 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
7f6e144f 291 } else if (state == STATE_SLEEP) {
b9570b66
GJ		 292 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
293 0xffffffff);
294 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID,
295 0xffffffff);
09a3311c
JK		 296 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_SLEEP,
297 0xff, 0x01);
a9b3a9f7
ID		 298 }
299
300 return 0;
301}
302
303static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
304 enum dev_state state)
305{
306 int retval = 0;
307
308 switch (state) {
309 case STATE_RADIO_ON:
a9b3a9f7
ID		 310 retval = rt2800pci_enable_radio(rt2x00dev);
311 break;
312 case STATE_RADIO_OFF:
313 /*
314 * After the radio has been disabled, the device should
315 * be put to sleep for powersaving.
316 */
317 rt2800pci_disable_radio(rt2x00dev);
318 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
319 break;
a9b3a9f7
ID		 320 case STATE_RADIO_IRQ_ON:
321 case STATE_RADIO_IRQ_OFF:
b5cfde3f 322 rt2800mmio_toggle_irq(rt2x00dev, state);
a9b3a9f7
ID		 323 break;
324 case STATE_DEEP_SLEEP:
325 case STATE_SLEEP:
326 case STATE_STANDBY:
327 case STATE_AWAKE:
328 retval = rt2800pci_set_state(rt2x00dev, state);
329 break;
330 default:
331 retval = -ENOTSUPP;
332 break;
333 }
334
335 if (unlikely(retval))
ec9c4989
JP		 336 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
337 state, retval);
a9b3a9f7
ID		 338
339 return retval;
340}
341
a9b3a9f7
ID		 342/*
343 * Device probe functions.
344 */
a02308e9 345static int rt2800pci_read_eeprom(struct rt2x00_dev *rt2x00dev)
7ab71325 346{
a02308e9
GJ		 347 int retval;
348
cea90e55 349 if (rt2x00_is_soc(rt2x00dev))
a02308e9 350 retval = rt2800pci_read_eeprom_soc(rt2x00dev);
cea90e55 351 else if (rt2800pci_efuse_detect(rt2x00dev))
a02308e9 352 retval = rt2800pci_read_eeprom_efuse(rt2x00dev);
cea90e55 353 else
a02308e9
GJ		 354 retval = rt2800pci_read_eeprom_pci(rt2x00dev);
355
356 return retval;
a9b3a9f7
ID		 357}
358
eeea863e 359#ifdef CONFIG_PCI
e783619e
HS		 360static const struct ieee80211_ops rt2800pci_mac80211_ops = {
361 .tx = rt2x00mac_tx,
362 .start = rt2x00mac_start,
363 .stop = rt2x00mac_stop,
364 .add_interface = rt2x00mac_add_interface,
365 .remove_interface = rt2x00mac_remove_interface,
366 .config = rt2x00mac_config,
367 .configure_filter = rt2x00mac_configure_filter,
e783619e
HS		 368 .set_key = rt2x00mac_set_key,
369 .sw_scan_start = rt2x00mac_sw_scan_start,
370 .sw_scan_complete = rt2x00mac_sw_scan_complete,
371 .get_stats = rt2x00mac_get_stats,
372 .get_tkip_seq = rt2800_get_tkip_seq,
373 .set_rts_threshold = rt2800_set_rts_threshold,
a2b1328a
HS		 374 .sta_add = rt2x00mac_sta_add,
375 .sta_remove = rt2x00mac_sta_remove,
e783619e
HS		 376 .bss_info_changed = rt2x00mac_bss_info_changed,
377 .conf_tx = rt2800_conf_tx,
378 .get_tsf = rt2800_get_tsf,
379 .rfkill_poll = rt2x00mac_rfkill_poll,
380 .ampdu_action = rt2800_ampdu_action,
f44df18c 381 .flush = rt2x00mac_flush,
977206d7 382 .get_survey = rt2800_get_survey,
e7dee444 383 .get_ringparam = rt2x00mac_get_ringparam,
5f0dd296 384 .tx_frames_pending = rt2x00mac_tx_frames_pending,
e783619e
HS		 385};
386
e796643e 387static const struct rt2800_ops rt2800pci_rt2800_ops = {
b9570b66
GJ		 388 .register_read = rt2x00mmio_register_read,
389 .register_read_lock = rt2x00mmio_register_read, /* same for PCI */
390 .register_write = rt2x00mmio_register_write,
391 .register_write_lock = rt2x00mmio_register_write, /* same for PCI */
392 .register_multiread = rt2x00mmio_register_multiread,
393 .register_multiwrite = rt2x00mmio_register_multiwrite,
394 .regbusy_read = rt2x00mmio_regbusy_read,
ad417a53
GW		 395 .read_eeprom = rt2800pci_read_eeprom,
396 .hwcrypt_disabled = rt2800pci_hwcrypt_disabled,
e796643e 397 .drv_write_firmware = rt2800pci_write_firmware,
7573afdf 398 .drv_init_registers = rt2800mmio_init_registers,
45c67550 399 .drv_get_txwi = rt2800mmio_get_txwi,
e796643e
ID		 400};
401
a9b3a9f7 402static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
b5cfde3f
GJ		 403 .irq_handler = rt2800mmio_interrupt,
404 .txstatus_tasklet = rt2800mmio_txstatus_tasklet,
405 .pretbtt_tasklet = rt2800mmio_pretbtt_tasklet,
406 .tbtt_tasklet = rt2800mmio_tbtt_tasklet,
407 .rxdone_tasklet = rt2800mmio_rxdone_tasklet,
408 .autowake_tasklet = rt2800mmio_autowake_tasklet,
ad417a53 409 .probe_hw = rt2800_probe_hw,
a9b3a9f7 410 .get_firmware_name = rt2800pci_get_firmware_name,
f31c9a8c
ID		 411 .check_firmware = rt2800_check_firmware,
412 .load_firmware = rt2800_load_firmware,
b9570b66
GJ		 413 .initialize = rt2x00mmio_initialize,
414 .uninitialize = rt2x00mmio_uninitialize,
7573afdf
GJ		 415 .get_entry_state = rt2800mmio_get_entry_state,
416 .clear_entry = rt2800mmio_clear_entry,
a9b3a9f7 417 .set_device_state = rt2800pci_set_device_state,
f4450616
BZ		 418 .rfkill_poll = rt2800_rfkill_poll,
419 .link_stats = rt2800_link_stats,
420 .reset_tuner = rt2800_reset_tuner,
421 .link_tuner = rt2800_link_tuner,
9e33a355 422 .gain_calibration = rt2800_gain_calibration,
2e9c43dd 423 .vco_calibration = rt2800_vco_calibration,
51e62469
GJ		 424 .start_queue = rt2800mmio_start_queue,
425 .kick_queue = rt2800mmio_kick_queue,
426 .stop_queue = rt2800mmio_stop_queue,
b9570b66 427 .flush_queue = rt2x00mmio_flush_queue,
45c67550 428 .write_tx_desc = rt2800mmio_write_tx_desc,
0c5879bc 429 .write_tx_data = rt2800_write_tx_data,
f0194b2d 430 .write_beacon = rt2800_write_beacon,
69cf36a4 431 .clear_beacon = rt2800_clear_beacon,
d10b7547 432 .fill_rxdone = rt2800mmio_fill_rxdone,
f4450616
BZ		 433 .config_shared_key = rt2800_config_shared_key,
434 .config_pairwise_key = rt2800_config_pairwise_key,
435 .config_filter = rt2800_config_filter,
436 .config_intf = rt2800_config_intf,
437 .config_erp = rt2800_config_erp,
438 .config_ant = rt2800_config_ant,
439 .config = rt2800_config,
a2b1328a
HS		 440 .sta_add = rt2800_sta_add,
441 .sta_remove = rt2800_sta_remove,
a9b3a9f7
ID		 442};
443
a9b3a9f7 444static const struct rt2x00_ops rt2800pci_ops = {
04d0362e 445 .name = KBUILD_MODNAME,
3a1c0128 446 .drv_data_size = sizeof(struct rt2800_drv_data),
04d0362e
GW		 447 .max_ap_intf = 8,
448 .eeprom_size = EEPROM_SIZE,
449 .rf_size = RF_SIZE,
450 .tx_queues = NUM_TX_QUEUES,
51e62469 451 .queue_init = rt2800mmio_queue_init,
04d0362e 452 .lib = &rt2800pci_rt2x00_ops,
e796643e 453 .drv = &rt2800pci_rt2800_ops,
e783619e 454 .hw = &rt2800pci_mac80211_ops,
a9b3a9f7 455#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 456 .debugfs = &rt2800_rt2x00debug,
a9b3a9f7
ID		 457#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
458};
459
460/*
461 * RT2800pci module information.
462 */
a3aa1884 463static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
e01ae27f
GW		 464 { PCI_DEVICE(0x1814, 0x0601) },
465 { PCI_DEVICE(0x1814, 0x0681) },
466 { PCI_DEVICE(0x1814, 0x0701) },
467 { PCI_DEVICE(0x1814, 0x0781) },
468 { PCI_DEVICE(0x1814, 0x3090) },
469 { PCI_DEVICE(0x1814, 0x3091) },
470 { PCI_DEVICE(0x1814, 0x3092) },
471 { PCI_DEVICE(0x1432, 0x7708) },
472 { PCI_DEVICE(0x1432, 0x7727) },
473 { PCI_DEVICE(0x1432, 0x7728) },
474 { PCI_DEVICE(0x1432, 0x7738) },
475 { PCI_DEVICE(0x1432, 0x7748) },
476 { PCI_DEVICE(0x1432, 0x7758) },
477 { PCI_DEVICE(0x1432, 0x7768) },
478 { PCI_DEVICE(0x1462, 0x891a) },
479 { PCI_DEVICE(0x1a3b, 0x1059) },
a89534ed
WH		 480#ifdef CONFIG_RT2800PCI_RT3290
481 { PCI_DEVICE(0x1814, 0x3290) },
482#endif
f93bc9b3 483#ifdef CONFIG_RT2800PCI_RT33XX
e01ae27f 484 { PCI_DEVICE(0x1814, 0x3390) },
f93bc9b3 485#endif
de1ebdce 486#ifdef CONFIG_RT2800PCI_RT35XX
e01ae27f
GW		 487 { PCI_DEVICE(0x1432, 0x7711) },
488 { PCI_DEVICE(0x1432, 0x7722) },
489 { PCI_DEVICE(0x1814, 0x3060) },
490 { PCI_DEVICE(0x1814, 0x3062) },
491 { PCI_DEVICE(0x1814, 0x3562) },
492 { PCI_DEVICE(0x1814, 0x3592) },
493 { PCI_DEVICE(0x1814, 0x3593) },
c4806014 494 { PCI_DEVICE(0x1814, 0x359f) },
60687ba7
RST		 495#endif
496#ifdef CONFIG_RT2800PCI_RT53XX
ccf91bd6 497 { PCI_DEVICE(0x1814, 0x5360) },
f57d7b6c 498 { PCI_DEVICE(0x1814, 0x5362) },
e01ae27f 499 { PCI_DEVICE(0x1814, 0x5390) },
f57d7b6c 500 { PCI_DEVICE(0x1814, 0x5392) },
5126d97e 501 { PCI_DEVICE(0x1814, 0x539a) },
2aed6915 502 { PCI_DEVICE(0x1814, 0x539b) },
71e0b38c 503 { PCI_DEVICE(0x1814, 0x539f) },
de1ebdce 504#endif
a9b3a9f7
ID		 505 { 0, }
506};
72c7296e 507#endif /* CONFIG_PCI */
a9b3a9f7
ID		 508
509MODULE_AUTHOR(DRV_PROJECT);
510MODULE_VERSION(DRV_VERSION);
511MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
512MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
72c7296e 513#ifdef CONFIG_PCI
a9b3a9f7
ID		 514MODULE_FIRMWARE(FIRMWARE_RT2860);
515MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
72c7296e 516#endif /* CONFIG_PCI */
a9b3a9f7
ID		 517MODULE_LICENSE("GPL");
518
5818a46a 519#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
eeea863e
GJ		 520static const struct ieee80211_ops rt2800soc_mac80211_ops = {
521 .tx = rt2x00mac_tx,
522 .start = rt2x00mac_start,
523 .stop = rt2x00mac_stop,
524 .add_interface = rt2x00mac_add_interface,
525 .remove_interface = rt2x00mac_remove_interface,
526 .config = rt2x00mac_config,
527 .configure_filter = rt2x00mac_configure_filter,
528 .set_key = rt2x00mac_set_key,
529 .sw_scan_start = rt2x00mac_sw_scan_start,
530 .sw_scan_complete = rt2x00mac_sw_scan_complete,
531 .get_stats = rt2x00mac_get_stats,
532 .get_tkip_seq = rt2800_get_tkip_seq,
533 .set_rts_threshold = rt2800_set_rts_threshold,
534 .sta_add = rt2x00mac_sta_add,
535 .sta_remove = rt2x00mac_sta_remove,
536 .bss_info_changed = rt2x00mac_bss_info_changed,
537 .conf_tx = rt2800_conf_tx,
538 .get_tsf = rt2800_get_tsf,
539 .rfkill_poll = rt2x00mac_rfkill_poll,
540 .ampdu_action = rt2800_ampdu_action,
541 .flush = rt2x00mac_flush,
542 .get_survey = rt2800_get_survey,
543 .get_ringparam = rt2x00mac_get_ringparam,
544 .tx_frames_pending = rt2x00mac_tx_frames_pending,
545};
546
547static const struct rt2800_ops rt2800soc_rt2800_ops = {
548 .register_read = rt2x00mmio_register_read,
549 .register_read_lock = rt2x00mmio_register_read, /* same for SoCs */
550 .register_write = rt2x00mmio_register_write,
551 .register_write_lock = rt2x00mmio_register_write, /* same for SoCs */
552 .register_multiread = rt2x00mmio_register_multiread,
553 .register_multiwrite = rt2x00mmio_register_multiwrite,
554 .regbusy_read = rt2x00mmio_regbusy_read,
555 .read_eeprom = rt2800pci_read_eeprom,
556 .hwcrypt_disabled = rt2800pci_hwcrypt_disabled,
557 .drv_write_firmware = rt2800pci_write_firmware,
558 .drv_init_registers = rt2800mmio_init_registers,
559 .drv_get_txwi = rt2800mmio_get_txwi,
560};
561
562static const struct rt2x00lib_ops rt2800soc_rt2x00_ops = {
563 .irq_handler = rt2800mmio_interrupt,
564 .txstatus_tasklet = rt2800mmio_txstatus_tasklet,
565 .pretbtt_tasklet = rt2800mmio_pretbtt_tasklet,
566 .tbtt_tasklet = rt2800mmio_tbtt_tasklet,
567 .rxdone_tasklet = rt2800mmio_rxdone_tasklet,
568 .autowake_tasklet = rt2800mmio_autowake_tasklet,
569 .probe_hw = rt2800_probe_hw,
570 .get_firmware_name = rt2800pci_get_firmware_name,
571 .check_firmware = rt2800_check_firmware,
572 .load_firmware = rt2800_load_firmware,
573 .initialize = rt2x00mmio_initialize,
574 .uninitialize = rt2x00mmio_uninitialize,
575 .get_entry_state = rt2800mmio_get_entry_state,
576 .clear_entry = rt2800mmio_clear_entry,
577 .set_device_state = rt2800pci_set_device_state,
578 .rfkill_poll = rt2800_rfkill_poll,
579 .link_stats = rt2800_link_stats,
580 .reset_tuner = rt2800_reset_tuner,
581 .link_tuner = rt2800_link_tuner,
582 .gain_calibration = rt2800_gain_calibration,
583 .vco_calibration = rt2800_vco_calibration,
584 .start_queue = rt2800mmio_start_queue,
585 .kick_queue = rt2800mmio_kick_queue,
586 .stop_queue = rt2800mmio_stop_queue,
587 .flush_queue = rt2x00mmio_flush_queue,
588 .write_tx_desc = rt2800mmio_write_tx_desc,
589 .write_tx_data = rt2800_write_tx_data,
590 .write_beacon = rt2800_write_beacon,
591 .clear_beacon = rt2800_clear_beacon,
592 .fill_rxdone = rt2800mmio_fill_rxdone,
593 .config_shared_key = rt2800_config_shared_key,
594 .config_pairwise_key = rt2800_config_pairwise_key,
595 .config_filter = rt2800_config_filter,
596 .config_intf = rt2800_config_intf,
597 .config_erp = rt2800_config_erp,
598 .config_ant = rt2800_config_ant,
599 .config = rt2800_config,
600 .sta_add = rt2800_sta_add,
601 .sta_remove = rt2800_sta_remove,
602};
603
604static const struct rt2x00_ops rt2800soc_ops = {
605 .name = KBUILD_MODNAME,
606 .drv_data_size = sizeof(struct rt2800_drv_data),
607 .max_ap_intf = 8,
608 .eeprom_size = EEPROM_SIZE,
609 .rf_size = RF_SIZE,
610 .tx_queues = NUM_TX_QUEUES,
611 .queue_init = rt2800mmio_queue_init,
612 .lib = &rt2800soc_rt2x00_ops,
613 .drv = &rt2800soc_rt2800_ops,
614 .hw = &rt2800soc_mac80211_ops,
615#ifdef CONFIG_RT2X00_LIB_DEBUGFS
616 .debugfs = &rt2800_rt2x00debug,
617#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
618};
619
714fa663
GW		 620static int rt2800soc_probe(struct platform_device *pdev)
621{
eeea863e 622 return rt2x00soc_probe(pdev, &rt2800soc_ops);
714fa663 623}
a9b3a9f7
ID		 624
625static struct platform_driver rt2800soc_driver = {
626 .driver = {
627 .name = "rt2800_wmac",
628 .owner = THIS_MODULE,
629 .mod_name = KBUILD_MODNAME,
630 },
714fa663 631 .probe = rt2800soc_probe,
69202359 632 .remove = rt2x00soc_remove,
a9b3a9f7
ID		 633 .suspend = rt2x00soc_suspend,
634 .resume = rt2x00soc_resume,
635};
5818a46a 636#endif /* CONFIG_SOC_RT288X || CONFIG_SOC_RT305X */
a9b3a9f7 637
72c7296e 638#ifdef CONFIG_PCI
e01ae27f
GW		 639static int rt2800pci_probe(struct pci_dev *pci_dev,
640 const struct pci_device_id *id)
641{
642 return rt2x00pci_probe(pci_dev, &rt2800pci_ops);
643}
644
a9b3a9f7
ID		 645static struct pci_driver rt2800pci_driver = {
646 .name = KBUILD_MODNAME,
647 .id_table = rt2800pci_device_table,
e01ae27f 648 .probe = rt2800pci_probe,
69202359 649 .remove = rt2x00pci_remove,
a9b3a9f7
ID		 650 .suspend = rt2x00pci_suspend,
651 .resume = rt2x00pci_resume,
652};
72c7296e 653#endif /* CONFIG_PCI */
a9b3a9f7
ID		 654
655static int __init rt2800pci_init(void)
656{
657 int ret = 0;
658
5818a46a 659#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
a9b3a9f7
ID		 660 ret = platform_driver_register(&rt2800soc_driver);
661 if (ret)
662 return ret;
663#endif
72c7296e 664#ifdef CONFIG_PCI
a9b3a9f7
ID		 665 ret = pci_register_driver(&rt2800pci_driver);
666 if (ret) {
5818a46a 667#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
a9b3a9f7
ID		 668 platform_driver_unregister(&rt2800soc_driver);
669#endif
670 return ret;
671 }
672#endif
673
674 return ret;
675}
676
677static void __exit rt2800pci_exit(void)
678{
72c7296e 679#ifdef CONFIG_PCI
a9b3a9f7
ID		 680 pci_unregister_driver(&rt2800pci_driver);
681#endif
5818a46a 682#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
a9b3a9f7
ID		 683 platform_driver_unregister(&rt2800soc_driver);
684#endif
685}
686
687module_init(rt2800pci_init);
688module_exit(rt2800pci_exit);
Linux kernel - Deliverables
This page took 0.732521 seconds and 5 git commands to generate.