rt2x00: use DECLARE_EWMA
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2x00.h
CommitLineData
95ea3627 1/*
7e613e16
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2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2004 - 2009 Gertjan van Wingerde <gwingerde@gmail.com>
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5 <http://rt2x00.serialmonkey.com>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
a05b8c58 18 along with this program; if not, see <http://www.gnu.org/licenses/>.
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19 */
20
21/*
22 Module: rt2x00
23 Abstract: rt2x00 global information.
24 */
25
26#ifndef RT2X00_H
27#define RT2X00_H
28
29#include <linux/bitops.h>
a6b7a407 30#include <linux/interrupt.h>
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31#include <linux/skbuff.h>
32#include <linux/workqueue.h>
33#include <linux/firmware.h>
a9450b70 34#include <linux/leds.h>
3d82346c 35#include <linux/mutex.h>
61af43c5 36#include <linux/etherdevice.h>
cca3e998 37#include <linux/input-polldev.h>
96c3da7d 38#include <linux/kfifo.h>
f421111b 39#include <linux/hrtimer.h>
1dc254ac 40#include <linux/average.h>
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41
42#include <net/mac80211.h>
43
44#include "rt2x00debug.h"
b4df4708 45#include "rt2x00dump.h"
a9450b70 46#include "rt2x00leds.h"
95ea3627 47#include "rt2x00reg.h"
181d6902 48#include "rt2x00queue.h"
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49
50/*
51 * Module information.
95ea3627 52 */
754be309 53#define DRV_VERSION "2.3.0"
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54#define DRV_PROJECT "http://rt2x00.serialmonkey.com"
55
ec9c4989 56/* Debug definitions.
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57 * Debug output has to be enabled during compile time.
58 */
95ea3627 59#ifdef CONFIG_RT2X00_DEBUG
ec9c4989 60#define DEBUG
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61#endif /* CONFIG_RT2X00_DEBUG */
62
ec9c4989
JP
63/* Utility printing macros
64 * rt2x00_probe_err is for messages when rt2x00_dev is uninitialized
95ea3627 65 */
ec9c4989
JP
66#define rt2x00_probe_err(fmt, ...) \
67 printk(KERN_ERR KBUILD_MODNAME ": %s: Error - " fmt, \
68 __func__, ##__VA_ARGS__)
69#define rt2x00_err(dev, fmt, ...) \
70 wiphy_err((dev)->hw->wiphy, "%s: Error - " fmt, \
71 __func__, ##__VA_ARGS__)
72#define rt2x00_warn(dev, fmt, ...) \
73 wiphy_warn((dev)->hw->wiphy, "%s: Warning - " fmt, \
74 __func__, ##__VA_ARGS__)
75#define rt2x00_info(dev, fmt, ...) \
76 wiphy_info((dev)->hw->wiphy, "%s: Info - " fmt, \
77 __func__, ##__VA_ARGS__)
78
79/* Various debug levels */
80#define rt2x00_dbg(dev, fmt, ...) \
81 wiphy_dbg((dev)->hw->wiphy, "%s: Debug - " fmt, \
82 __func__, ##__VA_ARGS__)
83#define rt2x00_eeprom_dbg(dev, fmt, ...) \
84 wiphy_dbg((dev)->hw->wiphy, "%s: EEPROM recovery - " fmt, \
85 __func__, ##__VA_ARGS__)
95ea3627 86
bad13639
ID
87/*
88 * Duration calculations
89 * The rate variable passed is: 100kbs.
90 * To convert from bytes to bits we multiply size with 8,
91 * then the size is multiplied with 10 to make the
92 * real rate -> rate argument correction.
93 */
94#define GET_DURATION(__size, __rate) (((__size) * 8 * 10) / (__rate))
95#define GET_DURATION_RES(__size, __rate)(((__size) * 8 * 10) % (__rate))
96
77e73d18
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97/*
98 * Determine the number of L2 padding bytes required between the header and
99 * the payload.
100 */
101#define L2PAD_SIZE(__hdrlen) (-(__hdrlen) & 3)
102
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103/*
104 * Determine the alignment requirement,
105 * to make sure the 802.11 payload is padded to a 4-byte boundrary
106 * we must determine the address of the payload and calculate the
107 * amount of bytes needed to move the data.
108 */
109#define ALIGN_SIZE(__skb, __header) \
110 ( ((unsigned long)((__skb)->data + (__header))) & 3 )
111
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112/*
113 * Constants for extra TX headroom for alignment purposes.
114 */
115#define RT2X00_ALIGN_SIZE 4 /* Only whole frame needs alignment */
116#define RT2X00_L2PAD_SIZE 8 /* Both header & payload need alignment */
117
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118/*
119 * Standard timing and size defines.
120 * These values should follow the ieee80211 specifications.
121 */
122#define ACK_SIZE 14
123#define IEEE80211_HEADER 24
124#define PLCP 48
125#define BEACON 100
126#define PREAMBLE 144
127#define SHORT_PREAMBLE 72
128#define SLOT_TIME 20
129#define SHORT_SLOT_TIME 9
130#define SIFS 10
131#define PIFS ( SIFS + SLOT_TIME )
132#define SHORT_PIFS ( SIFS + SHORT_SLOT_TIME )
133#define DIFS ( PIFS + SLOT_TIME )
134#define SHORT_DIFS ( SHORT_PIFS + SHORT_SLOT_TIME )
f2fdbc48 135#define EIFS ( SIFS + DIFS + \
bad13639 136 GET_DURATION(IEEE80211_HEADER + ACK_SIZE, 10) )
f2fdbc48 137#define SHORT_EIFS ( SIFS + SHORT_DIFS + \
bad13639 138 GET_DURATION(IEEE80211_HEADER + ACK_SIZE, 10) )
95ea3627 139
5822e070
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140enum rt2x00_chip_intf {
141 RT2X00_CHIP_INTF_PCI,
6e1fdd11 142 RT2X00_CHIP_INTF_PCIE,
5822e070 143 RT2X00_CHIP_INTF_USB,
cea90e55 144 RT2X00_CHIP_INTF_SOC,
5822e070
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145};
146
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147/*
148 * Chipset identification
149 * The chipset on the device is composed of a RT and RF chip.
150 * The chipset combination is important for determining device capabilities.
151 */
152struct rt2x00_chip {
153 u16 rt;
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GW
154#define RT2460 0x2460
155#define RT2560 0x2560
156#define RT2570 0x2570
157#define RT2661 0x2661
158#define RT2573 0x2573
5ed8f458 159#define RT2860 0x2860 /* 2.4GHz */
e148b4c8 160#define RT2872 0x2872 /* WSOC */
49e721ec 161#define RT2883 0x2883 /* WSOC */
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162#define RT3070 0x3070
163#define RT3071 0x3071
a9b3a9f7 164#define RT3090 0x3090 /* 2.4GHz PCIe */
a89534ed 165#define RT3290 0x3290
03839951 166#define RT3352 0x3352 /* WSOC */
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167#define RT3390 0x3390
168#define RT3572 0x3572
5a87e7a7 169#define RT3593 0x3593
e148b4c8 170#define RT3883 0x3883 /* WSOC */
70127cb6 171#define RT5390 0x5390 /* 2.4GHz */
2ed71884 172#define RT5392 0x5392 /* 2.4GHz */
b8863f8b 173#define RT5592 0x5592
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174
175 u16 rf;
49e721ec 176 u16 rev;
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177
178 enum rt2x00_chip_intf intf;
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179};
180
181/*
182 * RF register values that belong to a particular channel.
183 */
184struct rf_channel {
185 int channel;
186 u32 rf1;
187 u32 rf2;
188 u32 rf3;
189 u32 rf4;
190};
191
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192/*
193 * Channel information structure
194 */
195struct channel_info {
196 unsigned int flags;
197#define GEOGRAPHY_ALLOWED 0x00000001
198
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199 short max_power;
200 short default_power1;
201 short default_power2;
c0a14369 202 short default_power3;
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203};
204
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205/*
206 * Antenna setup values.
207 */
208struct antenna_setup {
209 enum antenna rx;
210 enum antenna tx;
d96aa640
RJH
211 u8 rx_chain_num;
212 u8 tx_chain_num;
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213};
214
95ea3627 215/*
ebcf26da 216 * Quality statistics about the currently active link.
95ea3627 217 */
ebcf26da 218struct link_qual {
95ea3627 219 /*
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220 * Statistics required for Link tuning by driver
221 * The rssi value is provided by rt2x00lib during the
222 * link_tuner() callback function.
223 * The false_cca field is filled during the link_stats()
224 * callback function and could be used during the
225 * link_tuner() callback function.
95ea3627 226 */
5352ff65 227 int rssi;
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228 int false_cca;
229
230 /*
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231 * VGC levels
232 * Hardware driver will tune the VGC level during each call
233 * to the link_tuner() callback function. This vgc_level is
234 * is determined based on the link quality statistics like
235 * average RSSI and the false CCA count.
95ea3627 236 *
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237 * In some cases the drivers need to differentiate between
238 * the currently "desired" VGC level and the level configured
239 * in the hardware. The latter is important to reduce the
240 * number of BBP register reads to reduce register access
241 * overhead. For this reason we store both values here.
242 */
243 u8 vgc_level;
244 u8 vgc_level_reg;
245
246 /*
247 * Statistics required for Signal quality calculation.
248 * These fields might be changed during the link_stats()
249 * callback function.
95ea3627 250 */
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251 int rx_success;
252 int rx_failed;
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253 int tx_success;
254 int tx_failed;
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255};
256
11ab35ed
JB
257DECLARE_EWMA(rssi, 1024, 8)
258
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259/*
260 * Antenna settings about the currently active link.
261 */
262struct link_ant {
263 /*
264 * Antenna flags
265 */
266 unsigned int flags;
267#define ANTENNA_RX_DIVERSITY 0x00000001
268#define ANTENNA_TX_DIVERSITY 0x00000002
269#define ANTENNA_MODE_SAMPLE 0x00000004
270
271 /*
272 * Currently active TX/RX antenna setup.
273 * When software diversity is used, this will indicate
274 * which antenna is actually used at this time.
275 */
276 struct antenna_setup active;
277
278 /*
193df183
LE
279 * RSSI history information for the antenna.
280 * Used to determine when to switch antenna
281 * when using software diversity.
69f81a2c 282 */
193df183 283 int rssi_history;
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284
285 /*
286 * Current RSSI average of the currently active antenna.
287 * Similar to the avg_rssi in the link_qual structure
288 * this value is updated by using the walking average.
289 */
11ab35ed 290 struct ewma_rssi rssi_ant;
69f81a2c
ID
291};
292
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293/*
294 * To optimize the quality of the link we need to store
295 * the quality of received frames and periodically
296 * optimize the link.
297 */
298struct link {
299 /*
300 * Link tuner counter
301 * The number of times the link has been tuned
302 * since the radio has been switched on.
303 */
304 u32 count;
305
306 /*
307 * Quality measurement values.
308 */
309 struct link_qual qual;
310
addc81bd 311 /*
69f81a2c 312 * TX/RX antenna setup.
addc81bd 313 */
69f81a2c 314 struct link_ant ant;
addc81bd 315
ebcf26da 316 /*
5352ff65 317 * Currently active average RSSI value
ebcf26da 318 */
11ab35ed 319 struct ewma_rssi avg_rssi;
eb20b4e8 320
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321 /*
322 * Work structure for scheduling periodic link tuning.
323 */
324 struct delayed_work work;
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ID
325
326 /*
327 * Work structure for scheduling periodic watchdog monitoring.
cdfd2c5c
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328 * This work must be scheduled on the kernel workqueue, while
329 * all other work structures must be queued on the mac80211
330 * workqueue. This guarantees that the watchdog can schedule
331 * other work structures and wait for their completion in order
332 * to bring the device/driver back into the desired state.
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333 */
334 struct delayed_work watchdog_work;
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HS
335
336 /*
337 * Work structure for scheduling periodic AGC adjustments.
338 */
339 struct delayed_work agc_work;
2e9c43dd
JL
340
341 /*
342 * Work structure for scheduling periodic VCO calibration.
343 */
344 struct delayed_work vco_work;
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345};
346
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347enum rt2x00_delayed_flags {
348 DELAYED_UPDATE_BEACON,
349};
350
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351/*
352 * Interface structure
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353 * Per interface configuration details, this structure
354 * is allocated as the private data for ieee80211_vif.
95ea3627 355 */
6bb40dd1 356struct rt2x00_intf {
17512dc3
IP
357 /*
358 * beacon->skb must be protected with the mutex.
359 */
360 struct mutex beacon_skb_mutex;
361
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362 /*
363 * Entry in the beacon queue which belongs to
364 * this interface. Each interface has its own
365 * dedicated beacon entry.
366 */
367 struct queue_entry *beacon;
69cf36a4 368 bool enable_beacon;
95ea3627 369
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370 /*
371 * Actions that needed rescheduling.
372 */
bfe6a15d 373 unsigned long delayed_flags;
f591fa5d 374
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375 /*
376 * Software sequence counter, this is only required
377 * for hardware which doesn't support hardware
378 * sequence counting.
379 */
e5851dac 380 atomic_t seqno;
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381};
382
383static inline struct rt2x00_intf* vif_to_intf(struct ieee80211_vif *vif)
95ea3627 384{
6bb40dd1 385 return (struct rt2x00_intf *)vif->drv_priv;
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386}
387
31562e80
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388/**
389 * struct hw_mode_spec: Hardware specifications structure
390 *
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391 * Details about the supported modes, rates and channels
392 * of a particular chipset. This is used by rt2x00lib
393 * to build the ieee80211_hw_mode array for mac80211.
31562e80
ID
394 *
395 * @supported_bands: Bitmask contained the supported bands (2.4GHz, 5.2GHz).
396 * @supported_rates: Rate types which are supported (CCK, OFDM).
397 * @num_channels: Number of supported channels. This is used as array size
398 * for @tx_power_a, @tx_power_bg and @channels.
9a46d44e 399 * @channels: Device/chipset specific channel values (See &struct rf_channel).
8c5e7a5f 400 * @channels_info: Additional information for channels (See &struct channel_info).
35f00cfc 401 * @ht: Driver HT Capabilities (See &ieee80211_sta_ht_cap).
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402 */
403struct hw_mode_spec {
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404 unsigned int supported_bands;
405#define SUPPORT_BAND_2GHZ 0x00000001
406#define SUPPORT_BAND_5GHZ 0x00000002
407
408 unsigned int supported_rates;
409#define SUPPORT_RATE_CCK 0x00000001
410#define SUPPORT_RATE_OFDM 0x00000002
411
412 unsigned int num_channels;
413 const struct rf_channel *channels;
8c5e7a5f 414 const struct channel_info *channels_info;
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415
416 struct ieee80211_sta_ht_cap ht;
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417};
418
5c58ee51
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419/*
420 * Configuration structure wrapper around the
421 * mac80211 configuration structure.
422 * When mac80211 configures the driver, rt2x00lib
423 * can precalculate values which are equal for all
424 * rt2x00 drivers. Those values can be stored in here.
425 */
426struct rt2x00lib_conf {
427 struct ieee80211_conf *conf;
8c5e7a5f 428
5c58ee51 429 struct rf_channel rf;
8c5e7a5f 430 struct channel_info channel;
5c58ee51
ID
431};
432
72810379
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433/*
434 * Configuration structure for erp settings.
435 */
436struct rt2x00lib_erp {
437 int short_preamble;
e360c4cb 438 int cts_protection;
72810379 439
881d948c 440 u32 basic_rates;
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ID
441
442 int slot_time;
443
444 short sifs;
445 short pifs;
446 short difs;
447 short eifs;
8a566afe
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448
449 u16 beacon_int;
87c1915d 450 u16 ht_opmode;
72810379
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451};
452
2bb057d0
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453/*
454 * Configuration structure for hardware encryption.
455 */
456struct rt2x00lib_crypto {
457 enum cipher cipher;
458
459 enum set_key_cmd cmd;
460 const u8 *address;
461
462 u32 bssidx;
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ID
463
464 u8 key[16];
465 u8 tx_mic[8];
466 u8 rx_mic[8];
f03fcfc1
HS
467
468 int wcid;
2bb057d0
ID
469};
470
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471/*
472 * Configuration structure wrapper around the
473 * rt2x00 interface configuration handler.
474 */
475struct rt2x00intf_conf {
476 /*
477 * Interface type
478 */
05c914fe 479 enum nl80211_iftype type;
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480
481 /*
25985edc 482 * TSF sync value, this is dependent on the operation type.
6bb40dd1
ID
483 */
484 enum tsf_sync sync;
485
486 /*
25985edc
LDM
487 * The MAC and BSSID addresses are simple array of bytes,
488 * these arrays are little endian, so when sending the addresses
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ID
489 * to the drivers, copy the it into a endian-signed variable.
490 *
491 * Note that all devices (except rt2500usb) have 32 bits
492 * register word sizes. This means that whatever variable we
493 * pass _must_ be a multiple of 32 bits. Otherwise the device
494 * might not accept what we are sending to it.
495 * This will also make it easier for the driver to write
496 * the data to the device.
497 */
498 __le32 mac[2];
499 __le32 bssid[2];
500};
501
b4943d81
HS
502/*
503 * Private structure for storing STA details
504 * wcid: Wireless Client ID
505 */
506struct rt2x00_sta {
507 int wcid;
508};
509
510static inline struct rt2x00_sta* sta_to_rt2x00_sta(struct ieee80211_sta *sta)
511{
512 return (struct rt2x00_sta *)sta->drv_priv;
513}
514
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515/*
516 * rt2x00lib callback functions.
517 */
518struct rt2x00lib_ops {
519 /*
520 * Interrupt handlers.
521 */
522 irq_handler_t irq_handler;
523
96c3da7d
HS
524 /*
525 * TX status tasklet handler.
526 */
527 void (*txstatus_tasklet) (unsigned long data);
c5c65761
HS
528 void (*pretbtt_tasklet) (unsigned long data);
529 void (*tbtt_tasklet) (unsigned long data);
530 void (*rxdone_tasklet) (unsigned long data);
531 void (*autowake_tasklet) (unsigned long data);
96c3da7d 532
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ID
533 /*
534 * Device init handlers.
535 */
536 int (*probe_hw) (struct rt2x00_dev *rt2x00dev);
537 char *(*get_firmware_name) (struct rt2x00_dev *rt2x00dev);
0cbe0064
ID
538 int (*check_firmware) (struct rt2x00_dev *rt2x00dev,
539 const u8 *data, const size_t len);
540 int (*load_firmware) (struct rt2x00_dev *rt2x00dev,
541 const u8 *data, const size_t len);
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542
543 /*
544 * Device initialization/deinitialization handlers.
545 */
546 int (*initialize) (struct rt2x00_dev *rt2x00dev);
547 void (*uninitialize) (struct rt2x00_dev *rt2x00dev);
548
837e7f24 549 /*
181d6902 550 * queue initialization handlers
837e7f24 551 */
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ID
552 bool (*get_entry_state) (struct queue_entry *entry);
553 void (*clear_entry) (struct queue_entry *entry);
837e7f24 554
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555 /*
556 * Radio control handlers.
557 */
558 int (*set_device_state) (struct rt2x00_dev *rt2x00dev,
559 enum dev_state state);
560 int (*rfkill_poll) (struct rt2x00_dev *rt2x00dev);
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ID
561 void (*link_stats) (struct rt2x00_dev *rt2x00dev,
562 struct link_qual *qual);
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ID
563 void (*reset_tuner) (struct rt2x00_dev *rt2x00dev,
564 struct link_qual *qual);
565 void (*link_tuner) (struct rt2x00_dev *rt2x00dev,
566 struct link_qual *qual, const u32 count);
9e33a355 567 void (*gain_calibration) (struct rt2x00_dev *rt2x00dev);
2e9c43dd 568 void (*vco_calibration) (struct rt2x00_dev *rt2x00dev);
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569
570 /*
571 * Data queue handlers.
572 */
c965c74b 573 void (*watchdog) (struct rt2x00_dev *rt2x00dev);
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574 void (*start_queue) (struct data_queue *queue);
575 void (*kick_queue) (struct data_queue *queue);
576 void (*stop_queue) (struct data_queue *queue);
152a5992 577 void (*flush_queue) (struct data_queue *queue, bool drop);
0e0d39e5 578 void (*tx_dma_done) (struct queue_entry *entry);
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579
580 /*
581 * TX control handlers
582 */
93331458 583 void (*write_tx_desc) (struct queue_entry *entry,
61486e0f 584 struct txentry_desc *txdesc);
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GW
585 void (*write_tx_data) (struct queue_entry *entry,
586 struct txentry_desc *txdesc);
f224f4ef
GW
587 void (*write_beacon) (struct queue_entry *entry,
588 struct txentry_desc *txdesc);
69cf36a4 589 void (*clear_beacon) (struct queue_entry *entry);
f1ca2167 590 int (*get_tx_data_len) (struct queue_entry *entry);
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591
592 /*
593 * RX control handlers
594 */
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595 void (*fill_rxdone) (struct queue_entry *entry,
596 struct rxdone_entry_desc *rxdesc);
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597
598 /*
599 * Configuration handlers.
600 */
2bb057d0
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601 int (*config_shared_key) (struct rt2x00_dev *rt2x00dev,
602 struct rt2x00lib_crypto *crypto,
603 struct ieee80211_key_conf *key);
604 int (*config_pairwise_key) (struct rt2x00_dev *rt2x00dev,
605 struct rt2x00lib_crypto *crypto,
606 struct ieee80211_key_conf *key);
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ID
607 void (*config_filter) (struct rt2x00_dev *rt2x00dev,
608 const unsigned int filter_flags);
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609 void (*config_intf) (struct rt2x00_dev *rt2x00dev,
610 struct rt2x00_intf *intf,
611 struct rt2x00intf_conf *conf,
612 const unsigned int flags);
613#define CONFIG_UPDATE_TYPE ( 1 << 1 )
614#define CONFIG_UPDATE_MAC ( 1 << 2 )
615#define CONFIG_UPDATE_BSSID ( 1 << 3 )
616
3a643d24 617 void (*config_erp) (struct rt2x00_dev *rt2x00dev,
02044643
HS
618 struct rt2x00lib_erp *erp,
619 u32 changed);
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620 void (*config_ant) (struct rt2x00_dev *rt2x00dev,
621 struct antenna_setup *ant);
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622 void (*config) (struct rt2x00_dev *rt2x00dev,
623 struct rt2x00lib_conf *libconf,
e4ea1c40 624 const unsigned int changed_flags);
b4943d81
HS
625 int (*sta_add) (struct rt2x00_dev *rt2x00dev,
626 struct ieee80211_vif *vif,
627 struct ieee80211_sta *sta);
628 int (*sta_remove) (struct rt2x00_dev *rt2x00dev,
629 int wcid);
95ea3627
ID
630};
631
632/*
633 * rt2x00 driver callback operation structure.
634 */
635struct rt2x00_ops {
636 const char *name;
1ebbc485 637 const unsigned int drv_data_size;
6bb40dd1 638 const unsigned int max_ap_intf;
95ea3627
ID
639 const unsigned int eeprom_size;
640 const unsigned int rf_size;
61448f88 641 const unsigned int tx_queues;
25bf6ce4 642 void (*queue_init)(struct data_queue *queue);
95ea3627 643 const struct rt2x00lib_ops *lib;
e796643e 644 const void *drv;
95ea3627
ID
645 const struct ieee80211_ops *hw;
646#ifdef CONFIG_RT2X00_LIB_DEBUGFS
647 const struct rt2x00debug *debugfs;
648#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
649};
650
483272f5 651/*
7dab73b3 652 * rt2x00 state flags
483272f5 653 */
7dab73b3 654enum rt2x00_state_flags {
483272f5 655 /*
7dab73b3 656 * Device flags
483272f5 657 */
0262ab0d
ID
658 DEVICE_STATE_PRESENT,
659 DEVICE_STATE_REGISTERED_HW,
660 DEVICE_STATE_INITIALIZED,
661 DEVICE_STATE_STARTED,
0262ab0d 662 DEVICE_STATE_ENABLED_RADIO,
d8147f9d 663 DEVICE_STATE_SCANNING,
483272f5 664
2bb057d0
ID
665 /*
666 * Driver configuration
667 */
35f00cfc 668 CONFIG_CHANNEL_HT40,
1c0bcf89 669 CONFIG_POWERSAVING,
da40f407 670 CONFIG_HT_DISABLED,
e66a8ddf 671 CONFIG_QOS_DISABLED,
f421111b
SG
672
673 /*
674 * Mark we currently are sequentially reading TX_STA_FIFO register
675 * FIXME: this is for only rt2800usb, should go to private data
676 */
677 TX_STATUS_READING,
483272f5
ID
678};
679
7dab73b3
ID
680/*
681 * rt2x00 capability flags
682 */
683enum rt2x00_capability_flags {
684 /*
685 * Requirements
686 */
687 REQUIRE_FIRMWARE,
688 REQUIRE_BEACON_GUARD,
689 REQUIRE_ATIM_QUEUE,
690 REQUIRE_DMA,
691 REQUIRE_COPY_IV,
692 REQUIRE_L2PAD,
693 REQUIRE_TXSTATUS_FIFO,
694 REQUIRE_TASKLET_CONTEXT,
695 REQUIRE_SW_SEQNO,
696 REQUIRE_HT_TX_DESC,
1c0bcf89 697 REQUIRE_PS_AUTOWAKE,
616a8394 698 REQUIRE_DELAYED_RFKILL,
7dab73b3
ID
699
700 /*
701 * Capabilities
702 */
703 CAPABILITY_HW_BUTTON,
704 CAPABILITY_HW_CRYPTO,
705 CAPABILITY_POWER_LIMIT,
706 CAPABILITY_CONTROL_FILTERS,
707 CAPABILITY_CONTROL_FILTER_PSPOLL,
708 CAPABILITY_PRE_TBTT_INTERRUPT,
709 CAPABILITY_LINK_TUNING,
710 CAPABILITY_FRAME_TYPE,
711 CAPABILITY_RF_SEQUENCE,
712 CAPABILITY_EXTERNAL_LNA_A,
713 CAPABILITY_EXTERNAL_LNA_BG,
714 CAPABILITY_DOUBLE_ANTENNA,
fdbc7b0a 715 CAPABILITY_BT_COEXIST,
2e9c43dd 716 CAPABILITY_VCO_RECALIBRATION,
7dab73b3
ID
717};
718
55d2e9da
GW
719/*
720 * Interface combinations
721 */
722enum {
723 IF_COMB_AP = 0,
724 NUM_IF_COMB,
725};
726
95ea3627
ID
727/*
728 * rt2x00 device structure.
729 */
730struct rt2x00_dev {
731 /*
732 * Device structure.
733 * The structure stored in here depends on the
734 * system bus (PCI or USB).
735 * When accessing this variable, the rt2x00dev_{pci,usb}
49513481 736 * macros should be used for correct typecasting.
95ea3627 737 */
14a3bf89 738 struct device *dev;
95ea3627
ID
739
740 /*
741 * Callback functions.
742 */
743 const struct rt2x00_ops *ops;
744
1ebbc485
GW
745 /*
746 * Driver data.
747 */
748 void *drv_data;
749
95ea3627
ID
750 /*
751 * IEEE80211 control structure.
752 */
753 struct ieee80211_hw *hw;
8318d78a
JB
754 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
755 enum ieee80211_band curr_band;
e5ef5bad 756 int curr_freq;
95ea3627 757
95ea3627
ID
758 /*
759 * If enabled, the debugfs interface structures
760 * required for deregistration of debugfs.
761 */
762#ifdef CONFIG_RT2X00_LIB_DEBUGFS
4d8dd66c 763 struct rt2x00debug_intf *debugfs_intf;
95ea3627
ID
764#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
765
a9450b70
ID
766 /*
767 * LED structure for changing the LED status
768 * by mac8011 or the kernel.
769 */
770#ifdef CONFIG_RT2X00_LIB_LEDS
a9450b70
ID
771 struct rt2x00_led led_radio;
772 struct rt2x00_led led_assoc;
773 struct rt2x00_led led_qual;
774 u16 led_mcu_reg;
775#endif /* CONFIG_RT2X00_LIB_LEDS */
776
95ea3627 777 /*
7dab73b3
ID
778 * Device state flags.
779 * In these flags the current status is stored.
780 * Access to these flags should occur atomically.
95ea3627
ID
781 */
782 unsigned long flags;
95ea3627 783
7dab73b3
ID
784 /*
785 * Device capabiltiy flags.
786 * In these flags the device/driver capabilities are stored.
787 * Access to these flags should occur non-atomically.
788 */
789 unsigned long cap_flags;
790
440ddada
ID
791 /*
792 * Device information, Bus IRQ and name (PCI, SoC)
793 */
794 int irq;
795 const char *name;
796
95ea3627
ID
797 /*
798 * Chipset identification.
799 */
800 struct rt2x00_chip chip;
801
802 /*
803 * hw capability specifications.
804 */
805 struct hw_mode_spec spec;
806
addc81bd
ID
807 /*
808 * This is the default TX/RX antenna setup as indicated
6d64360a 809 * by the device's EEPROM.
addc81bd
ID
810 */
811 struct antenna_setup default_ant;
812
95ea3627
ID
813 /*
814 * Register pointers
21795094
ID
815 * csr.base: CSR base register address. (PCI)
816 * csr.cache: CSR cache for usb_control_msg. (USB)
95ea3627 817 */
21795094
ID
818 union csr {
819 void __iomem *base;
820 void *cache;
821 } csr;
95ea3627 822
3d82346c 823 /*
8ff48a8b
ID
824 * Mutex to protect register accesses.
825 * For PCI and USB devices it protects against concurrent indirect
826 * register access (BBP, RF, MCU) since accessing those
827 * registers require multiple calls to the CSR registers.
828 * For USB devices it also protects the csr_cache since that
829 * field is used for normal CSR access and it cannot support
830 * multiple callers simultaneously.
831 */
832 struct mutex csr_mutex;
3d82346c 833
3c4f2085
ID
834 /*
835 * Current packet filter configuration for the device.
836 * This contains all currently active FIF_* flags send
837 * to us by mac80211 during configure_filter().
838 */
839 unsigned int packet_filter;
840
95ea3627 841 /*
6bb40dd1
ID
842 * Interface details:
843 * - Open ap interface count.
844 * - Open sta interface count.
845 * - Association count.
69cf36a4 846 * - Beaconing enabled count.
95ea3627 847 */
6bb40dd1
ID
848 unsigned int intf_ap_count;
849 unsigned int intf_sta_count;
850 unsigned int intf_associated;
69cf36a4 851 unsigned int intf_beaconing;
95ea3627 852
55d2e9da
GW
853 /*
854 * Interface combinations
855 */
856 struct ieee80211_iface_limit if_limits_ap;
857 struct ieee80211_iface_combination if_combinations[NUM_IF_COMB];
858
95ea3627
ID
859 /*
860 * Link quality
861 */
862 struct link link;
863
864 /*
865 * EEPROM data.
866 */
867 __le16 *eeprom;
868
869 /*
870 * Active RF register values.
871 * These are stored here so we don't need
872 * to read the rf registers and can directly
873 * use this value instead.
874 * This field should be accessed by using
875 * rt2x00_rf_read() and rt2x00_rf_write().
876 */
877 u32 *rf;
878
ba2ab471
ID
879 /*
880 * LNA gain
881 */
882 short lna_gain;
883
95ea3627
ID
884 /*
885 * Current TX power value.
886 */
887 u16 tx_power;
888
42c82857
ID
889 /*
890 * Current retry values.
891 */
892 u8 short_retry;
893 u8 long_retry;
894
95ea3627
ID
895 /*
896 * Rssi <-> Dbm offset
897 */
898 u8 rssi_offset;
899
900 /*
bef453dc 901 * Frequency offset.
95ea3627
ID
902 */
903 u8 freq_offset;
904
1c0bcf89
ID
905 /*
906 * Association id.
907 */
908 u16 aid;
909
6b347bff
ID
910 /*
911 * Beacon interval.
912 */
913 u16 beacon_int;
914
1c0bcf89
ID
915 /**
916 * Timestamp of last received beacon
917 */
918 unsigned long last_beacon;
919
95ea3627
ID
920 /*
921 * Low level statistics which will have
922 * to be kept up to date while device is running.
923 */
924 struct ieee80211_low_level_stats low_level_stats;
925
0439f536
ID
926 /**
927 * Work queue for all work which should not be placed
928 * on the mac80211 workqueue (because of dependencies
929 * between various work structures).
930 */
931 struct workqueue_struct *workqueue;
932
95ea3627 933 /*
4150c572 934 * Scheduled work.
8e260c22
ID
935 * NOTE: intf_work will use ieee80211_iterate_active_interfaces()
936 * which means it cannot be placed on the hw->workqueue
937 * due to RTNL locking requirements.
95ea3627 938 */
6bb40dd1 939 struct work_struct intf_work;
95ea3627 940
7e613e16
ID
941 /**
942 * Scheduled work for TX/RX done handling (USB devices)
943 */
944 struct work_struct rxdone_work;
945 struct work_struct txdone_work;
946
1c0bcf89
ID
947 /*
948 * Powersaving work
949 */
950 struct delayed_work autowakeup_work;
ed66ba47 951 struct work_struct sleep_work;
1c0bcf89 952
95ea3627 953 /*
e74df4a7 954 * Data queue arrays for RX, TX, Beacon and ATIM.
95ea3627 955 */
b869767b 956 unsigned int data_queues;
181d6902
ID
957 struct data_queue *rx;
958 struct data_queue *tx;
959 struct data_queue *bcn;
e74df4a7 960 struct data_queue *atim;
95ea3627
ID
961
962 /*
963 * Firmware image.
964 */
965 const struct firmware *fw;
ee134fcc 966
96c3da7d
HS
967 /*
968 * FIFO for storing tx status reports between isr and tasklet.
969 */
c4d63244 970 DECLARE_KFIFO_PTR(txstatus_fifo, u32);
96c3da7d 971
f0187a19
JS
972 /*
973 * Timer to ensure tx status reports are read (rt2800usb).
974 */
f421111b 975 struct hrtimer txstatus_timer;
f0187a19 976
96c3da7d
HS
977 /*
978 * Tasklet for processing tx status reports (rt2800pci).
979 */
980 struct tasklet_struct txstatus_tasklet;
c5c65761
HS
981 struct tasklet_struct pretbtt_tasklet;
982 struct tasklet_struct tbtt_tasklet;
983 struct tasklet_struct rxdone_tasklet;
984 struct tasklet_struct autowake_tasklet;
985
2e9c43dd
JL
986 /*
987 * Used for VCO periodic calibration.
988 */
989 int rf_channel;
990
c5c65761
HS
991 /*
992 * Protect the interrupt mask register.
993 */
994 spinlock_t irqmask_lock;
84e9e8eb
HS
995
996 /*
997 * List of BlockAckReq TX entries that need driver BlockAck processing.
998 */
999 struct list_head bar_list;
1000 spinlock_t bar_list_lock;
5616a6ef
GJ
1001
1002 /* Extra TX headroom required for alignment purposes. */
1003 unsigned int extra_tx_headroom;
84e9e8eb
HS
1004};
1005
1006struct rt2x00_bar_list_entry {
1007 struct list_head list;
1008 struct rcu_head head;
1009
1010 struct queue_entry *entry;
1011 int block_acked;
1012
1013 /* Relevant parts of the IEEE80211 BAR header */
1014 __u8 ra[6];
1015 __u8 ta[6];
1016 __le16 control;
1017 __le16 start_seq_num;
95ea3627
ID
1018};
1019
1f285f14
BZ
1020/*
1021 * Register defines.
1022 * Some registers require multiple attempts before success,
1023 * in those cases REGISTER_BUSY_COUNT attempts should be
7a5a7352
SG
1024 * taken with a REGISTER_BUSY_DELAY interval. Due to USB
1025 * bus delays, we do not have to loop so many times to wait
1026 * for valid register value on that bus.
1f285f14 1027 */
ae4ecb9f 1028#define REGISTER_BUSY_COUNT 100
7a5a7352 1029#define REGISTER_USB_BUSY_COUNT 20
1f285f14
BZ
1030#define REGISTER_BUSY_DELAY 100
1031
95ea3627
ID
1032/*
1033 * Generic RF access.
1034 * The RF is being accessed by word index.
1035 */
0e14f6d3 1036static inline void rt2x00_rf_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID
1037 const unsigned int word, u32 *data)
1038{
6b26dead
PR
1039 BUG_ON(word < 1 || word > rt2x00dev->ops->rf_size / sizeof(u32));
1040 *data = rt2x00dev->rf[word - 1];
95ea3627
ID
1041}
1042
0e14f6d3 1043static inline void rt2x00_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID
1044 const unsigned int word, u32 data)
1045{
6b26dead
PR
1046 BUG_ON(word < 1 || word > rt2x00dev->ops->rf_size / sizeof(u32));
1047 rt2x00dev->rf[word - 1] = data;
95ea3627
ID
1048}
1049
1050/*
8756130b 1051 * Generic EEPROM access. The EEPROM is being accessed by word or byte index.
95ea3627 1052 */
0e14f6d3 1053static inline void *rt2x00_eeprom_addr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID
1054 const unsigned int word)
1055{
1056 return (void *)&rt2x00dev->eeprom[word];
1057}
1058
0e14f6d3 1059static inline void rt2x00_eeprom_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID
1060 const unsigned int word, u16 *data)
1061{
1062 *data = le16_to_cpu(rt2x00dev->eeprom[word]);
1063}
1064
0e14f6d3 1065static inline void rt2x00_eeprom_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID
1066 const unsigned int word, u16 data)
1067{
1068 rt2x00dev->eeprom[word] = cpu_to_le16(data);
1069}
1070
8756130b
SG
1071static inline u8 rt2x00_eeprom_byte(struct rt2x00_dev *rt2x00dev,
1072 const unsigned int byte)
1073{
1074 return *(((u8 *)rt2x00dev->eeprom) + byte);
1075}
1076
95ea3627
ID
1077/*
1078 * Chipset handlers
1079 */
1080static inline void rt2x00_set_chip(struct rt2x00_dev *rt2x00dev,
49e721ec 1081 const u16 rt, const u16 rf, const u16 rev)
95ea3627 1082{
95ea3627
ID
1083 rt2x00dev->chip.rt = rt;
1084 rt2x00dev->chip.rf = rf;
1085 rt2x00dev->chip.rev = rev;
440ddada 1086
ec9c4989
JP
1087 rt2x00_info(rt2x00dev, "Chipset detected - rt: %04x, rf: %04x, rev: %04x\n",
1088 rt2x00dev->chip.rt, rt2x00dev->chip.rf,
1089 rt2x00dev->chip.rev);
16475b09
GW
1090}
1091
5ce69003
GJ
1092static inline void rt2x00_set_rt(struct rt2x00_dev *rt2x00dev,
1093 const u16 rt, const u16 rev)
1094{
1095 rt2x00dev->chip.rt = rt;
1096 rt2x00dev->chip.rev = rev;
1097
ec9c4989
JP
1098 rt2x00_info(rt2x00dev, "RT chipset %04x, rev %04x detected\n",
1099 rt2x00dev->chip.rt, rt2x00dev->chip.rev);
5ce69003
GJ
1100}
1101
1102static inline void rt2x00_set_rf(struct rt2x00_dev *rt2x00dev, const u16 rf)
1103{
1104 rt2x00dev->chip.rf = rf;
1105
ec9c4989
JP
1106 rt2x00_info(rt2x00dev, "RF chipset %04x detected\n",
1107 rt2x00dev->chip.rf);
5ce69003
GJ
1108}
1109
8d0c9b65 1110static inline bool rt2x00_rt(struct rt2x00_dev *rt2x00dev, const u16 rt)
95ea3627 1111{
5122d898 1112 return (rt2x00dev->chip.rt == rt);
95ea3627
ID
1113}
1114
8d0c9b65 1115static inline bool rt2x00_rf(struct rt2x00_dev *rt2x00dev, const u16 rf)
95ea3627 1116{
5122d898 1117 return (rt2x00dev->chip.rf == rf);
95ea3627
ID
1118}
1119
49e721ec 1120static inline u16 rt2x00_rev(struct rt2x00_dev *rt2x00dev)
95ea3627 1121{
5122d898 1122 return rt2x00dev->chip.rev;
95ea3627
ID
1123}
1124
8d0c9b65
GW
1125static inline bool rt2x00_rt_rev(struct rt2x00_dev *rt2x00dev,
1126 const u16 rt, const u16 rev)
1127{
1128 return (rt2x00_rt(rt2x00dev, rt) && rt2x00_rev(rt2x00dev) == rev);
1129}
1130
1131static inline bool rt2x00_rt_rev_lt(struct rt2x00_dev *rt2x00dev,
1132 const u16 rt, const u16 rev)
1133{
1134 return (rt2x00_rt(rt2x00dev, rt) && rt2x00_rev(rt2x00dev) < rev);
1135}
1136
1137static inline bool rt2x00_rt_rev_gte(struct rt2x00_dev *rt2x00dev,
1138 const u16 rt, const u16 rev)
1139{
1140 return (rt2x00_rt(rt2x00dev, rt) && rt2x00_rev(rt2x00dev) >= rev);
1141}
1142
5822e070
BZ
1143static inline void rt2x00_set_chip_intf(struct rt2x00_dev *rt2x00dev,
1144 enum rt2x00_chip_intf intf)
1145{
1146 rt2x00dev->chip.intf = intf;
1147}
1148
5122d898 1149static inline bool rt2x00_intf(struct rt2x00_dev *rt2x00dev,
5822e070
BZ
1150 enum rt2x00_chip_intf intf)
1151{
5122d898 1152 return (rt2x00dev->chip.intf == intf);
5822e070
BZ
1153}
1154
cea90e55 1155static inline bool rt2x00_is_pci(struct rt2x00_dev *rt2x00dev)
5822e070 1156{
6e1fdd11
GW
1157 return rt2x00_intf(rt2x00dev, RT2X00_CHIP_INTF_PCI) ||
1158 rt2x00_intf(rt2x00dev, RT2X00_CHIP_INTF_PCIE);
1159}
1160
1161static inline bool rt2x00_is_pcie(struct rt2x00_dev *rt2x00dev)
1162{
1163 return rt2x00_intf(rt2x00dev, RT2X00_CHIP_INTF_PCIE);
5822e070
BZ
1164}
1165
cea90e55 1166static inline bool rt2x00_is_usb(struct rt2x00_dev *rt2x00dev)
5822e070 1167{
5122d898 1168 return rt2x00_intf(rt2x00dev, RT2X00_CHIP_INTF_USB);
5822e070
BZ
1169}
1170
cea90e55
GW
1171static inline bool rt2x00_is_soc(struct rt2x00_dev *rt2x00dev)
1172{
1173 return rt2x00_intf(rt2x00dev, RT2X00_CHIP_INTF_SOC);
1174}
1175
a44d0141
GJ
1176/* Helpers for capability flags */
1177
1178static inline bool
1179rt2x00_has_cap_flag(struct rt2x00_dev *rt2x00dev,
1180 enum rt2x00_capability_flags cap_flag)
1181{
1182 return test_bit(cap_flag, &rt2x00dev->cap_flags);
1183}
1184
1185static inline bool
1186rt2x00_has_cap_hw_crypto(struct rt2x00_dev *rt2x00dev)
1187{
1188 return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_HW_CRYPTO);
1189}
1190
1191static inline bool
1192rt2x00_has_cap_power_limit(struct rt2x00_dev *rt2x00dev)
1193{
1194 return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_POWER_LIMIT);
1195}
1196
1197static inline bool
1198rt2x00_has_cap_control_filters(struct rt2x00_dev *rt2x00dev)
1199{
1200 return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_CONTROL_FILTERS);
1201}
1202
1203static inline bool
1204rt2x00_has_cap_control_filter_pspoll(struct rt2x00_dev *rt2x00dev)
1205{
1206 return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_CONTROL_FILTER_PSPOLL);
1207}
1208
1209static inline bool
1210rt2x00_has_cap_pre_tbtt_interrupt(struct rt2x00_dev *rt2x00dev)
1211{
1212 return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_PRE_TBTT_INTERRUPT);
1213}
1214
1215static inline bool
1216rt2x00_has_cap_link_tuning(struct rt2x00_dev *rt2x00dev)
1217{
1218 return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_LINK_TUNING);
1219}
1220
1221static inline bool
1222rt2x00_has_cap_frame_type(struct rt2x00_dev *rt2x00dev)
1223{
1224 return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_FRAME_TYPE);
1225}
1226
1227static inline bool
1228rt2x00_has_cap_rf_sequence(struct rt2x00_dev *rt2x00dev)
1229{
1230 return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_RF_SEQUENCE);
1231}
1232
1233static inline bool
1234rt2x00_has_cap_external_lna_a(struct rt2x00_dev *rt2x00dev)
1235{
1236 return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_EXTERNAL_LNA_A);
1237}
1238
1239static inline bool
1240rt2x00_has_cap_external_lna_bg(struct rt2x00_dev *rt2x00dev)
1241{
1242 return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_EXTERNAL_LNA_BG);
1243}
1244
1245static inline bool
1246rt2x00_has_cap_double_antenna(struct rt2x00_dev *rt2x00dev)
1247{
1248 return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_DOUBLE_ANTENNA);
1249}
1250
1251static inline bool
1252rt2x00_has_cap_bt_coexist(struct rt2x00_dev *rt2x00dev)
1253{
1254 return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_BT_COEXIST);
1255}
1256
1257static inline bool
1258rt2x00_has_cap_vco_recalibration(struct rt2x00_dev *rt2x00dev)
1259{
1260 return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_VCO_RECALIBRATION);
1261}
1262
239c249d 1263/**
c4da0048 1264 * rt2x00queue_map_txskb - Map a skb into DMA for TX purposes.
fa69560f 1265 * @entry: Pointer to &struct queue_entry
4ea545d4
SG
1266 *
1267 * Returns -ENOMEM if mapping fail, 0 otherwise.
239c249d 1268 */
4ea545d4 1269int rt2x00queue_map_txskb(struct queue_entry *entry);
239c249d 1270
0b8004aa
GW
1271/**
1272 * rt2x00queue_unmap_skb - Unmap a skb from DMA.
fa69560f 1273 * @entry: Pointer to &struct queue_entry
0b8004aa 1274 */
fa69560f 1275void rt2x00queue_unmap_skb(struct queue_entry *entry);
0b8004aa 1276
11f818e0
HS
1277/**
1278 * rt2x00queue_get_tx_queue - Convert tx queue index to queue pointer
1279 * @rt2x00dev: Pointer to &struct rt2x00_dev.
1280 * @queue: rt2x00 queue index (see &enum data_queue_qid).
1281 *
1282 * Returns NULL for non tx queues.
1283 */
1284static inline struct data_queue *
1285rt2x00queue_get_tx_queue(struct rt2x00_dev *rt2x00dev,
1286 const enum data_queue_qid queue)
1287{
1288 if (queue < rt2x00dev->ops->tx_queues && rt2x00dev->tx)
1289 return &rt2x00dev->tx[queue];
1290
61c6e489
GW
1291 if (queue == QID_ATIM)
1292 return rt2x00dev->atim;
1293
11f818e0
HS
1294 return NULL;
1295}
1296
181d6902
ID
1297/**
1298 * rt2x00queue_get_entry - Get queue entry where the given index points to.
9a46d44e 1299 * @queue: Pointer to &struct data_queue from where we obtain the entry.
181d6902
ID
1300 * @index: Index identifier for obtaining the correct index.
1301 */
1302struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue,
1303 enum queue_index index);
1304
0b7fde54
ID
1305/**
1306 * rt2x00queue_pause_queue - Pause a data queue
1307 * @queue: Pointer to &struct data_queue.
1308 *
1309 * This function will pause the data queue locally, preventing
1310 * new frames to be added to the queue (while the hardware is
1311 * still allowed to run).
1312 */
1313void rt2x00queue_pause_queue(struct data_queue *queue);
1314
1315/**
1316 * rt2x00queue_unpause_queue - unpause a data queue
1317 * @queue: Pointer to &struct data_queue.
1318 *
1319 * This function will unpause the data queue locally, allowing
1320 * new frames to be added to the queue again.
1321 */
1322void rt2x00queue_unpause_queue(struct data_queue *queue);
1323
1324/**
1325 * rt2x00queue_start_queue - Start a data queue
1326 * @queue: Pointer to &struct data_queue.
1327 *
1328 * This function will start handling all pending frames in the queue.
1329 */
1330void rt2x00queue_start_queue(struct data_queue *queue);
1331
1332/**
1333 * rt2x00queue_stop_queue - Halt a data queue
1334 * @queue: Pointer to &struct data_queue.
1335 *
1336 * This function will stop all pending frames in the queue.
1337 */
1338void rt2x00queue_stop_queue(struct data_queue *queue);
1339
5be65609
ID
1340/**
1341 * rt2x00queue_flush_queue - Flush a data queue
1342 * @queue: Pointer to &struct data_queue.
1343 * @drop: True to drop all pending frames.
1344 *
1345 * This function will flush the queue. After this call
25985edc 1346 * the queue is guaranteed to be empty.
5be65609
ID
1347 */
1348void rt2x00queue_flush_queue(struct data_queue *queue, bool drop);
1349
0b7fde54
ID
1350/**
1351 * rt2x00queue_start_queues - Start all data queues
1352 * @rt2x00dev: Pointer to &struct rt2x00_dev.
1353 *
1354 * This function will loop through all available queues to start them
1355 */
1356void rt2x00queue_start_queues(struct rt2x00_dev *rt2x00dev);
1357
1358/**
1359 * rt2x00queue_stop_queues - Halt all data queues
1360 * @rt2x00dev: Pointer to &struct rt2x00_dev.
1361 *
1362 * This function will loop through all available queues to stop
1363 * any pending frames.
1364 */
1365void rt2x00queue_stop_queues(struct rt2x00_dev *rt2x00dev);
1366
5be65609
ID
1367/**
1368 * rt2x00queue_flush_queues - Flush all data queues
1369 * @rt2x00dev: Pointer to &struct rt2x00_dev.
1370 * @drop: True to drop all pending frames.
1371 *
1372 * This function will loop through all available queues to flush
1373 * any pending frames.
1374 */
1375void rt2x00queue_flush_queues(struct rt2x00_dev *rt2x00dev, bool drop);
1376
b4df4708
GW
1377/*
1378 * Debugfs handlers.
1379 */
1380/**
1381 * rt2x00debug_dump_frame - Dump a frame to userspace through debugfs.
1382 * @rt2x00dev: Pointer to &struct rt2x00_dev.
1383 * @type: The type of frame that is being dumped.
1384 * @skb: The skb containing the frame to be dumped.
1385 */
1386#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1387void rt2x00debug_dump_frame(struct rt2x00_dev *rt2x00dev,
1388 enum rt2x00_dump_type type, struct sk_buff *skb);
1389#else
1390static inline void rt2x00debug_dump_frame(struct rt2x00_dev *rt2x00dev,
1391 enum rt2x00_dump_type type,
1392 struct sk_buff *skb)
1393{
1394}
1395#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1396
18325523
HS
1397/*
1398 * Utility functions.
1399 */
1400u32 rt2x00lib_get_bssidx(struct rt2x00_dev *rt2x00dev,
1401 struct ieee80211_vif *vif);
1402
95ea3627
ID
1403/*
1404 * Interrupt context handlers.
1405 */
1406void rt2x00lib_beacondone(struct rt2x00_dev *rt2x00dev);
9f926fb5 1407void rt2x00lib_pretbtt(struct rt2x00_dev *rt2x00dev);
64e7d723 1408void rt2x00lib_dmastart(struct queue_entry *entry);
652a9dd2 1409void rt2x00lib_dmadone(struct queue_entry *entry);
181d6902
ID
1410void rt2x00lib_txdone(struct queue_entry *entry,
1411 struct txdone_entry_desc *txdesc);
3392bece 1412void rt2x00lib_txdone_noinfo(struct queue_entry *entry, u32 status);
88211021 1413void rt2x00lib_rxdone(struct queue_entry *entry, gfp_t gfp);
95ea3627 1414
95ea3627
ID
1415/*
1416 * mac80211 handlers.
1417 */
36323f81
TH
1418void rt2x00mac_tx(struct ieee80211_hw *hw,
1419 struct ieee80211_tx_control *control,
1420 struct sk_buff *skb);
95ea3627
ID
1421int rt2x00mac_start(struct ieee80211_hw *hw);
1422void rt2x00mac_stop(struct ieee80211_hw *hw);
1423int rt2x00mac_add_interface(struct ieee80211_hw *hw,
1ed32e4f 1424 struct ieee80211_vif *vif);
95ea3627 1425void rt2x00mac_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 1426 struct ieee80211_vif *vif);
e8975581 1427int rt2x00mac_config(struct ieee80211_hw *hw, u32 changed);
3a643d24
ID
1428void rt2x00mac_configure_filter(struct ieee80211_hw *hw,
1429 unsigned int changed_flags,
1430 unsigned int *total_flags,
3ac64bee 1431 u64 multicast);
930c06f2
SS
1432int rt2x00mac_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
1433 bool set);
2bb057d0
ID
1434#ifdef CONFIG_RT2X00_LIB_CRYPTO
1435int rt2x00mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d 1436 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
2bb057d0
ID
1437 struct ieee80211_key_conf *key);
1438#else
1439#define rt2x00mac_set_key NULL
1440#endif /* CONFIG_RT2X00_LIB_CRYPTO */
b4943d81
HS
1441int rt2x00mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1442 struct ieee80211_sta *sta);
1443int rt2x00mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1444 struct ieee80211_sta *sta);
a344d677
JB
1445void rt2x00mac_sw_scan_start(struct ieee80211_hw *hw,
1446 struct ieee80211_vif *vif,
1447 const u8 *mac_addr);
1448void rt2x00mac_sw_scan_complete(struct ieee80211_hw *hw,
1449 struct ieee80211_vif *vif);
95ea3627
ID
1450int rt2x00mac_get_stats(struct ieee80211_hw *hw,
1451 struct ieee80211_low_level_stats *stats);
471b3efd
JB
1452void rt2x00mac_bss_info_changed(struct ieee80211_hw *hw,
1453 struct ieee80211_vif *vif,
1454 struct ieee80211_bss_conf *bss_conf,
1455 u32 changes);
8a3a3c85
EP
1456int rt2x00mac_conf_tx(struct ieee80211_hw *hw,
1457 struct ieee80211_vif *vif, u16 queue,
95ea3627 1458 const struct ieee80211_tx_queue_params *params);
e47a5cdd 1459void rt2x00mac_rfkill_poll(struct ieee80211_hw *hw);
77be2c54
EG
1460void rt2x00mac_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1461 u32 queues, bool drop);
0ed7b3c0
ID
1462int rt2x00mac_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant);
1463int rt2x00mac_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant);
e7dee444
ID
1464void rt2x00mac_get_ringparam(struct ieee80211_hw *hw,
1465 u32 *tx, u32 *tx_max, u32 *rx, u32 *rx_max);
5f0dd296 1466bool rt2x00mac_tx_frames_pending(struct ieee80211_hw *hw);
95ea3627
ID
1467
1468/*
1469 * Driver allocation handlers.
1470 */
1471int rt2x00lib_probe_dev(struct rt2x00_dev *rt2x00dev);
1472void rt2x00lib_remove_dev(struct rt2x00_dev *rt2x00dev);
1473#ifdef CONFIG_PM
1474int rt2x00lib_suspend(struct rt2x00_dev *rt2x00dev, pm_message_t state);
1475int rt2x00lib_resume(struct rt2x00_dev *rt2x00dev);
1476#endif /* CONFIG_PM */
1477
1478#endif /* RT2X00_H */
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