Commit | Line | Data |
---|---|---|
181d6902 | 1 | /* |
7e613e16 ID |
2 | Copyright (C) 2010 Willow Garage <http://www.willowgarage.com> |
3 | Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com> | |
9c9a0d14 | 4 | Copyright (C) 2004 - 2009 Gertjan van Wingerde <gwingerde@gmail.com> |
181d6902 ID |
5 | <http://rt2x00.serialmonkey.com> |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; if not, write to the | |
19 | Free Software Foundation, Inc., | |
20 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
21 | */ | |
22 | ||
23 | /* | |
24 | Module: rt2x00lib | |
25 | Abstract: rt2x00 queue specific routines. | |
26 | */ | |
27 | ||
5a0e3ad6 | 28 | #include <linux/slab.h> |
181d6902 ID |
29 | #include <linux/kernel.h> |
30 | #include <linux/module.h> | |
c4da0048 | 31 | #include <linux/dma-mapping.h> |
181d6902 ID |
32 | |
33 | #include "rt2x00.h" | |
34 | #include "rt2x00lib.h" | |
35 | ||
88211021 | 36 | struct sk_buff *rt2x00queue_alloc_rxskb(struct queue_entry *entry, gfp_t gfp) |
239c249d | 37 | { |
fa69560f | 38 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; |
c4da0048 GW |
39 | struct sk_buff *skb; |
40 | struct skb_frame_desc *skbdesc; | |
2bb057d0 ID |
41 | unsigned int frame_size; |
42 | unsigned int head_size = 0; | |
43 | unsigned int tail_size = 0; | |
239c249d GW |
44 | |
45 | /* | |
46 | * The frame size includes descriptor size, because the | |
47 | * hardware directly receive the frame into the skbuffer. | |
48 | */ | |
c4da0048 | 49 | frame_size = entry->queue->data_size + entry->queue->desc_size; |
239c249d GW |
50 | |
51 | /* | |
ff352391 ID |
52 | * The payload should be aligned to a 4-byte boundary, |
53 | * this means we need at least 3 bytes for moving the frame | |
54 | * into the correct offset. | |
239c249d | 55 | */ |
2bb057d0 ID |
56 | head_size = 4; |
57 | ||
58 | /* | |
59 | * For IV/EIV/ICV assembly we must make sure there is | |
60 | * at least 8 bytes bytes available in headroom for IV/EIV | |
9c3444d3 | 61 | * and 8 bytes for ICV data as tailroon. |
2bb057d0 | 62 | */ |
7dab73b3 | 63 | if (test_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags)) { |
2bb057d0 | 64 | head_size += 8; |
9c3444d3 | 65 | tail_size += 8; |
2bb057d0 | 66 | } |
239c249d GW |
67 | |
68 | /* | |
69 | * Allocate skbuffer. | |
70 | */ | |
88211021 | 71 | skb = __dev_alloc_skb(frame_size + head_size + tail_size, gfp); |
239c249d GW |
72 | if (!skb) |
73 | return NULL; | |
74 | ||
2bb057d0 ID |
75 | /* |
76 | * Make sure we not have a frame with the requested bytes | |
77 | * available in the head and tail. | |
78 | */ | |
79 | skb_reserve(skb, head_size); | |
239c249d GW |
80 | skb_put(skb, frame_size); |
81 | ||
c4da0048 GW |
82 | /* |
83 | * Populate skbdesc. | |
84 | */ | |
85 | skbdesc = get_skb_frame_desc(skb); | |
86 | memset(skbdesc, 0, sizeof(*skbdesc)); | |
87 | skbdesc->entry = entry; | |
88 | ||
7dab73b3 | 89 | if (test_bit(REQUIRE_DMA, &rt2x00dev->cap_flags)) { |
c4da0048 GW |
90 | skbdesc->skb_dma = dma_map_single(rt2x00dev->dev, |
91 | skb->data, | |
92 | skb->len, | |
93 | DMA_FROM_DEVICE); | |
94 | skbdesc->flags |= SKBDESC_DMA_MAPPED_RX; | |
95 | } | |
96 | ||
239c249d GW |
97 | return skb; |
98 | } | |
30caa6e3 | 99 | |
fa69560f | 100 | void rt2x00queue_map_txskb(struct queue_entry *entry) |
30caa6e3 | 101 | { |
fa69560f ID |
102 | struct device *dev = entry->queue->rt2x00dev->dev; |
103 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); | |
c4da0048 | 104 | |
3ee54a07 | 105 | skbdesc->skb_dma = |
fa69560f | 106 | dma_map_single(dev, entry->skb->data, entry->skb->len, DMA_TO_DEVICE); |
c4da0048 GW |
107 | skbdesc->flags |= SKBDESC_DMA_MAPPED_TX; |
108 | } | |
109 | EXPORT_SYMBOL_GPL(rt2x00queue_map_txskb); | |
110 | ||
fa69560f | 111 | void rt2x00queue_unmap_skb(struct queue_entry *entry) |
c4da0048 | 112 | { |
fa69560f ID |
113 | struct device *dev = entry->queue->rt2x00dev->dev; |
114 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); | |
c4da0048 GW |
115 | |
116 | if (skbdesc->flags & SKBDESC_DMA_MAPPED_RX) { | |
fa69560f | 117 | dma_unmap_single(dev, skbdesc->skb_dma, entry->skb->len, |
c4da0048 GW |
118 | DMA_FROM_DEVICE); |
119 | skbdesc->flags &= ~SKBDESC_DMA_MAPPED_RX; | |
546adf29 | 120 | } else if (skbdesc->flags & SKBDESC_DMA_MAPPED_TX) { |
fa69560f | 121 | dma_unmap_single(dev, skbdesc->skb_dma, entry->skb->len, |
c4da0048 GW |
122 | DMA_TO_DEVICE); |
123 | skbdesc->flags &= ~SKBDESC_DMA_MAPPED_TX; | |
124 | } | |
125 | } | |
0b8004aa | 126 | EXPORT_SYMBOL_GPL(rt2x00queue_unmap_skb); |
c4da0048 | 127 | |
fa69560f | 128 | void rt2x00queue_free_skb(struct queue_entry *entry) |
c4da0048 | 129 | { |
fa69560f | 130 | if (!entry->skb) |
9a613195 ID |
131 | return; |
132 | ||
fa69560f ID |
133 | rt2x00queue_unmap_skb(entry); |
134 | dev_kfree_skb_any(entry->skb); | |
135 | entry->skb = NULL; | |
30caa6e3 | 136 | } |
239c249d | 137 | |
daee6c09 | 138 | void rt2x00queue_align_frame(struct sk_buff *skb) |
9f166171 | 139 | { |
9f166171 | 140 | unsigned int frame_length = skb->len; |
daee6c09 | 141 | unsigned int align = ALIGN_SIZE(skb, 0); |
9f166171 ID |
142 | |
143 | if (!align) | |
144 | return; | |
145 | ||
daee6c09 ID |
146 | skb_push(skb, align); |
147 | memmove(skb->data, skb->data + align, frame_length); | |
148 | skb_trim(skb, frame_length); | |
149 | } | |
150 | ||
daee6c09 ID |
151 | void rt2x00queue_insert_l2pad(struct sk_buff *skb, unsigned int header_length) |
152 | { | |
2e331462 | 153 | unsigned int payload_length = skb->len - header_length; |
daee6c09 ID |
154 | unsigned int header_align = ALIGN_SIZE(skb, 0); |
155 | unsigned int payload_align = ALIGN_SIZE(skb, header_length); | |
e54be4e7 | 156 | unsigned int l2pad = payload_length ? L2PAD_SIZE(header_length) : 0; |
daee6c09 | 157 | |
2e331462 GW |
158 | /* |
159 | * Adjust the header alignment if the payload needs to be moved more | |
160 | * than the header. | |
161 | */ | |
162 | if (payload_align > header_align) | |
163 | header_align += 4; | |
164 | ||
165 | /* There is nothing to do if no alignment is needed */ | |
166 | if (!header_align) | |
167 | return; | |
daee6c09 | 168 | |
2e331462 GW |
169 | /* Reserve the amount of space needed in front of the frame */ |
170 | skb_push(skb, header_align); | |
171 | ||
172 | /* | |
173 | * Move the header. | |
174 | */ | |
175 | memmove(skb->data, skb->data + header_align, header_length); | |
176 | ||
177 | /* Move the payload, if present and if required */ | |
178 | if (payload_length && payload_align) | |
daee6c09 | 179 | memmove(skb->data + header_length + l2pad, |
a5186e99 | 180 | skb->data + header_length + l2pad + payload_align, |
2e331462 GW |
181 | payload_length); |
182 | ||
183 | /* Trim the skb to the correct size */ | |
184 | skb_trim(skb, header_length + l2pad + payload_length); | |
9f166171 ID |
185 | } |
186 | ||
daee6c09 ID |
187 | void rt2x00queue_remove_l2pad(struct sk_buff *skb, unsigned int header_length) |
188 | { | |
a061a93b GW |
189 | /* |
190 | * L2 padding is only present if the skb contains more than just the | |
191 | * IEEE 802.11 header. | |
192 | */ | |
193 | unsigned int l2pad = (skb->len > header_length) ? | |
194 | L2PAD_SIZE(header_length) : 0; | |
daee6c09 | 195 | |
354e39db | 196 | if (!l2pad) |
daee6c09 ID |
197 | return; |
198 | ||
a061a93b GW |
199 | memmove(skb->data + l2pad, skb->data, header_length); |
200 | skb_pull(skb, l2pad); | |
daee6c09 ID |
201 | } |
202 | ||
77b5621b GW |
203 | static void rt2x00queue_create_tx_descriptor_seq(struct rt2x00_dev *rt2x00dev, |
204 | struct sk_buff *skb, | |
7b40982e ID |
205 | struct txentry_desc *txdesc) |
206 | { | |
77b5621b GW |
207 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
208 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
7b40982e | 209 | struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif); |
7b40982e | 210 | |
c262e08b | 211 | if (!(tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)) |
7b40982e ID |
212 | return; |
213 | ||
7fe7ee77 HS |
214 | __set_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags); |
215 | ||
e66a8ddf SG |
216 | if (!test_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags)) { |
217 | /* | |
218 | * rt2800 has a H/W (or F/W) bug, device incorrectly increase | |
219 | * seqno on retransmited data (non-QOS) frames. To workaround | |
220 | * the problem let's generate seqno in software if QOS is | |
221 | * disabled. | |
222 | */ | |
223 | if (test_bit(CONFIG_QOS_DISABLED, &rt2x00dev->flags)) | |
224 | __clear_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags); | |
225 | else | |
226 | /* H/W will generate sequence number */ | |
227 | return; | |
228 | } | |
7fe7ee77 | 229 | |
7b40982e | 230 | /* |
7fe7ee77 HS |
231 | * The hardware is not able to insert a sequence number. Assign a |
232 | * software generated one here. | |
7b40982e ID |
233 | * |
234 | * This is wrong because beacons are not getting sequence | |
235 | * numbers assigned properly. | |
236 | * | |
237 | * A secondary problem exists for drivers that cannot toggle | |
238 | * sequence counting per-frame, since those will override the | |
239 | * sequence counter given by mac80211. | |
240 | */ | |
798eefde | 241 | spin_lock(&intf->seqlock); |
7b40982e ID |
242 | |
243 | if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags)) | |
244 | intf->seqno += 0x10; | |
245 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); | |
246 | hdr->seq_ctrl |= cpu_to_le16(intf->seqno); | |
247 | ||
798eefde | 248 | spin_unlock(&intf->seqlock); |
7b40982e | 249 | |
7b40982e ID |
250 | } |
251 | ||
77b5621b GW |
252 | static void rt2x00queue_create_tx_descriptor_plcp(struct rt2x00_dev *rt2x00dev, |
253 | struct sk_buff *skb, | |
7b40982e ID |
254 | struct txentry_desc *txdesc, |
255 | const struct rt2x00_rate *hwrate) | |
256 | { | |
77b5621b | 257 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
7b40982e ID |
258 | struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0]; |
259 | unsigned int data_length; | |
260 | unsigned int duration; | |
261 | unsigned int residual; | |
262 | ||
2517794b HS |
263 | /* |
264 | * Determine with what IFS priority this frame should be send. | |
265 | * Set ifs to IFS_SIFS when the this is not the first fragment, | |
266 | * or this fragment came after RTS/CTS. | |
267 | */ | |
268 | if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags)) | |
269 | txdesc->u.plcp.ifs = IFS_BACKOFF; | |
270 | else | |
271 | txdesc->u.plcp.ifs = IFS_SIFS; | |
272 | ||
7b40982e | 273 | /* Data length + CRC + Crypto overhead (IV/EIV/ICV/MIC) */ |
77b5621b GW |
274 | data_length = skb->len + 4; |
275 | data_length += rt2x00crypto_tx_overhead(rt2x00dev, skb); | |
7b40982e ID |
276 | |
277 | /* | |
278 | * PLCP setup | |
279 | * Length calculation depends on OFDM/CCK rate. | |
280 | */ | |
26a1d07f HS |
281 | txdesc->u.plcp.signal = hwrate->plcp; |
282 | txdesc->u.plcp.service = 0x04; | |
7b40982e ID |
283 | |
284 | if (hwrate->flags & DEV_RATE_OFDM) { | |
26a1d07f HS |
285 | txdesc->u.plcp.length_high = (data_length >> 6) & 0x3f; |
286 | txdesc->u.plcp.length_low = data_length & 0x3f; | |
7b40982e ID |
287 | } else { |
288 | /* | |
289 | * Convert length to microseconds. | |
290 | */ | |
291 | residual = GET_DURATION_RES(data_length, hwrate->bitrate); | |
292 | duration = GET_DURATION(data_length, hwrate->bitrate); | |
293 | ||
294 | if (residual != 0) { | |
295 | duration++; | |
296 | ||
297 | /* | |
298 | * Check if we need to set the Length Extension | |
299 | */ | |
300 | if (hwrate->bitrate == 110 && residual <= 30) | |
26a1d07f | 301 | txdesc->u.plcp.service |= 0x80; |
7b40982e ID |
302 | } |
303 | ||
26a1d07f HS |
304 | txdesc->u.plcp.length_high = (duration >> 8) & 0xff; |
305 | txdesc->u.plcp.length_low = duration & 0xff; | |
7b40982e ID |
306 | |
307 | /* | |
308 | * When preamble is enabled we should set the | |
309 | * preamble bit for the signal. | |
310 | */ | |
311 | if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) | |
26a1d07f | 312 | txdesc->u.plcp.signal |= 0x08; |
7b40982e ID |
313 | } |
314 | } | |
315 | ||
77b5621b GW |
316 | static void rt2x00queue_create_tx_descriptor_ht(struct rt2x00_dev *rt2x00dev, |
317 | struct sk_buff *skb, | |
46a01ec0 GW |
318 | struct txentry_desc *txdesc, |
319 | const struct rt2x00_rate *hwrate) | |
320 | { | |
77b5621b | 321 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
46a01ec0 | 322 | struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0]; |
77b5621b | 323 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
ead2bb64 | 324 | struct rt2x00_sta *sta_priv = NULL; |
46a01ec0 | 325 | |
ead2bb64 | 326 | if (tx_info->control.sta) { |
46a01ec0 GW |
327 | txdesc->u.ht.mpdu_density = |
328 | tx_info->control.sta->ht_cap.ampdu_density; | |
329 | ||
ead2bb64 HS |
330 | sta_priv = sta_to_rt2x00_sta(tx_info->control.sta); |
331 | txdesc->u.ht.wcid = sta_priv->wcid; | |
332 | } | |
333 | ||
46a01ec0 GW |
334 | /* |
335 | * If IEEE80211_TX_RC_MCS is set txrate->idx just contains the | |
336 | * mcs rate to be used | |
337 | */ | |
338 | if (txrate->flags & IEEE80211_TX_RC_MCS) { | |
339 | txdesc->u.ht.mcs = txrate->idx; | |
340 | ||
341 | /* | |
342 | * MIMO PS should be set to 1 for STA's using dynamic SM PS | |
343 | * when using more then one tx stream (>MCS7). | |
344 | */ | |
345 | if (tx_info->control.sta && txdesc->u.ht.mcs > 7 && | |
346 | ((tx_info->control.sta->ht_cap.cap & | |
347 | IEEE80211_HT_CAP_SM_PS) >> | |
348 | IEEE80211_HT_CAP_SM_PS_SHIFT) == | |
349 | WLAN_HT_CAP_SM_PS_DYNAMIC) | |
350 | __set_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags); | |
351 | } else { | |
352 | txdesc->u.ht.mcs = rt2x00_get_rate_mcs(hwrate->mcs); | |
353 | if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) | |
354 | txdesc->u.ht.mcs |= 0x08; | |
355 | } | |
356 | ||
da40f407 SG |
357 | if (test_bit(CONFIG_HT_DISABLED, &rt2x00dev->flags)) { |
358 | if (!(tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)) | |
359 | txdesc->u.ht.txop = TXOP_SIFS; | |
360 | else | |
361 | txdesc->u.ht.txop = TXOP_BACKOFF; | |
362 | ||
363 | /* Left zero on all other settings. */ | |
364 | return; | |
365 | } | |
366 | ||
367 | txdesc->u.ht.ba_size = 7; /* FIXME: What value is needed? */ | |
368 | ||
369 | /* | |
370 | * Only one STBC stream is supported for now. | |
371 | */ | |
372 | if (tx_info->flags & IEEE80211_TX_CTL_STBC) | |
373 | txdesc->u.ht.stbc = 1; | |
374 | ||
46a01ec0 GW |
375 | /* |
376 | * This frame is eligible for an AMPDU, however, don't aggregate | |
377 | * frames that are intended to probe a specific tx rate. | |
378 | */ | |
379 | if (tx_info->flags & IEEE80211_TX_CTL_AMPDU && | |
380 | !(tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) | |
381 | __set_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags); | |
382 | ||
383 | /* | |
384 | * Set 40Mhz mode if necessary (for legacy rates this will | |
385 | * duplicate the frame to both channels). | |
386 | */ | |
387 | if (txrate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH || | |
388 | txrate->flags & IEEE80211_TX_RC_DUP_DATA) | |
389 | __set_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags); | |
390 | if (txrate->flags & IEEE80211_TX_RC_SHORT_GI) | |
391 | __set_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags); | |
392 | ||
393 | /* | |
394 | * Determine IFS values | |
395 | * - Use TXOP_BACKOFF for management frames except beacons | |
396 | * - Use TXOP_SIFS for fragment bursts | |
397 | * - Use TXOP_HTTXOP for everything else | |
398 | * | |
399 | * Note: rt2800 devices won't use CTS protection (if used) | |
400 | * for frames not transmitted with TXOP_HTTXOP | |
401 | */ | |
402 | if (ieee80211_is_mgmt(hdr->frame_control) && | |
403 | !ieee80211_is_beacon(hdr->frame_control)) | |
404 | txdesc->u.ht.txop = TXOP_BACKOFF; | |
405 | else if (!(tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)) | |
406 | txdesc->u.ht.txop = TXOP_SIFS; | |
407 | else | |
408 | txdesc->u.ht.txop = TXOP_HTTXOP; | |
409 | } | |
410 | ||
77b5621b GW |
411 | static void rt2x00queue_create_tx_descriptor(struct rt2x00_dev *rt2x00dev, |
412 | struct sk_buff *skb, | |
bd88a781 | 413 | struct txentry_desc *txdesc) |
7050ec82 | 414 | { |
77b5621b GW |
415 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
416 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
55b585e2 HS |
417 | struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0]; |
418 | struct ieee80211_rate *rate; | |
419 | const struct rt2x00_rate *hwrate = NULL; | |
7050ec82 ID |
420 | |
421 | memset(txdesc, 0, sizeof(*txdesc)); | |
422 | ||
9f166171 | 423 | /* |
df624ca5 | 424 | * Header and frame information. |
9f166171 | 425 | */ |
77b5621b GW |
426 | txdesc->length = skb->len; |
427 | txdesc->header_length = ieee80211_get_hdrlen_from_skb(skb); | |
9f166171 | 428 | |
7050ec82 ID |
429 | /* |
430 | * Check whether this frame is to be acked. | |
431 | */ | |
e039fa4a | 432 | if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK)) |
7050ec82 ID |
433 | __set_bit(ENTRY_TXD_ACK, &txdesc->flags); |
434 | ||
435 | /* | |
436 | * Check if this is a RTS/CTS frame | |
437 | */ | |
ac104462 ID |
438 | if (ieee80211_is_rts(hdr->frame_control) || |
439 | ieee80211_is_cts(hdr->frame_control)) { | |
7050ec82 | 440 | __set_bit(ENTRY_TXD_BURST, &txdesc->flags); |
ac104462 | 441 | if (ieee80211_is_rts(hdr->frame_control)) |
7050ec82 | 442 | __set_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags); |
e039fa4a | 443 | else |
7050ec82 | 444 | __set_bit(ENTRY_TXD_CTS_FRAME, &txdesc->flags); |
e039fa4a | 445 | if (tx_info->control.rts_cts_rate_idx >= 0) |
2e92e6f2 | 446 | rate = |
e039fa4a | 447 | ieee80211_get_rts_cts_rate(rt2x00dev->hw, tx_info); |
7050ec82 ID |
448 | } |
449 | ||
450 | /* | |
451 | * Determine retry information. | |
452 | */ | |
e6a9854b | 453 | txdesc->retry_limit = tx_info->control.rates[0].count - 1; |
42c82857 | 454 | if (txdesc->retry_limit >= rt2x00dev->long_retry) |
7050ec82 ID |
455 | __set_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags); |
456 | ||
457 | /* | |
458 | * Check if more fragments are pending | |
459 | */ | |
2606e422 | 460 | if (ieee80211_has_morefrags(hdr->frame_control)) { |
7050ec82 ID |
461 | __set_bit(ENTRY_TXD_BURST, &txdesc->flags); |
462 | __set_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags); | |
463 | } | |
464 | ||
2606e422 HS |
465 | /* |
466 | * Check if more frames (!= fragments) are pending | |
467 | */ | |
468 | if (tx_info->flags & IEEE80211_TX_CTL_MORE_FRAMES) | |
469 | __set_bit(ENTRY_TXD_BURST, &txdesc->flags); | |
470 | ||
7050ec82 ID |
471 | /* |
472 | * Beacons and probe responses require the tsf timestamp | |
1bce85cf | 473 | * to be inserted into the frame. |
7050ec82 | 474 | */ |
1bce85cf HS |
475 | if (ieee80211_is_beacon(hdr->frame_control) || |
476 | ieee80211_is_probe_resp(hdr->frame_control)) | |
7050ec82 ID |
477 | __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags); |
478 | ||
7b40982e | 479 | if ((tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) && |
2517794b | 480 | !test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)) |
7050ec82 | 481 | __set_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags); |
7050ec82 | 482 | |
076f9582 ID |
483 | /* |
484 | * Determine rate modulation. | |
485 | */ | |
55b585e2 HS |
486 | if (txrate->flags & IEEE80211_TX_RC_GREEN_FIELD) |
487 | txdesc->rate_mode = RATE_MODE_HT_GREENFIELD; | |
488 | else if (txrate->flags & IEEE80211_TX_RC_MCS) | |
489 | txdesc->rate_mode = RATE_MODE_HT_MIX; | |
490 | else { | |
491 | rate = ieee80211_get_tx_rate(rt2x00dev->hw, tx_info); | |
492 | hwrate = rt2x00_get_rate(rate->hw_value); | |
493 | if (hwrate->flags & DEV_RATE_OFDM) | |
494 | txdesc->rate_mode = RATE_MODE_OFDM; | |
495 | else | |
496 | txdesc->rate_mode = RATE_MODE_CCK; | |
497 | } | |
7050ec82 | 498 | |
7b40982e ID |
499 | /* |
500 | * Apply TX descriptor handling by components | |
501 | */ | |
77b5621b GW |
502 | rt2x00crypto_create_tx_descriptor(rt2x00dev, skb, txdesc); |
503 | rt2x00queue_create_tx_descriptor_seq(rt2x00dev, skb, txdesc); | |
26a1d07f | 504 | |
7dab73b3 | 505 | if (test_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags)) |
77b5621b GW |
506 | rt2x00queue_create_tx_descriptor_ht(rt2x00dev, skb, txdesc, |
507 | hwrate); | |
26a1d07f | 508 | else |
77b5621b GW |
509 | rt2x00queue_create_tx_descriptor_plcp(rt2x00dev, skb, txdesc, |
510 | hwrate); | |
7050ec82 | 511 | } |
7050ec82 | 512 | |
78eea11b GW |
513 | static int rt2x00queue_write_tx_data(struct queue_entry *entry, |
514 | struct txentry_desc *txdesc) | |
515 | { | |
516 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; | |
517 | ||
518 | /* | |
519 | * This should not happen, we already checked the entry | |
520 | * was ours. When the hardware disagrees there has been | |
521 | * a queue corruption! | |
522 | */ | |
523 | if (unlikely(rt2x00dev->ops->lib->get_entry_state && | |
524 | rt2x00dev->ops->lib->get_entry_state(entry))) { | |
525 | ERROR(rt2x00dev, | |
526 | "Corrupt queue %d, accessing entry which is not ours.\n" | |
527 | "Please file bug report to %s.\n", | |
528 | entry->queue->qid, DRV_PROJECT); | |
529 | return -EINVAL; | |
530 | } | |
531 | ||
532 | /* | |
533 | * Add the requested extra tx headroom in front of the skb. | |
534 | */ | |
535 | skb_push(entry->skb, rt2x00dev->ops->extra_tx_headroom); | |
536 | memset(entry->skb->data, 0, rt2x00dev->ops->extra_tx_headroom); | |
537 | ||
538 | /* | |
76dd5ddf | 539 | * Call the driver's write_tx_data function, if it exists. |
78eea11b | 540 | */ |
76dd5ddf GW |
541 | if (rt2x00dev->ops->lib->write_tx_data) |
542 | rt2x00dev->ops->lib->write_tx_data(entry, txdesc); | |
78eea11b GW |
543 | |
544 | /* | |
545 | * Map the skb to DMA. | |
546 | */ | |
7dab73b3 | 547 | if (test_bit(REQUIRE_DMA, &rt2x00dev->cap_flags)) |
fa69560f | 548 | rt2x00queue_map_txskb(entry); |
78eea11b GW |
549 | |
550 | return 0; | |
551 | } | |
552 | ||
bd88a781 ID |
553 | static void rt2x00queue_write_tx_descriptor(struct queue_entry *entry, |
554 | struct txentry_desc *txdesc) | |
7050ec82 | 555 | { |
b869767b | 556 | struct data_queue *queue = entry->queue; |
7050ec82 | 557 | |
93331458 | 558 | queue->rt2x00dev->ops->lib->write_tx_desc(entry, txdesc); |
7050ec82 ID |
559 | |
560 | /* | |
561 | * All processing on the frame has been completed, this means | |
562 | * it is now ready to be dumped to userspace through debugfs. | |
563 | */ | |
93331458 | 564 | rt2x00debug_dump_frame(queue->rt2x00dev, DUMP_FRAME_TX, entry->skb); |
6295d815 GW |
565 | } |
566 | ||
8be4eed0 | 567 | static void rt2x00queue_kick_tx_queue(struct data_queue *queue, |
6295d815 GW |
568 | struct txentry_desc *txdesc) |
569 | { | |
7050ec82 | 570 | /* |
b869767b | 571 | * Check if we need to kick the queue, there are however a few rules |
6295d815 | 572 | * 1) Don't kick unless this is the last in frame in a burst. |
b869767b ID |
573 | * When the burst flag is set, this frame is always followed |
574 | * by another frame which in some way are related to eachother. | |
575 | * This is true for fragments, RTS or CTS-to-self frames. | |
6295d815 | 576 | * 2) Rule 1 can be broken when the available entries |
b869767b | 577 | * in the queue are less then a certain threshold. |
7050ec82 | 578 | */ |
b869767b ID |
579 | if (rt2x00queue_threshold(queue) || |
580 | !test_bit(ENTRY_TXD_BURST, &txdesc->flags)) | |
dbba306f | 581 | queue->rt2x00dev->ops->lib->kick_queue(queue); |
7050ec82 | 582 | } |
7050ec82 | 583 | |
7351c6bd JB |
584 | int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb, |
585 | bool local) | |
6db3786a | 586 | { |
e6a9854b | 587 | struct ieee80211_tx_info *tx_info; |
77a861c4 | 588 | struct queue_entry *entry; |
6db3786a | 589 | struct txentry_desc txdesc; |
d74f5ba4 | 590 | struct skb_frame_desc *skbdesc; |
e6a9854b | 591 | u8 rate_idx, rate_flags; |
77a861c4 GW |
592 | int ret = 0; |
593 | ||
6db3786a ID |
594 | /* |
595 | * Copy all TX descriptor information into txdesc, | |
596 | * after that we are free to use the skb->cb array | |
597 | * for our information. | |
598 | */ | |
77b5621b | 599 | rt2x00queue_create_tx_descriptor(queue->rt2x00dev, skb, &txdesc); |
6db3786a | 600 | |
d74f5ba4 | 601 | /* |
e6a9854b | 602 | * All information is retrieved from the skb->cb array, |
2bb057d0 | 603 | * now we should claim ownership of the driver part of that |
e6a9854b | 604 | * array, preserving the bitrate index and flags. |
d74f5ba4 | 605 | */ |
e6a9854b JB |
606 | tx_info = IEEE80211_SKB_CB(skb); |
607 | rate_idx = tx_info->control.rates[0].idx; | |
608 | rate_flags = tx_info->control.rates[0].flags; | |
0e3de998 | 609 | skbdesc = get_skb_frame_desc(skb); |
d74f5ba4 | 610 | memset(skbdesc, 0, sizeof(*skbdesc)); |
e6a9854b JB |
611 | skbdesc->tx_rate_idx = rate_idx; |
612 | skbdesc->tx_rate_flags = rate_flags; | |
d74f5ba4 | 613 | |
7351c6bd JB |
614 | if (local) |
615 | skbdesc->flags |= SKBDESC_NOT_MAC80211; | |
616 | ||
2bb057d0 ID |
617 | /* |
618 | * When hardware encryption is supported, and this frame | |
619 | * is to be encrypted, we should strip the IV/EIV data from | |
3ad2f3fb | 620 | * the frame so we can provide it to the driver separately. |
2bb057d0 ID |
621 | */ |
622 | if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc.flags) && | |
dddfb478 | 623 | !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc.flags)) { |
7dab73b3 | 624 | if (test_bit(REQUIRE_COPY_IV, &queue->rt2x00dev->cap_flags)) |
9eb4e21e | 625 | rt2x00crypto_tx_copy_iv(skb, &txdesc); |
dddfb478 | 626 | else |
9eb4e21e | 627 | rt2x00crypto_tx_remove_iv(skb, &txdesc); |
dddfb478 | 628 | } |
2bb057d0 | 629 | |
93354cbb | 630 | /* |
25985edc | 631 | * When DMA allocation is required we should guarantee to the |
93354cbb | 632 | * driver that the DMA is aligned to a 4-byte boundary. |
93354cbb ID |
633 | * However some drivers require L2 padding to pad the payload |
634 | * rather then the header. This could be a requirement for | |
635 | * PCI and USB devices, while header alignment only is valid | |
636 | * for PCI devices. | |
637 | */ | |
7dab73b3 | 638 | if (test_bit(REQUIRE_L2PAD, &queue->rt2x00dev->cap_flags)) |
128f8f77 | 639 | rt2x00queue_insert_l2pad(skb, txdesc.header_length); |
7dab73b3 | 640 | else if (test_bit(REQUIRE_DMA, &queue->rt2x00dev->cap_flags)) |
128f8f77 GW |
641 | rt2x00queue_align_frame(skb); |
642 | ||
3780d038 SG |
643 | /* |
644 | * That function must be called with bh disabled. | |
645 | */ | |
128f8f77 GW |
646 | spin_lock(&queue->tx_lock); |
647 | ||
648 | if (unlikely(rt2x00queue_full(queue))) { | |
649 | ERROR(queue->rt2x00dev, | |
650 | "Dropping frame due to full tx queue %d.\n", queue->qid); | |
651 | ret = -ENOBUFS; | |
652 | goto out; | |
653 | } | |
654 | ||
655 | entry = rt2x00queue_get_entry(queue, Q_INDEX); | |
656 | ||
657 | if (unlikely(test_and_set_bit(ENTRY_OWNER_DEVICE_DATA, | |
658 | &entry->flags))) { | |
659 | ERROR(queue->rt2x00dev, | |
660 | "Arrived at non-free entry in the non-full queue %d.\n" | |
661 | "Please file bug report to %s.\n", | |
662 | queue->qid, DRV_PROJECT); | |
663 | ret = -EINVAL; | |
664 | goto out; | |
665 | } | |
666 | ||
667 | skbdesc->entry = entry; | |
668 | entry->skb = skb; | |
9f166171 | 669 | |
2bb057d0 ID |
670 | /* |
671 | * It could be possible that the queue was corrupted and this | |
0e3de998 ID |
672 | * call failed. Since we always return NETDEV_TX_OK to mac80211, |
673 | * this frame will simply be dropped. | |
2bb057d0 | 674 | */ |
78eea11b | 675 | if (unlikely(rt2x00queue_write_tx_data(entry, &txdesc))) { |
0262ab0d | 676 | clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags); |
2bb057d0 | 677 | entry->skb = NULL; |
77a861c4 GW |
678 | ret = -EIO; |
679 | goto out; | |
6db3786a ID |
680 | } |
681 | ||
0262ab0d | 682 | set_bit(ENTRY_DATA_PENDING, &entry->flags); |
6db3786a | 683 | |
75256f03 | 684 | rt2x00queue_index_inc(entry, Q_INDEX); |
6db3786a | 685 | rt2x00queue_write_tx_descriptor(entry, &txdesc); |
8be4eed0 | 686 | rt2x00queue_kick_tx_queue(queue, &txdesc); |
6db3786a | 687 | |
77a861c4 GW |
688 | out: |
689 | spin_unlock(&queue->tx_lock); | |
690 | return ret; | |
6db3786a ID |
691 | } |
692 | ||
69cf36a4 HS |
693 | int rt2x00queue_clear_beacon(struct rt2x00_dev *rt2x00dev, |
694 | struct ieee80211_vif *vif) | |
695 | { | |
696 | struct rt2x00_intf *intf = vif_to_intf(vif); | |
697 | ||
698 | if (unlikely(!intf->beacon)) | |
699 | return -ENOBUFS; | |
700 | ||
701 | mutex_lock(&intf->beacon_skb_mutex); | |
702 | ||
703 | /* | |
704 | * Clean up the beacon skb. | |
705 | */ | |
706 | rt2x00queue_free_skb(intf->beacon); | |
707 | ||
708 | /* | |
709 | * Clear beacon (single bssid devices don't need to clear the beacon | |
710 | * since the beacon queue will get stopped anyway). | |
711 | */ | |
712 | if (rt2x00dev->ops->lib->clear_beacon) | |
713 | rt2x00dev->ops->lib->clear_beacon(intf->beacon); | |
714 | ||
715 | mutex_unlock(&intf->beacon_skb_mutex); | |
716 | ||
717 | return 0; | |
718 | } | |
719 | ||
8414ff07 HS |
720 | int rt2x00queue_update_beacon_locked(struct rt2x00_dev *rt2x00dev, |
721 | struct ieee80211_vif *vif) | |
bd88a781 ID |
722 | { |
723 | struct rt2x00_intf *intf = vif_to_intf(vif); | |
724 | struct skb_frame_desc *skbdesc; | |
725 | struct txentry_desc txdesc; | |
bd88a781 ID |
726 | |
727 | if (unlikely(!intf->beacon)) | |
728 | return -ENOBUFS; | |
729 | ||
17512dc3 IP |
730 | /* |
731 | * Clean up the beacon skb. | |
732 | */ | |
fa69560f | 733 | rt2x00queue_free_skb(intf->beacon); |
17512dc3 | 734 | |
bd88a781 | 735 | intf->beacon->skb = ieee80211_beacon_get(rt2x00dev->hw, vif); |
8414ff07 | 736 | if (!intf->beacon->skb) |
bd88a781 ID |
737 | return -ENOMEM; |
738 | ||
739 | /* | |
740 | * Copy all TX descriptor information into txdesc, | |
741 | * after that we are free to use the skb->cb array | |
742 | * for our information. | |
743 | */ | |
77b5621b | 744 | rt2x00queue_create_tx_descriptor(rt2x00dev, intf->beacon->skb, &txdesc); |
bd88a781 | 745 | |
bd88a781 ID |
746 | /* |
747 | * Fill in skb descriptor | |
748 | */ | |
749 | skbdesc = get_skb_frame_desc(intf->beacon->skb); | |
750 | memset(skbdesc, 0, sizeof(*skbdesc)); | |
bd88a781 ID |
751 | skbdesc->entry = intf->beacon; |
752 | ||
bd88a781 | 753 | /* |
69cf36a4 | 754 | * Send beacon to hardware. |
bd88a781 | 755 | */ |
f224f4ef | 756 | rt2x00dev->ops->lib->write_beacon(intf->beacon, &txdesc); |
bd88a781 | 757 | |
8414ff07 HS |
758 | return 0; |
759 | ||
760 | } | |
761 | ||
762 | int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev, | |
763 | struct ieee80211_vif *vif) | |
764 | { | |
765 | struct rt2x00_intf *intf = vif_to_intf(vif); | |
766 | int ret; | |
767 | ||
768 | mutex_lock(&intf->beacon_skb_mutex); | |
769 | ret = rt2x00queue_update_beacon_locked(rt2x00dev, vif); | |
17512dc3 IP |
770 | mutex_unlock(&intf->beacon_skb_mutex); |
771 | ||
8414ff07 | 772 | return ret; |
bd88a781 ID |
773 | } |
774 | ||
10e11568 | 775 | bool rt2x00queue_for_each_entry(struct data_queue *queue, |
5eb7efe8 ID |
776 | enum queue_index start, |
777 | enum queue_index end, | |
10e11568 HS |
778 | void *data, |
779 | bool (*fn)(struct queue_entry *entry, | |
780 | void *data)) | |
5eb7efe8 ID |
781 | { |
782 | unsigned long irqflags; | |
783 | unsigned int index_start; | |
784 | unsigned int index_end; | |
785 | unsigned int i; | |
786 | ||
787 | if (unlikely(start >= Q_INDEX_MAX || end >= Q_INDEX_MAX)) { | |
788 | ERROR(queue->rt2x00dev, | |
789 | "Entry requested from invalid index range (%d - %d)\n", | |
790 | start, end); | |
10e11568 | 791 | return true; |
5eb7efe8 ID |
792 | } |
793 | ||
794 | /* | |
795 | * Only protect the range we are going to loop over, | |
796 | * if during our loop a extra entry is set to pending | |
797 | * it should not be kicked during this run, since it | |
798 | * is part of another TX operation. | |
799 | */ | |
813f0339 | 800 | spin_lock_irqsave(&queue->index_lock, irqflags); |
5eb7efe8 ID |
801 | index_start = queue->index[start]; |
802 | index_end = queue->index[end]; | |
813f0339 | 803 | spin_unlock_irqrestore(&queue->index_lock, irqflags); |
5eb7efe8 ID |
804 | |
805 | /* | |
25985edc | 806 | * Start from the TX done pointer, this guarantees that we will |
5eb7efe8 ID |
807 | * send out all frames in the correct order. |
808 | */ | |
809 | if (index_start < index_end) { | |
10e11568 HS |
810 | for (i = index_start; i < index_end; i++) { |
811 | if (fn(&queue->entries[i], data)) | |
812 | return true; | |
813 | } | |
5eb7efe8 | 814 | } else { |
10e11568 HS |
815 | for (i = index_start; i < queue->limit; i++) { |
816 | if (fn(&queue->entries[i], data)) | |
817 | return true; | |
818 | } | |
5eb7efe8 | 819 | |
10e11568 HS |
820 | for (i = 0; i < index_end; i++) { |
821 | if (fn(&queue->entries[i], data)) | |
822 | return true; | |
823 | } | |
5eb7efe8 | 824 | } |
10e11568 HS |
825 | |
826 | return false; | |
5eb7efe8 ID |
827 | } |
828 | EXPORT_SYMBOL_GPL(rt2x00queue_for_each_entry); | |
829 | ||
181d6902 ID |
830 | struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue, |
831 | enum queue_index index) | |
832 | { | |
833 | struct queue_entry *entry; | |
5f46c4d0 | 834 | unsigned long irqflags; |
181d6902 ID |
835 | |
836 | if (unlikely(index >= Q_INDEX_MAX)) { | |
837 | ERROR(queue->rt2x00dev, | |
838 | "Entry requested from invalid index type (%d)\n", index); | |
839 | return NULL; | |
840 | } | |
841 | ||
813f0339 | 842 | spin_lock_irqsave(&queue->index_lock, irqflags); |
181d6902 ID |
843 | |
844 | entry = &queue->entries[queue->index[index]]; | |
845 | ||
813f0339 | 846 | spin_unlock_irqrestore(&queue->index_lock, irqflags); |
181d6902 ID |
847 | |
848 | return entry; | |
849 | } | |
850 | EXPORT_SYMBOL_GPL(rt2x00queue_get_entry); | |
851 | ||
75256f03 | 852 | void rt2x00queue_index_inc(struct queue_entry *entry, enum queue_index index) |
181d6902 | 853 | { |
75256f03 | 854 | struct data_queue *queue = entry->queue; |
5f46c4d0 ID |
855 | unsigned long irqflags; |
856 | ||
181d6902 ID |
857 | if (unlikely(index >= Q_INDEX_MAX)) { |
858 | ERROR(queue->rt2x00dev, | |
859 | "Index change on invalid index type (%d)\n", index); | |
860 | return; | |
861 | } | |
862 | ||
813f0339 | 863 | spin_lock_irqsave(&queue->index_lock, irqflags); |
181d6902 ID |
864 | |
865 | queue->index[index]++; | |
866 | if (queue->index[index] >= queue->limit) | |
867 | queue->index[index] = 0; | |
868 | ||
75256f03 | 869 | entry->last_action = jiffies; |
652a9dd2 | 870 | |
10b6b801 ID |
871 | if (index == Q_INDEX) { |
872 | queue->length++; | |
873 | } else if (index == Q_INDEX_DONE) { | |
874 | queue->length--; | |
55887511 | 875 | queue->count++; |
10b6b801 | 876 | } |
181d6902 | 877 | |
813f0339 | 878 | spin_unlock_irqrestore(&queue->index_lock, irqflags); |
181d6902 | 879 | } |
181d6902 | 880 | |
0b7fde54 ID |
881 | void rt2x00queue_pause_queue(struct data_queue *queue) |
882 | { | |
883 | if (!test_bit(DEVICE_STATE_PRESENT, &queue->rt2x00dev->flags) || | |
884 | !test_bit(QUEUE_STARTED, &queue->flags) || | |
885 | test_and_set_bit(QUEUE_PAUSED, &queue->flags)) | |
886 | return; | |
887 | ||
888 | switch (queue->qid) { | |
f615e9a3 ID |
889 | case QID_AC_VO: |
890 | case QID_AC_VI: | |
0b7fde54 ID |
891 | case QID_AC_BE: |
892 | case QID_AC_BK: | |
0b7fde54 ID |
893 | /* |
894 | * For TX queues, we have to disable the queue | |
895 | * inside mac80211. | |
896 | */ | |
897 | ieee80211_stop_queue(queue->rt2x00dev->hw, queue->qid); | |
898 | break; | |
899 | default: | |
900 | break; | |
901 | } | |
902 | } | |
903 | EXPORT_SYMBOL_GPL(rt2x00queue_pause_queue); | |
904 | ||
905 | void rt2x00queue_unpause_queue(struct data_queue *queue) | |
906 | { | |
907 | if (!test_bit(DEVICE_STATE_PRESENT, &queue->rt2x00dev->flags) || | |
908 | !test_bit(QUEUE_STARTED, &queue->flags) || | |
909 | !test_and_clear_bit(QUEUE_PAUSED, &queue->flags)) | |
910 | return; | |
911 | ||
912 | switch (queue->qid) { | |
f615e9a3 ID |
913 | case QID_AC_VO: |
914 | case QID_AC_VI: | |
0b7fde54 ID |
915 | case QID_AC_BE: |
916 | case QID_AC_BK: | |
0b7fde54 ID |
917 | /* |
918 | * For TX queues, we have to enable the queue | |
919 | * inside mac80211. | |
920 | */ | |
921 | ieee80211_wake_queue(queue->rt2x00dev->hw, queue->qid); | |
922 | break; | |
5be65609 ID |
923 | case QID_RX: |
924 | /* | |
925 | * For RX we need to kick the queue now in order to | |
926 | * receive frames. | |
927 | */ | |
928 | queue->rt2x00dev->ops->lib->kick_queue(queue); | |
0b7fde54 ID |
929 | default: |
930 | break; | |
931 | } | |
932 | } | |
933 | EXPORT_SYMBOL_GPL(rt2x00queue_unpause_queue); | |
934 | ||
935 | void rt2x00queue_start_queue(struct data_queue *queue) | |
936 | { | |
937 | mutex_lock(&queue->status_lock); | |
938 | ||
939 | if (!test_bit(DEVICE_STATE_PRESENT, &queue->rt2x00dev->flags) || | |
940 | test_and_set_bit(QUEUE_STARTED, &queue->flags)) { | |
941 | mutex_unlock(&queue->status_lock); | |
942 | return; | |
943 | } | |
944 | ||
945 | set_bit(QUEUE_PAUSED, &queue->flags); | |
946 | ||
947 | queue->rt2x00dev->ops->lib->start_queue(queue); | |
948 | ||
949 | rt2x00queue_unpause_queue(queue); | |
950 | ||
951 | mutex_unlock(&queue->status_lock); | |
952 | } | |
953 | EXPORT_SYMBOL_GPL(rt2x00queue_start_queue); | |
954 | ||
955 | void rt2x00queue_stop_queue(struct data_queue *queue) | |
956 | { | |
957 | mutex_lock(&queue->status_lock); | |
958 | ||
959 | if (!test_and_clear_bit(QUEUE_STARTED, &queue->flags)) { | |
960 | mutex_unlock(&queue->status_lock); | |
961 | return; | |
962 | } | |
963 | ||
964 | rt2x00queue_pause_queue(queue); | |
965 | ||
966 | queue->rt2x00dev->ops->lib->stop_queue(queue); | |
967 | ||
968 | mutex_unlock(&queue->status_lock); | |
969 | } | |
970 | EXPORT_SYMBOL_GPL(rt2x00queue_stop_queue); | |
971 | ||
5be65609 ID |
972 | void rt2x00queue_flush_queue(struct data_queue *queue, bool drop) |
973 | { | |
5be65609 ID |
974 | bool started; |
975 | bool tx_queue = | |
f615e9a3 | 976 | (queue->qid == QID_AC_VO) || |
5be65609 | 977 | (queue->qid == QID_AC_VI) || |
f615e9a3 ID |
978 | (queue->qid == QID_AC_BE) || |
979 | (queue->qid == QID_AC_BK); | |
5be65609 ID |
980 | |
981 | mutex_lock(&queue->status_lock); | |
982 | ||
983 | /* | |
984 | * If the queue has been started, we must stop it temporarily | |
985 | * to prevent any new frames to be queued on the device. If | |
986 | * we are not dropping the pending frames, the queue must | |
987 | * only be stopped in the software and not the hardware, | |
988 | * otherwise the queue will never become empty on its own. | |
989 | */ | |
990 | started = test_bit(QUEUE_STARTED, &queue->flags); | |
991 | if (started) { | |
992 | /* | |
993 | * Pause the queue | |
994 | */ | |
995 | rt2x00queue_pause_queue(queue); | |
996 | ||
997 | /* | |
998 | * If we are not supposed to drop any pending | |
999 | * frames, this means we must force a start (=kick) | |
1000 | * to the queue to make sure the hardware will | |
1001 | * start transmitting. | |
1002 | */ | |
1003 | if (!drop && tx_queue) | |
1004 | queue->rt2x00dev->ops->lib->kick_queue(queue); | |
1005 | } | |
1006 | ||
1007 | /* | |
152a5992 ID |
1008 | * Check if driver supports flushing, if that is the case we can |
1009 | * defer the flushing to the driver. Otherwise we must use the | |
1010 | * alternative which just waits for the queue to become empty. | |
5be65609 | 1011 | */ |
152a5992 ID |
1012 | if (likely(queue->rt2x00dev->ops->lib->flush_queue)) |
1013 | queue->rt2x00dev->ops->lib->flush_queue(queue, drop); | |
5be65609 ID |
1014 | |
1015 | /* | |
1016 | * The queue flush has failed... | |
1017 | */ | |
1018 | if (unlikely(!rt2x00queue_empty(queue))) | |
21957c31 | 1019 | WARNING(queue->rt2x00dev, "Queue %d failed to flush\n", queue->qid); |
5be65609 ID |
1020 | |
1021 | /* | |
1022 | * Restore the queue to the previous status | |
1023 | */ | |
1024 | if (started) | |
1025 | rt2x00queue_unpause_queue(queue); | |
1026 | ||
1027 | mutex_unlock(&queue->status_lock); | |
1028 | } | |
1029 | EXPORT_SYMBOL_GPL(rt2x00queue_flush_queue); | |
1030 | ||
0b7fde54 ID |
1031 | void rt2x00queue_start_queues(struct rt2x00_dev *rt2x00dev) |
1032 | { | |
1033 | struct data_queue *queue; | |
1034 | ||
1035 | /* | |
1036 | * rt2x00queue_start_queue will call ieee80211_wake_queue | |
1037 | * for each queue after is has been properly initialized. | |
1038 | */ | |
1039 | tx_queue_for_each(rt2x00dev, queue) | |
1040 | rt2x00queue_start_queue(queue); | |
1041 | ||
1042 | rt2x00queue_start_queue(rt2x00dev->rx); | |
1043 | } | |
1044 | EXPORT_SYMBOL_GPL(rt2x00queue_start_queues); | |
1045 | ||
1046 | void rt2x00queue_stop_queues(struct rt2x00_dev *rt2x00dev) | |
1047 | { | |
1048 | struct data_queue *queue; | |
1049 | ||
1050 | /* | |
1051 | * rt2x00queue_stop_queue will call ieee80211_stop_queue | |
1052 | * as well, but we are completely shutting doing everything | |
1053 | * now, so it is much safer to stop all TX queues at once, | |
1054 | * and use rt2x00queue_stop_queue for cleaning up. | |
1055 | */ | |
1056 | ieee80211_stop_queues(rt2x00dev->hw); | |
1057 | ||
1058 | tx_queue_for_each(rt2x00dev, queue) | |
1059 | rt2x00queue_stop_queue(queue); | |
1060 | ||
1061 | rt2x00queue_stop_queue(rt2x00dev->rx); | |
1062 | } | |
1063 | EXPORT_SYMBOL_GPL(rt2x00queue_stop_queues); | |
1064 | ||
5be65609 ID |
1065 | void rt2x00queue_flush_queues(struct rt2x00_dev *rt2x00dev, bool drop) |
1066 | { | |
1067 | struct data_queue *queue; | |
1068 | ||
1069 | tx_queue_for_each(rt2x00dev, queue) | |
1070 | rt2x00queue_flush_queue(queue, drop); | |
1071 | ||
1072 | rt2x00queue_flush_queue(rt2x00dev->rx, drop); | |
1073 | } | |
1074 | EXPORT_SYMBOL_GPL(rt2x00queue_flush_queues); | |
1075 | ||
181d6902 ID |
1076 | static void rt2x00queue_reset(struct data_queue *queue) |
1077 | { | |
5f46c4d0 | 1078 | unsigned long irqflags; |
652a9dd2 | 1079 | unsigned int i; |
5f46c4d0 | 1080 | |
813f0339 | 1081 | spin_lock_irqsave(&queue->index_lock, irqflags); |
181d6902 ID |
1082 | |
1083 | queue->count = 0; | |
1084 | queue->length = 0; | |
652a9dd2 | 1085 | |
75256f03 | 1086 | for (i = 0; i < Q_INDEX_MAX; i++) |
652a9dd2 | 1087 | queue->index[i] = 0; |
181d6902 | 1088 | |
813f0339 | 1089 | spin_unlock_irqrestore(&queue->index_lock, irqflags); |
181d6902 ID |
1090 | } |
1091 | ||
798b7adb | 1092 | void rt2x00queue_init_queues(struct rt2x00_dev *rt2x00dev) |
181d6902 ID |
1093 | { |
1094 | struct data_queue *queue; | |
1095 | unsigned int i; | |
1096 | ||
798b7adb | 1097 | queue_for_each(rt2x00dev, queue) { |
181d6902 ID |
1098 | rt2x00queue_reset(queue); |
1099 | ||
64e7d723 | 1100 | for (i = 0; i < queue->limit; i++) |
798b7adb | 1101 | rt2x00dev->ops->lib->clear_entry(&queue->entries[i]); |
181d6902 ID |
1102 | } |
1103 | } | |
1104 | ||
1105 | static int rt2x00queue_alloc_entries(struct data_queue *queue, | |
1106 | const struct data_queue_desc *qdesc) | |
1107 | { | |
1108 | struct queue_entry *entries; | |
1109 | unsigned int entry_size; | |
1110 | unsigned int i; | |
1111 | ||
1112 | rt2x00queue_reset(queue); | |
1113 | ||
1114 | queue->limit = qdesc->entry_num; | |
b869767b | 1115 | queue->threshold = DIV_ROUND_UP(qdesc->entry_num, 10); |
181d6902 ID |
1116 | queue->data_size = qdesc->data_size; |
1117 | queue->desc_size = qdesc->desc_size; | |
1118 | ||
1119 | /* | |
1120 | * Allocate all queue entries. | |
1121 | */ | |
1122 | entry_size = sizeof(*entries) + qdesc->priv_size; | |
baeb2ffa | 1123 | entries = kcalloc(queue->limit, entry_size, GFP_KERNEL); |
181d6902 ID |
1124 | if (!entries) |
1125 | return -ENOMEM; | |
1126 | ||
1127 | #define QUEUE_ENTRY_PRIV_OFFSET(__base, __index, __limit, __esize, __psize) \ | |
f8bfbc31 ME |
1128 | (((char *)(__base)) + ((__limit) * (__esize)) + \ |
1129 | ((__index) * (__psize))) | |
181d6902 ID |
1130 | |
1131 | for (i = 0; i < queue->limit; i++) { | |
1132 | entries[i].flags = 0; | |
1133 | entries[i].queue = queue; | |
1134 | entries[i].skb = NULL; | |
1135 | entries[i].entry_idx = i; | |
1136 | entries[i].priv_data = | |
1137 | QUEUE_ENTRY_PRIV_OFFSET(entries, i, queue->limit, | |
1138 | sizeof(*entries), qdesc->priv_size); | |
1139 | } | |
1140 | ||
1141 | #undef QUEUE_ENTRY_PRIV_OFFSET | |
1142 | ||
1143 | queue->entries = entries; | |
1144 | ||
1145 | return 0; | |
1146 | } | |
1147 | ||
fa69560f | 1148 | static void rt2x00queue_free_skbs(struct data_queue *queue) |
30caa6e3 GW |
1149 | { |
1150 | unsigned int i; | |
1151 | ||
1152 | if (!queue->entries) | |
1153 | return; | |
1154 | ||
1155 | for (i = 0; i < queue->limit; i++) { | |
fa69560f | 1156 | rt2x00queue_free_skb(&queue->entries[i]); |
30caa6e3 GW |
1157 | } |
1158 | } | |
1159 | ||
fa69560f | 1160 | static int rt2x00queue_alloc_rxskbs(struct data_queue *queue) |
30caa6e3 GW |
1161 | { |
1162 | unsigned int i; | |
1163 | struct sk_buff *skb; | |
1164 | ||
1165 | for (i = 0; i < queue->limit; i++) { | |
88211021 | 1166 | skb = rt2x00queue_alloc_rxskb(&queue->entries[i], GFP_KERNEL); |
30caa6e3 | 1167 | if (!skb) |
61243d8e | 1168 | return -ENOMEM; |
30caa6e3 GW |
1169 | queue->entries[i].skb = skb; |
1170 | } | |
1171 | ||
1172 | return 0; | |
30caa6e3 GW |
1173 | } |
1174 | ||
181d6902 ID |
1175 | int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev) |
1176 | { | |
1177 | struct data_queue *queue; | |
1178 | int status; | |
1179 | ||
181d6902 ID |
1180 | status = rt2x00queue_alloc_entries(rt2x00dev->rx, rt2x00dev->ops->rx); |
1181 | if (status) | |
1182 | goto exit; | |
1183 | ||
1184 | tx_queue_for_each(rt2x00dev, queue) { | |
1185 | status = rt2x00queue_alloc_entries(queue, rt2x00dev->ops->tx); | |
1186 | if (status) | |
1187 | goto exit; | |
1188 | } | |
1189 | ||
1190 | status = rt2x00queue_alloc_entries(rt2x00dev->bcn, rt2x00dev->ops->bcn); | |
1191 | if (status) | |
1192 | goto exit; | |
1193 | ||
7dab73b3 | 1194 | if (test_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags)) { |
e74df4a7 | 1195 | status = rt2x00queue_alloc_entries(rt2x00dev->atim, |
30caa6e3 GW |
1196 | rt2x00dev->ops->atim); |
1197 | if (status) | |
1198 | goto exit; | |
1199 | } | |
181d6902 | 1200 | |
fa69560f | 1201 | status = rt2x00queue_alloc_rxskbs(rt2x00dev->rx); |
181d6902 ID |
1202 | if (status) |
1203 | goto exit; | |
1204 | ||
1205 | return 0; | |
1206 | ||
1207 | exit: | |
1208 | ERROR(rt2x00dev, "Queue entries allocation failed.\n"); | |
1209 | ||
1210 | rt2x00queue_uninitialize(rt2x00dev); | |
1211 | ||
1212 | return status; | |
1213 | } | |
1214 | ||
1215 | void rt2x00queue_uninitialize(struct rt2x00_dev *rt2x00dev) | |
1216 | { | |
1217 | struct data_queue *queue; | |
1218 | ||
fa69560f | 1219 | rt2x00queue_free_skbs(rt2x00dev->rx); |
30caa6e3 | 1220 | |
181d6902 ID |
1221 | queue_for_each(rt2x00dev, queue) { |
1222 | kfree(queue->entries); | |
1223 | queue->entries = NULL; | |
1224 | } | |
1225 | } | |
1226 | ||
8f539276 ID |
1227 | static void rt2x00queue_init(struct rt2x00_dev *rt2x00dev, |
1228 | struct data_queue *queue, enum data_queue_qid qid) | |
1229 | { | |
0b7fde54 | 1230 | mutex_init(&queue->status_lock); |
77a861c4 | 1231 | spin_lock_init(&queue->tx_lock); |
813f0339 | 1232 | spin_lock_init(&queue->index_lock); |
8f539276 ID |
1233 | |
1234 | queue->rt2x00dev = rt2x00dev; | |
1235 | queue->qid = qid; | |
2af0a570 | 1236 | queue->txop = 0; |
8f539276 ID |
1237 | queue->aifs = 2; |
1238 | queue->cw_min = 5; | |
1239 | queue->cw_max = 10; | |
1240 | } | |
1241 | ||
181d6902 ID |
1242 | int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev) |
1243 | { | |
1244 | struct data_queue *queue; | |
1245 | enum data_queue_qid qid; | |
1246 | unsigned int req_atim = | |
7dab73b3 | 1247 | !!test_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags); |
181d6902 ID |
1248 | |
1249 | /* | |
1250 | * We need the following queues: | |
1251 | * RX: 1 | |
61448f88 | 1252 | * TX: ops->tx_queues |
181d6902 ID |
1253 | * Beacon: 1 |
1254 | * Atim: 1 (if required) | |
1255 | */ | |
61448f88 | 1256 | rt2x00dev->data_queues = 2 + rt2x00dev->ops->tx_queues + req_atim; |
181d6902 | 1257 | |
baeb2ffa | 1258 | queue = kcalloc(rt2x00dev->data_queues, sizeof(*queue), GFP_KERNEL); |
181d6902 ID |
1259 | if (!queue) { |
1260 | ERROR(rt2x00dev, "Queue allocation failed.\n"); | |
1261 | return -ENOMEM; | |
1262 | } | |
1263 | ||
1264 | /* | |
1265 | * Initialize pointers | |
1266 | */ | |
1267 | rt2x00dev->rx = queue; | |
1268 | rt2x00dev->tx = &queue[1]; | |
61448f88 | 1269 | rt2x00dev->bcn = &queue[1 + rt2x00dev->ops->tx_queues]; |
e74df4a7 | 1270 | rt2x00dev->atim = req_atim ? &queue[2 + rt2x00dev->ops->tx_queues] : NULL; |
181d6902 ID |
1271 | |
1272 | /* | |
1273 | * Initialize queue parameters. | |
1274 | * RX: qid = QID_RX | |
f615e9a3 | 1275 | * TX: qid = QID_AC_VO + index |
181d6902 ID |
1276 | * TX: cw_min: 2^5 = 32. |
1277 | * TX: cw_max: 2^10 = 1024. | |
565a019a ID |
1278 | * BCN: qid = QID_BEACON |
1279 | * ATIM: qid = QID_ATIM | |
181d6902 | 1280 | */ |
8f539276 | 1281 | rt2x00queue_init(rt2x00dev, rt2x00dev->rx, QID_RX); |
181d6902 | 1282 | |
f615e9a3 | 1283 | qid = QID_AC_VO; |
8f539276 ID |
1284 | tx_queue_for_each(rt2x00dev, queue) |
1285 | rt2x00queue_init(rt2x00dev, queue, qid++); | |
181d6902 | 1286 | |
e74df4a7 | 1287 | rt2x00queue_init(rt2x00dev, rt2x00dev->bcn, QID_BEACON); |
181d6902 | 1288 | if (req_atim) |
e74df4a7 | 1289 | rt2x00queue_init(rt2x00dev, rt2x00dev->atim, QID_ATIM); |
181d6902 ID |
1290 | |
1291 | return 0; | |
1292 | } | |
1293 | ||
1294 | void rt2x00queue_free(struct rt2x00_dev *rt2x00dev) | |
1295 | { | |
1296 | kfree(rt2x00dev->rx); | |
1297 | rt2x00dev->rx = NULL; | |
1298 | rt2x00dev->tx = NULL; | |
1299 | rt2x00dev->bcn = NULL; | |
1300 | } |