Commit | Line | Data |
---|---|---|
181d6902 | 1 | /* |
7e613e16 ID |
2 | Copyright (C) 2010 Willow Garage <http://www.willowgarage.com> |
3 | Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com> | |
9c9a0d14 | 4 | Copyright (C) 2004 - 2009 Gertjan van Wingerde <gwingerde@gmail.com> |
181d6902 ID |
5 | <http://rt2x00.serialmonkey.com> |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; if not, write to the | |
19 | Free Software Foundation, Inc., | |
20 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
21 | */ | |
22 | ||
23 | /* | |
24 | Module: rt2x00lib | |
25 | Abstract: rt2x00 queue specific routines. | |
26 | */ | |
27 | ||
5a0e3ad6 | 28 | #include <linux/slab.h> |
181d6902 ID |
29 | #include <linux/kernel.h> |
30 | #include <linux/module.h> | |
c4da0048 | 31 | #include <linux/dma-mapping.h> |
181d6902 ID |
32 | |
33 | #include "rt2x00.h" | |
34 | #include "rt2x00lib.h" | |
35 | ||
88211021 | 36 | struct sk_buff *rt2x00queue_alloc_rxskb(struct queue_entry *entry, gfp_t gfp) |
239c249d | 37 | { |
f0bda571 SG |
38 | struct data_queue *queue = entry->queue; |
39 | struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; | |
c4da0048 GW |
40 | struct sk_buff *skb; |
41 | struct skb_frame_desc *skbdesc; | |
2bb057d0 ID |
42 | unsigned int frame_size; |
43 | unsigned int head_size = 0; | |
44 | unsigned int tail_size = 0; | |
239c249d GW |
45 | |
46 | /* | |
47 | * The frame size includes descriptor size, because the | |
48 | * hardware directly receive the frame into the skbuffer. | |
49 | */ | |
f0bda571 | 50 | frame_size = queue->data_size + queue->desc_size + queue->winfo_size; |
239c249d GW |
51 | |
52 | /* | |
ff352391 ID |
53 | * The payload should be aligned to a 4-byte boundary, |
54 | * this means we need at least 3 bytes for moving the frame | |
55 | * into the correct offset. | |
239c249d | 56 | */ |
2bb057d0 ID |
57 | head_size = 4; |
58 | ||
59 | /* | |
60 | * For IV/EIV/ICV assembly we must make sure there is | |
61 | * at least 8 bytes bytes available in headroom for IV/EIV | |
9c3444d3 | 62 | * and 8 bytes for ICV data as tailroon. |
2bb057d0 | 63 | */ |
7b8a00dc | 64 | if (rt2x00_has_cap_hw_crypto(rt2x00dev)) { |
2bb057d0 | 65 | head_size += 8; |
9c3444d3 | 66 | tail_size += 8; |
2bb057d0 | 67 | } |
239c249d GW |
68 | |
69 | /* | |
70 | * Allocate skbuffer. | |
71 | */ | |
88211021 | 72 | skb = __dev_alloc_skb(frame_size + head_size + tail_size, gfp); |
239c249d GW |
73 | if (!skb) |
74 | return NULL; | |
75 | ||
2bb057d0 ID |
76 | /* |
77 | * Make sure we not have a frame with the requested bytes | |
78 | * available in the head and tail. | |
79 | */ | |
80 | skb_reserve(skb, head_size); | |
239c249d GW |
81 | skb_put(skb, frame_size); |
82 | ||
c4da0048 GW |
83 | /* |
84 | * Populate skbdesc. | |
85 | */ | |
86 | skbdesc = get_skb_frame_desc(skb); | |
87 | memset(skbdesc, 0, sizeof(*skbdesc)); | |
88 | skbdesc->entry = entry; | |
89 | ||
7dab73b3 | 90 | if (test_bit(REQUIRE_DMA, &rt2x00dev->cap_flags)) { |
4ea545d4 SG |
91 | dma_addr_t skb_dma; |
92 | ||
93 | skb_dma = dma_map_single(rt2x00dev->dev, skb->data, skb->len, | |
94 | DMA_FROM_DEVICE); | |
95 | if (unlikely(dma_mapping_error(rt2x00dev->dev, skb_dma))) { | |
96 | dev_kfree_skb_any(skb); | |
97 | return NULL; | |
98 | } | |
99 | ||
100 | skbdesc->skb_dma = skb_dma; | |
c4da0048 GW |
101 | skbdesc->flags |= SKBDESC_DMA_MAPPED_RX; |
102 | } | |
103 | ||
239c249d GW |
104 | return skb; |
105 | } | |
30caa6e3 | 106 | |
4ea545d4 | 107 | int rt2x00queue_map_txskb(struct queue_entry *entry) |
30caa6e3 | 108 | { |
fa69560f ID |
109 | struct device *dev = entry->queue->rt2x00dev->dev; |
110 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); | |
c4da0048 | 111 | |
3ee54a07 | 112 | skbdesc->skb_dma = |
fa69560f | 113 | dma_map_single(dev, entry->skb->data, entry->skb->len, DMA_TO_DEVICE); |
4ea545d4 SG |
114 | |
115 | if (unlikely(dma_mapping_error(dev, skbdesc->skb_dma))) | |
116 | return -ENOMEM; | |
117 | ||
c4da0048 | 118 | skbdesc->flags |= SKBDESC_DMA_MAPPED_TX; |
4ea545d4 | 119 | return 0; |
c4da0048 GW |
120 | } |
121 | EXPORT_SYMBOL_GPL(rt2x00queue_map_txskb); | |
122 | ||
fa69560f | 123 | void rt2x00queue_unmap_skb(struct queue_entry *entry) |
c4da0048 | 124 | { |
fa69560f ID |
125 | struct device *dev = entry->queue->rt2x00dev->dev; |
126 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); | |
c4da0048 GW |
127 | |
128 | if (skbdesc->flags & SKBDESC_DMA_MAPPED_RX) { | |
fa69560f | 129 | dma_unmap_single(dev, skbdesc->skb_dma, entry->skb->len, |
c4da0048 GW |
130 | DMA_FROM_DEVICE); |
131 | skbdesc->flags &= ~SKBDESC_DMA_MAPPED_RX; | |
546adf29 | 132 | } else if (skbdesc->flags & SKBDESC_DMA_MAPPED_TX) { |
fa69560f | 133 | dma_unmap_single(dev, skbdesc->skb_dma, entry->skb->len, |
c4da0048 GW |
134 | DMA_TO_DEVICE); |
135 | skbdesc->flags &= ~SKBDESC_DMA_MAPPED_TX; | |
136 | } | |
137 | } | |
0b8004aa | 138 | EXPORT_SYMBOL_GPL(rt2x00queue_unmap_skb); |
c4da0048 | 139 | |
fa69560f | 140 | void rt2x00queue_free_skb(struct queue_entry *entry) |
c4da0048 | 141 | { |
fa69560f | 142 | if (!entry->skb) |
9a613195 ID |
143 | return; |
144 | ||
fa69560f ID |
145 | rt2x00queue_unmap_skb(entry); |
146 | dev_kfree_skb_any(entry->skb); | |
147 | entry->skb = NULL; | |
30caa6e3 | 148 | } |
239c249d | 149 | |
daee6c09 | 150 | void rt2x00queue_align_frame(struct sk_buff *skb) |
9f166171 | 151 | { |
9f166171 | 152 | unsigned int frame_length = skb->len; |
daee6c09 | 153 | unsigned int align = ALIGN_SIZE(skb, 0); |
9f166171 ID |
154 | |
155 | if (!align) | |
156 | return; | |
157 | ||
daee6c09 ID |
158 | skb_push(skb, align); |
159 | memmove(skb->data, skb->data + align, frame_length); | |
160 | skb_trim(skb, frame_length); | |
161 | } | |
162 | ||
daee6c09 ID |
163 | void rt2x00queue_insert_l2pad(struct sk_buff *skb, unsigned int header_length) |
164 | { | |
2e331462 | 165 | unsigned int payload_length = skb->len - header_length; |
daee6c09 ID |
166 | unsigned int header_align = ALIGN_SIZE(skb, 0); |
167 | unsigned int payload_align = ALIGN_SIZE(skb, header_length); | |
e54be4e7 | 168 | unsigned int l2pad = payload_length ? L2PAD_SIZE(header_length) : 0; |
daee6c09 | 169 | |
2e331462 GW |
170 | /* |
171 | * Adjust the header alignment if the payload needs to be moved more | |
172 | * than the header. | |
173 | */ | |
174 | if (payload_align > header_align) | |
175 | header_align += 4; | |
176 | ||
177 | /* There is nothing to do if no alignment is needed */ | |
178 | if (!header_align) | |
179 | return; | |
daee6c09 | 180 | |
2e331462 GW |
181 | /* Reserve the amount of space needed in front of the frame */ |
182 | skb_push(skb, header_align); | |
183 | ||
184 | /* | |
185 | * Move the header. | |
186 | */ | |
187 | memmove(skb->data, skb->data + header_align, header_length); | |
188 | ||
189 | /* Move the payload, if present and if required */ | |
190 | if (payload_length && payload_align) | |
daee6c09 | 191 | memmove(skb->data + header_length + l2pad, |
a5186e99 | 192 | skb->data + header_length + l2pad + payload_align, |
2e331462 GW |
193 | payload_length); |
194 | ||
195 | /* Trim the skb to the correct size */ | |
196 | skb_trim(skb, header_length + l2pad + payload_length); | |
9f166171 ID |
197 | } |
198 | ||
daee6c09 ID |
199 | void rt2x00queue_remove_l2pad(struct sk_buff *skb, unsigned int header_length) |
200 | { | |
a061a93b GW |
201 | /* |
202 | * L2 padding is only present if the skb contains more than just the | |
203 | * IEEE 802.11 header. | |
204 | */ | |
205 | unsigned int l2pad = (skb->len > header_length) ? | |
206 | L2PAD_SIZE(header_length) : 0; | |
daee6c09 | 207 | |
354e39db | 208 | if (!l2pad) |
daee6c09 ID |
209 | return; |
210 | ||
a061a93b GW |
211 | memmove(skb->data + l2pad, skb->data, header_length); |
212 | skb_pull(skb, l2pad); | |
daee6c09 ID |
213 | } |
214 | ||
77b5621b GW |
215 | static void rt2x00queue_create_tx_descriptor_seq(struct rt2x00_dev *rt2x00dev, |
216 | struct sk_buff *skb, | |
7b40982e ID |
217 | struct txentry_desc *txdesc) |
218 | { | |
77b5621b GW |
219 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
220 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
7b40982e | 221 | struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif); |
e5851dac | 222 | u16 seqno; |
7b40982e | 223 | |
c262e08b | 224 | if (!(tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)) |
7b40982e ID |
225 | return; |
226 | ||
7fe7ee77 HS |
227 | __set_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags); |
228 | ||
e66a8ddf SG |
229 | if (!test_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags)) { |
230 | /* | |
231 | * rt2800 has a H/W (or F/W) bug, device incorrectly increase | |
232 | * seqno on retransmited data (non-QOS) frames. To workaround | |
233 | * the problem let's generate seqno in software if QOS is | |
234 | * disabled. | |
235 | */ | |
236 | if (test_bit(CONFIG_QOS_DISABLED, &rt2x00dev->flags)) | |
237 | __clear_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags); | |
238 | else | |
239 | /* H/W will generate sequence number */ | |
240 | return; | |
241 | } | |
7fe7ee77 | 242 | |
7b40982e | 243 | /* |
7fe7ee77 HS |
244 | * The hardware is not able to insert a sequence number. Assign a |
245 | * software generated one here. | |
7b40982e ID |
246 | * |
247 | * This is wrong because beacons are not getting sequence | |
248 | * numbers assigned properly. | |
249 | * | |
250 | * A secondary problem exists for drivers that cannot toggle | |
251 | * sequence counting per-frame, since those will override the | |
252 | * sequence counter given by mac80211. | |
253 | */ | |
7b40982e | 254 | if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags)) |
e5851dac SG |
255 | seqno = atomic_add_return(0x10, &intf->seqno); |
256 | else | |
257 | seqno = atomic_read(&intf->seqno); | |
7b40982e | 258 | |
e5851dac SG |
259 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); |
260 | hdr->seq_ctrl |= cpu_to_le16(seqno); | |
7b40982e ID |
261 | } |
262 | ||
77b5621b GW |
263 | static void rt2x00queue_create_tx_descriptor_plcp(struct rt2x00_dev *rt2x00dev, |
264 | struct sk_buff *skb, | |
7b40982e ID |
265 | struct txentry_desc *txdesc, |
266 | const struct rt2x00_rate *hwrate) | |
267 | { | |
77b5621b | 268 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
7b40982e ID |
269 | struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0]; |
270 | unsigned int data_length; | |
271 | unsigned int duration; | |
272 | unsigned int residual; | |
273 | ||
2517794b HS |
274 | /* |
275 | * Determine with what IFS priority this frame should be send. | |
276 | * Set ifs to IFS_SIFS when the this is not the first fragment, | |
277 | * or this fragment came after RTS/CTS. | |
278 | */ | |
279 | if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags)) | |
280 | txdesc->u.plcp.ifs = IFS_BACKOFF; | |
281 | else | |
282 | txdesc->u.plcp.ifs = IFS_SIFS; | |
283 | ||
7b40982e | 284 | /* Data length + CRC + Crypto overhead (IV/EIV/ICV/MIC) */ |
77b5621b GW |
285 | data_length = skb->len + 4; |
286 | data_length += rt2x00crypto_tx_overhead(rt2x00dev, skb); | |
7b40982e ID |
287 | |
288 | /* | |
289 | * PLCP setup | |
290 | * Length calculation depends on OFDM/CCK rate. | |
291 | */ | |
26a1d07f HS |
292 | txdesc->u.plcp.signal = hwrate->plcp; |
293 | txdesc->u.plcp.service = 0x04; | |
7b40982e ID |
294 | |
295 | if (hwrate->flags & DEV_RATE_OFDM) { | |
26a1d07f HS |
296 | txdesc->u.plcp.length_high = (data_length >> 6) & 0x3f; |
297 | txdesc->u.plcp.length_low = data_length & 0x3f; | |
7b40982e ID |
298 | } else { |
299 | /* | |
300 | * Convert length to microseconds. | |
301 | */ | |
302 | residual = GET_DURATION_RES(data_length, hwrate->bitrate); | |
303 | duration = GET_DURATION(data_length, hwrate->bitrate); | |
304 | ||
305 | if (residual != 0) { | |
306 | duration++; | |
307 | ||
308 | /* | |
309 | * Check if we need to set the Length Extension | |
310 | */ | |
311 | if (hwrate->bitrate == 110 && residual <= 30) | |
26a1d07f | 312 | txdesc->u.plcp.service |= 0x80; |
7b40982e ID |
313 | } |
314 | ||
26a1d07f HS |
315 | txdesc->u.plcp.length_high = (duration >> 8) & 0xff; |
316 | txdesc->u.plcp.length_low = duration & 0xff; | |
7b40982e ID |
317 | |
318 | /* | |
319 | * When preamble is enabled we should set the | |
320 | * preamble bit for the signal. | |
321 | */ | |
322 | if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) | |
26a1d07f | 323 | txdesc->u.plcp.signal |= 0x08; |
7b40982e ID |
324 | } |
325 | } | |
326 | ||
77b5621b GW |
327 | static void rt2x00queue_create_tx_descriptor_ht(struct rt2x00_dev *rt2x00dev, |
328 | struct sk_buff *skb, | |
46a01ec0 | 329 | struct txentry_desc *txdesc, |
36323f81 | 330 | struct ieee80211_sta *sta, |
46a01ec0 GW |
331 | const struct rt2x00_rate *hwrate) |
332 | { | |
77b5621b | 333 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
46a01ec0 | 334 | struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0]; |
77b5621b | 335 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
ead2bb64 | 336 | struct rt2x00_sta *sta_priv = NULL; |
46a01ec0 | 337 | |
36323f81 | 338 | if (sta) { |
46a01ec0 | 339 | txdesc->u.ht.mpdu_density = |
36323f81 | 340 | sta->ht_cap.ampdu_density; |
46a01ec0 | 341 | |
36323f81 | 342 | sta_priv = sta_to_rt2x00_sta(sta); |
ead2bb64 HS |
343 | txdesc->u.ht.wcid = sta_priv->wcid; |
344 | } | |
345 | ||
46a01ec0 GW |
346 | /* |
347 | * If IEEE80211_TX_RC_MCS is set txrate->idx just contains the | |
348 | * mcs rate to be used | |
349 | */ | |
350 | if (txrate->flags & IEEE80211_TX_RC_MCS) { | |
351 | txdesc->u.ht.mcs = txrate->idx; | |
352 | ||
353 | /* | |
354 | * MIMO PS should be set to 1 for STA's using dynamic SM PS | |
355 | * when using more then one tx stream (>MCS7). | |
356 | */ | |
36323f81 | 357 | if (sta && txdesc->u.ht.mcs > 7 && |
af0ed69b | 358 | sta->smps_mode == IEEE80211_SMPS_DYNAMIC) |
46a01ec0 GW |
359 | __set_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags); |
360 | } else { | |
361 | txdesc->u.ht.mcs = rt2x00_get_rate_mcs(hwrate->mcs); | |
362 | if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) | |
363 | txdesc->u.ht.mcs |= 0x08; | |
364 | } | |
365 | ||
da40f407 SG |
366 | if (test_bit(CONFIG_HT_DISABLED, &rt2x00dev->flags)) { |
367 | if (!(tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)) | |
368 | txdesc->u.ht.txop = TXOP_SIFS; | |
369 | else | |
370 | txdesc->u.ht.txop = TXOP_BACKOFF; | |
371 | ||
372 | /* Left zero on all other settings. */ | |
373 | return; | |
374 | } | |
375 | ||
376 | txdesc->u.ht.ba_size = 7; /* FIXME: What value is needed? */ | |
377 | ||
378 | /* | |
379 | * Only one STBC stream is supported for now. | |
380 | */ | |
381 | if (tx_info->flags & IEEE80211_TX_CTL_STBC) | |
382 | txdesc->u.ht.stbc = 1; | |
383 | ||
46a01ec0 GW |
384 | /* |
385 | * This frame is eligible for an AMPDU, however, don't aggregate | |
386 | * frames that are intended to probe a specific tx rate. | |
387 | */ | |
388 | if (tx_info->flags & IEEE80211_TX_CTL_AMPDU && | |
389 | !(tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) | |
390 | __set_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags); | |
391 | ||
392 | /* | |
393 | * Set 40Mhz mode if necessary (for legacy rates this will | |
394 | * duplicate the frame to both channels). | |
395 | */ | |
396 | if (txrate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH || | |
397 | txrate->flags & IEEE80211_TX_RC_DUP_DATA) | |
398 | __set_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags); | |
399 | if (txrate->flags & IEEE80211_TX_RC_SHORT_GI) | |
400 | __set_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags); | |
401 | ||
402 | /* | |
403 | * Determine IFS values | |
404 | * - Use TXOP_BACKOFF for management frames except beacons | |
405 | * - Use TXOP_SIFS for fragment bursts | |
406 | * - Use TXOP_HTTXOP for everything else | |
407 | * | |
408 | * Note: rt2800 devices won't use CTS protection (if used) | |
409 | * for frames not transmitted with TXOP_HTTXOP | |
410 | */ | |
411 | if (ieee80211_is_mgmt(hdr->frame_control) && | |
412 | !ieee80211_is_beacon(hdr->frame_control)) | |
413 | txdesc->u.ht.txop = TXOP_BACKOFF; | |
414 | else if (!(tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)) | |
415 | txdesc->u.ht.txop = TXOP_SIFS; | |
416 | else | |
417 | txdesc->u.ht.txop = TXOP_HTTXOP; | |
418 | } | |
419 | ||
77b5621b GW |
420 | static void rt2x00queue_create_tx_descriptor(struct rt2x00_dev *rt2x00dev, |
421 | struct sk_buff *skb, | |
36323f81 TH |
422 | struct txentry_desc *txdesc, |
423 | struct ieee80211_sta *sta) | |
7050ec82 | 424 | { |
77b5621b GW |
425 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
426 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
55b585e2 HS |
427 | struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0]; |
428 | struct ieee80211_rate *rate; | |
429 | const struct rt2x00_rate *hwrate = NULL; | |
7050ec82 ID |
430 | |
431 | memset(txdesc, 0, sizeof(*txdesc)); | |
432 | ||
9f166171 | 433 | /* |
df624ca5 | 434 | * Header and frame information. |
9f166171 | 435 | */ |
77b5621b GW |
436 | txdesc->length = skb->len; |
437 | txdesc->header_length = ieee80211_get_hdrlen_from_skb(skb); | |
9f166171 | 438 | |
7050ec82 ID |
439 | /* |
440 | * Check whether this frame is to be acked. | |
441 | */ | |
e039fa4a | 442 | if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK)) |
7050ec82 ID |
443 | __set_bit(ENTRY_TXD_ACK, &txdesc->flags); |
444 | ||
445 | /* | |
446 | * Check if this is a RTS/CTS frame | |
447 | */ | |
ac104462 ID |
448 | if (ieee80211_is_rts(hdr->frame_control) || |
449 | ieee80211_is_cts(hdr->frame_control)) { | |
7050ec82 | 450 | __set_bit(ENTRY_TXD_BURST, &txdesc->flags); |
ac104462 | 451 | if (ieee80211_is_rts(hdr->frame_control)) |
7050ec82 | 452 | __set_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags); |
e039fa4a | 453 | else |
7050ec82 | 454 | __set_bit(ENTRY_TXD_CTS_FRAME, &txdesc->flags); |
e039fa4a | 455 | if (tx_info->control.rts_cts_rate_idx >= 0) |
2e92e6f2 | 456 | rate = |
e039fa4a | 457 | ieee80211_get_rts_cts_rate(rt2x00dev->hw, tx_info); |
7050ec82 ID |
458 | } |
459 | ||
460 | /* | |
461 | * Determine retry information. | |
462 | */ | |
e6a9854b | 463 | txdesc->retry_limit = tx_info->control.rates[0].count - 1; |
42c82857 | 464 | if (txdesc->retry_limit >= rt2x00dev->long_retry) |
7050ec82 ID |
465 | __set_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags); |
466 | ||
467 | /* | |
468 | * Check if more fragments are pending | |
469 | */ | |
2606e422 | 470 | if (ieee80211_has_morefrags(hdr->frame_control)) { |
7050ec82 ID |
471 | __set_bit(ENTRY_TXD_BURST, &txdesc->flags); |
472 | __set_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags); | |
473 | } | |
474 | ||
2606e422 HS |
475 | /* |
476 | * Check if more frames (!= fragments) are pending | |
477 | */ | |
478 | if (tx_info->flags & IEEE80211_TX_CTL_MORE_FRAMES) | |
479 | __set_bit(ENTRY_TXD_BURST, &txdesc->flags); | |
480 | ||
7050ec82 ID |
481 | /* |
482 | * Beacons and probe responses require the tsf timestamp | |
1bce85cf | 483 | * to be inserted into the frame. |
7050ec82 | 484 | */ |
1bce85cf HS |
485 | if (ieee80211_is_beacon(hdr->frame_control) || |
486 | ieee80211_is_probe_resp(hdr->frame_control)) | |
7050ec82 ID |
487 | __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags); |
488 | ||
7b40982e | 489 | if ((tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) && |
2517794b | 490 | !test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)) |
7050ec82 | 491 | __set_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags); |
7050ec82 | 492 | |
076f9582 ID |
493 | /* |
494 | * Determine rate modulation. | |
495 | */ | |
55b585e2 HS |
496 | if (txrate->flags & IEEE80211_TX_RC_GREEN_FIELD) |
497 | txdesc->rate_mode = RATE_MODE_HT_GREENFIELD; | |
498 | else if (txrate->flags & IEEE80211_TX_RC_MCS) | |
499 | txdesc->rate_mode = RATE_MODE_HT_MIX; | |
500 | else { | |
501 | rate = ieee80211_get_tx_rate(rt2x00dev->hw, tx_info); | |
502 | hwrate = rt2x00_get_rate(rate->hw_value); | |
503 | if (hwrate->flags & DEV_RATE_OFDM) | |
504 | txdesc->rate_mode = RATE_MODE_OFDM; | |
505 | else | |
506 | txdesc->rate_mode = RATE_MODE_CCK; | |
507 | } | |
7050ec82 | 508 | |
7b40982e ID |
509 | /* |
510 | * Apply TX descriptor handling by components | |
511 | */ | |
77b5621b GW |
512 | rt2x00crypto_create_tx_descriptor(rt2x00dev, skb, txdesc); |
513 | rt2x00queue_create_tx_descriptor_seq(rt2x00dev, skb, txdesc); | |
26a1d07f | 514 | |
7dab73b3 | 515 | if (test_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags)) |
77b5621b | 516 | rt2x00queue_create_tx_descriptor_ht(rt2x00dev, skb, txdesc, |
36323f81 | 517 | sta, hwrate); |
26a1d07f | 518 | else |
77b5621b GW |
519 | rt2x00queue_create_tx_descriptor_plcp(rt2x00dev, skb, txdesc, |
520 | hwrate); | |
7050ec82 | 521 | } |
7050ec82 | 522 | |
78eea11b GW |
523 | static int rt2x00queue_write_tx_data(struct queue_entry *entry, |
524 | struct txentry_desc *txdesc) | |
525 | { | |
526 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; | |
527 | ||
528 | /* | |
529 | * This should not happen, we already checked the entry | |
530 | * was ours. When the hardware disagrees there has been | |
531 | * a queue corruption! | |
532 | */ | |
533 | if (unlikely(rt2x00dev->ops->lib->get_entry_state && | |
534 | rt2x00dev->ops->lib->get_entry_state(entry))) { | |
ec9c4989 JP |
535 | rt2x00_err(rt2x00dev, |
536 | "Corrupt queue %d, accessing entry which is not ours\n" | |
537 | "Please file bug report to %s\n", | |
538 | entry->queue->qid, DRV_PROJECT); | |
78eea11b GW |
539 | return -EINVAL; |
540 | } | |
541 | ||
542 | /* | |
543 | * Add the requested extra tx headroom in front of the skb. | |
544 | */ | |
5616a6ef GJ |
545 | skb_push(entry->skb, rt2x00dev->extra_tx_headroom); |
546 | memset(entry->skb->data, 0, rt2x00dev->extra_tx_headroom); | |
78eea11b GW |
547 | |
548 | /* | |
76dd5ddf | 549 | * Call the driver's write_tx_data function, if it exists. |
78eea11b | 550 | */ |
76dd5ddf GW |
551 | if (rt2x00dev->ops->lib->write_tx_data) |
552 | rt2x00dev->ops->lib->write_tx_data(entry, txdesc); | |
78eea11b GW |
553 | |
554 | /* | |
555 | * Map the skb to DMA. | |
556 | */ | |
4ea545d4 SG |
557 | if (test_bit(REQUIRE_DMA, &rt2x00dev->cap_flags) && |
558 | rt2x00queue_map_txskb(entry)) | |
559 | return -ENOMEM; | |
78eea11b GW |
560 | |
561 | return 0; | |
562 | } | |
563 | ||
bd88a781 ID |
564 | static void rt2x00queue_write_tx_descriptor(struct queue_entry *entry, |
565 | struct txentry_desc *txdesc) | |
7050ec82 | 566 | { |
b869767b | 567 | struct data_queue *queue = entry->queue; |
7050ec82 | 568 | |
93331458 | 569 | queue->rt2x00dev->ops->lib->write_tx_desc(entry, txdesc); |
7050ec82 ID |
570 | |
571 | /* | |
572 | * All processing on the frame has been completed, this means | |
573 | * it is now ready to be dumped to userspace through debugfs. | |
574 | */ | |
93331458 | 575 | rt2x00debug_dump_frame(queue->rt2x00dev, DUMP_FRAME_TX, entry->skb); |
6295d815 GW |
576 | } |
577 | ||
8be4eed0 | 578 | static void rt2x00queue_kick_tx_queue(struct data_queue *queue, |
6295d815 GW |
579 | struct txentry_desc *txdesc) |
580 | { | |
7050ec82 | 581 | /* |
b869767b | 582 | * Check if we need to kick the queue, there are however a few rules |
6295d815 | 583 | * 1) Don't kick unless this is the last in frame in a burst. |
b869767b ID |
584 | * When the burst flag is set, this frame is always followed |
585 | * by another frame which in some way are related to eachother. | |
586 | * This is true for fragments, RTS or CTS-to-self frames. | |
6295d815 | 587 | * 2) Rule 1 can be broken when the available entries |
b869767b | 588 | * in the queue are less then a certain threshold. |
7050ec82 | 589 | */ |
b869767b ID |
590 | if (rt2x00queue_threshold(queue) || |
591 | !test_bit(ENTRY_TXD_BURST, &txdesc->flags)) | |
dbba306f | 592 | queue->rt2x00dev->ops->lib->kick_queue(queue); |
7050ec82 | 593 | } |
7050ec82 | 594 | |
84e9e8eb HS |
595 | static void rt2x00queue_bar_check(struct queue_entry *entry) |
596 | { | |
597 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; | |
598 | struct ieee80211_bar *bar = (void *) (entry->skb->data + | |
5616a6ef | 599 | rt2x00dev->extra_tx_headroom); |
84e9e8eb HS |
600 | struct rt2x00_bar_list_entry *bar_entry; |
601 | ||
602 | if (likely(!ieee80211_is_back_req(bar->frame_control))) | |
603 | return; | |
604 | ||
605 | bar_entry = kmalloc(sizeof(*bar_entry), GFP_ATOMIC); | |
606 | ||
607 | /* | |
608 | * If the alloc fails we still send the BAR out but just don't track | |
609 | * it in our bar list. And as a result we will report it to mac80211 | |
610 | * back as failed. | |
611 | */ | |
612 | if (!bar_entry) | |
613 | return; | |
614 | ||
615 | bar_entry->entry = entry; | |
616 | bar_entry->block_acked = 0; | |
617 | ||
618 | /* | |
619 | * Copy the relevant parts of the 802.11 BAR into out check list | |
620 | * such that we can use RCU for less-overhead in the RX path since | |
621 | * sending BARs and processing the according BlockAck should be | |
622 | * the exception. | |
623 | */ | |
624 | memcpy(bar_entry->ra, bar->ra, sizeof(bar->ra)); | |
625 | memcpy(bar_entry->ta, bar->ta, sizeof(bar->ta)); | |
626 | bar_entry->control = bar->control; | |
627 | bar_entry->start_seq_num = bar->start_seq_num; | |
628 | ||
629 | /* | |
630 | * Insert BAR into our BAR check list. | |
631 | */ | |
632 | spin_lock_bh(&rt2x00dev->bar_list_lock); | |
633 | list_add_tail_rcu(&bar_entry->list, &rt2x00dev->bar_list); | |
634 | spin_unlock_bh(&rt2x00dev->bar_list_lock); | |
635 | } | |
636 | ||
7351c6bd JB |
637 | int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb, |
638 | bool local) | |
6db3786a | 639 | { |
e6a9854b | 640 | struct ieee80211_tx_info *tx_info; |
77a861c4 | 641 | struct queue_entry *entry; |
6db3786a | 642 | struct txentry_desc txdesc; |
d74f5ba4 | 643 | struct skb_frame_desc *skbdesc; |
e6a9854b | 644 | u8 rate_idx, rate_flags; |
77a861c4 GW |
645 | int ret = 0; |
646 | ||
6db3786a ID |
647 | /* |
648 | * Copy all TX descriptor information into txdesc, | |
649 | * after that we are free to use the skb->cb array | |
650 | * for our information. | |
651 | */ | |
36323f81 | 652 | rt2x00queue_create_tx_descriptor(queue->rt2x00dev, skb, &txdesc, NULL); |
6db3786a | 653 | |
d74f5ba4 | 654 | /* |
e6a9854b | 655 | * All information is retrieved from the skb->cb array, |
2bb057d0 | 656 | * now we should claim ownership of the driver part of that |
e6a9854b | 657 | * array, preserving the bitrate index and flags. |
d74f5ba4 | 658 | */ |
e6a9854b JB |
659 | tx_info = IEEE80211_SKB_CB(skb); |
660 | rate_idx = tx_info->control.rates[0].idx; | |
661 | rate_flags = tx_info->control.rates[0].flags; | |
0e3de998 | 662 | skbdesc = get_skb_frame_desc(skb); |
d74f5ba4 | 663 | memset(skbdesc, 0, sizeof(*skbdesc)); |
e6a9854b JB |
664 | skbdesc->tx_rate_idx = rate_idx; |
665 | skbdesc->tx_rate_flags = rate_flags; | |
d74f5ba4 | 666 | |
7351c6bd JB |
667 | if (local) |
668 | skbdesc->flags |= SKBDESC_NOT_MAC80211; | |
669 | ||
2bb057d0 ID |
670 | /* |
671 | * When hardware encryption is supported, and this frame | |
672 | * is to be encrypted, we should strip the IV/EIV data from | |
3ad2f3fb | 673 | * the frame so we can provide it to the driver separately. |
2bb057d0 ID |
674 | */ |
675 | if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc.flags) && | |
dddfb478 | 676 | !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc.flags)) { |
7dab73b3 | 677 | if (test_bit(REQUIRE_COPY_IV, &queue->rt2x00dev->cap_flags)) |
9eb4e21e | 678 | rt2x00crypto_tx_copy_iv(skb, &txdesc); |
dddfb478 | 679 | else |
9eb4e21e | 680 | rt2x00crypto_tx_remove_iv(skb, &txdesc); |
dddfb478 | 681 | } |
2bb057d0 | 682 | |
93354cbb | 683 | /* |
25985edc | 684 | * When DMA allocation is required we should guarantee to the |
93354cbb | 685 | * driver that the DMA is aligned to a 4-byte boundary. |
93354cbb ID |
686 | * However some drivers require L2 padding to pad the payload |
687 | * rather then the header. This could be a requirement for | |
688 | * PCI and USB devices, while header alignment only is valid | |
689 | * for PCI devices. | |
690 | */ | |
7dab73b3 | 691 | if (test_bit(REQUIRE_L2PAD, &queue->rt2x00dev->cap_flags)) |
128f8f77 | 692 | rt2x00queue_insert_l2pad(skb, txdesc.header_length); |
7dab73b3 | 693 | else if (test_bit(REQUIRE_DMA, &queue->rt2x00dev->cap_flags)) |
128f8f77 GW |
694 | rt2x00queue_align_frame(skb); |
695 | ||
3780d038 SG |
696 | /* |
697 | * That function must be called with bh disabled. | |
698 | */ | |
128f8f77 GW |
699 | spin_lock(&queue->tx_lock); |
700 | ||
701 | if (unlikely(rt2x00queue_full(queue))) { | |
ec9c4989 JP |
702 | rt2x00_err(queue->rt2x00dev, "Dropping frame due to full tx queue %d\n", |
703 | queue->qid); | |
128f8f77 GW |
704 | ret = -ENOBUFS; |
705 | goto out; | |
706 | } | |
707 | ||
708 | entry = rt2x00queue_get_entry(queue, Q_INDEX); | |
709 | ||
710 | if (unlikely(test_and_set_bit(ENTRY_OWNER_DEVICE_DATA, | |
711 | &entry->flags))) { | |
ec9c4989 JP |
712 | rt2x00_err(queue->rt2x00dev, |
713 | "Arrived at non-free entry in the non-full queue %d\n" | |
714 | "Please file bug report to %s\n", | |
715 | queue->qid, DRV_PROJECT); | |
128f8f77 GW |
716 | ret = -EINVAL; |
717 | goto out; | |
718 | } | |
719 | ||
720 | skbdesc->entry = entry; | |
721 | entry->skb = skb; | |
9f166171 | 722 | |
2bb057d0 ID |
723 | /* |
724 | * It could be possible that the queue was corrupted and this | |
0e3de998 ID |
725 | * call failed. Since we always return NETDEV_TX_OK to mac80211, |
726 | * this frame will simply be dropped. | |
2bb057d0 | 727 | */ |
78eea11b | 728 | if (unlikely(rt2x00queue_write_tx_data(entry, &txdesc))) { |
0262ab0d | 729 | clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags); |
2bb057d0 | 730 | entry->skb = NULL; |
77a861c4 GW |
731 | ret = -EIO; |
732 | goto out; | |
6db3786a ID |
733 | } |
734 | ||
84e9e8eb HS |
735 | /* |
736 | * Put BlockAckReqs into our check list for driver BA processing. | |
737 | */ | |
738 | rt2x00queue_bar_check(entry); | |
739 | ||
0262ab0d | 740 | set_bit(ENTRY_DATA_PENDING, &entry->flags); |
6db3786a | 741 | |
75256f03 | 742 | rt2x00queue_index_inc(entry, Q_INDEX); |
6db3786a | 743 | rt2x00queue_write_tx_descriptor(entry, &txdesc); |
8be4eed0 | 744 | rt2x00queue_kick_tx_queue(queue, &txdesc); |
6db3786a | 745 | |
77a861c4 GW |
746 | out: |
747 | spin_unlock(&queue->tx_lock); | |
748 | return ret; | |
6db3786a ID |
749 | } |
750 | ||
69cf36a4 HS |
751 | int rt2x00queue_clear_beacon(struct rt2x00_dev *rt2x00dev, |
752 | struct ieee80211_vif *vif) | |
753 | { | |
754 | struct rt2x00_intf *intf = vif_to_intf(vif); | |
755 | ||
756 | if (unlikely(!intf->beacon)) | |
757 | return -ENOBUFS; | |
758 | ||
759 | mutex_lock(&intf->beacon_skb_mutex); | |
760 | ||
761 | /* | |
762 | * Clean up the beacon skb. | |
763 | */ | |
764 | rt2x00queue_free_skb(intf->beacon); | |
765 | ||
766 | /* | |
767 | * Clear beacon (single bssid devices don't need to clear the beacon | |
768 | * since the beacon queue will get stopped anyway). | |
769 | */ | |
770 | if (rt2x00dev->ops->lib->clear_beacon) | |
771 | rt2x00dev->ops->lib->clear_beacon(intf->beacon); | |
772 | ||
773 | mutex_unlock(&intf->beacon_skb_mutex); | |
774 | ||
775 | return 0; | |
776 | } | |
777 | ||
8414ff07 HS |
778 | int rt2x00queue_update_beacon_locked(struct rt2x00_dev *rt2x00dev, |
779 | struct ieee80211_vif *vif) | |
bd88a781 ID |
780 | { |
781 | struct rt2x00_intf *intf = vif_to_intf(vif); | |
782 | struct skb_frame_desc *skbdesc; | |
783 | struct txentry_desc txdesc; | |
bd88a781 ID |
784 | |
785 | if (unlikely(!intf->beacon)) | |
786 | return -ENOBUFS; | |
787 | ||
17512dc3 IP |
788 | /* |
789 | * Clean up the beacon skb. | |
790 | */ | |
fa69560f | 791 | rt2x00queue_free_skb(intf->beacon); |
17512dc3 | 792 | |
bd88a781 | 793 | intf->beacon->skb = ieee80211_beacon_get(rt2x00dev->hw, vif); |
8414ff07 | 794 | if (!intf->beacon->skb) |
bd88a781 ID |
795 | return -ENOMEM; |
796 | ||
797 | /* | |
798 | * Copy all TX descriptor information into txdesc, | |
799 | * after that we are free to use the skb->cb array | |
800 | * for our information. | |
801 | */ | |
36323f81 | 802 | rt2x00queue_create_tx_descriptor(rt2x00dev, intf->beacon->skb, &txdesc, NULL); |
bd88a781 | 803 | |
bd88a781 ID |
804 | /* |
805 | * Fill in skb descriptor | |
806 | */ | |
807 | skbdesc = get_skb_frame_desc(intf->beacon->skb); | |
808 | memset(skbdesc, 0, sizeof(*skbdesc)); | |
bd88a781 ID |
809 | skbdesc->entry = intf->beacon; |
810 | ||
bd88a781 | 811 | /* |
69cf36a4 | 812 | * Send beacon to hardware. |
bd88a781 | 813 | */ |
f224f4ef | 814 | rt2x00dev->ops->lib->write_beacon(intf->beacon, &txdesc); |
bd88a781 | 815 | |
8414ff07 HS |
816 | return 0; |
817 | ||
818 | } | |
819 | ||
820 | int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev, | |
821 | struct ieee80211_vif *vif) | |
822 | { | |
823 | struct rt2x00_intf *intf = vif_to_intf(vif); | |
824 | int ret; | |
825 | ||
826 | mutex_lock(&intf->beacon_skb_mutex); | |
827 | ret = rt2x00queue_update_beacon_locked(rt2x00dev, vif); | |
17512dc3 IP |
828 | mutex_unlock(&intf->beacon_skb_mutex); |
829 | ||
8414ff07 | 830 | return ret; |
bd88a781 ID |
831 | } |
832 | ||
10e11568 | 833 | bool rt2x00queue_for_each_entry(struct data_queue *queue, |
5eb7efe8 ID |
834 | enum queue_index start, |
835 | enum queue_index end, | |
1dd0dbb3 HS |
836 | void *data, |
837 | bool (*fn)(struct queue_entry *entry, | |
838 | void *data)) | |
5eb7efe8 ID |
839 | { |
840 | unsigned long irqflags; | |
841 | unsigned int index_start; | |
842 | unsigned int index_end; | |
843 | unsigned int i; | |
844 | ||
845 | if (unlikely(start >= Q_INDEX_MAX || end >= Q_INDEX_MAX)) { | |
ec9c4989 JP |
846 | rt2x00_err(queue->rt2x00dev, |
847 | "Entry requested from invalid index range (%d - %d)\n", | |
848 | start, end); | |
10e11568 | 849 | return true; |
5eb7efe8 ID |
850 | } |
851 | ||
852 | /* | |
853 | * Only protect the range we are going to loop over, | |
854 | * if during our loop a extra entry is set to pending | |
855 | * it should not be kicked during this run, since it | |
856 | * is part of another TX operation. | |
857 | */ | |
813f0339 | 858 | spin_lock_irqsave(&queue->index_lock, irqflags); |
5eb7efe8 ID |
859 | index_start = queue->index[start]; |
860 | index_end = queue->index[end]; | |
813f0339 | 861 | spin_unlock_irqrestore(&queue->index_lock, irqflags); |
5eb7efe8 ID |
862 | |
863 | /* | |
25985edc | 864 | * Start from the TX done pointer, this guarantees that we will |
5eb7efe8 ID |
865 | * send out all frames in the correct order. |
866 | */ | |
867 | if (index_start < index_end) { | |
10e11568 | 868 | for (i = index_start; i < index_end; i++) { |
1dd0dbb3 | 869 | if (fn(&queue->entries[i], data)) |
10e11568 HS |
870 | return true; |
871 | } | |
5eb7efe8 | 872 | } else { |
10e11568 | 873 | for (i = index_start; i < queue->limit; i++) { |
1dd0dbb3 | 874 | if (fn(&queue->entries[i], data)) |
10e11568 HS |
875 | return true; |
876 | } | |
5eb7efe8 | 877 | |
10e11568 | 878 | for (i = 0; i < index_end; i++) { |
1dd0dbb3 | 879 | if (fn(&queue->entries[i], data)) |
10e11568 HS |
880 | return true; |
881 | } | |
5eb7efe8 | 882 | } |
10e11568 HS |
883 | |
884 | return false; | |
5eb7efe8 ID |
885 | } |
886 | EXPORT_SYMBOL_GPL(rt2x00queue_for_each_entry); | |
887 | ||
181d6902 ID |
888 | struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue, |
889 | enum queue_index index) | |
890 | { | |
891 | struct queue_entry *entry; | |
5f46c4d0 | 892 | unsigned long irqflags; |
181d6902 ID |
893 | |
894 | if (unlikely(index >= Q_INDEX_MAX)) { | |
ec9c4989 JP |
895 | rt2x00_err(queue->rt2x00dev, "Entry requested from invalid index type (%d)\n", |
896 | index); | |
181d6902 ID |
897 | return NULL; |
898 | } | |
899 | ||
813f0339 | 900 | spin_lock_irqsave(&queue->index_lock, irqflags); |
181d6902 ID |
901 | |
902 | entry = &queue->entries[queue->index[index]]; | |
903 | ||
813f0339 | 904 | spin_unlock_irqrestore(&queue->index_lock, irqflags); |
181d6902 ID |
905 | |
906 | return entry; | |
907 | } | |
908 | EXPORT_SYMBOL_GPL(rt2x00queue_get_entry); | |
909 | ||
75256f03 | 910 | void rt2x00queue_index_inc(struct queue_entry *entry, enum queue_index index) |
181d6902 | 911 | { |
75256f03 | 912 | struct data_queue *queue = entry->queue; |
5f46c4d0 ID |
913 | unsigned long irqflags; |
914 | ||
181d6902 | 915 | if (unlikely(index >= Q_INDEX_MAX)) { |
ec9c4989 JP |
916 | rt2x00_err(queue->rt2x00dev, |
917 | "Index change on invalid index type (%d)\n", index); | |
181d6902 ID |
918 | return; |
919 | } | |
920 | ||
813f0339 | 921 | spin_lock_irqsave(&queue->index_lock, irqflags); |
181d6902 ID |
922 | |
923 | queue->index[index]++; | |
924 | if (queue->index[index] >= queue->limit) | |
925 | queue->index[index] = 0; | |
926 | ||
75256f03 | 927 | entry->last_action = jiffies; |
652a9dd2 | 928 | |
10b6b801 ID |
929 | if (index == Q_INDEX) { |
930 | queue->length++; | |
931 | } else if (index == Q_INDEX_DONE) { | |
932 | queue->length--; | |
55887511 | 933 | queue->count++; |
10b6b801 | 934 | } |
181d6902 | 935 | |
813f0339 | 936 | spin_unlock_irqrestore(&queue->index_lock, irqflags); |
181d6902 | 937 | } |
181d6902 | 938 | |
6cdfc1de | 939 | static void rt2x00queue_pause_queue_nocheck(struct data_queue *queue) |
0b7fde54 | 940 | { |
0b7fde54 | 941 | switch (queue->qid) { |
f615e9a3 ID |
942 | case QID_AC_VO: |
943 | case QID_AC_VI: | |
0b7fde54 ID |
944 | case QID_AC_BE: |
945 | case QID_AC_BK: | |
0b7fde54 ID |
946 | /* |
947 | * For TX queues, we have to disable the queue | |
948 | * inside mac80211. | |
949 | */ | |
950 | ieee80211_stop_queue(queue->rt2x00dev->hw, queue->qid); | |
951 | break; | |
952 | default: | |
953 | break; | |
954 | } | |
955 | } | |
e2288b66 SG |
956 | void rt2x00queue_pause_queue(struct data_queue *queue) |
957 | { | |
958 | if (!test_bit(DEVICE_STATE_PRESENT, &queue->rt2x00dev->flags) || | |
959 | !test_bit(QUEUE_STARTED, &queue->flags) || | |
960 | test_and_set_bit(QUEUE_PAUSED, &queue->flags)) | |
961 | return; | |
962 | ||
963 | rt2x00queue_pause_queue_nocheck(queue); | |
964 | } | |
0b7fde54 ID |
965 | EXPORT_SYMBOL_GPL(rt2x00queue_pause_queue); |
966 | ||
967 | void rt2x00queue_unpause_queue(struct data_queue *queue) | |
968 | { | |
969 | if (!test_bit(DEVICE_STATE_PRESENT, &queue->rt2x00dev->flags) || | |
970 | !test_bit(QUEUE_STARTED, &queue->flags) || | |
971 | !test_and_clear_bit(QUEUE_PAUSED, &queue->flags)) | |
972 | return; | |
973 | ||
974 | switch (queue->qid) { | |
f615e9a3 ID |
975 | case QID_AC_VO: |
976 | case QID_AC_VI: | |
0b7fde54 ID |
977 | case QID_AC_BE: |
978 | case QID_AC_BK: | |
0b7fde54 ID |
979 | /* |
980 | * For TX queues, we have to enable the queue | |
981 | * inside mac80211. | |
982 | */ | |
983 | ieee80211_wake_queue(queue->rt2x00dev->hw, queue->qid); | |
984 | break; | |
5be65609 ID |
985 | case QID_RX: |
986 | /* | |
987 | * For RX we need to kick the queue now in order to | |
988 | * receive frames. | |
989 | */ | |
990 | queue->rt2x00dev->ops->lib->kick_queue(queue); | |
0b7fde54 ID |
991 | default: |
992 | break; | |
993 | } | |
994 | } | |
995 | EXPORT_SYMBOL_GPL(rt2x00queue_unpause_queue); | |
996 | ||
997 | void rt2x00queue_start_queue(struct data_queue *queue) | |
998 | { | |
999 | mutex_lock(&queue->status_lock); | |
1000 | ||
1001 | if (!test_bit(DEVICE_STATE_PRESENT, &queue->rt2x00dev->flags) || | |
1002 | test_and_set_bit(QUEUE_STARTED, &queue->flags)) { | |
1003 | mutex_unlock(&queue->status_lock); | |
1004 | return; | |
1005 | } | |
1006 | ||
1007 | set_bit(QUEUE_PAUSED, &queue->flags); | |
1008 | ||
1009 | queue->rt2x00dev->ops->lib->start_queue(queue); | |
1010 | ||
1011 | rt2x00queue_unpause_queue(queue); | |
1012 | ||
1013 | mutex_unlock(&queue->status_lock); | |
1014 | } | |
1015 | EXPORT_SYMBOL_GPL(rt2x00queue_start_queue); | |
1016 | ||
1017 | void rt2x00queue_stop_queue(struct data_queue *queue) | |
1018 | { | |
1019 | mutex_lock(&queue->status_lock); | |
1020 | ||
1021 | if (!test_and_clear_bit(QUEUE_STARTED, &queue->flags)) { | |
1022 | mutex_unlock(&queue->status_lock); | |
1023 | return; | |
1024 | } | |
1025 | ||
e2288b66 | 1026 | rt2x00queue_pause_queue_nocheck(queue); |
0b7fde54 ID |
1027 | |
1028 | queue->rt2x00dev->ops->lib->stop_queue(queue); | |
1029 | ||
1030 | mutex_unlock(&queue->status_lock); | |
1031 | } | |
1032 | EXPORT_SYMBOL_GPL(rt2x00queue_stop_queue); | |
1033 | ||
5be65609 ID |
1034 | void rt2x00queue_flush_queue(struct data_queue *queue, bool drop) |
1035 | { | |
5be65609 | 1036 | bool tx_queue = |
f615e9a3 | 1037 | (queue->qid == QID_AC_VO) || |
5be65609 | 1038 | (queue->qid == QID_AC_VI) || |
f615e9a3 ID |
1039 | (queue->qid == QID_AC_BE) || |
1040 | (queue->qid == QID_AC_BK); | |
5be65609 | 1041 | |
5be65609 ID |
1042 | |
1043 | /* | |
fdbdd25c SG |
1044 | * If we are not supposed to drop any pending |
1045 | * frames, this means we must force a start (=kick) | |
1046 | * to the queue to make sure the hardware will | |
1047 | * start transmitting. | |
5be65609 | 1048 | */ |
fdbdd25c SG |
1049 | if (!drop && tx_queue) |
1050 | queue->rt2x00dev->ops->lib->kick_queue(queue); | |
5be65609 ID |
1051 | |
1052 | /* | |
152a5992 ID |
1053 | * Check if driver supports flushing, if that is the case we can |
1054 | * defer the flushing to the driver. Otherwise we must use the | |
1055 | * alternative which just waits for the queue to become empty. | |
5be65609 | 1056 | */ |
152a5992 ID |
1057 | if (likely(queue->rt2x00dev->ops->lib->flush_queue)) |
1058 | queue->rt2x00dev->ops->lib->flush_queue(queue, drop); | |
5be65609 ID |
1059 | |
1060 | /* | |
1061 | * The queue flush has failed... | |
1062 | */ | |
1063 | if (unlikely(!rt2x00queue_empty(queue))) | |
ec9c4989 JP |
1064 | rt2x00_warn(queue->rt2x00dev, "Queue %d failed to flush\n", |
1065 | queue->qid); | |
5be65609 ID |
1066 | } |
1067 | EXPORT_SYMBOL_GPL(rt2x00queue_flush_queue); | |
1068 | ||
0b7fde54 ID |
1069 | void rt2x00queue_start_queues(struct rt2x00_dev *rt2x00dev) |
1070 | { | |
1071 | struct data_queue *queue; | |
1072 | ||
1073 | /* | |
1074 | * rt2x00queue_start_queue will call ieee80211_wake_queue | |
1075 | * for each queue after is has been properly initialized. | |
1076 | */ | |
1077 | tx_queue_for_each(rt2x00dev, queue) | |
1078 | rt2x00queue_start_queue(queue); | |
1079 | ||
1080 | rt2x00queue_start_queue(rt2x00dev->rx); | |
1081 | } | |
1082 | EXPORT_SYMBOL_GPL(rt2x00queue_start_queues); | |
1083 | ||
1084 | void rt2x00queue_stop_queues(struct rt2x00_dev *rt2x00dev) | |
1085 | { | |
1086 | struct data_queue *queue; | |
1087 | ||
1088 | /* | |
1089 | * rt2x00queue_stop_queue will call ieee80211_stop_queue | |
1090 | * as well, but we are completely shutting doing everything | |
1091 | * now, so it is much safer to stop all TX queues at once, | |
1092 | * and use rt2x00queue_stop_queue for cleaning up. | |
1093 | */ | |
1094 | ieee80211_stop_queues(rt2x00dev->hw); | |
1095 | ||
1096 | tx_queue_for_each(rt2x00dev, queue) | |
1097 | rt2x00queue_stop_queue(queue); | |
1098 | ||
1099 | rt2x00queue_stop_queue(rt2x00dev->rx); | |
1100 | } | |
1101 | EXPORT_SYMBOL_GPL(rt2x00queue_stop_queues); | |
1102 | ||
5be65609 ID |
1103 | void rt2x00queue_flush_queues(struct rt2x00_dev *rt2x00dev, bool drop) |
1104 | { | |
1105 | struct data_queue *queue; | |
1106 | ||
1107 | tx_queue_for_each(rt2x00dev, queue) | |
1108 | rt2x00queue_flush_queue(queue, drop); | |
1109 | ||
1110 | rt2x00queue_flush_queue(rt2x00dev->rx, drop); | |
1111 | } | |
1112 | EXPORT_SYMBOL_GPL(rt2x00queue_flush_queues); | |
1113 | ||
181d6902 ID |
1114 | static void rt2x00queue_reset(struct data_queue *queue) |
1115 | { | |
5f46c4d0 | 1116 | unsigned long irqflags; |
652a9dd2 | 1117 | unsigned int i; |
5f46c4d0 | 1118 | |
813f0339 | 1119 | spin_lock_irqsave(&queue->index_lock, irqflags); |
181d6902 ID |
1120 | |
1121 | queue->count = 0; | |
1122 | queue->length = 0; | |
652a9dd2 | 1123 | |
75256f03 | 1124 | for (i = 0; i < Q_INDEX_MAX; i++) |
652a9dd2 | 1125 | queue->index[i] = 0; |
181d6902 | 1126 | |
813f0339 | 1127 | spin_unlock_irqrestore(&queue->index_lock, irqflags); |
181d6902 ID |
1128 | } |
1129 | ||
798b7adb | 1130 | void rt2x00queue_init_queues(struct rt2x00_dev *rt2x00dev) |
181d6902 ID |
1131 | { |
1132 | struct data_queue *queue; | |
1133 | unsigned int i; | |
1134 | ||
798b7adb | 1135 | queue_for_each(rt2x00dev, queue) { |
181d6902 ID |
1136 | rt2x00queue_reset(queue); |
1137 | ||
64e7d723 | 1138 | for (i = 0; i < queue->limit; i++) |
798b7adb | 1139 | rt2x00dev->ops->lib->clear_entry(&queue->entries[i]); |
181d6902 ID |
1140 | } |
1141 | } | |
1142 | ||
15d6c079 | 1143 | static int rt2x00queue_alloc_entries(struct data_queue *queue) |
181d6902 ID |
1144 | { |
1145 | struct queue_entry *entries; | |
1146 | unsigned int entry_size; | |
1147 | unsigned int i; | |
1148 | ||
1149 | rt2x00queue_reset(queue); | |
1150 | ||
181d6902 ID |
1151 | /* |
1152 | * Allocate all queue entries. | |
1153 | */ | |
568f7a43 | 1154 | entry_size = sizeof(*entries) + queue->priv_size; |
baeb2ffa | 1155 | entries = kcalloc(queue->limit, entry_size, GFP_KERNEL); |
181d6902 ID |
1156 | if (!entries) |
1157 | return -ENOMEM; | |
1158 | ||
1159 | #define QUEUE_ENTRY_PRIV_OFFSET(__base, __index, __limit, __esize, __psize) \ | |
f8bfbc31 ME |
1160 | (((char *)(__base)) + ((__limit) * (__esize)) + \ |
1161 | ((__index) * (__psize))) | |
181d6902 ID |
1162 | |
1163 | for (i = 0; i < queue->limit; i++) { | |
1164 | entries[i].flags = 0; | |
1165 | entries[i].queue = queue; | |
1166 | entries[i].skb = NULL; | |
1167 | entries[i].entry_idx = i; | |
1168 | entries[i].priv_data = | |
1169 | QUEUE_ENTRY_PRIV_OFFSET(entries, i, queue->limit, | |
568f7a43 | 1170 | sizeof(*entries), queue->priv_size); |
181d6902 ID |
1171 | } |
1172 | ||
1173 | #undef QUEUE_ENTRY_PRIV_OFFSET | |
1174 | ||
1175 | queue->entries = entries; | |
1176 | ||
1177 | return 0; | |
1178 | } | |
1179 | ||
fa69560f | 1180 | static void rt2x00queue_free_skbs(struct data_queue *queue) |
30caa6e3 GW |
1181 | { |
1182 | unsigned int i; | |
1183 | ||
1184 | if (!queue->entries) | |
1185 | return; | |
1186 | ||
1187 | for (i = 0; i < queue->limit; i++) { | |
fa69560f | 1188 | rt2x00queue_free_skb(&queue->entries[i]); |
30caa6e3 GW |
1189 | } |
1190 | } | |
1191 | ||
fa69560f | 1192 | static int rt2x00queue_alloc_rxskbs(struct data_queue *queue) |
30caa6e3 GW |
1193 | { |
1194 | unsigned int i; | |
1195 | struct sk_buff *skb; | |
1196 | ||
1197 | for (i = 0; i < queue->limit; i++) { | |
88211021 | 1198 | skb = rt2x00queue_alloc_rxskb(&queue->entries[i], GFP_KERNEL); |
30caa6e3 | 1199 | if (!skb) |
61243d8e | 1200 | return -ENOMEM; |
30caa6e3 GW |
1201 | queue->entries[i].skb = skb; |
1202 | } | |
1203 | ||
1204 | return 0; | |
30caa6e3 GW |
1205 | } |
1206 | ||
181d6902 ID |
1207 | int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev) |
1208 | { | |
1209 | struct data_queue *queue; | |
1210 | int status; | |
1211 | ||
15d6c079 | 1212 | status = rt2x00queue_alloc_entries(rt2x00dev->rx); |
181d6902 ID |
1213 | if (status) |
1214 | goto exit; | |
1215 | ||
1216 | tx_queue_for_each(rt2x00dev, queue) { | |
15d6c079 | 1217 | status = rt2x00queue_alloc_entries(queue); |
181d6902 ID |
1218 | if (status) |
1219 | goto exit; | |
1220 | } | |
1221 | ||
15d6c079 | 1222 | status = rt2x00queue_alloc_entries(rt2x00dev->bcn); |
181d6902 ID |
1223 | if (status) |
1224 | goto exit; | |
1225 | ||
7dab73b3 | 1226 | if (test_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags)) { |
15d6c079 | 1227 | status = rt2x00queue_alloc_entries(rt2x00dev->atim); |
30caa6e3 GW |
1228 | if (status) |
1229 | goto exit; | |
1230 | } | |
181d6902 | 1231 | |
fa69560f | 1232 | status = rt2x00queue_alloc_rxskbs(rt2x00dev->rx); |
181d6902 ID |
1233 | if (status) |
1234 | goto exit; | |
1235 | ||
1236 | return 0; | |
1237 | ||
1238 | exit: | |
ec9c4989 | 1239 | rt2x00_err(rt2x00dev, "Queue entries allocation failed\n"); |
181d6902 ID |
1240 | |
1241 | rt2x00queue_uninitialize(rt2x00dev); | |
1242 | ||
1243 | return status; | |
1244 | } | |
1245 | ||
1246 | void rt2x00queue_uninitialize(struct rt2x00_dev *rt2x00dev) | |
1247 | { | |
1248 | struct data_queue *queue; | |
1249 | ||
fa69560f | 1250 | rt2x00queue_free_skbs(rt2x00dev->rx); |
30caa6e3 | 1251 | |
181d6902 ID |
1252 | queue_for_each(rt2x00dev, queue) { |
1253 | kfree(queue->entries); | |
1254 | queue->entries = NULL; | |
1255 | } | |
1256 | } | |
1257 | ||
8f539276 ID |
1258 | static void rt2x00queue_init(struct rt2x00_dev *rt2x00dev, |
1259 | struct data_queue *queue, enum data_queue_qid qid) | |
1260 | { | |
0b7fde54 | 1261 | mutex_init(&queue->status_lock); |
77a861c4 | 1262 | spin_lock_init(&queue->tx_lock); |
813f0339 | 1263 | spin_lock_init(&queue->index_lock); |
8f539276 ID |
1264 | |
1265 | queue->rt2x00dev = rt2x00dev; | |
1266 | queue->qid = qid; | |
2af0a570 | 1267 | queue->txop = 0; |
8f539276 ID |
1268 | queue->aifs = 2; |
1269 | queue->cw_min = 5; | |
1270 | queue->cw_max = 10; | |
10af87c3 | 1271 | |
705802bf | 1272 | rt2x00dev->ops->queue_init(queue); |
04453e9b GJ |
1273 | |
1274 | queue->threshold = DIV_ROUND_UP(queue->limit, 10); | |
8f539276 ID |
1275 | } |
1276 | ||
181d6902 ID |
1277 | int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev) |
1278 | { | |
1279 | struct data_queue *queue; | |
1280 | enum data_queue_qid qid; | |
1281 | unsigned int req_atim = | |
7dab73b3 | 1282 | !!test_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags); |
181d6902 ID |
1283 | |
1284 | /* | |
1285 | * We need the following queues: | |
1286 | * RX: 1 | |
61448f88 | 1287 | * TX: ops->tx_queues |
181d6902 ID |
1288 | * Beacon: 1 |
1289 | * Atim: 1 (if required) | |
1290 | */ | |
61448f88 | 1291 | rt2x00dev->data_queues = 2 + rt2x00dev->ops->tx_queues + req_atim; |
181d6902 | 1292 | |
baeb2ffa | 1293 | queue = kcalloc(rt2x00dev->data_queues, sizeof(*queue), GFP_KERNEL); |
181d6902 | 1294 | if (!queue) { |
ec9c4989 | 1295 | rt2x00_err(rt2x00dev, "Queue allocation failed\n"); |
181d6902 ID |
1296 | return -ENOMEM; |
1297 | } | |
1298 | ||
1299 | /* | |
1300 | * Initialize pointers | |
1301 | */ | |
1302 | rt2x00dev->rx = queue; | |
1303 | rt2x00dev->tx = &queue[1]; | |
61448f88 | 1304 | rt2x00dev->bcn = &queue[1 + rt2x00dev->ops->tx_queues]; |
e74df4a7 | 1305 | rt2x00dev->atim = req_atim ? &queue[2 + rt2x00dev->ops->tx_queues] : NULL; |
181d6902 ID |
1306 | |
1307 | /* | |
1308 | * Initialize queue parameters. | |
1309 | * RX: qid = QID_RX | |
f615e9a3 | 1310 | * TX: qid = QID_AC_VO + index |
181d6902 ID |
1311 | * TX: cw_min: 2^5 = 32. |
1312 | * TX: cw_max: 2^10 = 1024. | |
565a019a ID |
1313 | * BCN: qid = QID_BEACON |
1314 | * ATIM: qid = QID_ATIM | |
181d6902 | 1315 | */ |
8f539276 | 1316 | rt2x00queue_init(rt2x00dev, rt2x00dev->rx, QID_RX); |
181d6902 | 1317 | |
f615e9a3 | 1318 | qid = QID_AC_VO; |
8f539276 ID |
1319 | tx_queue_for_each(rt2x00dev, queue) |
1320 | rt2x00queue_init(rt2x00dev, queue, qid++); | |
181d6902 | 1321 | |
e74df4a7 | 1322 | rt2x00queue_init(rt2x00dev, rt2x00dev->bcn, QID_BEACON); |
181d6902 | 1323 | if (req_atim) |
e74df4a7 | 1324 | rt2x00queue_init(rt2x00dev, rt2x00dev->atim, QID_ATIM); |
181d6902 ID |
1325 | |
1326 | return 0; | |
1327 | } | |
1328 | ||
1329 | void rt2x00queue_free(struct rt2x00_dev *rt2x00dev) | |
1330 | { | |
1331 | kfree(rt2x00dev->rx); | |
1332 | rt2x00dev->rx = NULL; | |
1333 | rt2x00dev->tx = NULL; | |
1334 | rt2x00dev->bcn = NULL; | |
1335 | } |