rt2x00: Fix race conditions in flag handling
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2x00queue.c
CommitLineData
181d6902
ID
1/*
2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2x00lib
23 Abstract: rt2x00 queue specific routines.
24 */
25
26#include <linux/kernel.h>
27#include <linux/module.h>
c4da0048 28#include <linux/dma-mapping.h>
181d6902
ID
29
30#include "rt2x00.h"
31#include "rt2x00lib.h"
32
c4da0048
GW
33struct sk_buff *rt2x00queue_alloc_rxskb(struct rt2x00_dev *rt2x00dev,
34 struct queue_entry *entry)
239c249d 35{
c4da0048
GW
36 struct sk_buff *skb;
37 struct skb_frame_desc *skbdesc;
2bb057d0
ID
38 unsigned int frame_size;
39 unsigned int head_size = 0;
40 unsigned int tail_size = 0;
239c249d
GW
41
42 /*
43 * The frame size includes descriptor size, because the
44 * hardware directly receive the frame into the skbuffer.
45 */
c4da0048 46 frame_size = entry->queue->data_size + entry->queue->desc_size;
239c249d
GW
47
48 /*
ff352391
ID
49 * The payload should be aligned to a 4-byte boundary,
50 * this means we need at least 3 bytes for moving the frame
51 * into the correct offset.
239c249d 52 */
2bb057d0
ID
53 head_size = 4;
54
55 /*
56 * For IV/EIV/ICV assembly we must make sure there is
57 * at least 8 bytes bytes available in headroom for IV/EIV
58 * and 4 bytes for ICV data as tailroon.
59 */
60#ifdef CONFIG_RT2X00_LIB_CRYPTO
61 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
62 head_size += 8;
63 tail_size += 4;
64 }
65#endif /* CONFIG_RT2X00_LIB_CRYPTO */
239c249d
GW
66
67 /*
68 * Allocate skbuffer.
69 */
2bb057d0 70 skb = dev_alloc_skb(frame_size + head_size + tail_size);
239c249d
GW
71 if (!skb)
72 return NULL;
73
2bb057d0
ID
74 /*
75 * Make sure we not have a frame with the requested bytes
76 * available in the head and tail.
77 */
78 skb_reserve(skb, head_size);
239c249d
GW
79 skb_put(skb, frame_size);
80
c4da0048
GW
81 /*
82 * Populate skbdesc.
83 */
84 skbdesc = get_skb_frame_desc(skb);
85 memset(skbdesc, 0, sizeof(*skbdesc));
86 skbdesc->entry = entry;
87
88 if (test_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags)) {
89 skbdesc->skb_dma = dma_map_single(rt2x00dev->dev,
90 skb->data,
91 skb->len,
92 DMA_FROM_DEVICE);
93 skbdesc->flags |= SKBDESC_DMA_MAPPED_RX;
94 }
95
239c249d
GW
96 return skb;
97}
30caa6e3 98
c4da0048 99void rt2x00queue_map_txskb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
30caa6e3 100{
c4da0048
GW
101 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
102
103 skbdesc->skb_dma = dma_map_single(rt2x00dev->dev, skb->data, skb->len,
104 DMA_TO_DEVICE);
105 skbdesc->flags |= SKBDESC_DMA_MAPPED_TX;
106}
107EXPORT_SYMBOL_GPL(rt2x00queue_map_txskb);
108
109void rt2x00queue_unmap_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
110{
111 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
112
113 if (skbdesc->flags & SKBDESC_DMA_MAPPED_RX) {
114 dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma, skb->len,
115 DMA_FROM_DEVICE);
116 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_RX;
117 }
118
119 if (skbdesc->flags & SKBDESC_DMA_MAPPED_TX) {
120 dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma, skb->len,
121 DMA_TO_DEVICE);
122 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_TX;
123 }
124}
c4da0048
GW
125
126void rt2x00queue_free_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
127{
9a613195
ID
128 if (!skb)
129 return;
130
61243d8e 131 rt2x00queue_unmap_skb(rt2x00dev, skb);
30caa6e3
GW
132 dev_kfree_skb_any(skb);
133}
239c249d 134
bd88a781
ID
135static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry,
136 struct txentry_desc *txdesc)
7050ec82 137{
2e92e6f2 138 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
e039fa4a 139 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
5adf6d63 140 struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
7050ec82 141 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
2e92e6f2 142 struct ieee80211_rate *rate =
e039fa4a 143 ieee80211_get_tx_rate(rt2x00dev->hw, tx_info);
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ID
144 const struct rt2x00_rate *hwrate;
145 unsigned int data_length;
146 unsigned int duration;
147 unsigned int residual;
d4764b29 148 unsigned long irqflags;
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ID
149
150 memset(txdesc, 0, sizeof(*txdesc));
151
152 /*
153 * Initialize information from queue
154 */
155 txdesc->queue = entry->queue->qid;
156 txdesc->cw_min = entry->queue->cw_min;
157 txdesc->cw_max = entry->queue->cw_max;
158 txdesc->aifs = entry->queue->aifs;
159
2bb057d0 160 /* Data length + CRC + IV/EIV/ICV/MMIC (when using encryption) */
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ID
161 data_length = entry->skb->len + 4;
162
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ID
163 /*
164 * Check whether this frame is to be acked.
165 */
e039fa4a 166 if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK))
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ID
167 __set_bit(ENTRY_TXD_ACK, &txdesc->flags);
168
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ID
169#ifdef CONFIG_RT2X00_LIB_CRYPTO
170 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags) &&
171 !entry->skb->do_not_encrypt) {
172 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
173
174 __set_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags);
175
176 txdesc->cipher = rt2x00crypto_key_to_cipher(hw_key);
177
178 if (hw_key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
179 __set_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags);
180
181 txdesc->key_idx = hw_key->hw_key_idx;
182 txdesc->iv_offset = ieee80211_get_hdrlen_from_skb(entry->skb);
183
184 /*
185 * Extend frame length to include all encryption overhead
186 * that will be added by the hardware.
187 */
188 data_length += rt2x00crypto_tx_overhead(tx_info);
189
190 if (!(hw_key->flags & IEEE80211_KEY_FLAG_GENERATE_IV))
191 __set_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags);
192
193 if (!(hw_key->flags & IEEE80211_KEY_FLAG_GENERATE_MMIC))
194 __set_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags);
195 }
196#endif /* CONFIG_RT2X00_LIB_CRYPTO */
197
7050ec82
ID
198 /*
199 * Check if this is a RTS/CTS frame
200 */
ac104462
ID
201 if (ieee80211_is_rts(hdr->frame_control) ||
202 ieee80211_is_cts(hdr->frame_control)) {
7050ec82 203 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
ac104462 204 if (ieee80211_is_rts(hdr->frame_control))
7050ec82 205 __set_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags);
e039fa4a 206 else
7050ec82 207 __set_bit(ENTRY_TXD_CTS_FRAME, &txdesc->flags);
e039fa4a 208 if (tx_info->control.rts_cts_rate_idx >= 0)
2e92e6f2 209 rate =
e039fa4a 210 ieee80211_get_rts_cts_rate(rt2x00dev->hw, tx_info);
7050ec82
ID
211 }
212
213 /*
214 * Determine retry information.
215 */
e039fa4a
JB
216 txdesc->retry_limit = tx_info->control.retry_limit;
217 if (tx_info->flags & IEEE80211_TX_CTL_LONG_RETRY_LIMIT)
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ID
218 __set_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags);
219
220 /*
221 * Check if more fragments are pending
222 */
8b7b1e05 223 if (ieee80211_has_morefrags(hdr->frame_control)) {
7050ec82
ID
224 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
225 __set_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags);
226 }
227
228 /*
229 * Beacons and probe responses require the tsf timestamp
230 * to be inserted into the frame.
231 */
ac104462
ID
232 if (ieee80211_is_beacon(hdr->frame_control) ||
233 ieee80211_is_probe_resp(hdr->frame_control))
7050ec82
ID
234 __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags);
235
236 /*
237 * Determine with what IFS priority this frame should be send.
238 * Set ifs to IFS_SIFS when the this is not the first fragment,
239 * or this fragment came after RTS/CTS.
240 */
241 if (test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)) {
242 txdesc->ifs = IFS_SIFS;
e039fa4a 243 } else if (tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) {
7050ec82
ID
244 __set_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags);
245 txdesc->ifs = IFS_BACKOFF;
246 } else {
247 txdesc->ifs = IFS_SIFS;
248 }
249
5adf6d63
ID
250 /*
251 * Hardware should insert sequence counter.
252 * FIXME: We insert a software sequence counter first for
253 * hardware that doesn't support hardware sequence counting.
254 *
255 * This is wrong because beacons are not getting sequence
256 * numbers assigned properly.
257 *
258 * A secondary problem exists for drivers that cannot toggle
259 * sequence counting per-frame, since those will override the
260 * sequence counter given by mac80211.
261 */
262 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
d4764b29 263 spin_lock_irqsave(&intf->seqlock, irqflags);
5adf6d63
ID
264
265 if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags))
266 intf->seqno += 0x10;
267 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
268 hdr->seq_ctrl |= cpu_to_le16(intf->seqno);
269
d4764b29 270 spin_unlock_irqrestore(&intf->seqlock, irqflags);
5adf6d63
ID
271
272 __set_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags);
273 }
274
7050ec82
ID
275 /*
276 * PLCP setup
277 * Length calculation depends on OFDM/CCK rate.
278 */
279 hwrate = rt2x00_get_rate(rate->hw_value);
280 txdesc->signal = hwrate->plcp;
281 txdesc->service = 0x04;
282
283 if (hwrate->flags & DEV_RATE_OFDM) {
284 __set_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags);
285
286 txdesc->length_high = (data_length >> 6) & 0x3f;
287 txdesc->length_low = data_length & 0x3f;
288 } else {
289 /*
290 * Convert length to microseconds.
291 */
292 residual = get_duration_res(data_length, hwrate->bitrate);
293 duration = get_duration(data_length, hwrate->bitrate);
294
295 if (residual != 0) {
296 duration++;
297
298 /*
299 * Check if we need to set the Length Extension
300 */
301 if (hwrate->bitrate == 110 && residual <= 30)
302 txdesc->service |= 0x80;
303 }
304
305 txdesc->length_high = (duration >> 8) & 0xff;
306 txdesc->length_low = duration & 0xff;
307
308 /*
309 * When preamble is enabled we should set the
310 * preamble bit for the signal.
311 */
312 if (rt2x00_get_rate_preamble(rate->hw_value))
313 txdesc->signal |= 0x08;
314 }
315}
7050ec82 316
bd88a781
ID
317static void rt2x00queue_write_tx_descriptor(struct queue_entry *entry,
318 struct txentry_desc *txdesc)
7050ec82 319{
b869767b
ID
320 struct data_queue *queue = entry->queue;
321 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
7050ec82
ID
322
323 rt2x00dev->ops->lib->write_tx_desc(rt2x00dev, entry->skb, txdesc);
324
325 /*
326 * All processing on the frame has been completed, this means
327 * it is now ready to be dumped to userspace through debugfs.
328 */
329 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_TX, entry->skb);
330
331 /*
b869767b
ID
332 * Check if we need to kick the queue, there are however a few rules
333 * 1) Don't kick beacon queue
334 * 2) Don't kick unless this is the last in frame in a burst.
335 * When the burst flag is set, this frame is always followed
336 * by another frame which in some way are related to eachother.
337 * This is true for fragments, RTS or CTS-to-self frames.
338 * 3) Rule 2 can be broken when the available entries
339 * in the queue are less then a certain threshold.
7050ec82 340 */
b869767b
ID
341 if (entry->queue->qid == QID_BEACON)
342 return;
343
344 if (rt2x00queue_threshold(queue) ||
345 !test_bit(ENTRY_TXD_BURST, &txdesc->flags))
346 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, queue->qid);
7050ec82 347}
7050ec82 348
6db3786a
ID
349int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb)
350{
351 struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX);
352 struct txentry_desc txdesc;
d74f5ba4 353 struct skb_frame_desc *skbdesc;
2bb057d0 354 unsigned int iv_len = IEEE80211_SKB_CB(skb)->control.iv_len;
6db3786a
ID
355
356 if (unlikely(rt2x00queue_full(queue)))
357 return -EINVAL;
358
0262ab0d 359 if (test_and_set_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags)) {
6db3786a
ID
360 ERROR(queue->rt2x00dev,
361 "Arrived at non-free entry in the non-full queue %d.\n"
362 "Please file bug report to %s.\n",
363 queue->qid, DRV_PROJECT);
364 return -EINVAL;
365 }
366
367 /*
368 * Copy all TX descriptor information into txdesc,
369 * after that we are free to use the skb->cb array
370 * for our information.
371 */
372 entry->skb = skb;
373 rt2x00queue_create_tx_descriptor(entry, &txdesc);
374
d74f5ba4 375 /*
2bb057d0
ID
376 * All information is retreived from the skb->cb array,
377 * now we should claim ownership of the driver part of that
378 * array.
d74f5ba4
ID
379 */
380 skbdesc = get_skb_frame_desc(entry->skb);
381 memset(skbdesc, 0, sizeof(*skbdesc));
382 skbdesc->entry = entry;
383
2bb057d0
ID
384 /*
385 * When hardware encryption is supported, and this frame
386 * is to be encrypted, we should strip the IV/EIV data from
387 * the frame so we can provide it to the driver seperately.
388 */
389 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc.flags) &&
390 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc.flags))
391 rt2x00crypto_tx_remove_iv(skb, iv_len);
392
393 /*
394 * It could be possible that the queue was corrupted and this
395 * call failed. Just drop the frame, we cannot rollback and pass
396 * the frame to mac80211 because the skb->cb has now been tainted.
397 */
6db3786a 398 if (unlikely(queue->rt2x00dev->ops->lib->write_tx_data(entry))) {
0262ab0d 399 clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
2bb057d0
ID
400 dev_kfree_skb_any(entry->skb);
401 entry->skb = NULL;
402 return 0;
6db3786a
ID
403 }
404
d74f5ba4
ID
405 if (test_bit(DRIVER_REQUIRE_DMA, &queue->rt2x00dev->flags))
406 rt2x00queue_map_txskb(queue->rt2x00dev, skb);
407
0262ab0d 408 set_bit(ENTRY_DATA_PENDING, &entry->flags);
6db3786a
ID
409
410 rt2x00queue_index_inc(queue, Q_INDEX);
411 rt2x00queue_write_tx_descriptor(entry, &txdesc);
412
413 return 0;
414}
415
bd88a781
ID
416int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev,
417 struct ieee80211_vif *vif)
418{
419 struct rt2x00_intf *intf = vif_to_intf(vif);
420 struct skb_frame_desc *skbdesc;
421 struct txentry_desc txdesc;
422 __le32 desc[16];
423
424 if (unlikely(!intf->beacon))
425 return -ENOBUFS;
426
427 intf->beacon->skb = ieee80211_beacon_get(rt2x00dev->hw, vif);
428 if (!intf->beacon->skb)
429 return -ENOMEM;
430
431 /*
432 * Copy all TX descriptor information into txdesc,
433 * after that we are free to use the skb->cb array
434 * for our information.
435 */
436 rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc);
437
438 /*
439 * For the descriptor we use a local array from where the
440 * driver can move it to the correct location required for
441 * the hardware.
442 */
443 memset(desc, 0, sizeof(desc));
444
445 /*
446 * Fill in skb descriptor
447 */
448 skbdesc = get_skb_frame_desc(intf->beacon->skb);
449 memset(skbdesc, 0, sizeof(*skbdesc));
450 skbdesc->desc = desc;
451 skbdesc->desc_len = intf->beacon->queue->desc_size;
452 skbdesc->entry = intf->beacon;
453
454 /*
455 * Write TX descriptor into reserved room in front of the beacon.
456 */
457 rt2x00queue_write_tx_descriptor(intf->beacon, &txdesc);
458
459 /*
460 * Send beacon to hardware.
461 * Also enable beacon generation, which might have been disabled
462 * by the driver during the config_beacon() callback function.
463 */
464 rt2x00dev->ops->lib->write_beacon(intf->beacon);
465 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, QID_BEACON);
466
467 return 0;
468}
469
181d6902 470struct data_queue *rt2x00queue_get_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 471 const enum data_queue_qid queue)
181d6902
ID
472{
473 int atim = test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
474
61448f88 475 if (queue < rt2x00dev->ops->tx_queues && rt2x00dev->tx)
181d6902
ID
476 return &rt2x00dev->tx[queue];
477
478 if (!rt2x00dev->bcn)
479 return NULL;
480
e58c6aca 481 if (queue == QID_BEACON)
181d6902 482 return &rt2x00dev->bcn[0];
e58c6aca 483 else if (queue == QID_ATIM && atim)
181d6902
ID
484 return &rt2x00dev->bcn[1];
485
486 return NULL;
487}
488EXPORT_SYMBOL_GPL(rt2x00queue_get_queue);
489
490struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue,
491 enum queue_index index)
492{
493 struct queue_entry *entry;
5f46c4d0 494 unsigned long irqflags;
181d6902
ID
495
496 if (unlikely(index >= Q_INDEX_MAX)) {
497 ERROR(queue->rt2x00dev,
498 "Entry requested from invalid index type (%d)\n", index);
499 return NULL;
500 }
501
5f46c4d0 502 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
503
504 entry = &queue->entries[queue->index[index]];
505
5f46c4d0 506 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902
ID
507
508 return entry;
509}
510EXPORT_SYMBOL_GPL(rt2x00queue_get_entry);
511
512void rt2x00queue_index_inc(struct data_queue *queue, enum queue_index index)
513{
5f46c4d0
ID
514 unsigned long irqflags;
515
181d6902
ID
516 if (unlikely(index >= Q_INDEX_MAX)) {
517 ERROR(queue->rt2x00dev,
518 "Index change on invalid index type (%d)\n", index);
519 return;
520 }
521
5f46c4d0 522 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
523
524 queue->index[index]++;
525 if (queue->index[index] >= queue->limit)
526 queue->index[index] = 0;
527
10b6b801
ID
528 if (index == Q_INDEX) {
529 queue->length++;
530 } else if (index == Q_INDEX_DONE) {
531 queue->length--;
532 queue->count ++;
533 }
181d6902 534
5f46c4d0 535 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902 536}
181d6902
ID
537
538static void rt2x00queue_reset(struct data_queue *queue)
539{
5f46c4d0
ID
540 unsigned long irqflags;
541
542 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
543
544 queue->count = 0;
545 queue->length = 0;
546 memset(queue->index, 0, sizeof(queue->index));
547
5f46c4d0 548 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902
ID
549}
550
551void rt2x00queue_init_rx(struct rt2x00_dev *rt2x00dev)
552{
553 struct data_queue *queue = rt2x00dev->rx;
554 unsigned int i;
555
556 rt2x00queue_reset(queue);
557
558 if (!rt2x00dev->ops->lib->init_rxentry)
559 return;
560
9c0ab712
ID
561 for (i = 0; i < queue->limit; i++) {
562 queue->entries[i].flags = 0;
563
181d6902
ID
564 rt2x00dev->ops->lib->init_rxentry(rt2x00dev,
565 &queue->entries[i]);
9c0ab712 566 }
181d6902
ID
567}
568
569void rt2x00queue_init_tx(struct rt2x00_dev *rt2x00dev)
570{
571 struct data_queue *queue;
572 unsigned int i;
573
574 txall_queue_for_each(rt2x00dev, queue) {
575 rt2x00queue_reset(queue);
576
577 if (!rt2x00dev->ops->lib->init_txentry)
578 continue;
579
9c0ab712
ID
580 for (i = 0; i < queue->limit; i++) {
581 queue->entries[i].flags = 0;
582
181d6902
ID
583 rt2x00dev->ops->lib->init_txentry(rt2x00dev,
584 &queue->entries[i]);
9c0ab712 585 }
181d6902
ID
586 }
587}
588
589static int rt2x00queue_alloc_entries(struct data_queue *queue,
590 const struct data_queue_desc *qdesc)
591{
592 struct queue_entry *entries;
593 unsigned int entry_size;
594 unsigned int i;
595
596 rt2x00queue_reset(queue);
597
598 queue->limit = qdesc->entry_num;
b869767b 599 queue->threshold = DIV_ROUND_UP(qdesc->entry_num, 10);
181d6902
ID
600 queue->data_size = qdesc->data_size;
601 queue->desc_size = qdesc->desc_size;
602
603 /*
604 * Allocate all queue entries.
605 */
606 entry_size = sizeof(*entries) + qdesc->priv_size;
607 entries = kzalloc(queue->limit * entry_size, GFP_KERNEL);
608 if (!entries)
609 return -ENOMEM;
610
611#define QUEUE_ENTRY_PRIV_OFFSET(__base, __index, __limit, __esize, __psize) \
231be4e9
AB
612 ( ((char *)(__base)) + ((__limit) * (__esize)) + \
613 ((__index) * (__psize)) )
181d6902
ID
614
615 for (i = 0; i < queue->limit; i++) {
616 entries[i].flags = 0;
617 entries[i].queue = queue;
618 entries[i].skb = NULL;
619 entries[i].entry_idx = i;
620 entries[i].priv_data =
621 QUEUE_ENTRY_PRIV_OFFSET(entries, i, queue->limit,
622 sizeof(*entries), qdesc->priv_size);
623 }
624
625#undef QUEUE_ENTRY_PRIV_OFFSET
626
627 queue->entries = entries;
628
629 return 0;
630}
631
c4da0048
GW
632static void rt2x00queue_free_skbs(struct rt2x00_dev *rt2x00dev,
633 struct data_queue *queue)
30caa6e3
GW
634{
635 unsigned int i;
636
637 if (!queue->entries)
638 return;
639
640 for (i = 0; i < queue->limit; i++) {
641 if (queue->entries[i].skb)
c4da0048 642 rt2x00queue_free_skb(rt2x00dev, queue->entries[i].skb);
30caa6e3
GW
643 }
644}
645
c4da0048
GW
646static int rt2x00queue_alloc_rxskbs(struct rt2x00_dev *rt2x00dev,
647 struct data_queue *queue)
30caa6e3
GW
648{
649 unsigned int i;
650 struct sk_buff *skb;
651
652 for (i = 0; i < queue->limit; i++) {
c4da0048 653 skb = rt2x00queue_alloc_rxskb(rt2x00dev, &queue->entries[i]);
30caa6e3 654 if (!skb)
61243d8e 655 return -ENOMEM;
30caa6e3
GW
656 queue->entries[i].skb = skb;
657 }
658
659 return 0;
30caa6e3
GW
660}
661
181d6902
ID
662int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev)
663{
664 struct data_queue *queue;
665 int status;
666
181d6902
ID
667 status = rt2x00queue_alloc_entries(rt2x00dev->rx, rt2x00dev->ops->rx);
668 if (status)
669 goto exit;
670
671 tx_queue_for_each(rt2x00dev, queue) {
672 status = rt2x00queue_alloc_entries(queue, rt2x00dev->ops->tx);
673 if (status)
674 goto exit;
675 }
676
677 status = rt2x00queue_alloc_entries(rt2x00dev->bcn, rt2x00dev->ops->bcn);
678 if (status)
679 goto exit;
680
30caa6e3
GW
681 if (test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags)) {
682 status = rt2x00queue_alloc_entries(&rt2x00dev->bcn[1],
683 rt2x00dev->ops->atim);
684 if (status)
685 goto exit;
686 }
181d6902 687
c4da0048 688 status = rt2x00queue_alloc_rxskbs(rt2x00dev, rt2x00dev->rx);
181d6902
ID
689 if (status)
690 goto exit;
691
692 return 0;
693
694exit:
695 ERROR(rt2x00dev, "Queue entries allocation failed.\n");
696
697 rt2x00queue_uninitialize(rt2x00dev);
698
699 return status;
700}
701
702void rt2x00queue_uninitialize(struct rt2x00_dev *rt2x00dev)
703{
704 struct data_queue *queue;
705
c4da0048 706 rt2x00queue_free_skbs(rt2x00dev, rt2x00dev->rx);
30caa6e3 707
181d6902
ID
708 queue_for_each(rt2x00dev, queue) {
709 kfree(queue->entries);
710 queue->entries = NULL;
711 }
712}
713
8f539276
ID
714static void rt2x00queue_init(struct rt2x00_dev *rt2x00dev,
715 struct data_queue *queue, enum data_queue_qid qid)
716{
717 spin_lock_init(&queue->lock);
718
719 queue->rt2x00dev = rt2x00dev;
720 queue->qid = qid;
721 queue->aifs = 2;
722 queue->cw_min = 5;
723 queue->cw_max = 10;
724}
725
181d6902
ID
726int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
727{
728 struct data_queue *queue;
729 enum data_queue_qid qid;
730 unsigned int req_atim =
731 !!test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
732
733 /*
734 * We need the following queues:
735 * RX: 1
61448f88 736 * TX: ops->tx_queues
181d6902
ID
737 * Beacon: 1
738 * Atim: 1 (if required)
739 */
61448f88 740 rt2x00dev->data_queues = 2 + rt2x00dev->ops->tx_queues + req_atim;
181d6902
ID
741
742 queue = kzalloc(rt2x00dev->data_queues * sizeof(*queue), GFP_KERNEL);
743 if (!queue) {
744 ERROR(rt2x00dev, "Queue allocation failed.\n");
745 return -ENOMEM;
746 }
747
748 /*
749 * Initialize pointers
750 */
751 rt2x00dev->rx = queue;
752 rt2x00dev->tx = &queue[1];
61448f88 753 rt2x00dev->bcn = &queue[1 + rt2x00dev->ops->tx_queues];
181d6902
ID
754
755 /*
756 * Initialize queue parameters.
757 * RX: qid = QID_RX
758 * TX: qid = QID_AC_BE + index
759 * TX: cw_min: 2^5 = 32.
760 * TX: cw_max: 2^10 = 1024.
565a019a
ID
761 * BCN: qid = QID_BEACON
762 * ATIM: qid = QID_ATIM
181d6902 763 */
8f539276 764 rt2x00queue_init(rt2x00dev, rt2x00dev->rx, QID_RX);
181d6902 765
8f539276
ID
766 qid = QID_AC_BE;
767 tx_queue_for_each(rt2x00dev, queue)
768 rt2x00queue_init(rt2x00dev, queue, qid++);
181d6902 769
565a019a 770 rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[0], QID_BEACON);
181d6902 771 if (req_atim)
565a019a 772 rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[1], QID_ATIM);
181d6902
ID
773
774 return 0;
775}
776
777void rt2x00queue_free(struct rt2x00_dev *rt2x00dev)
778{
779 kfree(rt2x00dev->rx);
780 rt2x00dev->rx = NULL;
781 rt2x00dev->tx = NULL;
782 rt2x00dev->bcn = NULL;
783}
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