WE: Fix set events not propagated
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2x00queue.c
CommitLineData
181d6902 1/*
9c9a0d14
GW
2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2004 - 2009 Gertjan van Wingerde <gwingerde@gmail.com>
181d6902
ID
4 <http://rt2x00.serialmonkey.com>
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the
18 Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22/*
23 Module: rt2x00lib
24 Abstract: rt2x00 queue specific routines.
25 */
26
27#include <linux/kernel.h>
28#include <linux/module.h>
c4da0048 29#include <linux/dma-mapping.h>
181d6902
ID
30
31#include "rt2x00.h"
32#include "rt2x00lib.h"
33
c4da0048
GW
34struct sk_buff *rt2x00queue_alloc_rxskb(struct rt2x00_dev *rt2x00dev,
35 struct queue_entry *entry)
239c249d 36{
c4da0048
GW
37 struct sk_buff *skb;
38 struct skb_frame_desc *skbdesc;
2bb057d0
ID
39 unsigned int frame_size;
40 unsigned int head_size = 0;
41 unsigned int tail_size = 0;
239c249d
GW
42
43 /*
44 * The frame size includes descriptor size, because the
45 * hardware directly receive the frame into the skbuffer.
46 */
c4da0048 47 frame_size = entry->queue->data_size + entry->queue->desc_size;
239c249d
GW
48
49 /*
ff352391
ID
50 * The payload should be aligned to a 4-byte boundary,
51 * this means we need at least 3 bytes for moving the frame
52 * into the correct offset.
239c249d 53 */
2bb057d0
ID
54 head_size = 4;
55
56 /*
57 * For IV/EIV/ICV assembly we must make sure there is
58 * at least 8 bytes bytes available in headroom for IV/EIV
9c3444d3 59 * and 8 bytes for ICV data as tailroon.
2bb057d0 60 */
2bb057d0
ID
61 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
62 head_size += 8;
9c3444d3 63 tail_size += 8;
2bb057d0 64 }
239c249d
GW
65
66 /*
67 * Allocate skbuffer.
68 */
2bb057d0 69 skb = dev_alloc_skb(frame_size + head_size + tail_size);
239c249d
GW
70 if (!skb)
71 return NULL;
72
2bb057d0
ID
73 /*
74 * Make sure we not have a frame with the requested bytes
75 * available in the head and tail.
76 */
77 skb_reserve(skb, head_size);
239c249d
GW
78 skb_put(skb, frame_size);
79
c4da0048
GW
80 /*
81 * Populate skbdesc.
82 */
83 skbdesc = get_skb_frame_desc(skb);
84 memset(skbdesc, 0, sizeof(*skbdesc));
85 skbdesc->entry = entry;
86
87 if (test_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags)) {
88 skbdesc->skb_dma = dma_map_single(rt2x00dev->dev,
89 skb->data,
90 skb->len,
91 DMA_FROM_DEVICE);
92 skbdesc->flags |= SKBDESC_DMA_MAPPED_RX;
93 }
94
239c249d
GW
95 return skb;
96}
30caa6e3 97
c4da0048 98void rt2x00queue_map_txskb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
30caa6e3 99{
c4da0048
GW
100 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
101
3ee54a07
ID
102 /*
103 * If device has requested headroom, we should make sure that
104 * is also mapped to the DMA so it can be used for transfering
105 * additional descriptor information to the hardware.
106 */
107 skb_push(skb, rt2x00dev->hw->extra_tx_headroom);
108
109 skbdesc->skb_dma =
110 dma_map_single(rt2x00dev->dev, skb->data, skb->len, DMA_TO_DEVICE);
111
112 /*
113 * Restore data pointer to original location again.
114 */
115 skb_pull(skb, rt2x00dev->hw->extra_tx_headroom);
116
c4da0048
GW
117 skbdesc->flags |= SKBDESC_DMA_MAPPED_TX;
118}
119EXPORT_SYMBOL_GPL(rt2x00queue_map_txskb);
120
121void rt2x00queue_unmap_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
122{
123 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
124
125 if (skbdesc->flags & SKBDESC_DMA_MAPPED_RX) {
126 dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma, skb->len,
127 DMA_FROM_DEVICE);
128 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_RX;
129 }
130
131 if (skbdesc->flags & SKBDESC_DMA_MAPPED_TX) {
3ee54a07
ID
132 /*
133 * Add headroom to the skb length, it has been removed
134 * by the driver, but it was actually mapped to DMA.
135 */
136 dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma,
137 skb->len + rt2x00dev->hw->extra_tx_headroom,
c4da0048
GW
138 DMA_TO_DEVICE);
139 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_TX;
140 }
141}
c4da0048
GW
142
143void rt2x00queue_free_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
144{
9a613195
ID
145 if (!skb)
146 return;
147
61243d8e 148 rt2x00queue_unmap_skb(rt2x00dev, skb);
30caa6e3
GW
149 dev_kfree_skb_any(skb);
150}
239c249d 151
daee6c09 152void rt2x00queue_align_frame(struct sk_buff *skb)
9f166171 153{
9f166171 154 unsigned int frame_length = skb->len;
daee6c09 155 unsigned int align = ALIGN_SIZE(skb, 0);
9f166171
ID
156
157 if (!align)
158 return;
159
daee6c09
ID
160 skb_push(skb, align);
161 memmove(skb->data, skb->data + align, frame_length);
162 skb_trim(skb, frame_length);
163}
164
95d69aa0 165void rt2x00queue_align_payload(struct sk_buff *skb, unsigned int header_length)
daee6c09
ID
166{
167 unsigned int frame_length = skb->len;
95d69aa0 168 unsigned int align = ALIGN_SIZE(skb, header_length);
daee6c09
ID
169
170 if (!align)
171 return;
172
173 skb_push(skb, align);
174 memmove(skb->data, skb->data + align, frame_length);
175 skb_trim(skb, frame_length);
176}
177
178void rt2x00queue_insert_l2pad(struct sk_buff *skb, unsigned int header_length)
179{
180 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
181 unsigned int frame_length = skb->len;
182 unsigned int header_align = ALIGN_SIZE(skb, 0);
183 unsigned int payload_align = ALIGN_SIZE(skb, header_length);
184 unsigned int l2pad = 4 - (payload_align - header_align);
185
186 if (header_align == payload_align) {
187 /*
188 * Both header and payload must be moved the same
189 * amount of bytes to align them properly. This means
190 * we don't use the L2 padding but just move the entire
191 * frame.
192 */
193 rt2x00queue_align_frame(skb);
194 } else if (!payload_align) {
195 /*
196 * Simple L2 padding, only the header needs to be moved,
197 * the payload is already properly aligned.
198 */
199 skb_push(skb, header_align);
200 memmove(skb->data, skb->data + header_align, frame_length);
201 skbdesc->flags |= SKBDESC_L2_PADDED;
9f166171 202 } else {
daee6c09
ID
203 /*
204 *
205 * Complicated L2 padding, both header and payload need
206 * to be moved. By default we only move to the start
207 * of the buffer, so our header alignment needs to be
208 * increased if there is not enough room for the header
209 * to be moved.
210 */
211 if (payload_align > header_align)
212 header_align += 4;
213
214 skb_push(skb, header_align);
215 memmove(skb->data, skb->data + header_align, header_length);
216 memmove(skb->data + header_length + l2pad,
217 skb->data + header_length + l2pad + header_align,
218 frame_length - header_length);
219 skbdesc->flags |= SKBDESC_L2_PADDED;
9f166171
ID
220 }
221}
222
daee6c09
ID
223void rt2x00queue_remove_l2pad(struct sk_buff *skb, unsigned int header_length)
224{
225 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
226 unsigned int l2pad = 4 - (header_length & 3);
227
228 if (!l2pad || (skbdesc->flags & SKBDESC_L2_PADDED))
229 return;
230
231 memmove(skb->data + l2pad, skb->data, header_length);
232 skb_pull(skb, l2pad);
233}
234
7b40982e
ID
235static void rt2x00queue_create_tx_descriptor_seq(struct queue_entry *entry,
236 struct txentry_desc *txdesc)
237{
238 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
239 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
240 struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
241 unsigned long irqflags;
242
243 if (!(tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) ||
244 unlikely(!tx_info->control.vif))
245 return;
246
247 /*
248 * Hardware should insert sequence counter.
249 * FIXME: We insert a software sequence counter first for
250 * hardware that doesn't support hardware sequence counting.
251 *
252 * This is wrong because beacons are not getting sequence
253 * numbers assigned properly.
254 *
255 * A secondary problem exists for drivers that cannot toggle
256 * sequence counting per-frame, since those will override the
257 * sequence counter given by mac80211.
258 */
259 spin_lock_irqsave(&intf->seqlock, irqflags);
260
261 if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags))
262 intf->seqno += 0x10;
263 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
264 hdr->seq_ctrl |= cpu_to_le16(intf->seqno);
265
266 spin_unlock_irqrestore(&intf->seqlock, irqflags);
267
268 __set_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags);
269}
270
271static void rt2x00queue_create_tx_descriptor_plcp(struct queue_entry *entry,
272 struct txentry_desc *txdesc,
273 const struct rt2x00_rate *hwrate)
274{
275 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
276 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
277 struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0];
278 unsigned int data_length;
279 unsigned int duration;
280 unsigned int residual;
281
282 /* Data length + CRC + Crypto overhead (IV/EIV/ICV/MIC) */
283 data_length = entry->skb->len + 4;
284 data_length += rt2x00crypto_tx_overhead(rt2x00dev, entry->skb);
285
286 /*
287 * PLCP setup
288 * Length calculation depends on OFDM/CCK rate.
289 */
290 txdesc->signal = hwrate->plcp;
291 txdesc->service = 0x04;
292
293 if (hwrate->flags & DEV_RATE_OFDM) {
294 txdesc->length_high = (data_length >> 6) & 0x3f;
295 txdesc->length_low = data_length & 0x3f;
296 } else {
297 /*
298 * Convert length to microseconds.
299 */
300 residual = GET_DURATION_RES(data_length, hwrate->bitrate);
301 duration = GET_DURATION(data_length, hwrate->bitrate);
302
303 if (residual != 0) {
304 duration++;
305
306 /*
307 * Check if we need to set the Length Extension
308 */
309 if (hwrate->bitrate == 110 && residual <= 30)
310 txdesc->service |= 0x80;
311 }
312
313 txdesc->length_high = (duration >> 8) & 0xff;
314 txdesc->length_low = duration & 0xff;
315
316 /*
317 * When preamble is enabled we should set the
318 * preamble bit for the signal.
319 */
320 if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
321 txdesc->signal |= 0x08;
322 }
323}
324
bd88a781
ID
325static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry,
326 struct txentry_desc *txdesc)
7050ec82 327{
2e92e6f2 328 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
e039fa4a 329 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
7050ec82 330 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
2e92e6f2 331 struct ieee80211_rate *rate =
e039fa4a 332 ieee80211_get_tx_rate(rt2x00dev->hw, tx_info);
7050ec82 333 const struct rt2x00_rate *hwrate;
7050ec82
ID
334
335 memset(txdesc, 0, sizeof(*txdesc));
336
337 /*
338 * Initialize information from queue
339 */
340 txdesc->queue = entry->queue->qid;
341 txdesc->cw_min = entry->queue->cw_min;
342 txdesc->cw_max = entry->queue->cw_max;
343 txdesc->aifs = entry->queue->aifs;
344
9f166171
ID
345 /*
346 * Header and alignment information.
347 */
348 txdesc->header_length = ieee80211_get_hdrlen_from_skb(entry->skb);
349 txdesc->l2pad = ALIGN_SIZE(entry->skb, txdesc->header_length);
350
7050ec82
ID
351 /*
352 * Check whether this frame is to be acked.
353 */
e039fa4a 354 if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK))
7050ec82
ID
355 __set_bit(ENTRY_TXD_ACK, &txdesc->flags);
356
357 /*
358 * Check if this is a RTS/CTS frame
359 */
ac104462
ID
360 if (ieee80211_is_rts(hdr->frame_control) ||
361 ieee80211_is_cts(hdr->frame_control)) {
7050ec82 362 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
ac104462 363 if (ieee80211_is_rts(hdr->frame_control))
7050ec82 364 __set_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags);
e039fa4a 365 else
7050ec82 366 __set_bit(ENTRY_TXD_CTS_FRAME, &txdesc->flags);
e039fa4a 367 if (tx_info->control.rts_cts_rate_idx >= 0)
2e92e6f2 368 rate =
e039fa4a 369 ieee80211_get_rts_cts_rate(rt2x00dev->hw, tx_info);
7050ec82
ID
370 }
371
372 /*
373 * Determine retry information.
374 */
e6a9854b 375 txdesc->retry_limit = tx_info->control.rates[0].count - 1;
42c82857 376 if (txdesc->retry_limit >= rt2x00dev->long_retry)
7050ec82
ID
377 __set_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags);
378
379 /*
380 * Check if more fragments are pending
381 */
267e8987
ID
382 if (ieee80211_has_morefrags(hdr->frame_control) ||
383 (tx_info->flags & IEEE80211_TX_CTL_MORE_FRAMES)) {
7050ec82
ID
384 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
385 __set_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags);
386 }
387
388 /*
389 * Beacons and probe responses require the tsf timestamp
390 * to be inserted into the frame.
391 */
ac104462
ID
392 if (ieee80211_is_beacon(hdr->frame_control) ||
393 ieee80211_is_probe_resp(hdr->frame_control))
7050ec82
ID
394 __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags);
395
396 /*
397 * Determine with what IFS priority this frame should be send.
398 * Set ifs to IFS_SIFS when the this is not the first fragment,
399 * or this fragment came after RTS/CTS.
400 */
7b40982e
ID
401 if ((tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) &&
402 !test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)) {
7050ec82
ID
403 __set_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags);
404 txdesc->ifs = IFS_BACKOFF;
7b40982e 405 } else
7050ec82 406 txdesc->ifs = IFS_SIFS;
7050ec82 407
076f9582
ID
408 /*
409 * Determine rate modulation.
410 */
7050ec82 411 hwrate = rt2x00_get_rate(rate->hw_value);
076f9582 412 txdesc->rate_mode = RATE_MODE_CCK;
7b40982e 413 if (hwrate->flags & DEV_RATE_OFDM)
076f9582 414 txdesc->rate_mode = RATE_MODE_OFDM;
7050ec82 415
7b40982e
ID
416 /*
417 * Apply TX descriptor handling by components
418 */
419 rt2x00crypto_create_tx_descriptor(entry, txdesc);
35f00cfc 420 rt2x00ht_create_tx_descriptor(entry, txdesc, hwrate);
7b40982e
ID
421 rt2x00queue_create_tx_descriptor_seq(entry, txdesc);
422 rt2x00queue_create_tx_descriptor_plcp(entry, txdesc, hwrate);
7050ec82 423}
7050ec82 424
bd88a781
ID
425static void rt2x00queue_write_tx_descriptor(struct queue_entry *entry,
426 struct txentry_desc *txdesc)
7050ec82 427{
b869767b
ID
428 struct data_queue *queue = entry->queue;
429 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
7050ec82
ID
430
431 rt2x00dev->ops->lib->write_tx_desc(rt2x00dev, entry->skb, txdesc);
432
433 /*
434 * All processing on the frame has been completed, this means
435 * it is now ready to be dumped to userspace through debugfs.
436 */
437 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_TX, entry->skb);
438
439 /*
b869767b
ID
440 * Check if we need to kick the queue, there are however a few rules
441 * 1) Don't kick beacon queue
442 * 2) Don't kick unless this is the last in frame in a burst.
443 * When the burst flag is set, this frame is always followed
444 * by another frame which in some way are related to eachother.
445 * This is true for fragments, RTS or CTS-to-self frames.
446 * 3) Rule 2 can be broken when the available entries
447 * in the queue are less then a certain threshold.
7050ec82 448 */
b869767b
ID
449 if (entry->queue->qid == QID_BEACON)
450 return;
451
452 if (rt2x00queue_threshold(queue) ||
453 !test_bit(ENTRY_TXD_BURST, &txdesc->flags))
454 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, queue->qid);
7050ec82 455}
7050ec82 456
7351c6bd
JB
457int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
458 bool local)
6db3786a 459{
e6a9854b 460 struct ieee80211_tx_info *tx_info;
6db3786a
ID
461 struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX);
462 struct txentry_desc txdesc;
d74f5ba4 463 struct skb_frame_desc *skbdesc;
e6a9854b 464 u8 rate_idx, rate_flags;
6db3786a
ID
465
466 if (unlikely(rt2x00queue_full(queue)))
0e3de998 467 return -ENOBUFS;
6db3786a 468
0262ab0d 469 if (test_and_set_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags)) {
6db3786a
ID
470 ERROR(queue->rt2x00dev,
471 "Arrived at non-free entry in the non-full queue %d.\n"
472 "Please file bug report to %s.\n",
473 queue->qid, DRV_PROJECT);
474 return -EINVAL;
475 }
476
477 /*
478 * Copy all TX descriptor information into txdesc,
479 * after that we are free to use the skb->cb array
480 * for our information.
481 */
482 entry->skb = skb;
483 rt2x00queue_create_tx_descriptor(entry, &txdesc);
484
d74f5ba4 485 /*
e6a9854b 486 * All information is retrieved from the skb->cb array,
2bb057d0 487 * now we should claim ownership of the driver part of that
e6a9854b 488 * array, preserving the bitrate index and flags.
d74f5ba4 489 */
e6a9854b
JB
490 tx_info = IEEE80211_SKB_CB(skb);
491 rate_idx = tx_info->control.rates[0].idx;
492 rate_flags = tx_info->control.rates[0].flags;
0e3de998 493 skbdesc = get_skb_frame_desc(skb);
d74f5ba4
ID
494 memset(skbdesc, 0, sizeof(*skbdesc));
495 skbdesc->entry = entry;
e6a9854b
JB
496 skbdesc->tx_rate_idx = rate_idx;
497 skbdesc->tx_rate_flags = rate_flags;
d74f5ba4 498
7351c6bd
JB
499 if (local)
500 skbdesc->flags |= SKBDESC_NOT_MAC80211;
501
2bb057d0
ID
502 /*
503 * When hardware encryption is supported, and this frame
504 * is to be encrypted, we should strip the IV/EIV data from
505 * the frame so we can provide it to the driver seperately.
506 */
507 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc.flags) &&
dddfb478 508 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc.flags)) {
3f787bd6 509 if (test_bit(DRIVER_REQUIRE_COPY_IV, &queue->rt2x00dev->flags))
9eb4e21e 510 rt2x00crypto_tx_copy_iv(skb, &txdesc);
dddfb478 511 else
9eb4e21e 512 rt2x00crypto_tx_remove_iv(skb, &txdesc);
dddfb478 513 }
2bb057d0 514
93354cbb
ID
515 /*
516 * When DMA allocation is required we should guarentee to the
517 * driver that the DMA is aligned to a 4-byte boundary.
93354cbb
ID
518 * However some drivers require L2 padding to pad the payload
519 * rather then the header. This could be a requirement for
520 * PCI and USB devices, while header alignment only is valid
521 * for PCI devices.
522 */
9f166171 523 if (test_bit(DRIVER_REQUIRE_L2PAD, &queue->rt2x00dev->flags))
daee6c09 524 rt2x00queue_insert_l2pad(entry->skb, txdesc.header_length);
93354cbb 525 else if (test_bit(DRIVER_REQUIRE_DMA, &queue->rt2x00dev->flags))
daee6c09 526 rt2x00queue_align_frame(entry->skb);
9f166171 527
2bb057d0
ID
528 /*
529 * It could be possible that the queue was corrupted and this
0e3de998
ID
530 * call failed. Since we always return NETDEV_TX_OK to mac80211,
531 * this frame will simply be dropped.
2bb057d0 532 */
6db3786a 533 if (unlikely(queue->rt2x00dev->ops->lib->write_tx_data(entry))) {
0262ab0d 534 clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
2bb057d0 535 entry->skb = NULL;
0e3de998 536 return -EIO;
6db3786a
ID
537 }
538
d74f5ba4
ID
539 if (test_bit(DRIVER_REQUIRE_DMA, &queue->rt2x00dev->flags))
540 rt2x00queue_map_txskb(queue->rt2x00dev, skb);
541
0262ab0d 542 set_bit(ENTRY_DATA_PENDING, &entry->flags);
6db3786a
ID
543
544 rt2x00queue_index_inc(queue, Q_INDEX);
545 rt2x00queue_write_tx_descriptor(entry, &txdesc);
546
547 return 0;
548}
549
bd88a781 550int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev,
a2c9b652
ID
551 struct ieee80211_vif *vif,
552 const bool enable_beacon)
bd88a781
ID
553{
554 struct rt2x00_intf *intf = vif_to_intf(vif);
555 struct skb_frame_desc *skbdesc;
556 struct txentry_desc txdesc;
557 __le32 desc[16];
558
559 if (unlikely(!intf->beacon))
560 return -ENOBUFS;
561
17512dc3
IP
562 mutex_lock(&intf->beacon_skb_mutex);
563
564 /*
565 * Clean up the beacon skb.
566 */
567 rt2x00queue_free_skb(rt2x00dev, intf->beacon->skb);
568 intf->beacon->skb = NULL;
569
a2c9b652
ID
570 if (!enable_beacon) {
571 rt2x00dev->ops->lib->kill_tx_queue(rt2x00dev, QID_BEACON);
17512dc3 572 mutex_unlock(&intf->beacon_skb_mutex);
a2c9b652
ID
573 return 0;
574 }
575
bd88a781 576 intf->beacon->skb = ieee80211_beacon_get(rt2x00dev->hw, vif);
17512dc3
IP
577 if (!intf->beacon->skb) {
578 mutex_unlock(&intf->beacon_skb_mutex);
bd88a781 579 return -ENOMEM;
17512dc3 580 }
bd88a781
ID
581
582 /*
583 * Copy all TX descriptor information into txdesc,
584 * after that we are free to use the skb->cb array
585 * for our information.
586 */
587 rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc);
588
589 /*
590 * For the descriptor we use a local array from where the
591 * driver can move it to the correct location required for
592 * the hardware.
593 */
594 memset(desc, 0, sizeof(desc));
595
596 /*
597 * Fill in skb descriptor
598 */
599 skbdesc = get_skb_frame_desc(intf->beacon->skb);
600 memset(skbdesc, 0, sizeof(*skbdesc));
601 skbdesc->desc = desc;
602 skbdesc->desc_len = intf->beacon->queue->desc_size;
603 skbdesc->entry = intf->beacon;
604
605 /*
606 * Write TX descriptor into reserved room in front of the beacon.
607 */
608 rt2x00queue_write_tx_descriptor(intf->beacon, &txdesc);
609
610 /*
611 * Send beacon to hardware.
612 * Also enable beacon generation, which might have been disabled
613 * by the driver during the config_beacon() callback function.
614 */
615 rt2x00dev->ops->lib->write_beacon(intf->beacon);
616 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, QID_BEACON);
617
17512dc3
IP
618 mutex_unlock(&intf->beacon_skb_mutex);
619
bd88a781
ID
620 return 0;
621}
622
181d6902 623struct data_queue *rt2x00queue_get_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 624 const enum data_queue_qid queue)
181d6902
ID
625{
626 int atim = test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
627
a2c9b652
ID
628 if (queue == QID_RX)
629 return rt2x00dev->rx;
630
61448f88 631 if (queue < rt2x00dev->ops->tx_queues && rt2x00dev->tx)
181d6902
ID
632 return &rt2x00dev->tx[queue];
633
634 if (!rt2x00dev->bcn)
635 return NULL;
636
e58c6aca 637 if (queue == QID_BEACON)
181d6902 638 return &rt2x00dev->bcn[0];
e58c6aca 639 else if (queue == QID_ATIM && atim)
181d6902
ID
640 return &rt2x00dev->bcn[1];
641
642 return NULL;
643}
644EXPORT_SYMBOL_GPL(rt2x00queue_get_queue);
645
646struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue,
647 enum queue_index index)
648{
649 struct queue_entry *entry;
5f46c4d0 650 unsigned long irqflags;
181d6902
ID
651
652 if (unlikely(index >= Q_INDEX_MAX)) {
653 ERROR(queue->rt2x00dev,
654 "Entry requested from invalid index type (%d)\n", index);
655 return NULL;
656 }
657
5f46c4d0 658 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
659
660 entry = &queue->entries[queue->index[index]];
661
5f46c4d0 662 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902
ID
663
664 return entry;
665}
666EXPORT_SYMBOL_GPL(rt2x00queue_get_entry);
667
668void rt2x00queue_index_inc(struct data_queue *queue, enum queue_index index)
669{
5f46c4d0
ID
670 unsigned long irqflags;
671
181d6902
ID
672 if (unlikely(index >= Q_INDEX_MAX)) {
673 ERROR(queue->rt2x00dev,
674 "Index change on invalid index type (%d)\n", index);
675 return;
676 }
677
5f46c4d0 678 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
679
680 queue->index[index]++;
681 if (queue->index[index] >= queue->limit)
682 queue->index[index] = 0;
683
10b6b801
ID
684 if (index == Q_INDEX) {
685 queue->length++;
686 } else if (index == Q_INDEX_DONE) {
687 queue->length--;
55887511 688 queue->count++;
10b6b801 689 }
181d6902 690
5f46c4d0 691 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902 692}
181d6902
ID
693
694static void rt2x00queue_reset(struct data_queue *queue)
695{
5f46c4d0
ID
696 unsigned long irqflags;
697
698 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
699
700 queue->count = 0;
701 queue->length = 0;
702 memset(queue->index, 0, sizeof(queue->index));
703
5f46c4d0 704 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902
ID
705}
706
a2c9b652
ID
707void rt2x00queue_stop_queues(struct rt2x00_dev *rt2x00dev)
708{
709 struct data_queue *queue;
710
711 txall_queue_for_each(rt2x00dev, queue)
712 rt2x00dev->ops->lib->kill_tx_queue(rt2x00dev, queue->qid);
713}
714
798b7adb 715void rt2x00queue_init_queues(struct rt2x00_dev *rt2x00dev)
181d6902
ID
716{
717 struct data_queue *queue;
718 unsigned int i;
719
798b7adb 720 queue_for_each(rt2x00dev, queue) {
181d6902
ID
721 rt2x00queue_reset(queue);
722
9c0ab712
ID
723 for (i = 0; i < queue->limit; i++) {
724 queue->entries[i].flags = 0;
725
798b7adb 726 rt2x00dev->ops->lib->clear_entry(&queue->entries[i]);
9c0ab712 727 }
181d6902
ID
728 }
729}
730
731static int rt2x00queue_alloc_entries(struct data_queue *queue,
732 const struct data_queue_desc *qdesc)
733{
734 struct queue_entry *entries;
735 unsigned int entry_size;
736 unsigned int i;
737
738 rt2x00queue_reset(queue);
739
740 queue->limit = qdesc->entry_num;
b869767b 741 queue->threshold = DIV_ROUND_UP(qdesc->entry_num, 10);
181d6902
ID
742 queue->data_size = qdesc->data_size;
743 queue->desc_size = qdesc->desc_size;
744
745 /*
746 * Allocate all queue entries.
747 */
748 entry_size = sizeof(*entries) + qdesc->priv_size;
749 entries = kzalloc(queue->limit * entry_size, GFP_KERNEL);
750 if (!entries)
751 return -ENOMEM;
752
753#define QUEUE_ENTRY_PRIV_OFFSET(__base, __index, __limit, __esize, __psize) \
231be4e9
AB
754 ( ((char *)(__base)) + ((__limit) * (__esize)) + \
755 ((__index) * (__psize)) )
181d6902
ID
756
757 for (i = 0; i < queue->limit; i++) {
758 entries[i].flags = 0;
759 entries[i].queue = queue;
760 entries[i].skb = NULL;
761 entries[i].entry_idx = i;
762 entries[i].priv_data =
763 QUEUE_ENTRY_PRIV_OFFSET(entries, i, queue->limit,
764 sizeof(*entries), qdesc->priv_size);
765 }
766
767#undef QUEUE_ENTRY_PRIV_OFFSET
768
769 queue->entries = entries;
770
771 return 0;
772}
773
c4da0048
GW
774static void rt2x00queue_free_skbs(struct rt2x00_dev *rt2x00dev,
775 struct data_queue *queue)
30caa6e3
GW
776{
777 unsigned int i;
778
779 if (!queue->entries)
780 return;
781
782 for (i = 0; i < queue->limit; i++) {
783 if (queue->entries[i].skb)
c4da0048 784 rt2x00queue_free_skb(rt2x00dev, queue->entries[i].skb);
30caa6e3
GW
785 }
786}
787
c4da0048
GW
788static int rt2x00queue_alloc_rxskbs(struct rt2x00_dev *rt2x00dev,
789 struct data_queue *queue)
30caa6e3
GW
790{
791 unsigned int i;
792 struct sk_buff *skb;
793
794 for (i = 0; i < queue->limit; i++) {
c4da0048 795 skb = rt2x00queue_alloc_rxskb(rt2x00dev, &queue->entries[i]);
30caa6e3 796 if (!skb)
61243d8e 797 return -ENOMEM;
30caa6e3
GW
798 queue->entries[i].skb = skb;
799 }
800
801 return 0;
30caa6e3
GW
802}
803
181d6902
ID
804int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev)
805{
806 struct data_queue *queue;
807 int status;
808
181d6902
ID
809 status = rt2x00queue_alloc_entries(rt2x00dev->rx, rt2x00dev->ops->rx);
810 if (status)
811 goto exit;
812
813 tx_queue_for_each(rt2x00dev, queue) {
814 status = rt2x00queue_alloc_entries(queue, rt2x00dev->ops->tx);
815 if (status)
816 goto exit;
817 }
818
819 status = rt2x00queue_alloc_entries(rt2x00dev->bcn, rt2x00dev->ops->bcn);
820 if (status)
821 goto exit;
822
30caa6e3
GW
823 if (test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags)) {
824 status = rt2x00queue_alloc_entries(&rt2x00dev->bcn[1],
825 rt2x00dev->ops->atim);
826 if (status)
827 goto exit;
828 }
181d6902 829
c4da0048 830 status = rt2x00queue_alloc_rxskbs(rt2x00dev, rt2x00dev->rx);
181d6902
ID
831 if (status)
832 goto exit;
833
834 return 0;
835
836exit:
837 ERROR(rt2x00dev, "Queue entries allocation failed.\n");
838
839 rt2x00queue_uninitialize(rt2x00dev);
840
841 return status;
842}
843
844void rt2x00queue_uninitialize(struct rt2x00_dev *rt2x00dev)
845{
846 struct data_queue *queue;
847
c4da0048 848 rt2x00queue_free_skbs(rt2x00dev, rt2x00dev->rx);
30caa6e3 849
181d6902
ID
850 queue_for_each(rt2x00dev, queue) {
851 kfree(queue->entries);
852 queue->entries = NULL;
853 }
854}
855
8f539276
ID
856static void rt2x00queue_init(struct rt2x00_dev *rt2x00dev,
857 struct data_queue *queue, enum data_queue_qid qid)
858{
859 spin_lock_init(&queue->lock);
860
861 queue->rt2x00dev = rt2x00dev;
862 queue->qid = qid;
2af0a570 863 queue->txop = 0;
8f539276
ID
864 queue->aifs = 2;
865 queue->cw_min = 5;
866 queue->cw_max = 10;
867}
868
181d6902
ID
869int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
870{
871 struct data_queue *queue;
872 enum data_queue_qid qid;
873 unsigned int req_atim =
874 !!test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
875
876 /*
877 * We need the following queues:
878 * RX: 1
61448f88 879 * TX: ops->tx_queues
181d6902
ID
880 * Beacon: 1
881 * Atim: 1 (if required)
882 */
61448f88 883 rt2x00dev->data_queues = 2 + rt2x00dev->ops->tx_queues + req_atim;
181d6902
ID
884
885 queue = kzalloc(rt2x00dev->data_queues * sizeof(*queue), GFP_KERNEL);
886 if (!queue) {
887 ERROR(rt2x00dev, "Queue allocation failed.\n");
888 return -ENOMEM;
889 }
890
891 /*
892 * Initialize pointers
893 */
894 rt2x00dev->rx = queue;
895 rt2x00dev->tx = &queue[1];
61448f88 896 rt2x00dev->bcn = &queue[1 + rt2x00dev->ops->tx_queues];
181d6902
ID
897
898 /*
899 * Initialize queue parameters.
900 * RX: qid = QID_RX
901 * TX: qid = QID_AC_BE + index
902 * TX: cw_min: 2^5 = 32.
903 * TX: cw_max: 2^10 = 1024.
565a019a
ID
904 * BCN: qid = QID_BEACON
905 * ATIM: qid = QID_ATIM
181d6902 906 */
8f539276 907 rt2x00queue_init(rt2x00dev, rt2x00dev->rx, QID_RX);
181d6902 908
8f539276
ID
909 qid = QID_AC_BE;
910 tx_queue_for_each(rt2x00dev, queue)
911 rt2x00queue_init(rt2x00dev, queue, qid++);
181d6902 912
565a019a 913 rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[0], QID_BEACON);
181d6902 914 if (req_atim)
565a019a 915 rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[1], QID_ATIM);
181d6902
ID
916
917 return 0;
918}
919
920void rt2x00queue_free(struct rt2x00_dev *rt2x00dev)
921{
922 kfree(rt2x00dev->rx);
923 rt2x00dev->rx = NULL;
924 rt2x00dev->tx = NULL;
925 rt2x00dev->bcn = NULL;
926}
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