rt2x00: Use IEEE80211_TX_CTL_MORE_FRAMES flag
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2x00queue.c
CommitLineData
181d6902 1/*
4e54c711 2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
181d6902
ID
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2x00lib
23 Abstract: rt2x00 queue specific routines.
24 */
25
26#include <linux/kernel.h>
27#include <linux/module.h>
c4da0048 28#include <linux/dma-mapping.h>
181d6902
ID
29
30#include "rt2x00.h"
31#include "rt2x00lib.h"
32
c4da0048
GW
33struct sk_buff *rt2x00queue_alloc_rxskb(struct rt2x00_dev *rt2x00dev,
34 struct queue_entry *entry)
239c249d 35{
c4da0048
GW
36 struct sk_buff *skb;
37 struct skb_frame_desc *skbdesc;
2bb057d0
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38 unsigned int frame_size;
39 unsigned int head_size = 0;
40 unsigned int tail_size = 0;
239c249d
GW
41
42 /*
43 * The frame size includes descriptor size, because the
44 * hardware directly receive the frame into the skbuffer.
45 */
c4da0048 46 frame_size = entry->queue->data_size + entry->queue->desc_size;
239c249d
GW
47
48 /*
ff352391
ID
49 * The payload should be aligned to a 4-byte boundary,
50 * this means we need at least 3 bytes for moving the frame
51 * into the correct offset.
239c249d 52 */
2bb057d0
ID
53 head_size = 4;
54
55 /*
56 * For IV/EIV/ICV assembly we must make sure there is
57 * at least 8 bytes bytes available in headroom for IV/EIV
9c3444d3 58 * and 8 bytes for ICV data as tailroon.
2bb057d0 59 */
2bb057d0
ID
60 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
61 head_size += 8;
9c3444d3 62 tail_size += 8;
2bb057d0 63 }
239c249d
GW
64
65 /*
66 * Allocate skbuffer.
67 */
2bb057d0 68 skb = dev_alloc_skb(frame_size + head_size + tail_size);
239c249d
GW
69 if (!skb)
70 return NULL;
71
2bb057d0
ID
72 /*
73 * Make sure we not have a frame with the requested bytes
74 * available in the head and tail.
75 */
76 skb_reserve(skb, head_size);
239c249d
GW
77 skb_put(skb, frame_size);
78
c4da0048
GW
79 /*
80 * Populate skbdesc.
81 */
82 skbdesc = get_skb_frame_desc(skb);
83 memset(skbdesc, 0, sizeof(*skbdesc));
84 skbdesc->entry = entry;
85
86 if (test_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags)) {
87 skbdesc->skb_dma = dma_map_single(rt2x00dev->dev,
88 skb->data,
89 skb->len,
90 DMA_FROM_DEVICE);
91 skbdesc->flags |= SKBDESC_DMA_MAPPED_RX;
92 }
93
239c249d
GW
94 return skb;
95}
30caa6e3 96
c4da0048 97void rt2x00queue_map_txskb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
30caa6e3 98{
c4da0048
GW
99 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
100
3ee54a07
ID
101 /*
102 * If device has requested headroom, we should make sure that
103 * is also mapped to the DMA so it can be used for transfering
104 * additional descriptor information to the hardware.
105 */
106 skb_push(skb, rt2x00dev->hw->extra_tx_headroom);
107
108 skbdesc->skb_dma =
109 dma_map_single(rt2x00dev->dev, skb->data, skb->len, DMA_TO_DEVICE);
110
111 /*
112 * Restore data pointer to original location again.
113 */
114 skb_pull(skb, rt2x00dev->hw->extra_tx_headroom);
115
c4da0048
GW
116 skbdesc->flags |= SKBDESC_DMA_MAPPED_TX;
117}
118EXPORT_SYMBOL_GPL(rt2x00queue_map_txskb);
119
120void rt2x00queue_unmap_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
121{
122 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
123
124 if (skbdesc->flags & SKBDESC_DMA_MAPPED_RX) {
125 dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma, skb->len,
126 DMA_FROM_DEVICE);
127 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_RX;
128 }
129
130 if (skbdesc->flags & SKBDESC_DMA_MAPPED_TX) {
3ee54a07
ID
131 /*
132 * Add headroom to the skb length, it has been removed
133 * by the driver, but it was actually mapped to DMA.
134 */
135 dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma,
136 skb->len + rt2x00dev->hw->extra_tx_headroom,
c4da0048
GW
137 DMA_TO_DEVICE);
138 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_TX;
139 }
140}
c4da0048
GW
141
142void rt2x00queue_free_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
143{
9a613195
ID
144 if (!skb)
145 return;
146
61243d8e 147 rt2x00queue_unmap_skb(rt2x00dev, skb);
30caa6e3
GW
148 dev_kfree_skb_any(skb);
149}
239c249d 150
9f166171
ID
151void rt2x00queue_payload_align(struct sk_buff *skb,
152 bool l2pad, unsigned int header_length)
153{
154 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
155 unsigned int frame_length = skb->len;
156 unsigned int align = ALIGN_SIZE(skb, header_length);
157
158 if (!align)
159 return;
160
161 if (l2pad) {
162 if (skbdesc->flags & SKBDESC_L2_PADDED) {
163 /* Remove L2 padding */
164 memmove(skb->data + align, skb->data, header_length);
165 skb_pull(skb, align);
166 skbdesc->flags &= ~SKBDESC_L2_PADDED;
167 } else {
168 /* Add L2 padding */
169 skb_push(skb, align);
170 memmove(skb->data, skb->data + align, header_length);
171 skbdesc->flags |= SKBDESC_L2_PADDED;
172 }
173 } else {
174 /* Generic payload alignment to 4-byte boundary */
175 skb_push(skb, align);
176 memmove(skb->data, skb->data + align, frame_length);
177 }
178}
179
7b40982e
ID
180static void rt2x00queue_create_tx_descriptor_seq(struct queue_entry *entry,
181 struct txentry_desc *txdesc)
182{
183 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
184 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
185 struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
186 unsigned long irqflags;
187
188 if (!(tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) ||
189 unlikely(!tx_info->control.vif))
190 return;
191
192 /*
193 * Hardware should insert sequence counter.
194 * FIXME: We insert a software sequence counter first for
195 * hardware that doesn't support hardware sequence counting.
196 *
197 * This is wrong because beacons are not getting sequence
198 * numbers assigned properly.
199 *
200 * A secondary problem exists for drivers that cannot toggle
201 * sequence counting per-frame, since those will override the
202 * sequence counter given by mac80211.
203 */
204 spin_lock_irqsave(&intf->seqlock, irqflags);
205
206 if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags))
207 intf->seqno += 0x10;
208 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
209 hdr->seq_ctrl |= cpu_to_le16(intf->seqno);
210
211 spin_unlock_irqrestore(&intf->seqlock, irqflags);
212
213 __set_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags);
214}
215
216static void rt2x00queue_create_tx_descriptor_plcp(struct queue_entry *entry,
217 struct txentry_desc *txdesc,
218 const struct rt2x00_rate *hwrate)
219{
220 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
221 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
222 struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0];
223 unsigned int data_length;
224 unsigned int duration;
225 unsigned int residual;
226
227 /* Data length + CRC + Crypto overhead (IV/EIV/ICV/MIC) */
228 data_length = entry->skb->len + 4;
229 data_length += rt2x00crypto_tx_overhead(rt2x00dev, entry->skb);
230
231 /*
232 * PLCP setup
233 * Length calculation depends on OFDM/CCK rate.
234 */
235 txdesc->signal = hwrate->plcp;
236 txdesc->service = 0x04;
237
238 if (hwrate->flags & DEV_RATE_OFDM) {
239 txdesc->length_high = (data_length >> 6) & 0x3f;
240 txdesc->length_low = data_length & 0x3f;
241 } else {
242 /*
243 * Convert length to microseconds.
244 */
245 residual = GET_DURATION_RES(data_length, hwrate->bitrate);
246 duration = GET_DURATION(data_length, hwrate->bitrate);
247
248 if (residual != 0) {
249 duration++;
250
251 /*
252 * Check if we need to set the Length Extension
253 */
254 if (hwrate->bitrate == 110 && residual <= 30)
255 txdesc->service |= 0x80;
256 }
257
258 txdesc->length_high = (duration >> 8) & 0xff;
259 txdesc->length_low = duration & 0xff;
260
261 /*
262 * When preamble is enabled we should set the
263 * preamble bit for the signal.
264 */
265 if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
266 txdesc->signal |= 0x08;
267 }
268}
269
bd88a781
ID
270static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry,
271 struct txentry_desc *txdesc)
7050ec82 272{
2e92e6f2 273 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
e039fa4a 274 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
7050ec82 275 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
2e92e6f2 276 struct ieee80211_rate *rate =
e039fa4a 277 ieee80211_get_tx_rate(rt2x00dev->hw, tx_info);
7050ec82 278 const struct rt2x00_rate *hwrate;
7050ec82
ID
279
280 memset(txdesc, 0, sizeof(*txdesc));
281
282 /*
283 * Initialize information from queue
284 */
285 txdesc->queue = entry->queue->qid;
286 txdesc->cw_min = entry->queue->cw_min;
287 txdesc->cw_max = entry->queue->cw_max;
288 txdesc->aifs = entry->queue->aifs;
289
9f166171
ID
290 /*
291 * Header and alignment information.
292 */
293 txdesc->header_length = ieee80211_get_hdrlen_from_skb(entry->skb);
294 txdesc->l2pad = ALIGN_SIZE(entry->skb, txdesc->header_length);
295
7050ec82
ID
296 /*
297 * Check whether this frame is to be acked.
298 */
e039fa4a 299 if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK))
7050ec82
ID
300 __set_bit(ENTRY_TXD_ACK, &txdesc->flags);
301
302 /*
303 * Check if this is a RTS/CTS frame
304 */
ac104462
ID
305 if (ieee80211_is_rts(hdr->frame_control) ||
306 ieee80211_is_cts(hdr->frame_control)) {
7050ec82 307 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
ac104462 308 if (ieee80211_is_rts(hdr->frame_control))
7050ec82 309 __set_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags);
e039fa4a 310 else
7050ec82 311 __set_bit(ENTRY_TXD_CTS_FRAME, &txdesc->flags);
e039fa4a 312 if (tx_info->control.rts_cts_rate_idx >= 0)
2e92e6f2 313 rate =
e039fa4a 314 ieee80211_get_rts_cts_rate(rt2x00dev->hw, tx_info);
7050ec82
ID
315 }
316
317 /*
318 * Determine retry information.
319 */
e6a9854b 320 txdesc->retry_limit = tx_info->control.rates[0].count - 1;
42c82857 321 if (txdesc->retry_limit >= rt2x00dev->long_retry)
7050ec82
ID
322 __set_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags);
323
324 /*
325 * Check if more fragments are pending
326 */
267e8987
ID
327 if (ieee80211_has_morefrags(hdr->frame_control) ||
328 (tx_info->flags & IEEE80211_TX_CTL_MORE_FRAMES)) {
7050ec82
ID
329 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
330 __set_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags);
331 }
332
333 /*
334 * Beacons and probe responses require the tsf timestamp
335 * to be inserted into the frame.
336 */
ac104462
ID
337 if (ieee80211_is_beacon(hdr->frame_control) ||
338 ieee80211_is_probe_resp(hdr->frame_control))
7050ec82
ID
339 __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags);
340
341 /*
342 * Determine with what IFS priority this frame should be send.
343 * Set ifs to IFS_SIFS when the this is not the first fragment,
344 * or this fragment came after RTS/CTS.
345 */
7b40982e
ID
346 if ((tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) &&
347 !test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)) {
7050ec82
ID
348 __set_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags);
349 txdesc->ifs = IFS_BACKOFF;
7b40982e 350 } else
7050ec82 351 txdesc->ifs = IFS_SIFS;
7050ec82 352
076f9582
ID
353 /*
354 * Determine rate modulation.
355 */
7050ec82 356 hwrate = rt2x00_get_rate(rate->hw_value);
076f9582 357 txdesc->rate_mode = RATE_MODE_CCK;
7b40982e 358 if (hwrate->flags & DEV_RATE_OFDM)
076f9582 359 txdesc->rate_mode = RATE_MODE_OFDM;
7050ec82 360
7b40982e
ID
361 /*
362 * Apply TX descriptor handling by components
363 */
364 rt2x00crypto_create_tx_descriptor(entry, txdesc);
35f00cfc 365 rt2x00ht_create_tx_descriptor(entry, txdesc, hwrate);
7b40982e
ID
366 rt2x00queue_create_tx_descriptor_seq(entry, txdesc);
367 rt2x00queue_create_tx_descriptor_plcp(entry, txdesc, hwrate);
7050ec82 368}
7050ec82 369
bd88a781
ID
370static void rt2x00queue_write_tx_descriptor(struct queue_entry *entry,
371 struct txentry_desc *txdesc)
7050ec82 372{
b869767b
ID
373 struct data_queue *queue = entry->queue;
374 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
7050ec82
ID
375
376 rt2x00dev->ops->lib->write_tx_desc(rt2x00dev, entry->skb, txdesc);
377
378 /*
379 * All processing on the frame has been completed, this means
380 * it is now ready to be dumped to userspace through debugfs.
381 */
382 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_TX, entry->skb);
383
384 /*
b869767b
ID
385 * Check if we need to kick the queue, there are however a few rules
386 * 1) Don't kick beacon queue
387 * 2) Don't kick unless this is the last in frame in a burst.
388 * When the burst flag is set, this frame is always followed
389 * by another frame which in some way are related to eachother.
390 * This is true for fragments, RTS or CTS-to-self frames.
391 * 3) Rule 2 can be broken when the available entries
392 * in the queue are less then a certain threshold.
7050ec82 393 */
b869767b
ID
394 if (entry->queue->qid == QID_BEACON)
395 return;
396
397 if (rt2x00queue_threshold(queue) ||
398 !test_bit(ENTRY_TXD_BURST, &txdesc->flags))
399 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, queue->qid);
7050ec82 400}
7050ec82 401
6db3786a
ID
402int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb)
403{
e6a9854b 404 struct ieee80211_tx_info *tx_info;
6db3786a
ID
405 struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX);
406 struct txentry_desc txdesc;
d74f5ba4 407 struct skb_frame_desc *skbdesc;
e6a9854b 408 u8 rate_idx, rate_flags;
6db3786a
ID
409
410 if (unlikely(rt2x00queue_full(queue)))
0e3de998 411 return -ENOBUFS;
6db3786a 412
0262ab0d 413 if (test_and_set_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags)) {
6db3786a
ID
414 ERROR(queue->rt2x00dev,
415 "Arrived at non-free entry in the non-full queue %d.\n"
416 "Please file bug report to %s.\n",
417 queue->qid, DRV_PROJECT);
418 return -EINVAL;
419 }
420
421 /*
422 * Copy all TX descriptor information into txdesc,
423 * after that we are free to use the skb->cb array
424 * for our information.
425 */
426 entry->skb = skb;
427 rt2x00queue_create_tx_descriptor(entry, &txdesc);
428
d74f5ba4 429 /*
e6a9854b 430 * All information is retrieved from the skb->cb array,
2bb057d0 431 * now we should claim ownership of the driver part of that
e6a9854b 432 * array, preserving the bitrate index and flags.
d74f5ba4 433 */
e6a9854b
JB
434 tx_info = IEEE80211_SKB_CB(skb);
435 rate_idx = tx_info->control.rates[0].idx;
436 rate_flags = tx_info->control.rates[0].flags;
0e3de998 437 skbdesc = get_skb_frame_desc(skb);
d74f5ba4
ID
438 memset(skbdesc, 0, sizeof(*skbdesc));
439 skbdesc->entry = entry;
e6a9854b
JB
440 skbdesc->tx_rate_idx = rate_idx;
441 skbdesc->tx_rate_flags = rate_flags;
d74f5ba4 442
2bb057d0
ID
443 /*
444 * When hardware encryption is supported, and this frame
445 * is to be encrypted, we should strip the IV/EIV data from
446 * the frame so we can provide it to the driver seperately.
447 */
448 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc.flags) &&
dddfb478 449 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc.flags)) {
3f787bd6 450 if (test_bit(DRIVER_REQUIRE_COPY_IV, &queue->rt2x00dev->flags))
9eb4e21e 451 rt2x00crypto_tx_copy_iv(skb, &txdesc);
dddfb478 452 else
9eb4e21e 453 rt2x00crypto_tx_remove_iv(skb, &txdesc);
dddfb478 454 }
2bb057d0 455
9f166171
ID
456 if (test_bit(DRIVER_REQUIRE_L2PAD, &queue->rt2x00dev->flags))
457 rt2x00queue_payload_align(entry->skb, true,
458 txdesc.header_length);
459
2bb057d0
ID
460 /*
461 * It could be possible that the queue was corrupted and this
0e3de998
ID
462 * call failed. Since we always return NETDEV_TX_OK to mac80211,
463 * this frame will simply be dropped.
2bb057d0 464 */
6db3786a 465 if (unlikely(queue->rt2x00dev->ops->lib->write_tx_data(entry))) {
0262ab0d 466 clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
2bb057d0 467 entry->skb = NULL;
0e3de998 468 return -EIO;
6db3786a
ID
469 }
470
d74f5ba4
ID
471 if (test_bit(DRIVER_REQUIRE_DMA, &queue->rt2x00dev->flags))
472 rt2x00queue_map_txskb(queue->rt2x00dev, skb);
473
0262ab0d 474 set_bit(ENTRY_DATA_PENDING, &entry->flags);
6db3786a
ID
475
476 rt2x00queue_index_inc(queue, Q_INDEX);
477 rt2x00queue_write_tx_descriptor(entry, &txdesc);
478
479 return 0;
480}
481
bd88a781 482int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev,
a2c9b652
ID
483 struct ieee80211_vif *vif,
484 const bool enable_beacon)
bd88a781
ID
485{
486 struct rt2x00_intf *intf = vif_to_intf(vif);
487 struct skb_frame_desc *skbdesc;
488 struct txentry_desc txdesc;
489 __le32 desc[16];
490
491 if (unlikely(!intf->beacon))
492 return -ENOBUFS;
493
a2c9b652
ID
494 if (!enable_beacon) {
495 rt2x00dev->ops->lib->kill_tx_queue(rt2x00dev, QID_BEACON);
496 return 0;
497 }
498
bd88a781
ID
499 intf->beacon->skb = ieee80211_beacon_get(rt2x00dev->hw, vif);
500 if (!intf->beacon->skb)
501 return -ENOMEM;
502
503 /*
504 * Copy all TX descriptor information into txdesc,
505 * after that we are free to use the skb->cb array
506 * for our information.
507 */
508 rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc);
509
510 /*
511 * For the descriptor we use a local array from where the
512 * driver can move it to the correct location required for
513 * the hardware.
514 */
515 memset(desc, 0, sizeof(desc));
516
517 /*
518 * Fill in skb descriptor
519 */
520 skbdesc = get_skb_frame_desc(intf->beacon->skb);
521 memset(skbdesc, 0, sizeof(*skbdesc));
522 skbdesc->desc = desc;
523 skbdesc->desc_len = intf->beacon->queue->desc_size;
524 skbdesc->entry = intf->beacon;
525
526 /*
527 * Write TX descriptor into reserved room in front of the beacon.
528 */
529 rt2x00queue_write_tx_descriptor(intf->beacon, &txdesc);
530
531 /*
532 * Send beacon to hardware.
533 * Also enable beacon generation, which might have been disabled
534 * by the driver during the config_beacon() callback function.
535 */
536 rt2x00dev->ops->lib->write_beacon(intf->beacon);
537 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, QID_BEACON);
538
539 return 0;
540}
541
181d6902 542struct data_queue *rt2x00queue_get_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 543 const enum data_queue_qid queue)
181d6902
ID
544{
545 int atim = test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
546
a2c9b652
ID
547 if (queue == QID_RX)
548 return rt2x00dev->rx;
549
61448f88 550 if (queue < rt2x00dev->ops->tx_queues && rt2x00dev->tx)
181d6902
ID
551 return &rt2x00dev->tx[queue];
552
553 if (!rt2x00dev->bcn)
554 return NULL;
555
e58c6aca 556 if (queue == QID_BEACON)
181d6902 557 return &rt2x00dev->bcn[0];
e58c6aca 558 else if (queue == QID_ATIM && atim)
181d6902
ID
559 return &rt2x00dev->bcn[1];
560
561 return NULL;
562}
563EXPORT_SYMBOL_GPL(rt2x00queue_get_queue);
564
565struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue,
566 enum queue_index index)
567{
568 struct queue_entry *entry;
5f46c4d0 569 unsigned long irqflags;
181d6902
ID
570
571 if (unlikely(index >= Q_INDEX_MAX)) {
572 ERROR(queue->rt2x00dev,
573 "Entry requested from invalid index type (%d)\n", index);
574 return NULL;
575 }
576
5f46c4d0 577 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
578
579 entry = &queue->entries[queue->index[index]];
580
5f46c4d0 581 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902
ID
582
583 return entry;
584}
585EXPORT_SYMBOL_GPL(rt2x00queue_get_entry);
586
587void rt2x00queue_index_inc(struct data_queue *queue, enum queue_index index)
588{
5f46c4d0
ID
589 unsigned long irqflags;
590
181d6902
ID
591 if (unlikely(index >= Q_INDEX_MAX)) {
592 ERROR(queue->rt2x00dev,
593 "Index change on invalid index type (%d)\n", index);
594 return;
595 }
596
5f46c4d0 597 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
598
599 queue->index[index]++;
600 if (queue->index[index] >= queue->limit)
601 queue->index[index] = 0;
602
10b6b801
ID
603 if (index == Q_INDEX) {
604 queue->length++;
605 } else if (index == Q_INDEX_DONE) {
606 queue->length--;
55887511 607 queue->count++;
10b6b801 608 }
181d6902 609
5f46c4d0 610 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902 611}
181d6902
ID
612
613static void rt2x00queue_reset(struct data_queue *queue)
614{
5f46c4d0
ID
615 unsigned long irqflags;
616
617 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
618
619 queue->count = 0;
620 queue->length = 0;
621 memset(queue->index, 0, sizeof(queue->index));
622
5f46c4d0 623 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902
ID
624}
625
a2c9b652
ID
626void rt2x00queue_stop_queues(struct rt2x00_dev *rt2x00dev)
627{
628 struct data_queue *queue;
629
630 txall_queue_for_each(rt2x00dev, queue)
631 rt2x00dev->ops->lib->kill_tx_queue(rt2x00dev, queue->qid);
632}
633
798b7adb 634void rt2x00queue_init_queues(struct rt2x00_dev *rt2x00dev)
181d6902
ID
635{
636 struct data_queue *queue;
637 unsigned int i;
638
798b7adb 639 queue_for_each(rt2x00dev, queue) {
181d6902
ID
640 rt2x00queue_reset(queue);
641
9c0ab712
ID
642 for (i = 0; i < queue->limit; i++) {
643 queue->entries[i].flags = 0;
644
798b7adb 645 rt2x00dev->ops->lib->clear_entry(&queue->entries[i]);
9c0ab712 646 }
181d6902
ID
647 }
648}
649
650static int rt2x00queue_alloc_entries(struct data_queue *queue,
651 const struct data_queue_desc *qdesc)
652{
653 struct queue_entry *entries;
654 unsigned int entry_size;
655 unsigned int i;
656
657 rt2x00queue_reset(queue);
658
659 queue->limit = qdesc->entry_num;
b869767b 660 queue->threshold = DIV_ROUND_UP(qdesc->entry_num, 10);
181d6902
ID
661 queue->data_size = qdesc->data_size;
662 queue->desc_size = qdesc->desc_size;
663
664 /*
665 * Allocate all queue entries.
666 */
667 entry_size = sizeof(*entries) + qdesc->priv_size;
668 entries = kzalloc(queue->limit * entry_size, GFP_KERNEL);
669 if (!entries)
670 return -ENOMEM;
671
672#define QUEUE_ENTRY_PRIV_OFFSET(__base, __index, __limit, __esize, __psize) \
231be4e9
AB
673 ( ((char *)(__base)) + ((__limit) * (__esize)) + \
674 ((__index) * (__psize)) )
181d6902
ID
675
676 for (i = 0; i < queue->limit; i++) {
677 entries[i].flags = 0;
678 entries[i].queue = queue;
679 entries[i].skb = NULL;
680 entries[i].entry_idx = i;
681 entries[i].priv_data =
682 QUEUE_ENTRY_PRIV_OFFSET(entries, i, queue->limit,
683 sizeof(*entries), qdesc->priv_size);
684 }
685
686#undef QUEUE_ENTRY_PRIV_OFFSET
687
688 queue->entries = entries;
689
690 return 0;
691}
692
c4da0048
GW
693static void rt2x00queue_free_skbs(struct rt2x00_dev *rt2x00dev,
694 struct data_queue *queue)
30caa6e3
GW
695{
696 unsigned int i;
697
698 if (!queue->entries)
699 return;
700
701 for (i = 0; i < queue->limit; i++) {
702 if (queue->entries[i].skb)
c4da0048 703 rt2x00queue_free_skb(rt2x00dev, queue->entries[i].skb);
30caa6e3
GW
704 }
705}
706
c4da0048
GW
707static int rt2x00queue_alloc_rxskbs(struct rt2x00_dev *rt2x00dev,
708 struct data_queue *queue)
30caa6e3
GW
709{
710 unsigned int i;
711 struct sk_buff *skb;
712
713 for (i = 0; i < queue->limit; i++) {
c4da0048 714 skb = rt2x00queue_alloc_rxskb(rt2x00dev, &queue->entries[i]);
30caa6e3 715 if (!skb)
61243d8e 716 return -ENOMEM;
30caa6e3
GW
717 queue->entries[i].skb = skb;
718 }
719
720 return 0;
30caa6e3
GW
721}
722
181d6902
ID
723int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev)
724{
725 struct data_queue *queue;
726 int status;
727
181d6902
ID
728 status = rt2x00queue_alloc_entries(rt2x00dev->rx, rt2x00dev->ops->rx);
729 if (status)
730 goto exit;
731
732 tx_queue_for_each(rt2x00dev, queue) {
733 status = rt2x00queue_alloc_entries(queue, rt2x00dev->ops->tx);
734 if (status)
735 goto exit;
736 }
737
738 status = rt2x00queue_alloc_entries(rt2x00dev->bcn, rt2x00dev->ops->bcn);
739 if (status)
740 goto exit;
741
30caa6e3
GW
742 if (test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags)) {
743 status = rt2x00queue_alloc_entries(&rt2x00dev->bcn[1],
744 rt2x00dev->ops->atim);
745 if (status)
746 goto exit;
747 }
181d6902 748
c4da0048 749 status = rt2x00queue_alloc_rxskbs(rt2x00dev, rt2x00dev->rx);
181d6902
ID
750 if (status)
751 goto exit;
752
753 return 0;
754
755exit:
756 ERROR(rt2x00dev, "Queue entries allocation failed.\n");
757
758 rt2x00queue_uninitialize(rt2x00dev);
759
760 return status;
761}
762
763void rt2x00queue_uninitialize(struct rt2x00_dev *rt2x00dev)
764{
765 struct data_queue *queue;
766
c4da0048 767 rt2x00queue_free_skbs(rt2x00dev, rt2x00dev->rx);
30caa6e3 768
181d6902
ID
769 queue_for_each(rt2x00dev, queue) {
770 kfree(queue->entries);
771 queue->entries = NULL;
772 }
773}
774
8f539276
ID
775static void rt2x00queue_init(struct rt2x00_dev *rt2x00dev,
776 struct data_queue *queue, enum data_queue_qid qid)
777{
778 spin_lock_init(&queue->lock);
779
780 queue->rt2x00dev = rt2x00dev;
781 queue->qid = qid;
2af0a570 782 queue->txop = 0;
8f539276
ID
783 queue->aifs = 2;
784 queue->cw_min = 5;
785 queue->cw_max = 10;
786}
787
181d6902
ID
788int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
789{
790 struct data_queue *queue;
791 enum data_queue_qid qid;
792 unsigned int req_atim =
793 !!test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
794
795 /*
796 * We need the following queues:
797 * RX: 1
61448f88 798 * TX: ops->tx_queues
181d6902
ID
799 * Beacon: 1
800 * Atim: 1 (if required)
801 */
61448f88 802 rt2x00dev->data_queues = 2 + rt2x00dev->ops->tx_queues + req_atim;
181d6902
ID
803
804 queue = kzalloc(rt2x00dev->data_queues * sizeof(*queue), GFP_KERNEL);
805 if (!queue) {
806 ERROR(rt2x00dev, "Queue allocation failed.\n");
807 return -ENOMEM;
808 }
809
810 /*
811 * Initialize pointers
812 */
813 rt2x00dev->rx = queue;
814 rt2x00dev->tx = &queue[1];
61448f88 815 rt2x00dev->bcn = &queue[1 + rt2x00dev->ops->tx_queues];
181d6902
ID
816
817 /*
818 * Initialize queue parameters.
819 * RX: qid = QID_RX
820 * TX: qid = QID_AC_BE + index
821 * TX: cw_min: 2^5 = 32.
822 * TX: cw_max: 2^10 = 1024.
565a019a
ID
823 * BCN: qid = QID_BEACON
824 * ATIM: qid = QID_ATIM
181d6902 825 */
8f539276 826 rt2x00queue_init(rt2x00dev, rt2x00dev->rx, QID_RX);
181d6902 827
8f539276
ID
828 qid = QID_AC_BE;
829 tx_queue_for_each(rt2x00dev, queue)
830 rt2x00queue_init(rt2x00dev, queue, qid++);
181d6902 831
565a019a 832 rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[0], QID_BEACON);
181d6902 833 if (req_atim)
565a019a 834 rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[1], QID_ATIM);
181d6902
ID
835
836 return 0;
837}
838
839void rt2x00queue_free(struct rt2x00_dev *rt2x00dev)
840{
841 kfree(rt2x00dev->rx);
842 rt2x00dev->rx = NULL;
843 rt2x00dev->tx = NULL;
844 rt2x00dev->bcn = NULL;
845}
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