Commit | Line | Data |
---|---|---|
181d6902 ID |
1 | /* |
2 | Copyright (C) 2004 - 2008 rt2x00 SourceForge Project | |
3 | <http://rt2x00.serialmonkey.com> | |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the | |
17 | Free Software Foundation, Inc., | |
18 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | */ | |
20 | ||
21 | /* | |
22 | Module: rt2x00lib | |
23 | Abstract: rt2x00 queue specific routines. | |
24 | */ | |
25 | ||
26 | #include <linux/kernel.h> | |
27 | #include <linux/module.h> | |
c4da0048 | 28 | #include <linux/dma-mapping.h> |
181d6902 ID |
29 | |
30 | #include "rt2x00.h" | |
31 | #include "rt2x00lib.h" | |
32 | ||
c4da0048 GW |
33 | struct sk_buff *rt2x00queue_alloc_rxskb(struct rt2x00_dev *rt2x00dev, |
34 | struct queue_entry *entry) | |
239c249d | 35 | { |
239c249d GW |
36 | unsigned int frame_size; |
37 | unsigned int reserved_size; | |
c4da0048 GW |
38 | struct sk_buff *skb; |
39 | struct skb_frame_desc *skbdesc; | |
239c249d GW |
40 | |
41 | /* | |
42 | * The frame size includes descriptor size, because the | |
43 | * hardware directly receive the frame into the skbuffer. | |
44 | */ | |
c4da0048 | 45 | frame_size = entry->queue->data_size + entry->queue->desc_size; |
239c249d GW |
46 | |
47 | /* | |
ff352391 ID |
48 | * The payload should be aligned to a 4-byte boundary, |
49 | * this means we need at least 3 bytes for moving the frame | |
50 | * into the correct offset. | |
239c249d | 51 | */ |
ff352391 | 52 | reserved_size = 4; |
239c249d GW |
53 | |
54 | /* | |
55 | * Allocate skbuffer. | |
56 | */ | |
57 | skb = dev_alloc_skb(frame_size + reserved_size); | |
58 | if (!skb) | |
59 | return NULL; | |
60 | ||
61 | skb_reserve(skb, reserved_size); | |
62 | skb_put(skb, frame_size); | |
63 | ||
c4da0048 GW |
64 | /* |
65 | * Populate skbdesc. | |
66 | */ | |
67 | skbdesc = get_skb_frame_desc(skb); | |
68 | memset(skbdesc, 0, sizeof(*skbdesc)); | |
69 | skbdesc->entry = entry; | |
70 | ||
71 | if (test_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags)) { | |
72 | skbdesc->skb_dma = dma_map_single(rt2x00dev->dev, | |
73 | skb->data, | |
74 | skb->len, | |
75 | DMA_FROM_DEVICE); | |
76 | skbdesc->flags |= SKBDESC_DMA_MAPPED_RX; | |
77 | } | |
78 | ||
239c249d GW |
79 | return skb; |
80 | } | |
30caa6e3 | 81 | |
c4da0048 | 82 | void rt2x00queue_map_txskb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb) |
30caa6e3 | 83 | { |
c4da0048 GW |
84 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); |
85 | ||
86 | skbdesc->skb_dma = dma_map_single(rt2x00dev->dev, skb->data, skb->len, | |
87 | DMA_TO_DEVICE); | |
88 | skbdesc->flags |= SKBDESC_DMA_MAPPED_TX; | |
89 | } | |
90 | EXPORT_SYMBOL_GPL(rt2x00queue_map_txskb); | |
91 | ||
92 | void rt2x00queue_unmap_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb) | |
93 | { | |
94 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); | |
95 | ||
96 | if (skbdesc->flags & SKBDESC_DMA_MAPPED_RX) { | |
97 | dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma, skb->len, | |
98 | DMA_FROM_DEVICE); | |
99 | skbdesc->flags &= ~SKBDESC_DMA_MAPPED_RX; | |
100 | } | |
101 | ||
102 | if (skbdesc->flags & SKBDESC_DMA_MAPPED_TX) { | |
103 | dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma, skb->len, | |
104 | DMA_TO_DEVICE); | |
105 | skbdesc->flags &= ~SKBDESC_DMA_MAPPED_TX; | |
106 | } | |
107 | } | |
c4da0048 GW |
108 | |
109 | void rt2x00queue_free_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb) | |
110 | { | |
61243d8e | 111 | rt2x00queue_unmap_skb(rt2x00dev, skb); |
30caa6e3 GW |
112 | dev_kfree_skb_any(skb); |
113 | } | |
239c249d | 114 | |
7050ec82 | 115 | void rt2x00queue_create_tx_descriptor(struct queue_entry *entry, |
e039fa4a | 116 | struct txentry_desc *txdesc) |
7050ec82 | 117 | { |
2e92e6f2 | 118 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; |
e039fa4a | 119 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb); |
7050ec82 | 120 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data; |
2e92e6f2 | 121 | struct ieee80211_rate *rate = |
e039fa4a | 122 | ieee80211_get_tx_rate(rt2x00dev->hw, tx_info); |
7050ec82 ID |
123 | const struct rt2x00_rate *hwrate; |
124 | unsigned int data_length; | |
125 | unsigned int duration; | |
126 | unsigned int residual; | |
7050ec82 ID |
127 | |
128 | memset(txdesc, 0, sizeof(*txdesc)); | |
129 | ||
130 | /* | |
131 | * Initialize information from queue | |
132 | */ | |
133 | txdesc->queue = entry->queue->qid; | |
134 | txdesc->cw_min = entry->queue->cw_min; | |
135 | txdesc->cw_max = entry->queue->cw_max; | |
136 | txdesc->aifs = entry->queue->aifs; | |
137 | ||
138 | /* Data length should be extended with 4 bytes for CRC */ | |
139 | data_length = entry->skb->len + 4; | |
140 | ||
7050ec82 ID |
141 | /* |
142 | * Check whether this frame is to be acked. | |
143 | */ | |
e039fa4a | 144 | if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK)) |
7050ec82 ID |
145 | __set_bit(ENTRY_TXD_ACK, &txdesc->flags); |
146 | ||
147 | /* | |
148 | * Check if this is a RTS/CTS frame | |
149 | */ | |
ac104462 ID |
150 | if (ieee80211_is_rts(hdr->frame_control) || |
151 | ieee80211_is_cts(hdr->frame_control)) { | |
7050ec82 | 152 | __set_bit(ENTRY_TXD_BURST, &txdesc->flags); |
ac104462 | 153 | if (ieee80211_is_rts(hdr->frame_control)) |
7050ec82 | 154 | __set_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags); |
e039fa4a | 155 | else |
7050ec82 | 156 | __set_bit(ENTRY_TXD_CTS_FRAME, &txdesc->flags); |
e039fa4a | 157 | if (tx_info->control.rts_cts_rate_idx >= 0) |
2e92e6f2 | 158 | rate = |
e039fa4a | 159 | ieee80211_get_rts_cts_rate(rt2x00dev->hw, tx_info); |
7050ec82 ID |
160 | } |
161 | ||
162 | /* | |
163 | * Determine retry information. | |
164 | */ | |
e039fa4a JB |
165 | txdesc->retry_limit = tx_info->control.retry_limit; |
166 | if (tx_info->flags & IEEE80211_TX_CTL_LONG_RETRY_LIMIT) | |
7050ec82 ID |
167 | __set_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags); |
168 | ||
169 | /* | |
170 | * Check if more fragments are pending | |
171 | */ | |
8b7b1e05 | 172 | if (ieee80211_has_morefrags(hdr->frame_control)) { |
7050ec82 ID |
173 | __set_bit(ENTRY_TXD_BURST, &txdesc->flags); |
174 | __set_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags); | |
175 | } | |
176 | ||
177 | /* | |
178 | * Beacons and probe responses require the tsf timestamp | |
179 | * to be inserted into the frame. | |
180 | */ | |
ac104462 ID |
181 | if (ieee80211_is_beacon(hdr->frame_control) || |
182 | ieee80211_is_probe_resp(hdr->frame_control)) | |
7050ec82 ID |
183 | __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags); |
184 | ||
185 | /* | |
186 | * Determine with what IFS priority this frame should be send. | |
187 | * Set ifs to IFS_SIFS when the this is not the first fragment, | |
188 | * or this fragment came after RTS/CTS. | |
189 | */ | |
190 | if (test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)) { | |
191 | txdesc->ifs = IFS_SIFS; | |
e039fa4a | 192 | } else if (tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) { |
7050ec82 ID |
193 | __set_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags); |
194 | txdesc->ifs = IFS_BACKOFF; | |
195 | } else { | |
196 | txdesc->ifs = IFS_SIFS; | |
197 | } | |
198 | ||
199 | /* | |
200 | * PLCP setup | |
201 | * Length calculation depends on OFDM/CCK rate. | |
202 | */ | |
203 | hwrate = rt2x00_get_rate(rate->hw_value); | |
204 | txdesc->signal = hwrate->plcp; | |
205 | txdesc->service = 0x04; | |
206 | ||
207 | if (hwrate->flags & DEV_RATE_OFDM) { | |
208 | __set_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags); | |
209 | ||
210 | txdesc->length_high = (data_length >> 6) & 0x3f; | |
211 | txdesc->length_low = data_length & 0x3f; | |
212 | } else { | |
213 | /* | |
214 | * Convert length to microseconds. | |
215 | */ | |
216 | residual = get_duration_res(data_length, hwrate->bitrate); | |
217 | duration = get_duration(data_length, hwrate->bitrate); | |
218 | ||
219 | if (residual != 0) { | |
220 | duration++; | |
221 | ||
222 | /* | |
223 | * Check if we need to set the Length Extension | |
224 | */ | |
225 | if (hwrate->bitrate == 110 && residual <= 30) | |
226 | txdesc->service |= 0x80; | |
227 | } | |
228 | ||
229 | txdesc->length_high = (duration >> 8) & 0xff; | |
230 | txdesc->length_low = duration & 0xff; | |
231 | ||
232 | /* | |
233 | * When preamble is enabled we should set the | |
234 | * preamble bit for the signal. | |
235 | */ | |
236 | if (rt2x00_get_rate_preamble(rate->hw_value)) | |
237 | txdesc->signal |= 0x08; | |
238 | } | |
239 | } | |
240 | EXPORT_SYMBOL_GPL(rt2x00queue_create_tx_descriptor); | |
241 | ||
242 | void rt2x00queue_write_tx_descriptor(struct queue_entry *entry, | |
243 | struct txentry_desc *txdesc) | |
244 | { | |
b869767b ID |
245 | struct data_queue *queue = entry->queue; |
246 | struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; | |
7050ec82 ID |
247 | |
248 | rt2x00dev->ops->lib->write_tx_desc(rt2x00dev, entry->skb, txdesc); | |
249 | ||
250 | /* | |
251 | * All processing on the frame has been completed, this means | |
252 | * it is now ready to be dumped to userspace through debugfs. | |
253 | */ | |
254 | rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_TX, entry->skb); | |
255 | ||
256 | /* | |
b869767b ID |
257 | * Check if we need to kick the queue, there are however a few rules |
258 | * 1) Don't kick beacon queue | |
259 | * 2) Don't kick unless this is the last in frame in a burst. | |
260 | * When the burst flag is set, this frame is always followed | |
261 | * by another frame which in some way are related to eachother. | |
262 | * This is true for fragments, RTS or CTS-to-self frames. | |
263 | * 3) Rule 2 can be broken when the available entries | |
264 | * in the queue are less then a certain threshold. | |
7050ec82 | 265 | */ |
b869767b ID |
266 | if (entry->queue->qid == QID_BEACON) |
267 | return; | |
268 | ||
269 | if (rt2x00queue_threshold(queue) || | |
270 | !test_bit(ENTRY_TXD_BURST, &txdesc->flags)) | |
271 | rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, queue->qid); | |
7050ec82 ID |
272 | } |
273 | EXPORT_SYMBOL_GPL(rt2x00queue_write_tx_descriptor); | |
274 | ||
6db3786a ID |
275 | int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb) |
276 | { | |
277 | struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX); | |
278 | struct txentry_desc txdesc; | |
d74f5ba4 | 279 | struct skb_frame_desc *skbdesc; |
6db3786a ID |
280 | |
281 | if (unlikely(rt2x00queue_full(queue))) | |
282 | return -EINVAL; | |
283 | ||
284 | if (__test_and_set_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags)) { | |
285 | ERROR(queue->rt2x00dev, | |
286 | "Arrived at non-free entry in the non-full queue %d.\n" | |
287 | "Please file bug report to %s.\n", | |
288 | queue->qid, DRV_PROJECT); | |
289 | return -EINVAL; | |
290 | } | |
291 | ||
292 | /* | |
293 | * Copy all TX descriptor information into txdesc, | |
294 | * after that we are free to use the skb->cb array | |
295 | * for our information. | |
296 | */ | |
297 | entry->skb = skb; | |
298 | rt2x00queue_create_tx_descriptor(entry, &txdesc); | |
299 | ||
d74f5ba4 ID |
300 | /* |
301 | * skb->cb array is now ours and we are free to use it. | |
302 | */ | |
303 | skbdesc = get_skb_frame_desc(entry->skb); | |
304 | memset(skbdesc, 0, sizeof(*skbdesc)); | |
305 | skbdesc->entry = entry; | |
306 | ||
6db3786a ID |
307 | if (unlikely(queue->rt2x00dev->ops->lib->write_tx_data(entry))) { |
308 | __clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags); | |
309 | return -EIO; | |
310 | } | |
311 | ||
d74f5ba4 ID |
312 | if (test_bit(DRIVER_REQUIRE_DMA, &queue->rt2x00dev->flags)) |
313 | rt2x00queue_map_txskb(queue->rt2x00dev, skb); | |
314 | ||
6db3786a ID |
315 | __set_bit(ENTRY_DATA_PENDING, &entry->flags); |
316 | ||
317 | rt2x00queue_index_inc(queue, Q_INDEX); | |
318 | rt2x00queue_write_tx_descriptor(entry, &txdesc); | |
319 | ||
320 | return 0; | |
321 | } | |
322 | ||
181d6902 | 323 | struct data_queue *rt2x00queue_get_queue(struct rt2x00_dev *rt2x00dev, |
e58c6aca | 324 | const enum data_queue_qid queue) |
181d6902 ID |
325 | { |
326 | int atim = test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags); | |
327 | ||
61448f88 | 328 | if (queue < rt2x00dev->ops->tx_queues && rt2x00dev->tx) |
181d6902 ID |
329 | return &rt2x00dev->tx[queue]; |
330 | ||
331 | if (!rt2x00dev->bcn) | |
332 | return NULL; | |
333 | ||
e58c6aca | 334 | if (queue == QID_BEACON) |
181d6902 | 335 | return &rt2x00dev->bcn[0]; |
e58c6aca | 336 | else if (queue == QID_ATIM && atim) |
181d6902 ID |
337 | return &rt2x00dev->bcn[1]; |
338 | ||
339 | return NULL; | |
340 | } | |
341 | EXPORT_SYMBOL_GPL(rt2x00queue_get_queue); | |
342 | ||
343 | struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue, | |
344 | enum queue_index index) | |
345 | { | |
346 | struct queue_entry *entry; | |
5f46c4d0 | 347 | unsigned long irqflags; |
181d6902 ID |
348 | |
349 | if (unlikely(index >= Q_INDEX_MAX)) { | |
350 | ERROR(queue->rt2x00dev, | |
351 | "Entry requested from invalid index type (%d)\n", index); | |
352 | return NULL; | |
353 | } | |
354 | ||
5f46c4d0 | 355 | spin_lock_irqsave(&queue->lock, irqflags); |
181d6902 ID |
356 | |
357 | entry = &queue->entries[queue->index[index]]; | |
358 | ||
5f46c4d0 | 359 | spin_unlock_irqrestore(&queue->lock, irqflags); |
181d6902 ID |
360 | |
361 | return entry; | |
362 | } | |
363 | EXPORT_SYMBOL_GPL(rt2x00queue_get_entry); | |
364 | ||
365 | void rt2x00queue_index_inc(struct data_queue *queue, enum queue_index index) | |
366 | { | |
5f46c4d0 ID |
367 | unsigned long irqflags; |
368 | ||
181d6902 ID |
369 | if (unlikely(index >= Q_INDEX_MAX)) { |
370 | ERROR(queue->rt2x00dev, | |
371 | "Index change on invalid index type (%d)\n", index); | |
372 | return; | |
373 | } | |
374 | ||
5f46c4d0 | 375 | spin_lock_irqsave(&queue->lock, irqflags); |
181d6902 ID |
376 | |
377 | queue->index[index]++; | |
378 | if (queue->index[index] >= queue->limit) | |
379 | queue->index[index] = 0; | |
380 | ||
10b6b801 ID |
381 | if (index == Q_INDEX) { |
382 | queue->length++; | |
383 | } else if (index == Q_INDEX_DONE) { | |
384 | queue->length--; | |
385 | queue->count ++; | |
386 | } | |
181d6902 | 387 | |
5f46c4d0 | 388 | spin_unlock_irqrestore(&queue->lock, irqflags); |
181d6902 | 389 | } |
181d6902 ID |
390 | |
391 | static void rt2x00queue_reset(struct data_queue *queue) | |
392 | { | |
5f46c4d0 ID |
393 | unsigned long irqflags; |
394 | ||
395 | spin_lock_irqsave(&queue->lock, irqflags); | |
181d6902 ID |
396 | |
397 | queue->count = 0; | |
398 | queue->length = 0; | |
399 | memset(queue->index, 0, sizeof(queue->index)); | |
400 | ||
5f46c4d0 | 401 | spin_unlock_irqrestore(&queue->lock, irqflags); |
181d6902 ID |
402 | } |
403 | ||
404 | void rt2x00queue_init_rx(struct rt2x00_dev *rt2x00dev) | |
405 | { | |
406 | struct data_queue *queue = rt2x00dev->rx; | |
407 | unsigned int i; | |
408 | ||
409 | rt2x00queue_reset(queue); | |
410 | ||
411 | if (!rt2x00dev->ops->lib->init_rxentry) | |
412 | return; | |
413 | ||
414 | for (i = 0; i < queue->limit; i++) | |
415 | rt2x00dev->ops->lib->init_rxentry(rt2x00dev, | |
416 | &queue->entries[i]); | |
417 | } | |
418 | ||
419 | void rt2x00queue_init_tx(struct rt2x00_dev *rt2x00dev) | |
420 | { | |
421 | struct data_queue *queue; | |
422 | unsigned int i; | |
423 | ||
424 | txall_queue_for_each(rt2x00dev, queue) { | |
425 | rt2x00queue_reset(queue); | |
426 | ||
427 | if (!rt2x00dev->ops->lib->init_txentry) | |
428 | continue; | |
429 | ||
430 | for (i = 0; i < queue->limit; i++) | |
431 | rt2x00dev->ops->lib->init_txentry(rt2x00dev, | |
432 | &queue->entries[i]); | |
433 | } | |
434 | } | |
435 | ||
436 | static int rt2x00queue_alloc_entries(struct data_queue *queue, | |
437 | const struct data_queue_desc *qdesc) | |
438 | { | |
439 | struct queue_entry *entries; | |
440 | unsigned int entry_size; | |
441 | unsigned int i; | |
442 | ||
443 | rt2x00queue_reset(queue); | |
444 | ||
445 | queue->limit = qdesc->entry_num; | |
b869767b | 446 | queue->threshold = DIV_ROUND_UP(qdesc->entry_num, 10); |
181d6902 ID |
447 | queue->data_size = qdesc->data_size; |
448 | queue->desc_size = qdesc->desc_size; | |
449 | ||
450 | /* | |
451 | * Allocate all queue entries. | |
452 | */ | |
453 | entry_size = sizeof(*entries) + qdesc->priv_size; | |
454 | entries = kzalloc(queue->limit * entry_size, GFP_KERNEL); | |
455 | if (!entries) | |
456 | return -ENOMEM; | |
457 | ||
458 | #define QUEUE_ENTRY_PRIV_OFFSET(__base, __index, __limit, __esize, __psize) \ | |
231be4e9 AB |
459 | ( ((char *)(__base)) + ((__limit) * (__esize)) + \ |
460 | ((__index) * (__psize)) ) | |
181d6902 ID |
461 | |
462 | for (i = 0; i < queue->limit; i++) { | |
463 | entries[i].flags = 0; | |
464 | entries[i].queue = queue; | |
465 | entries[i].skb = NULL; | |
466 | entries[i].entry_idx = i; | |
467 | entries[i].priv_data = | |
468 | QUEUE_ENTRY_PRIV_OFFSET(entries, i, queue->limit, | |
469 | sizeof(*entries), qdesc->priv_size); | |
470 | } | |
471 | ||
472 | #undef QUEUE_ENTRY_PRIV_OFFSET | |
473 | ||
474 | queue->entries = entries; | |
475 | ||
476 | return 0; | |
477 | } | |
478 | ||
c4da0048 GW |
479 | static void rt2x00queue_free_skbs(struct rt2x00_dev *rt2x00dev, |
480 | struct data_queue *queue) | |
30caa6e3 GW |
481 | { |
482 | unsigned int i; | |
483 | ||
484 | if (!queue->entries) | |
485 | return; | |
486 | ||
487 | for (i = 0; i < queue->limit; i++) { | |
488 | if (queue->entries[i].skb) | |
c4da0048 | 489 | rt2x00queue_free_skb(rt2x00dev, queue->entries[i].skb); |
30caa6e3 GW |
490 | } |
491 | } | |
492 | ||
c4da0048 GW |
493 | static int rt2x00queue_alloc_rxskbs(struct rt2x00_dev *rt2x00dev, |
494 | struct data_queue *queue) | |
30caa6e3 GW |
495 | { |
496 | unsigned int i; | |
497 | struct sk_buff *skb; | |
498 | ||
499 | for (i = 0; i < queue->limit; i++) { | |
c4da0048 | 500 | skb = rt2x00queue_alloc_rxskb(rt2x00dev, &queue->entries[i]); |
30caa6e3 | 501 | if (!skb) |
61243d8e | 502 | return -ENOMEM; |
30caa6e3 GW |
503 | queue->entries[i].skb = skb; |
504 | } | |
505 | ||
506 | return 0; | |
30caa6e3 GW |
507 | } |
508 | ||
181d6902 ID |
509 | int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev) |
510 | { | |
511 | struct data_queue *queue; | |
512 | int status; | |
513 | ||
181d6902 ID |
514 | status = rt2x00queue_alloc_entries(rt2x00dev->rx, rt2x00dev->ops->rx); |
515 | if (status) | |
516 | goto exit; | |
517 | ||
518 | tx_queue_for_each(rt2x00dev, queue) { | |
519 | status = rt2x00queue_alloc_entries(queue, rt2x00dev->ops->tx); | |
520 | if (status) | |
521 | goto exit; | |
522 | } | |
523 | ||
524 | status = rt2x00queue_alloc_entries(rt2x00dev->bcn, rt2x00dev->ops->bcn); | |
525 | if (status) | |
526 | goto exit; | |
527 | ||
30caa6e3 GW |
528 | if (test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags)) { |
529 | status = rt2x00queue_alloc_entries(&rt2x00dev->bcn[1], | |
530 | rt2x00dev->ops->atim); | |
531 | if (status) | |
532 | goto exit; | |
533 | } | |
181d6902 | 534 | |
c4da0048 | 535 | status = rt2x00queue_alloc_rxskbs(rt2x00dev, rt2x00dev->rx); |
181d6902 ID |
536 | if (status) |
537 | goto exit; | |
538 | ||
539 | return 0; | |
540 | ||
541 | exit: | |
542 | ERROR(rt2x00dev, "Queue entries allocation failed.\n"); | |
543 | ||
544 | rt2x00queue_uninitialize(rt2x00dev); | |
545 | ||
546 | return status; | |
547 | } | |
548 | ||
549 | void rt2x00queue_uninitialize(struct rt2x00_dev *rt2x00dev) | |
550 | { | |
551 | struct data_queue *queue; | |
552 | ||
c4da0048 | 553 | rt2x00queue_free_skbs(rt2x00dev, rt2x00dev->rx); |
30caa6e3 | 554 | |
181d6902 ID |
555 | queue_for_each(rt2x00dev, queue) { |
556 | kfree(queue->entries); | |
557 | queue->entries = NULL; | |
558 | } | |
559 | } | |
560 | ||
8f539276 ID |
561 | static void rt2x00queue_init(struct rt2x00_dev *rt2x00dev, |
562 | struct data_queue *queue, enum data_queue_qid qid) | |
563 | { | |
564 | spin_lock_init(&queue->lock); | |
565 | ||
566 | queue->rt2x00dev = rt2x00dev; | |
567 | queue->qid = qid; | |
568 | queue->aifs = 2; | |
569 | queue->cw_min = 5; | |
570 | queue->cw_max = 10; | |
571 | } | |
572 | ||
181d6902 ID |
573 | int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev) |
574 | { | |
575 | struct data_queue *queue; | |
576 | enum data_queue_qid qid; | |
577 | unsigned int req_atim = | |
578 | !!test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags); | |
579 | ||
580 | /* | |
581 | * We need the following queues: | |
582 | * RX: 1 | |
61448f88 | 583 | * TX: ops->tx_queues |
181d6902 ID |
584 | * Beacon: 1 |
585 | * Atim: 1 (if required) | |
586 | */ | |
61448f88 | 587 | rt2x00dev->data_queues = 2 + rt2x00dev->ops->tx_queues + req_atim; |
181d6902 ID |
588 | |
589 | queue = kzalloc(rt2x00dev->data_queues * sizeof(*queue), GFP_KERNEL); | |
590 | if (!queue) { | |
591 | ERROR(rt2x00dev, "Queue allocation failed.\n"); | |
592 | return -ENOMEM; | |
593 | } | |
594 | ||
595 | /* | |
596 | * Initialize pointers | |
597 | */ | |
598 | rt2x00dev->rx = queue; | |
599 | rt2x00dev->tx = &queue[1]; | |
61448f88 | 600 | rt2x00dev->bcn = &queue[1 + rt2x00dev->ops->tx_queues]; |
181d6902 ID |
601 | |
602 | /* | |
603 | * Initialize queue parameters. | |
604 | * RX: qid = QID_RX | |
605 | * TX: qid = QID_AC_BE + index | |
606 | * TX: cw_min: 2^5 = 32. | |
607 | * TX: cw_max: 2^10 = 1024. | |
565a019a ID |
608 | * BCN: qid = QID_BEACON |
609 | * ATIM: qid = QID_ATIM | |
181d6902 | 610 | */ |
8f539276 | 611 | rt2x00queue_init(rt2x00dev, rt2x00dev->rx, QID_RX); |
181d6902 | 612 | |
8f539276 ID |
613 | qid = QID_AC_BE; |
614 | tx_queue_for_each(rt2x00dev, queue) | |
615 | rt2x00queue_init(rt2x00dev, queue, qid++); | |
181d6902 | 616 | |
565a019a | 617 | rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[0], QID_BEACON); |
181d6902 | 618 | if (req_atim) |
565a019a | 619 | rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[1], QID_ATIM); |
181d6902 ID |
620 | |
621 | return 0; | |
622 | } | |
623 | ||
624 | void rt2x00queue_free(struct rt2x00_dev *rt2x00dev) | |
625 | { | |
626 | kfree(rt2x00dev->rx); | |
627 | rt2x00dev->rx = NULL; | |
628 | rt2x00dev->tx = NULL; | |
629 | rt2x00dev->bcn = NULL; | |
630 | } |