rt2x00: Optimize unmapping of skbs
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2x00queue.c
CommitLineData
181d6902 1/*
7e613e16
ID
2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2004 - 2009 Gertjan van Wingerde <gwingerde@gmail.com>
181d6902
ID
5 <http://rt2x00.serialmonkey.com>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the
19 Free Software Foundation, Inc.,
20 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22
23/*
24 Module: rt2x00lib
25 Abstract: rt2x00 queue specific routines.
26 */
27
5a0e3ad6 28#include <linux/slab.h>
181d6902
ID
29#include <linux/kernel.h>
30#include <linux/module.h>
c4da0048 31#include <linux/dma-mapping.h>
181d6902
ID
32
33#include "rt2x00.h"
34#include "rt2x00lib.h"
35
c4da0048
GW
36struct sk_buff *rt2x00queue_alloc_rxskb(struct rt2x00_dev *rt2x00dev,
37 struct queue_entry *entry)
239c249d 38{
c4da0048
GW
39 struct sk_buff *skb;
40 struct skb_frame_desc *skbdesc;
2bb057d0
ID
41 unsigned int frame_size;
42 unsigned int head_size = 0;
43 unsigned int tail_size = 0;
239c249d
GW
44
45 /*
46 * The frame size includes descriptor size, because the
47 * hardware directly receive the frame into the skbuffer.
48 */
c4da0048 49 frame_size = entry->queue->data_size + entry->queue->desc_size;
239c249d
GW
50
51 /*
ff352391
ID
52 * The payload should be aligned to a 4-byte boundary,
53 * this means we need at least 3 bytes for moving the frame
54 * into the correct offset.
239c249d 55 */
2bb057d0
ID
56 head_size = 4;
57
58 /*
59 * For IV/EIV/ICV assembly we must make sure there is
60 * at least 8 bytes bytes available in headroom for IV/EIV
9c3444d3 61 * and 8 bytes for ICV data as tailroon.
2bb057d0 62 */
2bb057d0
ID
63 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
64 head_size += 8;
9c3444d3 65 tail_size += 8;
2bb057d0 66 }
239c249d
GW
67
68 /*
69 * Allocate skbuffer.
70 */
2bb057d0 71 skb = dev_alloc_skb(frame_size + head_size + tail_size);
239c249d
GW
72 if (!skb)
73 return NULL;
74
2bb057d0
ID
75 /*
76 * Make sure we not have a frame with the requested bytes
77 * available in the head and tail.
78 */
79 skb_reserve(skb, head_size);
239c249d
GW
80 skb_put(skb, frame_size);
81
c4da0048
GW
82 /*
83 * Populate skbdesc.
84 */
85 skbdesc = get_skb_frame_desc(skb);
86 memset(skbdesc, 0, sizeof(*skbdesc));
87 skbdesc->entry = entry;
88
89 if (test_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags)) {
90 skbdesc->skb_dma = dma_map_single(rt2x00dev->dev,
91 skb->data,
92 skb->len,
93 DMA_FROM_DEVICE);
94 skbdesc->flags |= SKBDESC_DMA_MAPPED_RX;
95 }
96
239c249d
GW
97 return skb;
98}
30caa6e3 99
c4da0048 100void rt2x00queue_map_txskb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
30caa6e3 101{
c4da0048
GW
102 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
103
3ee54a07
ID
104 skbdesc->skb_dma =
105 dma_map_single(rt2x00dev->dev, skb->data, skb->len, DMA_TO_DEVICE);
c4da0048
GW
106 skbdesc->flags |= SKBDESC_DMA_MAPPED_TX;
107}
108EXPORT_SYMBOL_GPL(rt2x00queue_map_txskb);
109
110void rt2x00queue_unmap_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
111{
112 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
113
114 if (skbdesc->flags & SKBDESC_DMA_MAPPED_RX) {
115 dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma, skb->len,
116 DMA_FROM_DEVICE);
117 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_RX;
546adf29 118 } else if (skbdesc->flags & SKBDESC_DMA_MAPPED_TX) {
0b8004aa 119 dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma, skb->len,
c4da0048
GW
120 DMA_TO_DEVICE);
121 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_TX;
122 }
123}
0b8004aa 124EXPORT_SYMBOL_GPL(rt2x00queue_unmap_skb);
c4da0048
GW
125
126void rt2x00queue_free_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
127{
9a613195
ID
128 if (!skb)
129 return;
130
61243d8e 131 rt2x00queue_unmap_skb(rt2x00dev, skb);
30caa6e3
GW
132 dev_kfree_skb_any(skb);
133}
239c249d 134
daee6c09 135void rt2x00queue_align_frame(struct sk_buff *skb)
9f166171 136{
9f166171 137 unsigned int frame_length = skb->len;
daee6c09 138 unsigned int align = ALIGN_SIZE(skb, 0);
9f166171
ID
139
140 if (!align)
141 return;
142
daee6c09
ID
143 skb_push(skb, align);
144 memmove(skb->data, skb->data + align, frame_length);
145 skb_trim(skb, frame_length);
146}
147
95d69aa0 148void rt2x00queue_align_payload(struct sk_buff *skb, unsigned int header_length)
daee6c09
ID
149{
150 unsigned int frame_length = skb->len;
95d69aa0 151 unsigned int align = ALIGN_SIZE(skb, header_length);
daee6c09
ID
152
153 if (!align)
154 return;
155
156 skb_push(skb, align);
157 memmove(skb->data, skb->data + align, frame_length);
158 skb_trim(skb, frame_length);
159}
160
161void rt2x00queue_insert_l2pad(struct sk_buff *skb, unsigned int header_length)
162{
2e331462 163 unsigned int payload_length = skb->len - header_length;
daee6c09
ID
164 unsigned int header_align = ALIGN_SIZE(skb, 0);
165 unsigned int payload_align = ALIGN_SIZE(skb, header_length);
e54be4e7 166 unsigned int l2pad = payload_length ? L2PAD_SIZE(header_length) : 0;
daee6c09 167
2e331462
GW
168 /*
169 * Adjust the header alignment if the payload needs to be moved more
170 * than the header.
171 */
172 if (payload_align > header_align)
173 header_align += 4;
174
175 /* There is nothing to do if no alignment is needed */
176 if (!header_align)
177 return;
daee6c09 178
2e331462
GW
179 /* Reserve the amount of space needed in front of the frame */
180 skb_push(skb, header_align);
181
182 /*
183 * Move the header.
184 */
185 memmove(skb->data, skb->data + header_align, header_length);
186
187 /* Move the payload, if present and if required */
188 if (payload_length && payload_align)
daee6c09 189 memmove(skb->data + header_length + l2pad,
a5186e99 190 skb->data + header_length + l2pad + payload_align,
2e331462
GW
191 payload_length);
192
193 /* Trim the skb to the correct size */
194 skb_trim(skb, header_length + l2pad + payload_length);
9f166171
ID
195}
196
daee6c09
ID
197void rt2x00queue_remove_l2pad(struct sk_buff *skb, unsigned int header_length)
198{
77e73d18 199 unsigned int l2pad = L2PAD_SIZE(header_length);
daee6c09 200
354e39db 201 if (!l2pad)
daee6c09
ID
202 return;
203
204 memmove(skb->data + l2pad, skb->data, header_length);
205 skb_pull(skb, l2pad);
206}
207
7b40982e
ID
208static void rt2x00queue_create_tx_descriptor_seq(struct queue_entry *entry,
209 struct txentry_desc *txdesc)
210{
211 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
212 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
213 struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
214 unsigned long irqflags;
215
216 if (!(tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) ||
217 unlikely(!tx_info->control.vif))
218 return;
219
220 /*
221 * Hardware should insert sequence counter.
222 * FIXME: We insert a software sequence counter first for
223 * hardware that doesn't support hardware sequence counting.
224 *
225 * This is wrong because beacons are not getting sequence
226 * numbers assigned properly.
227 *
228 * A secondary problem exists for drivers that cannot toggle
229 * sequence counting per-frame, since those will override the
230 * sequence counter given by mac80211.
231 */
232 spin_lock_irqsave(&intf->seqlock, irqflags);
233
234 if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags))
235 intf->seqno += 0x10;
236 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
237 hdr->seq_ctrl |= cpu_to_le16(intf->seqno);
238
239 spin_unlock_irqrestore(&intf->seqlock, irqflags);
240
241 __set_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags);
242}
243
244static void rt2x00queue_create_tx_descriptor_plcp(struct queue_entry *entry,
245 struct txentry_desc *txdesc,
246 const struct rt2x00_rate *hwrate)
247{
248 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
249 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
250 struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0];
251 unsigned int data_length;
252 unsigned int duration;
253 unsigned int residual;
254
255 /* Data length + CRC + Crypto overhead (IV/EIV/ICV/MIC) */
256 data_length = entry->skb->len + 4;
257 data_length += rt2x00crypto_tx_overhead(rt2x00dev, entry->skb);
258
259 /*
260 * PLCP setup
261 * Length calculation depends on OFDM/CCK rate.
262 */
263 txdesc->signal = hwrate->plcp;
264 txdesc->service = 0x04;
265
266 if (hwrate->flags & DEV_RATE_OFDM) {
267 txdesc->length_high = (data_length >> 6) & 0x3f;
268 txdesc->length_low = data_length & 0x3f;
269 } else {
270 /*
271 * Convert length to microseconds.
272 */
273 residual = GET_DURATION_RES(data_length, hwrate->bitrate);
274 duration = GET_DURATION(data_length, hwrate->bitrate);
275
276 if (residual != 0) {
277 duration++;
278
279 /*
280 * Check if we need to set the Length Extension
281 */
282 if (hwrate->bitrate == 110 && residual <= 30)
283 txdesc->service |= 0x80;
284 }
285
286 txdesc->length_high = (duration >> 8) & 0xff;
287 txdesc->length_low = duration & 0xff;
288
289 /*
290 * When preamble is enabled we should set the
291 * preamble bit for the signal.
292 */
293 if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
294 txdesc->signal |= 0x08;
295 }
296}
297
bd88a781
ID
298static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry,
299 struct txentry_desc *txdesc)
7050ec82 300{
2e92e6f2 301 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
e039fa4a 302 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
7050ec82 303 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
2e92e6f2 304 struct ieee80211_rate *rate =
e039fa4a 305 ieee80211_get_tx_rate(rt2x00dev->hw, tx_info);
7050ec82 306 const struct rt2x00_rate *hwrate;
7050ec82
ID
307
308 memset(txdesc, 0, sizeof(*txdesc));
309
310 /*
311 * Initialize information from queue
312 */
a908a743 313 txdesc->qid = entry->queue->qid;
7050ec82
ID
314 txdesc->cw_min = entry->queue->cw_min;
315 txdesc->cw_max = entry->queue->cw_max;
316 txdesc->aifs = entry->queue->aifs;
317
9f166171 318 /*
df624ca5 319 * Header and frame information.
9f166171 320 */
df624ca5 321 txdesc->length = entry->skb->len;
9f166171 322 txdesc->header_length = ieee80211_get_hdrlen_from_skb(entry->skb);
9f166171 323
7050ec82
ID
324 /*
325 * Check whether this frame is to be acked.
326 */
e039fa4a 327 if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK))
7050ec82
ID
328 __set_bit(ENTRY_TXD_ACK, &txdesc->flags);
329
330 /*
331 * Check if this is a RTS/CTS frame
332 */
ac104462
ID
333 if (ieee80211_is_rts(hdr->frame_control) ||
334 ieee80211_is_cts(hdr->frame_control)) {
7050ec82 335 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
ac104462 336 if (ieee80211_is_rts(hdr->frame_control))
7050ec82 337 __set_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags);
e039fa4a 338 else
7050ec82 339 __set_bit(ENTRY_TXD_CTS_FRAME, &txdesc->flags);
e039fa4a 340 if (tx_info->control.rts_cts_rate_idx >= 0)
2e92e6f2 341 rate =
e039fa4a 342 ieee80211_get_rts_cts_rate(rt2x00dev->hw, tx_info);
7050ec82
ID
343 }
344
345 /*
346 * Determine retry information.
347 */
e6a9854b 348 txdesc->retry_limit = tx_info->control.rates[0].count - 1;
42c82857 349 if (txdesc->retry_limit >= rt2x00dev->long_retry)
7050ec82
ID
350 __set_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags);
351
352 /*
353 * Check if more fragments are pending
354 */
2606e422 355 if (ieee80211_has_morefrags(hdr->frame_control)) {
7050ec82
ID
356 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
357 __set_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags);
358 }
359
2606e422
HS
360 /*
361 * Check if more frames (!= fragments) are pending
362 */
363 if (tx_info->flags & IEEE80211_TX_CTL_MORE_FRAMES)
364 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
365
7050ec82
ID
366 /*
367 * Beacons and probe responses require the tsf timestamp
e81e0aef
AB
368 * to be inserted into the frame, except for a frame that has been injected
369 * through a monitor interface. This latter is needed for testing a
370 * monitor interface.
7050ec82 371 */
e81e0aef
AB
372 if ((ieee80211_is_beacon(hdr->frame_control) ||
373 ieee80211_is_probe_resp(hdr->frame_control)) &&
374 (!(tx_info->flags & IEEE80211_TX_CTL_INJECTED)))
7050ec82
ID
375 __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags);
376
377 /*
378 * Determine with what IFS priority this frame should be send.
379 * Set ifs to IFS_SIFS when the this is not the first fragment,
380 * or this fragment came after RTS/CTS.
381 */
7b40982e
ID
382 if ((tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) &&
383 !test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)) {
7050ec82
ID
384 __set_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags);
385 txdesc->ifs = IFS_BACKOFF;
7b40982e 386 } else
7050ec82 387 txdesc->ifs = IFS_SIFS;
7050ec82 388
076f9582
ID
389 /*
390 * Determine rate modulation.
391 */
7050ec82 392 hwrate = rt2x00_get_rate(rate->hw_value);
076f9582 393 txdesc->rate_mode = RATE_MODE_CCK;
7b40982e 394 if (hwrate->flags & DEV_RATE_OFDM)
076f9582 395 txdesc->rate_mode = RATE_MODE_OFDM;
7050ec82 396
7b40982e
ID
397 /*
398 * Apply TX descriptor handling by components
399 */
400 rt2x00crypto_create_tx_descriptor(entry, txdesc);
35f00cfc 401 rt2x00ht_create_tx_descriptor(entry, txdesc, hwrate);
7b40982e
ID
402 rt2x00queue_create_tx_descriptor_seq(entry, txdesc);
403 rt2x00queue_create_tx_descriptor_plcp(entry, txdesc, hwrate);
7050ec82 404}
7050ec82 405
78eea11b
GW
406static int rt2x00queue_write_tx_data(struct queue_entry *entry,
407 struct txentry_desc *txdesc)
408{
409 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
410
411 /*
412 * This should not happen, we already checked the entry
413 * was ours. When the hardware disagrees there has been
414 * a queue corruption!
415 */
416 if (unlikely(rt2x00dev->ops->lib->get_entry_state &&
417 rt2x00dev->ops->lib->get_entry_state(entry))) {
418 ERROR(rt2x00dev,
419 "Corrupt queue %d, accessing entry which is not ours.\n"
420 "Please file bug report to %s.\n",
421 entry->queue->qid, DRV_PROJECT);
422 return -EINVAL;
423 }
424
425 /*
426 * Add the requested extra tx headroom in front of the skb.
427 */
428 skb_push(entry->skb, rt2x00dev->ops->extra_tx_headroom);
429 memset(entry->skb->data, 0, rt2x00dev->ops->extra_tx_headroom);
430
431 /*
76dd5ddf 432 * Call the driver's write_tx_data function, if it exists.
78eea11b 433 */
76dd5ddf
GW
434 if (rt2x00dev->ops->lib->write_tx_data)
435 rt2x00dev->ops->lib->write_tx_data(entry, txdesc);
78eea11b
GW
436
437 /*
438 * Map the skb to DMA.
439 */
440 if (test_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags))
441 rt2x00queue_map_txskb(rt2x00dev, entry->skb);
442
443 return 0;
444}
445
bd88a781
ID
446static void rt2x00queue_write_tx_descriptor(struct queue_entry *entry,
447 struct txentry_desc *txdesc)
7050ec82 448{
b869767b 449 struct data_queue *queue = entry->queue;
7050ec82 450
93331458 451 queue->rt2x00dev->ops->lib->write_tx_desc(entry, txdesc);
7050ec82
ID
452
453 /*
454 * All processing on the frame has been completed, this means
455 * it is now ready to be dumped to userspace through debugfs.
456 */
93331458 457 rt2x00debug_dump_frame(queue->rt2x00dev, DUMP_FRAME_TX, entry->skb);
6295d815
GW
458}
459
460static void rt2x00queue_kick_tx_queue(struct queue_entry *entry,
461 struct txentry_desc *txdesc)
462{
463 struct data_queue *queue = entry->queue;
464 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
7050ec82
ID
465
466 /*
b869767b 467 * Check if we need to kick the queue, there are however a few rules
6295d815 468 * 1) Don't kick unless this is the last in frame in a burst.
b869767b
ID
469 * When the burst flag is set, this frame is always followed
470 * by another frame which in some way are related to eachother.
471 * This is true for fragments, RTS or CTS-to-self frames.
6295d815 472 * 2) Rule 1 can be broken when the available entries
b869767b 473 * in the queue are less then a certain threshold.
7050ec82 474 */
b869767b
ID
475 if (rt2x00queue_threshold(queue) ||
476 !test_bit(ENTRY_TXD_BURST, &txdesc->flags))
93331458 477 rt2x00dev->ops->lib->kick_tx_queue(queue);
7050ec82 478}
7050ec82 479
7351c6bd
JB
480int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
481 bool local)
6db3786a 482{
e6a9854b 483 struct ieee80211_tx_info *tx_info;
6db3786a
ID
484 struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX);
485 struct txentry_desc txdesc;
d74f5ba4 486 struct skb_frame_desc *skbdesc;
e6a9854b 487 u8 rate_idx, rate_flags;
6db3786a
ID
488
489 if (unlikely(rt2x00queue_full(queue)))
0e3de998 490 return -ENOBUFS;
6db3786a 491
0262ab0d 492 if (test_and_set_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags)) {
6db3786a
ID
493 ERROR(queue->rt2x00dev,
494 "Arrived at non-free entry in the non-full queue %d.\n"
495 "Please file bug report to %s.\n",
496 queue->qid, DRV_PROJECT);
497 return -EINVAL;
498 }
499
500 /*
501 * Copy all TX descriptor information into txdesc,
502 * after that we are free to use the skb->cb array
503 * for our information.
504 */
505 entry->skb = skb;
506 rt2x00queue_create_tx_descriptor(entry, &txdesc);
507
d74f5ba4 508 /*
e6a9854b 509 * All information is retrieved from the skb->cb array,
2bb057d0 510 * now we should claim ownership of the driver part of that
e6a9854b 511 * array, preserving the bitrate index and flags.
d74f5ba4 512 */
e6a9854b
JB
513 tx_info = IEEE80211_SKB_CB(skb);
514 rate_idx = tx_info->control.rates[0].idx;
515 rate_flags = tx_info->control.rates[0].flags;
0e3de998 516 skbdesc = get_skb_frame_desc(skb);
d74f5ba4
ID
517 memset(skbdesc, 0, sizeof(*skbdesc));
518 skbdesc->entry = entry;
e6a9854b
JB
519 skbdesc->tx_rate_idx = rate_idx;
520 skbdesc->tx_rate_flags = rate_flags;
d74f5ba4 521
7351c6bd
JB
522 if (local)
523 skbdesc->flags |= SKBDESC_NOT_MAC80211;
524
2bb057d0
ID
525 /*
526 * When hardware encryption is supported, and this frame
527 * is to be encrypted, we should strip the IV/EIV data from
3ad2f3fb 528 * the frame so we can provide it to the driver separately.
2bb057d0
ID
529 */
530 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc.flags) &&
dddfb478 531 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc.flags)) {
3f787bd6 532 if (test_bit(DRIVER_REQUIRE_COPY_IV, &queue->rt2x00dev->flags))
9eb4e21e 533 rt2x00crypto_tx_copy_iv(skb, &txdesc);
dddfb478 534 else
9eb4e21e 535 rt2x00crypto_tx_remove_iv(skb, &txdesc);
dddfb478 536 }
2bb057d0 537
93354cbb
ID
538 /*
539 * When DMA allocation is required we should guarentee to the
540 * driver that the DMA is aligned to a 4-byte boundary.
93354cbb
ID
541 * However some drivers require L2 padding to pad the payload
542 * rather then the header. This could be a requirement for
543 * PCI and USB devices, while header alignment only is valid
544 * for PCI devices.
545 */
9f166171 546 if (test_bit(DRIVER_REQUIRE_L2PAD, &queue->rt2x00dev->flags))
daee6c09 547 rt2x00queue_insert_l2pad(entry->skb, txdesc.header_length);
93354cbb 548 else if (test_bit(DRIVER_REQUIRE_DMA, &queue->rt2x00dev->flags))
daee6c09 549 rt2x00queue_align_frame(entry->skb);
9f166171 550
2bb057d0
ID
551 /*
552 * It could be possible that the queue was corrupted and this
0e3de998
ID
553 * call failed. Since we always return NETDEV_TX_OK to mac80211,
554 * this frame will simply be dropped.
2bb057d0 555 */
78eea11b 556 if (unlikely(rt2x00queue_write_tx_data(entry, &txdesc))) {
0262ab0d 557 clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
2bb057d0 558 entry->skb = NULL;
0e3de998 559 return -EIO;
6db3786a
ID
560 }
561
0262ab0d 562 set_bit(ENTRY_DATA_PENDING, &entry->flags);
6db3786a
ID
563
564 rt2x00queue_index_inc(queue, Q_INDEX);
565 rt2x00queue_write_tx_descriptor(entry, &txdesc);
6295d815 566 rt2x00queue_kick_tx_queue(entry, &txdesc);
6db3786a
ID
567
568 return 0;
569}
570
bd88a781 571int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev,
a2c9b652
ID
572 struct ieee80211_vif *vif,
573 const bool enable_beacon)
bd88a781
ID
574{
575 struct rt2x00_intf *intf = vif_to_intf(vif);
576 struct skb_frame_desc *skbdesc;
577 struct txentry_desc txdesc;
bd88a781
ID
578
579 if (unlikely(!intf->beacon))
580 return -ENOBUFS;
581
17512dc3
IP
582 mutex_lock(&intf->beacon_skb_mutex);
583
584 /*
585 * Clean up the beacon skb.
586 */
587 rt2x00queue_free_skb(rt2x00dev, intf->beacon->skb);
588 intf->beacon->skb = NULL;
589
a2c9b652 590 if (!enable_beacon) {
93331458 591 rt2x00dev->ops->lib->kill_tx_queue(intf->beacon->queue);
17512dc3 592 mutex_unlock(&intf->beacon_skb_mutex);
a2c9b652
ID
593 return 0;
594 }
595
bd88a781 596 intf->beacon->skb = ieee80211_beacon_get(rt2x00dev->hw, vif);
17512dc3
IP
597 if (!intf->beacon->skb) {
598 mutex_unlock(&intf->beacon_skb_mutex);
bd88a781 599 return -ENOMEM;
17512dc3 600 }
bd88a781
ID
601
602 /*
603 * Copy all TX descriptor information into txdesc,
604 * after that we are free to use the skb->cb array
605 * for our information.
606 */
607 rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc);
608
bd88a781
ID
609 /*
610 * Fill in skb descriptor
611 */
612 skbdesc = get_skb_frame_desc(intf->beacon->skb);
613 memset(skbdesc, 0, sizeof(*skbdesc));
bd88a781
ID
614 skbdesc->entry = intf->beacon;
615
bd88a781 616 /*
d61cb266 617 * Send beacon to hardware and enable beacon genaration..
bd88a781 618 */
f224f4ef 619 rt2x00dev->ops->lib->write_beacon(intf->beacon, &txdesc);
bd88a781 620
17512dc3
IP
621 mutex_unlock(&intf->beacon_skb_mutex);
622
bd88a781
ID
623 return 0;
624}
625
5eb7efe8
ID
626void rt2x00queue_for_each_entry(struct data_queue *queue,
627 enum queue_index start,
628 enum queue_index end,
629 void (*fn)(struct queue_entry *entry))
630{
631 unsigned long irqflags;
632 unsigned int index_start;
633 unsigned int index_end;
634 unsigned int i;
635
636 if (unlikely(start >= Q_INDEX_MAX || end >= Q_INDEX_MAX)) {
637 ERROR(queue->rt2x00dev,
638 "Entry requested from invalid index range (%d - %d)\n",
639 start, end);
640 return;
641 }
642
643 /*
644 * Only protect the range we are going to loop over,
645 * if during our loop a extra entry is set to pending
646 * it should not be kicked during this run, since it
647 * is part of another TX operation.
648 */
649 spin_lock_irqsave(&queue->lock, irqflags);
650 index_start = queue->index[start];
651 index_end = queue->index[end];
652 spin_unlock_irqrestore(&queue->lock, irqflags);
653
654 /*
655 * Start from the TX done pointer, this guarentees that we will
656 * send out all frames in the correct order.
657 */
658 if (index_start < index_end) {
659 for (i = index_start; i < index_end; i++)
660 fn(&queue->entries[i]);
661 } else {
662 for (i = index_start; i < queue->limit; i++)
663 fn(&queue->entries[i]);
664
665 for (i = 0; i < index_end; i++)
666 fn(&queue->entries[i]);
667 }
668}
669EXPORT_SYMBOL_GPL(rt2x00queue_for_each_entry);
670
181d6902 671struct data_queue *rt2x00queue_get_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 672 const enum data_queue_qid queue)
181d6902
ID
673{
674 int atim = test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
675
a2c9b652
ID
676 if (queue == QID_RX)
677 return rt2x00dev->rx;
678
61448f88 679 if (queue < rt2x00dev->ops->tx_queues && rt2x00dev->tx)
181d6902
ID
680 return &rt2x00dev->tx[queue];
681
682 if (!rt2x00dev->bcn)
683 return NULL;
684
e58c6aca 685 if (queue == QID_BEACON)
181d6902 686 return &rt2x00dev->bcn[0];
e58c6aca 687 else if (queue == QID_ATIM && atim)
181d6902
ID
688 return &rt2x00dev->bcn[1];
689
690 return NULL;
691}
692EXPORT_SYMBOL_GPL(rt2x00queue_get_queue);
693
694struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue,
695 enum queue_index index)
696{
697 struct queue_entry *entry;
5f46c4d0 698 unsigned long irqflags;
181d6902
ID
699
700 if (unlikely(index >= Q_INDEX_MAX)) {
701 ERROR(queue->rt2x00dev,
702 "Entry requested from invalid index type (%d)\n", index);
703 return NULL;
704 }
705
5f46c4d0 706 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
707
708 entry = &queue->entries[queue->index[index]];
709
5f46c4d0 710 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902
ID
711
712 return entry;
713}
714EXPORT_SYMBOL_GPL(rt2x00queue_get_entry);
715
716void rt2x00queue_index_inc(struct data_queue *queue, enum queue_index index)
717{
5f46c4d0
ID
718 unsigned long irqflags;
719
181d6902
ID
720 if (unlikely(index >= Q_INDEX_MAX)) {
721 ERROR(queue->rt2x00dev,
722 "Index change on invalid index type (%d)\n", index);
723 return;
724 }
725
5f46c4d0 726 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
727
728 queue->index[index]++;
729 if (queue->index[index] >= queue->limit)
730 queue->index[index] = 0;
731
652a9dd2
ID
732 queue->last_action[index] = jiffies;
733
10b6b801
ID
734 if (index == Q_INDEX) {
735 queue->length++;
736 } else if (index == Q_INDEX_DONE) {
737 queue->length--;
55887511 738 queue->count++;
10b6b801 739 }
181d6902 740
5f46c4d0 741 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902 742}
181d6902
ID
743
744static void rt2x00queue_reset(struct data_queue *queue)
745{
5f46c4d0 746 unsigned long irqflags;
652a9dd2 747 unsigned int i;
5f46c4d0
ID
748
749 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
750
751 queue->count = 0;
752 queue->length = 0;
652a9dd2
ID
753
754 for (i = 0; i < Q_INDEX_MAX; i++) {
755 queue->index[i] = 0;
756 queue->last_action[i] = jiffies;
757 }
181d6902 758
5f46c4d0 759 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902
ID
760}
761
a2c9b652
ID
762void rt2x00queue_stop_queues(struct rt2x00_dev *rt2x00dev)
763{
764 struct data_queue *queue;
765
766 txall_queue_for_each(rt2x00dev, queue)
93331458 767 rt2x00dev->ops->lib->kill_tx_queue(queue);
a2c9b652
ID
768}
769
798b7adb 770void rt2x00queue_init_queues(struct rt2x00_dev *rt2x00dev)
181d6902
ID
771{
772 struct data_queue *queue;
773 unsigned int i;
774
798b7adb 775 queue_for_each(rt2x00dev, queue) {
181d6902
ID
776 rt2x00queue_reset(queue);
777
9c0ab712 778 for (i = 0; i < queue->limit; i++) {
798b7adb 779 rt2x00dev->ops->lib->clear_entry(&queue->entries[i]);
7e613e16
ID
780 if (queue->qid == QID_RX)
781 rt2x00queue_index_inc(queue, Q_INDEX);
9c0ab712 782 }
181d6902
ID
783 }
784}
785
786static int rt2x00queue_alloc_entries(struct data_queue *queue,
787 const struct data_queue_desc *qdesc)
788{
789 struct queue_entry *entries;
790 unsigned int entry_size;
791 unsigned int i;
792
793 rt2x00queue_reset(queue);
794
795 queue->limit = qdesc->entry_num;
b869767b 796 queue->threshold = DIV_ROUND_UP(qdesc->entry_num, 10);
181d6902
ID
797 queue->data_size = qdesc->data_size;
798 queue->desc_size = qdesc->desc_size;
799
800 /*
801 * Allocate all queue entries.
802 */
803 entry_size = sizeof(*entries) + qdesc->priv_size;
804 entries = kzalloc(queue->limit * entry_size, GFP_KERNEL);
805 if (!entries)
806 return -ENOMEM;
807
808#define QUEUE_ENTRY_PRIV_OFFSET(__base, __index, __limit, __esize, __psize) \
231be4e9
AB
809 ( ((char *)(__base)) + ((__limit) * (__esize)) + \
810 ((__index) * (__psize)) )
181d6902
ID
811
812 for (i = 0; i < queue->limit; i++) {
813 entries[i].flags = 0;
814 entries[i].queue = queue;
815 entries[i].skb = NULL;
816 entries[i].entry_idx = i;
817 entries[i].priv_data =
818 QUEUE_ENTRY_PRIV_OFFSET(entries, i, queue->limit,
819 sizeof(*entries), qdesc->priv_size);
820 }
821
822#undef QUEUE_ENTRY_PRIV_OFFSET
823
824 queue->entries = entries;
825
826 return 0;
827}
828
c4da0048
GW
829static void rt2x00queue_free_skbs(struct rt2x00_dev *rt2x00dev,
830 struct data_queue *queue)
30caa6e3
GW
831{
832 unsigned int i;
833
834 if (!queue->entries)
835 return;
836
837 for (i = 0; i < queue->limit; i++) {
838 if (queue->entries[i].skb)
c4da0048 839 rt2x00queue_free_skb(rt2x00dev, queue->entries[i].skb);
30caa6e3
GW
840 }
841}
842
c4da0048
GW
843static int rt2x00queue_alloc_rxskbs(struct rt2x00_dev *rt2x00dev,
844 struct data_queue *queue)
30caa6e3
GW
845{
846 unsigned int i;
847 struct sk_buff *skb;
848
849 for (i = 0; i < queue->limit; i++) {
c4da0048 850 skb = rt2x00queue_alloc_rxskb(rt2x00dev, &queue->entries[i]);
30caa6e3 851 if (!skb)
61243d8e 852 return -ENOMEM;
30caa6e3
GW
853 queue->entries[i].skb = skb;
854 }
855
856 return 0;
30caa6e3
GW
857}
858
181d6902
ID
859int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev)
860{
861 struct data_queue *queue;
862 int status;
863
181d6902
ID
864 status = rt2x00queue_alloc_entries(rt2x00dev->rx, rt2x00dev->ops->rx);
865 if (status)
866 goto exit;
867
868 tx_queue_for_each(rt2x00dev, queue) {
869 status = rt2x00queue_alloc_entries(queue, rt2x00dev->ops->tx);
870 if (status)
871 goto exit;
872 }
873
874 status = rt2x00queue_alloc_entries(rt2x00dev->bcn, rt2x00dev->ops->bcn);
875 if (status)
876 goto exit;
877
30caa6e3
GW
878 if (test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags)) {
879 status = rt2x00queue_alloc_entries(&rt2x00dev->bcn[1],
880 rt2x00dev->ops->atim);
881 if (status)
882 goto exit;
883 }
181d6902 884
c4da0048 885 status = rt2x00queue_alloc_rxskbs(rt2x00dev, rt2x00dev->rx);
181d6902
ID
886 if (status)
887 goto exit;
888
889 return 0;
890
891exit:
892 ERROR(rt2x00dev, "Queue entries allocation failed.\n");
893
894 rt2x00queue_uninitialize(rt2x00dev);
895
896 return status;
897}
898
899void rt2x00queue_uninitialize(struct rt2x00_dev *rt2x00dev)
900{
901 struct data_queue *queue;
902
c4da0048 903 rt2x00queue_free_skbs(rt2x00dev, rt2x00dev->rx);
30caa6e3 904
181d6902
ID
905 queue_for_each(rt2x00dev, queue) {
906 kfree(queue->entries);
907 queue->entries = NULL;
908 }
909}
910
8f539276
ID
911static void rt2x00queue_init(struct rt2x00_dev *rt2x00dev,
912 struct data_queue *queue, enum data_queue_qid qid)
913{
914 spin_lock_init(&queue->lock);
915
916 queue->rt2x00dev = rt2x00dev;
917 queue->qid = qid;
2af0a570 918 queue->txop = 0;
8f539276
ID
919 queue->aifs = 2;
920 queue->cw_min = 5;
921 queue->cw_max = 10;
922}
923
181d6902
ID
924int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
925{
926 struct data_queue *queue;
927 enum data_queue_qid qid;
928 unsigned int req_atim =
929 !!test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
930
931 /*
932 * We need the following queues:
933 * RX: 1
61448f88 934 * TX: ops->tx_queues
181d6902
ID
935 * Beacon: 1
936 * Atim: 1 (if required)
937 */
61448f88 938 rt2x00dev->data_queues = 2 + rt2x00dev->ops->tx_queues + req_atim;
181d6902
ID
939
940 queue = kzalloc(rt2x00dev->data_queues * sizeof(*queue), GFP_KERNEL);
941 if (!queue) {
942 ERROR(rt2x00dev, "Queue allocation failed.\n");
943 return -ENOMEM;
944 }
945
946 /*
947 * Initialize pointers
948 */
949 rt2x00dev->rx = queue;
950 rt2x00dev->tx = &queue[1];
61448f88 951 rt2x00dev->bcn = &queue[1 + rt2x00dev->ops->tx_queues];
181d6902
ID
952
953 /*
954 * Initialize queue parameters.
955 * RX: qid = QID_RX
956 * TX: qid = QID_AC_BE + index
957 * TX: cw_min: 2^5 = 32.
958 * TX: cw_max: 2^10 = 1024.
565a019a
ID
959 * BCN: qid = QID_BEACON
960 * ATIM: qid = QID_ATIM
181d6902 961 */
8f539276 962 rt2x00queue_init(rt2x00dev, rt2x00dev->rx, QID_RX);
181d6902 963
8f539276
ID
964 qid = QID_AC_BE;
965 tx_queue_for_each(rt2x00dev, queue)
966 rt2x00queue_init(rt2x00dev, queue, qid++);
181d6902 967
565a019a 968 rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[0], QID_BEACON);
181d6902 969 if (req_atim)
565a019a 970 rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[1], QID_ATIM);
181d6902
ID
971
972 return 0;
973}
974
975void rt2x00queue_free(struct rt2x00_dev *rt2x00dev)
976{
977 kfree(rt2x00dev->rx);
978 rt2x00dev->rx = NULL;
979 rt2x00dev->tx = NULL;
980 rt2x00dev->bcn = NULL;
981}
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