rt2x00: Serialize TX operations on a queue.
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2x00queue.c
CommitLineData
181d6902 1/*
7e613e16
ID
2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2004 - 2009 Gertjan van Wingerde <gwingerde@gmail.com>
181d6902
ID
5 <http://rt2x00.serialmonkey.com>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the
19 Free Software Foundation, Inc.,
20 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22
23/*
24 Module: rt2x00lib
25 Abstract: rt2x00 queue specific routines.
26 */
27
5a0e3ad6 28#include <linux/slab.h>
181d6902
ID
29#include <linux/kernel.h>
30#include <linux/module.h>
c4da0048 31#include <linux/dma-mapping.h>
181d6902
ID
32
33#include "rt2x00.h"
34#include "rt2x00lib.h"
35
fa69560f 36struct sk_buff *rt2x00queue_alloc_rxskb(struct queue_entry *entry)
239c249d 37{
fa69560f 38 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
c4da0048
GW
39 struct sk_buff *skb;
40 struct skb_frame_desc *skbdesc;
2bb057d0
ID
41 unsigned int frame_size;
42 unsigned int head_size = 0;
43 unsigned int tail_size = 0;
239c249d
GW
44
45 /*
46 * The frame size includes descriptor size, because the
47 * hardware directly receive the frame into the skbuffer.
48 */
c4da0048 49 frame_size = entry->queue->data_size + entry->queue->desc_size;
239c249d
GW
50
51 /*
ff352391
ID
52 * The payload should be aligned to a 4-byte boundary,
53 * this means we need at least 3 bytes for moving the frame
54 * into the correct offset.
239c249d 55 */
2bb057d0
ID
56 head_size = 4;
57
58 /*
59 * For IV/EIV/ICV assembly we must make sure there is
60 * at least 8 bytes bytes available in headroom for IV/EIV
9c3444d3 61 * and 8 bytes for ICV data as tailroon.
2bb057d0 62 */
7dab73b3 63 if (test_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags)) {
2bb057d0 64 head_size += 8;
9c3444d3 65 tail_size += 8;
2bb057d0 66 }
239c249d
GW
67
68 /*
69 * Allocate skbuffer.
70 */
2bb057d0 71 skb = dev_alloc_skb(frame_size + head_size + tail_size);
239c249d
GW
72 if (!skb)
73 return NULL;
74
2bb057d0
ID
75 /*
76 * Make sure we not have a frame with the requested bytes
77 * available in the head and tail.
78 */
79 skb_reserve(skb, head_size);
239c249d
GW
80 skb_put(skb, frame_size);
81
c4da0048
GW
82 /*
83 * Populate skbdesc.
84 */
85 skbdesc = get_skb_frame_desc(skb);
86 memset(skbdesc, 0, sizeof(*skbdesc));
87 skbdesc->entry = entry;
88
7dab73b3 89 if (test_bit(REQUIRE_DMA, &rt2x00dev->cap_flags)) {
c4da0048
GW
90 skbdesc->skb_dma = dma_map_single(rt2x00dev->dev,
91 skb->data,
92 skb->len,
93 DMA_FROM_DEVICE);
94 skbdesc->flags |= SKBDESC_DMA_MAPPED_RX;
95 }
96
239c249d
GW
97 return skb;
98}
30caa6e3 99
fa69560f 100void rt2x00queue_map_txskb(struct queue_entry *entry)
30caa6e3 101{
fa69560f
ID
102 struct device *dev = entry->queue->rt2x00dev->dev;
103 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
c4da0048 104
3ee54a07 105 skbdesc->skb_dma =
fa69560f 106 dma_map_single(dev, entry->skb->data, entry->skb->len, DMA_TO_DEVICE);
c4da0048
GW
107 skbdesc->flags |= SKBDESC_DMA_MAPPED_TX;
108}
109EXPORT_SYMBOL_GPL(rt2x00queue_map_txskb);
110
fa69560f 111void rt2x00queue_unmap_skb(struct queue_entry *entry)
c4da0048 112{
fa69560f
ID
113 struct device *dev = entry->queue->rt2x00dev->dev;
114 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
c4da0048
GW
115
116 if (skbdesc->flags & SKBDESC_DMA_MAPPED_RX) {
fa69560f 117 dma_unmap_single(dev, skbdesc->skb_dma, entry->skb->len,
c4da0048
GW
118 DMA_FROM_DEVICE);
119 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_RX;
546adf29 120 } else if (skbdesc->flags & SKBDESC_DMA_MAPPED_TX) {
fa69560f 121 dma_unmap_single(dev, skbdesc->skb_dma, entry->skb->len,
c4da0048
GW
122 DMA_TO_DEVICE);
123 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_TX;
124 }
125}
0b8004aa 126EXPORT_SYMBOL_GPL(rt2x00queue_unmap_skb);
c4da0048 127
fa69560f 128void rt2x00queue_free_skb(struct queue_entry *entry)
c4da0048 129{
fa69560f 130 if (!entry->skb)
9a613195
ID
131 return;
132
fa69560f
ID
133 rt2x00queue_unmap_skb(entry);
134 dev_kfree_skb_any(entry->skb);
135 entry->skb = NULL;
30caa6e3 136}
239c249d 137
daee6c09 138void rt2x00queue_align_frame(struct sk_buff *skb)
9f166171 139{
9f166171 140 unsigned int frame_length = skb->len;
daee6c09 141 unsigned int align = ALIGN_SIZE(skb, 0);
9f166171
ID
142
143 if (!align)
144 return;
145
daee6c09
ID
146 skb_push(skb, align);
147 memmove(skb->data, skb->data + align, frame_length);
148 skb_trim(skb, frame_length);
149}
150
daee6c09
ID
151void rt2x00queue_insert_l2pad(struct sk_buff *skb, unsigned int header_length)
152{
2e331462 153 unsigned int payload_length = skb->len - header_length;
daee6c09
ID
154 unsigned int header_align = ALIGN_SIZE(skb, 0);
155 unsigned int payload_align = ALIGN_SIZE(skb, header_length);
e54be4e7 156 unsigned int l2pad = payload_length ? L2PAD_SIZE(header_length) : 0;
daee6c09 157
2e331462
GW
158 /*
159 * Adjust the header alignment if the payload needs to be moved more
160 * than the header.
161 */
162 if (payload_align > header_align)
163 header_align += 4;
164
165 /* There is nothing to do if no alignment is needed */
166 if (!header_align)
167 return;
daee6c09 168
2e331462
GW
169 /* Reserve the amount of space needed in front of the frame */
170 skb_push(skb, header_align);
171
172 /*
173 * Move the header.
174 */
175 memmove(skb->data, skb->data + header_align, header_length);
176
177 /* Move the payload, if present and if required */
178 if (payload_length && payload_align)
daee6c09 179 memmove(skb->data + header_length + l2pad,
a5186e99 180 skb->data + header_length + l2pad + payload_align,
2e331462
GW
181 payload_length);
182
183 /* Trim the skb to the correct size */
184 skb_trim(skb, header_length + l2pad + payload_length);
9f166171
ID
185}
186
daee6c09
ID
187void rt2x00queue_remove_l2pad(struct sk_buff *skb, unsigned int header_length)
188{
a061a93b
GW
189 /*
190 * L2 padding is only present if the skb contains more than just the
191 * IEEE 802.11 header.
192 */
193 unsigned int l2pad = (skb->len > header_length) ?
194 L2PAD_SIZE(header_length) : 0;
daee6c09 195
354e39db 196 if (!l2pad)
daee6c09
ID
197 return;
198
a061a93b
GW
199 memmove(skb->data + l2pad, skb->data, header_length);
200 skb_pull(skb, l2pad);
daee6c09
ID
201}
202
7b40982e
ID
203static void rt2x00queue_create_tx_descriptor_seq(struct queue_entry *entry,
204 struct txentry_desc *txdesc)
205{
206 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
207 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
208 struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
7b40982e 209
c262e08b 210 if (!(tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ))
7b40982e
ID
211 return;
212
7fe7ee77
HS
213 __set_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags);
214
7dab73b3 215 if (!test_bit(REQUIRE_SW_SEQNO, &entry->queue->rt2x00dev->cap_flags))
7fe7ee77
HS
216 return;
217
7b40982e 218 /*
7fe7ee77
HS
219 * The hardware is not able to insert a sequence number. Assign a
220 * software generated one here.
7b40982e
ID
221 *
222 * This is wrong because beacons are not getting sequence
223 * numbers assigned properly.
224 *
225 * A secondary problem exists for drivers that cannot toggle
226 * sequence counting per-frame, since those will override the
227 * sequence counter given by mac80211.
228 */
798eefde 229 spin_lock(&intf->seqlock);
7b40982e
ID
230
231 if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags))
232 intf->seqno += 0x10;
233 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
234 hdr->seq_ctrl |= cpu_to_le16(intf->seqno);
235
798eefde 236 spin_unlock(&intf->seqlock);
7b40982e 237
7b40982e
ID
238}
239
240static void rt2x00queue_create_tx_descriptor_plcp(struct queue_entry *entry,
241 struct txentry_desc *txdesc,
242 const struct rt2x00_rate *hwrate)
243{
244 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
245 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
246 struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0];
247 unsigned int data_length;
248 unsigned int duration;
249 unsigned int residual;
250
2517794b
HS
251 /*
252 * Determine with what IFS priority this frame should be send.
253 * Set ifs to IFS_SIFS when the this is not the first fragment,
254 * or this fragment came after RTS/CTS.
255 */
256 if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags))
257 txdesc->u.plcp.ifs = IFS_BACKOFF;
258 else
259 txdesc->u.plcp.ifs = IFS_SIFS;
260
7b40982e
ID
261 /* Data length + CRC + Crypto overhead (IV/EIV/ICV/MIC) */
262 data_length = entry->skb->len + 4;
263 data_length += rt2x00crypto_tx_overhead(rt2x00dev, entry->skb);
264
265 /*
266 * PLCP setup
267 * Length calculation depends on OFDM/CCK rate.
268 */
26a1d07f
HS
269 txdesc->u.plcp.signal = hwrate->plcp;
270 txdesc->u.plcp.service = 0x04;
7b40982e
ID
271
272 if (hwrate->flags & DEV_RATE_OFDM) {
26a1d07f
HS
273 txdesc->u.plcp.length_high = (data_length >> 6) & 0x3f;
274 txdesc->u.plcp.length_low = data_length & 0x3f;
7b40982e
ID
275 } else {
276 /*
277 * Convert length to microseconds.
278 */
279 residual = GET_DURATION_RES(data_length, hwrate->bitrate);
280 duration = GET_DURATION(data_length, hwrate->bitrate);
281
282 if (residual != 0) {
283 duration++;
284
285 /*
286 * Check if we need to set the Length Extension
287 */
288 if (hwrate->bitrate == 110 && residual <= 30)
26a1d07f 289 txdesc->u.plcp.service |= 0x80;
7b40982e
ID
290 }
291
26a1d07f
HS
292 txdesc->u.plcp.length_high = (duration >> 8) & 0xff;
293 txdesc->u.plcp.length_low = duration & 0xff;
7b40982e
ID
294
295 /*
296 * When preamble is enabled we should set the
297 * preamble bit for the signal.
298 */
299 if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
26a1d07f 300 txdesc->u.plcp.signal |= 0x08;
7b40982e
ID
301 }
302}
303
46a01ec0
GW
304static void rt2x00queue_create_tx_descriptor_ht(struct queue_entry *entry,
305 struct txentry_desc *txdesc,
306 const struct rt2x00_rate *hwrate)
307{
308 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
309 struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0];
310 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
311
312 if (tx_info->control.sta)
313 txdesc->u.ht.mpdu_density =
314 tx_info->control.sta->ht_cap.ampdu_density;
315
316 txdesc->u.ht.ba_size = 7; /* FIXME: What value is needed? */
317
318 /*
319 * Only one STBC stream is supported for now.
320 */
321 if (tx_info->flags & IEEE80211_TX_CTL_STBC)
322 txdesc->u.ht.stbc = 1;
323
324 /*
325 * If IEEE80211_TX_RC_MCS is set txrate->idx just contains the
326 * mcs rate to be used
327 */
328 if (txrate->flags & IEEE80211_TX_RC_MCS) {
329 txdesc->u.ht.mcs = txrate->idx;
330
331 /*
332 * MIMO PS should be set to 1 for STA's using dynamic SM PS
333 * when using more then one tx stream (>MCS7).
334 */
335 if (tx_info->control.sta && txdesc->u.ht.mcs > 7 &&
336 ((tx_info->control.sta->ht_cap.cap &
337 IEEE80211_HT_CAP_SM_PS) >>
338 IEEE80211_HT_CAP_SM_PS_SHIFT) ==
339 WLAN_HT_CAP_SM_PS_DYNAMIC)
340 __set_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags);
341 } else {
342 txdesc->u.ht.mcs = rt2x00_get_rate_mcs(hwrate->mcs);
343 if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
344 txdesc->u.ht.mcs |= 0x08;
345 }
346
347 /*
348 * This frame is eligible for an AMPDU, however, don't aggregate
349 * frames that are intended to probe a specific tx rate.
350 */
351 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU &&
352 !(tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE))
353 __set_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags);
354
355 /*
356 * Set 40Mhz mode if necessary (for legacy rates this will
357 * duplicate the frame to both channels).
358 */
359 if (txrate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH ||
360 txrate->flags & IEEE80211_TX_RC_DUP_DATA)
361 __set_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags);
362 if (txrate->flags & IEEE80211_TX_RC_SHORT_GI)
363 __set_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags);
364
365 /*
366 * Determine IFS values
367 * - Use TXOP_BACKOFF for management frames except beacons
368 * - Use TXOP_SIFS for fragment bursts
369 * - Use TXOP_HTTXOP for everything else
370 *
371 * Note: rt2800 devices won't use CTS protection (if used)
372 * for frames not transmitted with TXOP_HTTXOP
373 */
374 if (ieee80211_is_mgmt(hdr->frame_control) &&
375 !ieee80211_is_beacon(hdr->frame_control))
376 txdesc->u.ht.txop = TXOP_BACKOFF;
377 else if (!(tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT))
378 txdesc->u.ht.txop = TXOP_SIFS;
379 else
380 txdesc->u.ht.txop = TXOP_HTTXOP;
381}
382
bd88a781
ID
383static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry,
384 struct txentry_desc *txdesc)
7050ec82 385{
2e92e6f2 386 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
e039fa4a 387 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
7050ec82 388 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
55b585e2
HS
389 struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0];
390 struct ieee80211_rate *rate;
391 const struct rt2x00_rate *hwrate = NULL;
7050ec82
ID
392
393 memset(txdesc, 0, sizeof(*txdesc));
394
9f166171 395 /*
df624ca5 396 * Header and frame information.
9f166171 397 */
df624ca5 398 txdesc->length = entry->skb->len;
9f166171 399 txdesc->header_length = ieee80211_get_hdrlen_from_skb(entry->skb);
9f166171 400
7050ec82
ID
401 /*
402 * Check whether this frame is to be acked.
403 */
e039fa4a 404 if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK))
7050ec82
ID
405 __set_bit(ENTRY_TXD_ACK, &txdesc->flags);
406
407 /*
408 * Check if this is a RTS/CTS frame
409 */
ac104462
ID
410 if (ieee80211_is_rts(hdr->frame_control) ||
411 ieee80211_is_cts(hdr->frame_control)) {
7050ec82 412 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
ac104462 413 if (ieee80211_is_rts(hdr->frame_control))
7050ec82 414 __set_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags);
e039fa4a 415 else
7050ec82 416 __set_bit(ENTRY_TXD_CTS_FRAME, &txdesc->flags);
e039fa4a 417 if (tx_info->control.rts_cts_rate_idx >= 0)
2e92e6f2 418 rate =
e039fa4a 419 ieee80211_get_rts_cts_rate(rt2x00dev->hw, tx_info);
7050ec82
ID
420 }
421
422 /*
423 * Determine retry information.
424 */
e6a9854b 425 txdesc->retry_limit = tx_info->control.rates[0].count - 1;
42c82857 426 if (txdesc->retry_limit >= rt2x00dev->long_retry)
7050ec82
ID
427 __set_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags);
428
429 /*
430 * Check if more fragments are pending
431 */
2606e422 432 if (ieee80211_has_morefrags(hdr->frame_control)) {
7050ec82
ID
433 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
434 __set_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags);
435 }
436
2606e422
HS
437 /*
438 * Check if more frames (!= fragments) are pending
439 */
440 if (tx_info->flags & IEEE80211_TX_CTL_MORE_FRAMES)
441 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
442
7050ec82
ID
443 /*
444 * Beacons and probe responses require the tsf timestamp
1bce85cf 445 * to be inserted into the frame.
7050ec82 446 */
1bce85cf
HS
447 if (ieee80211_is_beacon(hdr->frame_control) ||
448 ieee80211_is_probe_resp(hdr->frame_control))
7050ec82
ID
449 __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags);
450
7b40982e 451 if ((tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) &&
2517794b 452 !test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags))
7050ec82 453 __set_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags);
7050ec82 454
076f9582
ID
455 /*
456 * Determine rate modulation.
457 */
55b585e2
HS
458 if (txrate->flags & IEEE80211_TX_RC_GREEN_FIELD)
459 txdesc->rate_mode = RATE_MODE_HT_GREENFIELD;
460 else if (txrate->flags & IEEE80211_TX_RC_MCS)
461 txdesc->rate_mode = RATE_MODE_HT_MIX;
462 else {
463 rate = ieee80211_get_tx_rate(rt2x00dev->hw, tx_info);
464 hwrate = rt2x00_get_rate(rate->hw_value);
465 if (hwrate->flags & DEV_RATE_OFDM)
466 txdesc->rate_mode = RATE_MODE_OFDM;
467 else
468 txdesc->rate_mode = RATE_MODE_CCK;
469 }
7050ec82 470
7b40982e
ID
471 /*
472 * Apply TX descriptor handling by components
473 */
474 rt2x00crypto_create_tx_descriptor(entry, txdesc);
475 rt2x00queue_create_tx_descriptor_seq(entry, txdesc);
26a1d07f 476
7dab73b3 477 if (test_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags))
46a01ec0 478 rt2x00queue_create_tx_descriptor_ht(entry, txdesc, hwrate);
26a1d07f
HS
479 else
480 rt2x00queue_create_tx_descriptor_plcp(entry, txdesc, hwrate);
7050ec82 481}
7050ec82 482
78eea11b
GW
483static int rt2x00queue_write_tx_data(struct queue_entry *entry,
484 struct txentry_desc *txdesc)
485{
486 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
487
488 /*
489 * This should not happen, we already checked the entry
490 * was ours. When the hardware disagrees there has been
491 * a queue corruption!
492 */
493 if (unlikely(rt2x00dev->ops->lib->get_entry_state &&
494 rt2x00dev->ops->lib->get_entry_state(entry))) {
495 ERROR(rt2x00dev,
496 "Corrupt queue %d, accessing entry which is not ours.\n"
497 "Please file bug report to %s.\n",
498 entry->queue->qid, DRV_PROJECT);
499 return -EINVAL;
500 }
501
502 /*
503 * Add the requested extra tx headroom in front of the skb.
504 */
505 skb_push(entry->skb, rt2x00dev->ops->extra_tx_headroom);
506 memset(entry->skb->data, 0, rt2x00dev->ops->extra_tx_headroom);
507
508 /*
76dd5ddf 509 * Call the driver's write_tx_data function, if it exists.
78eea11b 510 */
76dd5ddf
GW
511 if (rt2x00dev->ops->lib->write_tx_data)
512 rt2x00dev->ops->lib->write_tx_data(entry, txdesc);
78eea11b
GW
513
514 /*
515 * Map the skb to DMA.
516 */
7dab73b3 517 if (test_bit(REQUIRE_DMA, &rt2x00dev->cap_flags))
fa69560f 518 rt2x00queue_map_txskb(entry);
78eea11b
GW
519
520 return 0;
521}
522
bd88a781
ID
523static void rt2x00queue_write_tx_descriptor(struct queue_entry *entry,
524 struct txentry_desc *txdesc)
7050ec82 525{
b869767b 526 struct data_queue *queue = entry->queue;
7050ec82 527
93331458 528 queue->rt2x00dev->ops->lib->write_tx_desc(entry, txdesc);
7050ec82
ID
529
530 /*
531 * All processing on the frame has been completed, this means
532 * it is now ready to be dumped to userspace through debugfs.
533 */
93331458 534 rt2x00debug_dump_frame(queue->rt2x00dev, DUMP_FRAME_TX, entry->skb);
6295d815
GW
535}
536
8be4eed0 537static void rt2x00queue_kick_tx_queue(struct data_queue *queue,
6295d815
GW
538 struct txentry_desc *txdesc)
539{
7050ec82 540 /*
b869767b 541 * Check if we need to kick the queue, there are however a few rules
6295d815 542 * 1) Don't kick unless this is the last in frame in a burst.
b869767b
ID
543 * When the burst flag is set, this frame is always followed
544 * by another frame which in some way are related to eachother.
545 * This is true for fragments, RTS or CTS-to-self frames.
6295d815 546 * 2) Rule 1 can be broken when the available entries
b869767b 547 * in the queue are less then a certain threshold.
7050ec82 548 */
b869767b
ID
549 if (rt2x00queue_threshold(queue) ||
550 !test_bit(ENTRY_TXD_BURST, &txdesc->flags))
dbba306f 551 queue->rt2x00dev->ops->lib->kick_queue(queue);
7050ec82 552}
7050ec82 553
7351c6bd
JB
554int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
555 bool local)
6db3786a 556{
e6a9854b 557 struct ieee80211_tx_info *tx_info;
77a861c4 558 struct queue_entry *entry;
6db3786a 559 struct txentry_desc txdesc;
d74f5ba4 560 struct skb_frame_desc *skbdesc;
e6a9854b 561 u8 rate_idx, rate_flags;
77a861c4
GW
562 int ret = 0;
563
564 spin_lock(&queue->tx_lock);
565
566 entry = rt2x00queue_get_entry(queue, Q_INDEX);
6db3786a 567
6a4c499e
HS
568 if (unlikely(rt2x00queue_full(queue))) {
569 ERROR(queue->rt2x00dev,
570 "Dropping frame due to full tx queue %d.\n", queue->qid);
77a861c4
GW
571 ret = -ENOBUFS;
572 goto out;
6a4c499e 573 }
6db3786a 574
c6084d5f
HS
575 if (unlikely(test_and_set_bit(ENTRY_OWNER_DEVICE_DATA,
576 &entry->flags))) {
6db3786a
ID
577 ERROR(queue->rt2x00dev,
578 "Arrived at non-free entry in the non-full queue %d.\n"
579 "Please file bug report to %s.\n",
580 queue->qid, DRV_PROJECT);
77a861c4
GW
581 ret = -EINVAL;
582 goto out;
6db3786a
ID
583 }
584
585 /*
586 * Copy all TX descriptor information into txdesc,
587 * after that we are free to use the skb->cb array
588 * for our information.
589 */
590 entry->skb = skb;
591 rt2x00queue_create_tx_descriptor(entry, &txdesc);
592
d74f5ba4 593 /*
e6a9854b 594 * All information is retrieved from the skb->cb array,
2bb057d0 595 * now we should claim ownership of the driver part of that
e6a9854b 596 * array, preserving the bitrate index and flags.
d74f5ba4 597 */
e6a9854b
JB
598 tx_info = IEEE80211_SKB_CB(skb);
599 rate_idx = tx_info->control.rates[0].idx;
600 rate_flags = tx_info->control.rates[0].flags;
0e3de998 601 skbdesc = get_skb_frame_desc(skb);
d74f5ba4
ID
602 memset(skbdesc, 0, sizeof(*skbdesc));
603 skbdesc->entry = entry;
e6a9854b
JB
604 skbdesc->tx_rate_idx = rate_idx;
605 skbdesc->tx_rate_flags = rate_flags;
d74f5ba4 606
7351c6bd
JB
607 if (local)
608 skbdesc->flags |= SKBDESC_NOT_MAC80211;
609
2bb057d0
ID
610 /*
611 * When hardware encryption is supported, and this frame
612 * is to be encrypted, we should strip the IV/EIV data from
3ad2f3fb 613 * the frame so we can provide it to the driver separately.
2bb057d0
ID
614 */
615 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc.flags) &&
dddfb478 616 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc.flags)) {
7dab73b3 617 if (test_bit(REQUIRE_COPY_IV, &queue->rt2x00dev->cap_flags))
9eb4e21e 618 rt2x00crypto_tx_copy_iv(skb, &txdesc);
dddfb478 619 else
9eb4e21e 620 rt2x00crypto_tx_remove_iv(skb, &txdesc);
dddfb478 621 }
2bb057d0 622
93354cbb 623 /*
25985edc 624 * When DMA allocation is required we should guarantee to the
93354cbb 625 * driver that the DMA is aligned to a 4-byte boundary.
93354cbb
ID
626 * However some drivers require L2 padding to pad the payload
627 * rather then the header. This could be a requirement for
628 * PCI and USB devices, while header alignment only is valid
629 * for PCI devices.
630 */
7dab73b3 631 if (test_bit(REQUIRE_L2PAD, &queue->rt2x00dev->cap_flags))
daee6c09 632 rt2x00queue_insert_l2pad(entry->skb, txdesc.header_length);
7dab73b3 633 else if (test_bit(REQUIRE_DMA, &queue->rt2x00dev->cap_flags))
daee6c09 634 rt2x00queue_align_frame(entry->skb);
9f166171 635
2bb057d0
ID
636 /*
637 * It could be possible that the queue was corrupted and this
0e3de998
ID
638 * call failed. Since we always return NETDEV_TX_OK to mac80211,
639 * this frame will simply be dropped.
2bb057d0 640 */
78eea11b 641 if (unlikely(rt2x00queue_write_tx_data(entry, &txdesc))) {
0262ab0d 642 clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
2bb057d0 643 entry->skb = NULL;
77a861c4
GW
644 ret = -EIO;
645 goto out;
6db3786a
ID
646 }
647
0262ab0d 648 set_bit(ENTRY_DATA_PENDING, &entry->flags);
6db3786a 649
75256f03 650 rt2x00queue_index_inc(entry, Q_INDEX);
6db3786a 651 rt2x00queue_write_tx_descriptor(entry, &txdesc);
8be4eed0 652 rt2x00queue_kick_tx_queue(queue, &txdesc);
6db3786a 653
77a861c4
GW
654out:
655 spin_unlock(&queue->tx_lock);
656 return ret;
6db3786a
ID
657}
658
69cf36a4
HS
659int rt2x00queue_clear_beacon(struct rt2x00_dev *rt2x00dev,
660 struct ieee80211_vif *vif)
661{
662 struct rt2x00_intf *intf = vif_to_intf(vif);
663
664 if (unlikely(!intf->beacon))
665 return -ENOBUFS;
666
667 mutex_lock(&intf->beacon_skb_mutex);
668
669 /*
670 * Clean up the beacon skb.
671 */
672 rt2x00queue_free_skb(intf->beacon);
673
674 /*
675 * Clear beacon (single bssid devices don't need to clear the beacon
676 * since the beacon queue will get stopped anyway).
677 */
678 if (rt2x00dev->ops->lib->clear_beacon)
679 rt2x00dev->ops->lib->clear_beacon(intf->beacon);
680
681 mutex_unlock(&intf->beacon_skb_mutex);
682
683 return 0;
684}
685
8414ff07
HS
686int rt2x00queue_update_beacon_locked(struct rt2x00_dev *rt2x00dev,
687 struct ieee80211_vif *vif)
bd88a781
ID
688{
689 struct rt2x00_intf *intf = vif_to_intf(vif);
690 struct skb_frame_desc *skbdesc;
691 struct txentry_desc txdesc;
bd88a781
ID
692
693 if (unlikely(!intf->beacon))
694 return -ENOBUFS;
695
17512dc3
IP
696 /*
697 * Clean up the beacon skb.
698 */
fa69560f 699 rt2x00queue_free_skb(intf->beacon);
17512dc3 700
bd88a781 701 intf->beacon->skb = ieee80211_beacon_get(rt2x00dev->hw, vif);
8414ff07 702 if (!intf->beacon->skb)
bd88a781
ID
703 return -ENOMEM;
704
705 /*
706 * Copy all TX descriptor information into txdesc,
707 * after that we are free to use the skb->cb array
708 * for our information.
709 */
710 rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc);
711
bd88a781
ID
712 /*
713 * Fill in skb descriptor
714 */
715 skbdesc = get_skb_frame_desc(intf->beacon->skb);
716 memset(skbdesc, 0, sizeof(*skbdesc));
bd88a781
ID
717 skbdesc->entry = intf->beacon;
718
bd88a781 719 /*
69cf36a4 720 * Send beacon to hardware.
bd88a781 721 */
f224f4ef 722 rt2x00dev->ops->lib->write_beacon(intf->beacon, &txdesc);
bd88a781 723
8414ff07
HS
724 return 0;
725
726}
727
728int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev,
729 struct ieee80211_vif *vif)
730{
731 struct rt2x00_intf *intf = vif_to_intf(vif);
732 int ret;
733
734 mutex_lock(&intf->beacon_skb_mutex);
735 ret = rt2x00queue_update_beacon_locked(rt2x00dev, vif);
17512dc3
IP
736 mutex_unlock(&intf->beacon_skb_mutex);
737
8414ff07 738 return ret;
bd88a781
ID
739}
740
10e11568 741bool rt2x00queue_for_each_entry(struct data_queue *queue,
5eb7efe8
ID
742 enum queue_index start,
743 enum queue_index end,
10e11568
HS
744 void *data,
745 bool (*fn)(struct queue_entry *entry,
746 void *data))
5eb7efe8
ID
747{
748 unsigned long irqflags;
749 unsigned int index_start;
750 unsigned int index_end;
751 unsigned int i;
752
753 if (unlikely(start >= Q_INDEX_MAX || end >= Q_INDEX_MAX)) {
754 ERROR(queue->rt2x00dev,
755 "Entry requested from invalid index range (%d - %d)\n",
756 start, end);
10e11568 757 return true;
5eb7efe8
ID
758 }
759
760 /*
761 * Only protect the range we are going to loop over,
762 * if during our loop a extra entry is set to pending
763 * it should not be kicked during this run, since it
764 * is part of another TX operation.
765 */
813f0339 766 spin_lock_irqsave(&queue->index_lock, irqflags);
5eb7efe8
ID
767 index_start = queue->index[start];
768 index_end = queue->index[end];
813f0339 769 spin_unlock_irqrestore(&queue->index_lock, irqflags);
5eb7efe8
ID
770
771 /*
25985edc 772 * Start from the TX done pointer, this guarantees that we will
5eb7efe8
ID
773 * send out all frames in the correct order.
774 */
775 if (index_start < index_end) {
10e11568
HS
776 for (i = index_start; i < index_end; i++) {
777 if (fn(&queue->entries[i], data))
778 return true;
779 }
5eb7efe8 780 } else {
10e11568
HS
781 for (i = index_start; i < queue->limit; i++) {
782 if (fn(&queue->entries[i], data))
783 return true;
784 }
5eb7efe8 785
10e11568
HS
786 for (i = 0; i < index_end; i++) {
787 if (fn(&queue->entries[i], data))
788 return true;
789 }
5eb7efe8 790 }
10e11568
HS
791
792 return false;
5eb7efe8
ID
793}
794EXPORT_SYMBOL_GPL(rt2x00queue_for_each_entry);
795
181d6902
ID
796struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue,
797 enum queue_index index)
798{
799 struct queue_entry *entry;
5f46c4d0 800 unsigned long irqflags;
181d6902
ID
801
802 if (unlikely(index >= Q_INDEX_MAX)) {
803 ERROR(queue->rt2x00dev,
804 "Entry requested from invalid index type (%d)\n", index);
805 return NULL;
806 }
807
813f0339 808 spin_lock_irqsave(&queue->index_lock, irqflags);
181d6902
ID
809
810 entry = &queue->entries[queue->index[index]];
811
813f0339 812 spin_unlock_irqrestore(&queue->index_lock, irqflags);
181d6902
ID
813
814 return entry;
815}
816EXPORT_SYMBOL_GPL(rt2x00queue_get_entry);
817
75256f03 818void rt2x00queue_index_inc(struct queue_entry *entry, enum queue_index index)
181d6902 819{
75256f03 820 struct data_queue *queue = entry->queue;
5f46c4d0
ID
821 unsigned long irqflags;
822
181d6902
ID
823 if (unlikely(index >= Q_INDEX_MAX)) {
824 ERROR(queue->rt2x00dev,
825 "Index change on invalid index type (%d)\n", index);
826 return;
827 }
828
813f0339 829 spin_lock_irqsave(&queue->index_lock, irqflags);
181d6902
ID
830
831 queue->index[index]++;
832 if (queue->index[index] >= queue->limit)
833 queue->index[index] = 0;
834
75256f03 835 entry->last_action = jiffies;
652a9dd2 836
10b6b801
ID
837 if (index == Q_INDEX) {
838 queue->length++;
839 } else if (index == Q_INDEX_DONE) {
840 queue->length--;
55887511 841 queue->count++;
10b6b801 842 }
181d6902 843
813f0339 844 spin_unlock_irqrestore(&queue->index_lock, irqflags);
181d6902 845}
181d6902 846
0b7fde54
ID
847void rt2x00queue_pause_queue(struct data_queue *queue)
848{
849 if (!test_bit(DEVICE_STATE_PRESENT, &queue->rt2x00dev->flags) ||
850 !test_bit(QUEUE_STARTED, &queue->flags) ||
851 test_and_set_bit(QUEUE_PAUSED, &queue->flags))
852 return;
853
854 switch (queue->qid) {
f615e9a3
ID
855 case QID_AC_VO:
856 case QID_AC_VI:
0b7fde54
ID
857 case QID_AC_BE:
858 case QID_AC_BK:
0b7fde54
ID
859 /*
860 * For TX queues, we have to disable the queue
861 * inside mac80211.
862 */
863 ieee80211_stop_queue(queue->rt2x00dev->hw, queue->qid);
864 break;
865 default:
866 break;
867 }
868}
869EXPORT_SYMBOL_GPL(rt2x00queue_pause_queue);
870
871void rt2x00queue_unpause_queue(struct data_queue *queue)
872{
873 if (!test_bit(DEVICE_STATE_PRESENT, &queue->rt2x00dev->flags) ||
874 !test_bit(QUEUE_STARTED, &queue->flags) ||
875 !test_and_clear_bit(QUEUE_PAUSED, &queue->flags))
876 return;
877
878 switch (queue->qid) {
f615e9a3
ID
879 case QID_AC_VO:
880 case QID_AC_VI:
0b7fde54
ID
881 case QID_AC_BE:
882 case QID_AC_BK:
0b7fde54
ID
883 /*
884 * For TX queues, we have to enable the queue
885 * inside mac80211.
886 */
887 ieee80211_wake_queue(queue->rt2x00dev->hw, queue->qid);
888 break;
5be65609
ID
889 case QID_RX:
890 /*
891 * For RX we need to kick the queue now in order to
892 * receive frames.
893 */
894 queue->rt2x00dev->ops->lib->kick_queue(queue);
0b7fde54
ID
895 default:
896 break;
897 }
898}
899EXPORT_SYMBOL_GPL(rt2x00queue_unpause_queue);
900
901void rt2x00queue_start_queue(struct data_queue *queue)
902{
903 mutex_lock(&queue->status_lock);
904
905 if (!test_bit(DEVICE_STATE_PRESENT, &queue->rt2x00dev->flags) ||
906 test_and_set_bit(QUEUE_STARTED, &queue->flags)) {
907 mutex_unlock(&queue->status_lock);
908 return;
909 }
910
911 set_bit(QUEUE_PAUSED, &queue->flags);
912
913 queue->rt2x00dev->ops->lib->start_queue(queue);
914
915 rt2x00queue_unpause_queue(queue);
916
917 mutex_unlock(&queue->status_lock);
918}
919EXPORT_SYMBOL_GPL(rt2x00queue_start_queue);
920
921void rt2x00queue_stop_queue(struct data_queue *queue)
922{
923 mutex_lock(&queue->status_lock);
924
925 if (!test_and_clear_bit(QUEUE_STARTED, &queue->flags)) {
926 mutex_unlock(&queue->status_lock);
927 return;
928 }
929
930 rt2x00queue_pause_queue(queue);
931
932 queue->rt2x00dev->ops->lib->stop_queue(queue);
933
934 mutex_unlock(&queue->status_lock);
935}
936EXPORT_SYMBOL_GPL(rt2x00queue_stop_queue);
937
5be65609
ID
938void rt2x00queue_flush_queue(struct data_queue *queue, bool drop)
939{
5be65609
ID
940 bool started;
941 bool tx_queue =
f615e9a3 942 (queue->qid == QID_AC_VO) ||
5be65609 943 (queue->qid == QID_AC_VI) ||
f615e9a3
ID
944 (queue->qid == QID_AC_BE) ||
945 (queue->qid == QID_AC_BK);
5be65609
ID
946
947 mutex_lock(&queue->status_lock);
948
949 /*
950 * If the queue has been started, we must stop it temporarily
951 * to prevent any new frames to be queued on the device. If
952 * we are not dropping the pending frames, the queue must
953 * only be stopped in the software and not the hardware,
954 * otherwise the queue will never become empty on its own.
955 */
956 started = test_bit(QUEUE_STARTED, &queue->flags);
957 if (started) {
958 /*
959 * Pause the queue
960 */
961 rt2x00queue_pause_queue(queue);
962
963 /*
964 * If we are not supposed to drop any pending
965 * frames, this means we must force a start (=kick)
966 * to the queue to make sure the hardware will
967 * start transmitting.
968 */
969 if (!drop && tx_queue)
970 queue->rt2x00dev->ops->lib->kick_queue(queue);
971 }
972
973 /*
152a5992
ID
974 * Check if driver supports flushing, if that is the case we can
975 * defer the flushing to the driver. Otherwise we must use the
976 * alternative which just waits for the queue to become empty.
5be65609 977 */
152a5992
ID
978 if (likely(queue->rt2x00dev->ops->lib->flush_queue))
979 queue->rt2x00dev->ops->lib->flush_queue(queue, drop);
5be65609
ID
980
981 /*
982 * The queue flush has failed...
983 */
984 if (unlikely(!rt2x00queue_empty(queue)))
21957c31 985 WARNING(queue->rt2x00dev, "Queue %d failed to flush\n", queue->qid);
5be65609
ID
986
987 /*
988 * Restore the queue to the previous status
989 */
990 if (started)
991 rt2x00queue_unpause_queue(queue);
992
993 mutex_unlock(&queue->status_lock);
994}
995EXPORT_SYMBOL_GPL(rt2x00queue_flush_queue);
996
0b7fde54
ID
997void rt2x00queue_start_queues(struct rt2x00_dev *rt2x00dev)
998{
999 struct data_queue *queue;
1000
1001 /*
1002 * rt2x00queue_start_queue will call ieee80211_wake_queue
1003 * for each queue after is has been properly initialized.
1004 */
1005 tx_queue_for_each(rt2x00dev, queue)
1006 rt2x00queue_start_queue(queue);
1007
1008 rt2x00queue_start_queue(rt2x00dev->rx);
1009}
1010EXPORT_SYMBOL_GPL(rt2x00queue_start_queues);
1011
1012void rt2x00queue_stop_queues(struct rt2x00_dev *rt2x00dev)
1013{
1014 struct data_queue *queue;
1015
1016 /*
1017 * rt2x00queue_stop_queue will call ieee80211_stop_queue
1018 * as well, but we are completely shutting doing everything
1019 * now, so it is much safer to stop all TX queues at once,
1020 * and use rt2x00queue_stop_queue for cleaning up.
1021 */
1022 ieee80211_stop_queues(rt2x00dev->hw);
1023
1024 tx_queue_for_each(rt2x00dev, queue)
1025 rt2x00queue_stop_queue(queue);
1026
1027 rt2x00queue_stop_queue(rt2x00dev->rx);
1028}
1029EXPORT_SYMBOL_GPL(rt2x00queue_stop_queues);
1030
5be65609
ID
1031void rt2x00queue_flush_queues(struct rt2x00_dev *rt2x00dev, bool drop)
1032{
1033 struct data_queue *queue;
1034
1035 tx_queue_for_each(rt2x00dev, queue)
1036 rt2x00queue_flush_queue(queue, drop);
1037
1038 rt2x00queue_flush_queue(rt2x00dev->rx, drop);
1039}
1040EXPORT_SYMBOL_GPL(rt2x00queue_flush_queues);
1041
181d6902
ID
1042static void rt2x00queue_reset(struct data_queue *queue)
1043{
5f46c4d0 1044 unsigned long irqflags;
652a9dd2 1045 unsigned int i;
5f46c4d0 1046
813f0339 1047 spin_lock_irqsave(&queue->index_lock, irqflags);
181d6902
ID
1048
1049 queue->count = 0;
1050 queue->length = 0;
652a9dd2 1051
75256f03 1052 for (i = 0; i < Q_INDEX_MAX; i++)
652a9dd2 1053 queue->index[i] = 0;
181d6902 1054
813f0339 1055 spin_unlock_irqrestore(&queue->index_lock, irqflags);
181d6902
ID
1056}
1057
798b7adb 1058void rt2x00queue_init_queues(struct rt2x00_dev *rt2x00dev)
181d6902
ID
1059{
1060 struct data_queue *queue;
1061 unsigned int i;
1062
798b7adb 1063 queue_for_each(rt2x00dev, queue) {
181d6902
ID
1064 rt2x00queue_reset(queue);
1065
64e7d723 1066 for (i = 0; i < queue->limit; i++)
798b7adb 1067 rt2x00dev->ops->lib->clear_entry(&queue->entries[i]);
181d6902
ID
1068 }
1069}
1070
1071static int rt2x00queue_alloc_entries(struct data_queue *queue,
1072 const struct data_queue_desc *qdesc)
1073{
1074 struct queue_entry *entries;
1075 unsigned int entry_size;
1076 unsigned int i;
1077
1078 rt2x00queue_reset(queue);
1079
1080 queue->limit = qdesc->entry_num;
b869767b 1081 queue->threshold = DIV_ROUND_UP(qdesc->entry_num, 10);
181d6902
ID
1082 queue->data_size = qdesc->data_size;
1083 queue->desc_size = qdesc->desc_size;
1084
1085 /*
1086 * Allocate all queue entries.
1087 */
1088 entry_size = sizeof(*entries) + qdesc->priv_size;
baeb2ffa 1089 entries = kcalloc(queue->limit, entry_size, GFP_KERNEL);
181d6902
ID
1090 if (!entries)
1091 return -ENOMEM;
1092
1093#define QUEUE_ENTRY_PRIV_OFFSET(__base, __index, __limit, __esize, __psize) \
f8bfbc31
ME
1094 (((char *)(__base)) + ((__limit) * (__esize)) + \
1095 ((__index) * (__psize)))
181d6902
ID
1096
1097 for (i = 0; i < queue->limit; i++) {
1098 entries[i].flags = 0;
1099 entries[i].queue = queue;
1100 entries[i].skb = NULL;
1101 entries[i].entry_idx = i;
1102 entries[i].priv_data =
1103 QUEUE_ENTRY_PRIV_OFFSET(entries, i, queue->limit,
1104 sizeof(*entries), qdesc->priv_size);
1105 }
1106
1107#undef QUEUE_ENTRY_PRIV_OFFSET
1108
1109 queue->entries = entries;
1110
1111 return 0;
1112}
1113
fa69560f 1114static void rt2x00queue_free_skbs(struct data_queue *queue)
30caa6e3
GW
1115{
1116 unsigned int i;
1117
1118 if (!queue->entries)
1119 return;
1120
1121 for (i = 0; i < queue->limit; i++) {
fa69560f 1122 rt2x00queue_free_skb(&queue->entries[i]);
30caa6e3
GW
1123 }
1124}
1125
fa69560f 1126static int rt2x00queue_alloc_rxskbs(struct data_queue *queue)
30caa6e3
GW
1127{
1128 unsigned int i;
1129 struct sk_buff *skb;
1130
1131 for (i = 0; i < queue->limit; i++) {
fa69560f 1132 skb = rt2x00queue_alloc_rxskb(&queue->entries[i]);
30caa6e3 1133 if (!skb)
61243d8e 1134 return -ENOMEM;
30caa6e3
GW
1135 queue->entries[i].skb = skb;
1136 }
1137
1138 return 0;
30caa6e3
GW
1139}
1140
181d6902
ID
1141int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev)
1142{
1143 struct data_queue *queue;
1144 int status;
1145
181d6902
ID
1146 status = rt2x00queue_alloc_entries(rt2x00dev->rx, rt2x00dev->ops->rx);
1147 if (status)
1148 goto exit;
1149
1150 tx_queue_for_each(rt2x00dev, queue) {
1151 status = rt2x00queue_alloc_entries(queue, rt2x00dev->ops->tx);
1152 if (status)
1153 goto exit;
1154 }
1155
1156 status = rt2x00queue_alloc_entries(rt2x00dev->bcn, rt2x00dev->ops->bcn);
1157 if (status)
1158 goto exit;
1159
7dab73b3 1160 if (test_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags)) {
e74df4a7 1161 status = rt2x00queue_alloc_entries(rt2x00dev->atim,
30caa6e3
GW
1162 rt2x00dev->ops->atim);
1163 if (status)
1164 goto exit;
1165 }
181d6902 1166
fa69560f 1167 status = rt2x00queue_alloc_rxskbs(rt2x00dev->rx);
181d6902
ID
1168 if (status)
1169 goto exit;
1170
1171 return 0;
1172
1173exit:
1174 ERROR(rt2x00dev, "Queue entries allocation failed.\n");
1175
1176 rt2x00queue_uninitialize(rt2x00dev);
1177
1178 return status;
1179}
1180
1181void rt2x00queue_uninitialize(struct rt2x00_dev *rt2x00dev)
1182{
1183 struct data_queue *queue;
1184
fa69560f 1185 rt2x00queue_free_skbs(rt2x00dev->rx);
30caa6e3 1186
181d6902
ID
1187 queue_for_each(rt2x00dev, queue) {
1188 kfree(queue->entries);
1189 queue->entries = NULL;
1190 }
1191}
1192
8f539276
ID
1193static void rt2x00queue_init(struct rt2x00_dev *rt2x00dev,
1194 struct data_queue *queue, enum data_queue_qid qid)
1195{
0b7fde54 1196 mutex_init(&queue->status_lock);
77a861c4 1197 spin_lock_init(&queue->tx_lock);
813f0339 1198 spin_lock_init(&queue->index_lock);
8f539276
ID
1199
1200 queue->rt2x00dev = rt2x00dev;
1201 queue->qid = qid;
2af0a570 1202 queue->txop = 0;
8f539276
ID
1203 queue->aifs = 2;
1204 queue->cw_min = 5;
1205 queue->cw_max = 10;
1206}
1207
181d6902
ID
1208int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
1209{
1210 struct data_queue *queue;
1211 enum data_queue_qid qid;
1212 unsigned int req_atim =
7dab73b3 1213 !!test_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags);
181d6902
ID
1214
1215 /*
1216 * We need the following queues:
1217 * RX: 1
61448f88 1218 * TX: ops->tx_queues
181d6902
ID
1219 * Beacon: 1
1220 * Atim: 1 (if required)
1221 */
61448f88 1222 rt2x00dev->data_queues = 2 + rt2x00dev->ops->tx_queues + req_atim;
181d6902 1223
baeb2ffa 1224 queue = kcalloc(rt2x00dev->data_queues, sizeof(*queue), GFP_KERNEL);
181d6902
ID
1225 if (!queue) {
1226 ERROR(rt2x00dev, "Queue allocation failed.\n");
1227 return -ENOMEM;
1228 }
1229
1230 /*
1231 * Initialize pointers
1232 */
1233 rt2x00dev->rx = queue;
1234 rt2x00dev->tx = &queue[1];
61448f88 1235 rt2x00dev->bcn = &queue[1 + rt2x00dev->ops->tx_queues];
e74df4a7 1236 rt2x00dev->atim = req_atim ? &queue[2 + rt2x00dev->ops->tx_queues] : NULL;
181d6902
ID
1237
1238 /*
1239 * Initialize queue parameters.
1240 * RX: qid = QID_RX
f615e9a3 1241 * TX: qid = QID_AC_VO + index
181d6902
ID
1242 * TX: cw_min: 2^5 = 32.
1243 * TX: cw_max: 2^10 = 1024.
565a019a
ID
1244 * BCN: qid = QID_BEACON
1245 * ATIM: qid = QID_ATIM
181d6902 1246 */
8f539276 1247 rt2x00queue_init(rt2x00dev, rt2x00dev->rx, QID_RX);
181d6902 1248
f615e9a3 1249 qid = QID_AC_VO;
8f539276
ID
1250 tx_queue_for_each(rt2x00dev, queue)
1251 rt2x00queue_init(rt2x00dev, queue, qid++);
181d6902 1252
e74df4a7 1253 rt2x00queue_init(rt2x00dev, rt2x00dev->bcn, QID_BEACON);
181d6902 1254 if (req_atim)
e74df4a7 1255 rt2x00queue_init(rt2x00dev, rt2x00dev->atim, QID_ATIM);
181d6902
ID
1256
1257 return 0;
1258}
1259
1260void rt2x00queue_free(struct rt2x00_dev *rt2x00dev)
1261{
1262 kfree(rt2x00dev->rx);
1263 rt2x00dev->rx = NULL;
1264 rt2x00dev->tx = NULL;
1265 rt2x00dev->bcn = NULL;
1266}
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