Commit | Line | Data |
---|---|---|
181d6902 | 1 | /* |
7e613e16 ID |
2 | Copyright (C) 2010 Willow Garage <http://www.willowgarage.com> |
3 | Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com> | |
9c9a0d14 | 4 | Copyright (C) 2004 - 2009 Gertjan van Wingerde <gwingerde@gmail.com> |
181d6902 ID |
5 | <http://rt2x00.serialmonkey.com> |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; if not, write to the | |
19 | Free Software Foundation, Inc., | |
20 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
21 | */ | |
22 | ||
23 | /* | |
24 | Module: rt2x00lib | |
25 | Abstract: rt2x00 queue specific routines. | |
26 | */ | |
27 | ||
5a0e3ad6 | 28 | #include <linux/slab.h> |
181d6902 ID |
29 | #include <linux/kernel.h> |
30 | #include <linux/module.h> | |
c4da0048 | 31 | #include <linux/dma-mapping.h> |
181d6902 ID |
32 | |
33 | #include "rt2x00.h" | |
34 | #include "rt2x00lib.h" | |
35 | ||
88211021 | 36 | struct sk_buff *rt2x00queue_alloc_rxskb(struct queue_entry *entry, gfp_t gfp) |
239c249d | 37 | { |
fa69560f | 38 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; |
c4da0048 GW |
39 | struct sk_buff *skb; |
40 | struct skb_frame_desc *skbdesc; | |
2bb057d0 ID |
41 | unsigned int frame_size; |
42 | unsigned int head_size = 0; | |
43 | unsigned int tail_size = 0; | |
239c249d GW |
44 | |
45 | /* | |
46 | * The frame size includes descriptor size, because the | |
47 | * hardware directly receive the frame into the skbuffer. | |
48 | */ | |
c4da0048 | 49 | frame_size = entry->queue->data_size + entry->queue->desc_size; |
239c249d GW |
50 | |
51 | /* | |
ff352391 ID |
52 | * The payload should be aligned to a 4-byte boundary, |
53 | * this means we need at least 3 bytes for moving the frame | |
54 | * into the correct offset. | |
239c249d | 55 | */ |
2bb057d0 ID |
56 | head_size = 4; |
57 | ||
58 | /* | |
59 | * For IV/EIV/ICV assembly we must make sure there is | |
60 | * at least 8 bytes bytes available in headroom for IV/EIV | |
9c3444d3 | 61 | * and 8 bytes for ICV data as tailroon. |
2bb057d0 | 62 | */ |
7dab73b3 | 63 | if (test_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags)) { |
2bb057d0 | 64 | head_size += 8; |
9c3444d3 | 65 | tail_size += 8; |
2bb057d0 | 66 | } |
239c249d GW |
67 | |
68 | /* | |
69 | * Allocate skbuffer. | |
70 | */ | |
88211021 | 71 | skb = __dev_alloc_skb(frame_size + head_size + tail_size, gfp); |
239c249d GW |
72 | if (!skb) |
73 | return NULL; | |
74 | ||
2bb057d0 ID |
75 | /* |
76 | * Make sure we not have a frame with the requested bytes | |
77 | * available in the head and tail. | |
78 | */ | |
79 | skb_reserve(skb, head_size); | |
239c249d GW |
80 | skb_put(skb, frame_size); |
81 | ||
c4da0048 GW |
82 | /* |
83 | * Populate skbdesc. | |
84 | */ | |
85 | skbdesc = get_skb_frame_desc(skb); | |
86 | memset(skbdesc, 0, sizeof(*skbdesc)); | |
87 | skbdesc->entry = entry; | |
88 | ||
7dab73b3 | 89 | if (test_bit(REQUIRE_DMA, &rt2x00dev->cap_flags)) { |
c4da0048 GW |
90 | skbdesc->skb_dma = dma_map_single(rt2x00dev->dev, |
91 | skb->data, | |
92 | skb->len, | |
93 | DMA_FROM_DEVICE); | |
94 | skbdesc->flags |= SKBDESC_DMA_MAPPED_RX; | |
95 | } | |
96 | ||
239c249d GW |
97 | return skb; |
98 | } | |
30caa6e3 | 99 | |
fa69560f | 100 | void rt2x00queue_map_txskb(struct queue_entry *entry) |
30caa6e3 | 101 | { |
fa69560f ID |
102 | struct device *dev = entry->queue->rt2x00dev->dev; |
103 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); | |
c4da0048 | 104 | |
3ee54a07 | 105 | skbdesc->skb_dma = |
fa69560f | 106 | dma_map_single(dev, entry->skb->data, entry->skb->len, DMA_TO_DEVICE); |
c4da0048 GW |
107 | skbdesc->flags |= SKBDESC_DMA_MAPPED_TX; |
108 | } | |
109 | EXPORT_SYMBOL_GPL(rt2x00queue_map_txskb); | |
110 | ||
fa69560f | 111 | void rt2x00queue_unmap_skb(struct queue_entry *entry) |
c4da0048 | 112 | { |
fa69560f ID |
113 | struct device *dev = entry->queue->rt2x00dev->dev; |
114 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); | |
c4da0048 GW |
115 | |
116 | if (skbdesc->flags & SKBDESC_DMA_MAPPED_RX) { | |
fa69560f | 117 | dma_unmap_single(dev, skbdesc->skb_dma, entry->skb->len, |
c4da0048 GW |
118 | DMA_FROM_DEVICE); |
119 | skbdesc->flags &= ~SKBDESC_DMA_MAPPED_RX; | |
546adf29 | 120 | } else if (skbdesc->flags & SKBDESC_DMA_MAPPED_TX) { |
fa69560f | 121 | dma_unmap_single(dev, skbdesc->skb_dma, entry->skb->len, |
c4da0048 GW |
122 | DMA_TO_DEVICE); |
123 | skbdesc->flags &= ~SKBDESC_DMA_MAPPED_TX; | |
124 | } | |
125 | } | |
0b8004aa | 126 | EXPORT_SYMBOL_GPL(rt2x00queue_unmap_skb); |
c4da0048 | 127 | |
fa69560f | 128 | void rt2x00queue_free_skb(struct queue_entry *entry) |
c4da0048 | 129 | { |
fa69560f | 130 | if (!entry->skb) |
9a613195 ID |
131 | return; |
132 | ||
fa69560f ID |
133 | rt2x00queue_unmap_skb(entry); |
134 | dev_kfree_skb_any(entry->skb); | |
135 | entry->skb = NULL; | |
30caa6e3 | 136 | } |
239c249d | 137 | |
daee6c09 | 138 | void rt2x00queue_align_frame(struct sk_buff *skb) |
9f166171 | 139 | { |
9f166171 | 140 | unsigned int frame_length = skb->len; |
daee6c09 | 141 | unsigned int align = ALIGN_SIZE(skb, 0); |
9f166171 ID |
142 | |
143 | if (!align) | |
144 | return; | |
145 | ||
daee6c09 ID |
146 | skb_push(skb, align); |
147 | memmove(skb->data, skb->data + align, frame_length); | |
148 | skb_trim(skb, frame_length); | |
149 | } | |
150 | ||
daee6c09 ID |
151 | void rt2x00queue_insert_l2pad(struct sk_buff *skb, unsigned int header_length) |
152 | { | |
2e331462 | 153 | unsigned int payload_length = skb->len - header_length; |
daee6c09 ID |
154 | unsigned int header_align = ALIGN_SIZE(skb, 0); |
155 | unsigned int payload_align = ALIGN_SIZE(skb, header_length); | |
e54be4e7 | 156 | unsigned int l2pad = payload_length ? L2PAD_SIZE(header_length) : 0; |
daee6c09 | 157 | |
2e331462 GW |
158 | /* |
159 | * Adjust the header alignment if the payload needs to be moved more | |
160 | * than the header. | |
161 | */ | |
162 | if (payload_align > header_align) | |
163 | header_align += 4; | |
164 | ||
165 | /* There is nothing to do if no alignment is needed */ | |
166 | if (!header_align) | |
167 | return; | |
daee6c09 | 168 | |
2e331462 GW |
169 | /* Reserve the amount of space needed in front of the frame */ |
170 | skb_push(skb, header_align); | |
171 | ||
172 | /* | |
173 | * Move the header. | |
174 | */ | |
175 | memmove(skb->data, skb->data + header_align, header_length); | |
176 | ||
177 | /* Move the payload, if present and if required */ | |
178 | if (payload_length && payload_align) | |
daee6c09 | 179 | memmove(skb->data + header_length + l2pad, |
a5186e99 | 180 | skb->data + header_length + l2pad + payload_align, |
2e331462 GW |
181 | payload_length); |
182 | ||
183 | /* Trim the skb to the correct size */ | |
184 | skb_trim(skb, header_length + l2pad + payload_length); | |
9f166171 ID |
185 | } |
186 | ||
daee6c09 ID |
187 | void rt2x00queue_remove_l2pad(struct sk_buff *skb, unsigned int header_length) |
188 | { | |
a061a93b GW |
189 | /* |
190 | * L2 padding is only present if the skb contains more than just the | |
191 | * IEEE 802.11 header. | |
192 | */ | |
193 | unsigned int l2pad = (skb->len > header_length) ? | |
194 | L2PAD_SIZE(header_length) : 0; | |
daee6c09 | 195 | |
354e39db | 196 | if (!l2pad) |
daee6c09 ID |
197 | return; |
198 | ||
a061a93b GW |
199 | memmove(skb->data + l2pad, skb->data, header_length); |
200 | skb_pull(skb, l2pad); | |
daee6c09 ID |
201 | } |
202 | ||
77b5621b GW |
203 | static void rt2x00queue_create_tx_descriptor_seq(struct rt2x00_dev *rt2x00dev, |
204 | struct sk_buff *skb, | |
7b40982e ID |
205 | struct txentry_desc *txdesc) |
206 | { | |
77b5621b GW |
207 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
208 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
7b40982e | 209 | struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif); |
e5851dac | 210 | u16 seqno; |
7b40982e | 211 | |
c262e08b | 212 | if (!(tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)) |
7b40982e ID |
213 | return; |
214 | ||
7fe7ee77 HS |
215 | __set_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags); |
216 | ||
e66a8ddf SG |
217 | if (!test_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags)) { |
218 | /* | |
219 | * rt2800 has a H/W (or F/W) bug, device incorrectly increase | |
220 | * seqno on retransmited data (non-QOS) frames. To workaround | |
221 | * the problem let's generate seqno in software if QOS is | |
222 | * disabled. | |
223 | */ | |
224 | if (test_bit(CONFIG_QOS_DISABLED, &rt2x00dev->flags)) | |
225 | __clear_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags); | |
226 | else | |
227 | /* H/W will generate sequence number */ | |
228 | return; | |
229 | } | |
7fe7ee77 | 230 | |
7b40982e | 231 | /* |
7fe7ee77 HS |
232 | * The hardware is not able to insert a sequence number. Assign a |
233 | * software generated one here. | |
7b40982e ID |
234 | * |
235 | * This is wrong because beacons are not getting sequence | |
236 | * numbers assigned properly. | |
237 | * | |
238 | * A secondary problem exists for drivers that cannot toggle | |
239 | * sequence counting per-frame, since those will override the | |
240 | * sequence counter given by mac80211. | |
241 | */ | |
7b40982e | 242 | if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags)) |
e5851dac SG |
243 | seqno = atomic_add_return(0x10, &intf->seqno); |
244 | else | |
245 | seqno = atomic_read(&intf->seqno); | |
7b40982e | 246 | |
e5851dac SG |
247 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); |
248 | hdr->seq_ctrl |= cpu_to_le16(seqno); | |
7b40982e ID |
249 | } |
250 | ||
77b5621b GW |
251 | static void rt2x00queue_create_tx_descriptor_plcp(struct rt2x00_dev *rt2x00dev, |
252 | struct sk_buff *skb, | |
7b40982e ID |
253 | struct txentry_desc *txdesc, |
254 | const struct rt2x00_rate *hwrate) | |
255 | { | |
77b5621b | 256 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
7b40982e ID |
257 | struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0]; |
258 | unsigned int data_length; | |
259 | unsigned int duration; | |
260 | unsigned int residual; | |
261 | ||
2517794b HS |
262 | /* |
263 | * Determine with what IFS priority this frame should be send. | |
264 | * Set ifs to IFS_SIFS when the this is not the first fragment, | |
265 | * or this fragment came after RTS/CTS. | |
266 | */ | |
267 | if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags)) | |
268 | txdesc->u.plcp.ifs = IFS_BACKOFF; | |
269 | else | |
270 | txdesc->u.plcp.ifs = IFS_SIFS; | |
271 | ||
7b40982e | 272 | /* Data length + CRC + Crypto overhead (IV/EIV/ICV/MIC) */ |
77b5621b GW |
273 | data_length = skb->len + 4; |
274 | data_length += rt2x00crypto_tx_overhead(rt2x00dev, skb); | |
7b40982e ID |
275 | |
276 | /* | |
277 | * PLCP setup | |
278 | * Length calculation depends on OFDM/CCK rate. | |
279 | */ | |
26a1d07f HS |
280 | txdesc->u.plcp.signal = hwrate->plcp; |
281 | txdesc->u.plcp.service = 0x04; | |
7b40982e ID |
282 | |
283 | if (hwrate->flags & DEV_RATE_OFDM) { | |
26a1d07f HS |
284 | txdesc->u.plcp.length_high = (data_length >> 6) & 0x3f; |
285 | txdesc->u.plcp.length_low = data_length & 0x3f; | |
7b40982e ID |
286 | } else { |
287 | /* | |
288 | * Convert length to microseconds. | |
289 | */ | |
290 | residual = GET_DURATION_RES(data_length, hwrate->bitrate); | |
291 | duration = GET_DURATION(data_length, hwrate->bitrate); | |
292 | ||
293 | if (residual != 0) { | |
294 | duration++; | |
295 | ||
296 | /* | |
297 | * Check if we need to set the Length Extension | |
298 | */ | |
299 | if (hwrate->bitrate == 110 && residual <= 30) | |
26a1d07f | 300 | txdesc->u.plcp.service |= 0x80; |
7b40982e ID |
301 | } |
302 | ||
26a1d07f HS |
303 | txdesc->u.plcp.length_high = (duration >> 8) & 0xff; |
304 | txdesc->u.plcp.length_low = duration & 0xff; | |
7b40982e ID |
305 | |
306 | /* | |
307 | * When preamble is enabled we should set the | |
308 | * preamble bit for the signal. | |
309 | */ | |
310 | if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) | |
26a1d07f | 311 | txdesc->u.plcp.signal |= 0x08; |
7b40982e ID |
312 | } |
313 | } | |
314 | ||
77b5621b GW |
315 | static void rt2x00queue_create_tx_descriptor_ht(struct rt2x00_dev *rt2x00dev, |
316 | struct sk_buff *skb, | |
46a01ec0 GW |
317 | struct txentry_desc *txdesc, |
318 | const struct rt2x00_rate *hwrate) | |
319 | { | |
77b5621b | 320 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
46a01ec0 | 321 | struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0]; |
77b5621b | 322 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
ead2bb64 | 323 | struct rt2x00_sta *sta_priv = NULL; |
46a01ec0 | 324 | |
ead2bb64 | 325 | if (tx_info->control.sta) { |
46a01ec0 GW |
326 | txdesc->u.ht.mpdu_density = |
327 | tx_info->control.sta->ht_cap.ampdu_density; | |
328 | ||
ead2bb64 HS |
329 | sta_priv = sta_to_rt2x00_sta(tx_info->control.sta); |
330 | txdesc->u.ht.wcid = sta_priv->wcid; | |
331 | } | |
332 | ||
46a01ec0 GW |
333 | /* |
334 | * If IEEE80211_TX_RC_MCS is set txrate->idx just contains the | |
335 | * mcs rate to be used | |
336 | */ | |
337 | if (txrate->flags & IEEE80211_TX_RC_MCS) { | |
338 | txdesc->u.ht.mcs = txrate->idx; | |
339 | ||
340 | /* | |
341 | * MIMO PS should be set to 1 for STA's using dynamic SM PS | |
342 | * when using more then one tx stream (>MCS7). | |
343 | */ | |
344 | if (tx_info->control.sta && txdesc->u.ht.mcs > 7 && | |
345 | ((tx_info->control.sta->ht_cap.cap & | |
346 | IEEE80211_HT_CAP_SM_PS) >> | |
347 | IEEE80211_HT_CAP_SM_PS_SHIFT) == | |
348 | WLAN_HT_CAP_SM_PS_DYNAMIC) | |
349 | __set_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags); | |
350 | } else { | |
351 | txdesc->u.ht.mcs = rt2x00_get_rate_mcs(hwrate->mcs); | |
352 | if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) | |
353 | txdesc->u.ht.mcs |= 0x08; | |
354 | } | |
355 | ||
da40f407 SG |
356 | if (test_bit(CONFIG_HT_DISABLED, &rt2x00dev->flags)) { |
357 | if (!(tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)) | |
358 | txdesc->u.ht.txop = TXOP_SIFS; | |
359 | else | |
360 | txdesc->u.ht.txop = TXOP_BACKOFF; | |
361 | ||
362 | /* Left zero on all other settings. */ | |
363 | return; | |
364 | } | |
365 | ||
366 | txdesc->u.ht.ba_size = 7; /* FIXME: What value is needed? */ | |
367 | ||
368 | /* | |
369 | * Only one STBC stream is supported for now. | |
370 | */ | |
371 | if (tx_info->flags & IEEE80211_TX_CTL_STBC) | |
372 | txdesc->u.ht.stbc = 1; | |
373 | ||
46a01ec0 GW |
374 | /* |
375 | * This frame is eligible for an AMPDU, however, don't aggregate | |
376 | * frames that are intended to probe a specific tx rate. | |
377 | */ | |
378 | if (tx_info->flags & IEEE80211_TX_CTL_AMPDU && | |
379 | !(tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) | |
380 | __set_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags); | |
381 | ||
382 | /* | |
383 | * Set 40Mhz mode if necessary (for legacy rates this will | |
384 | * duplicate the frame to both channels). | |
385 | */ | |
386 | if (txrate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH || | |
387 | txrate->flags & IEEE80211_TX_RC_DUP_DATA) | |
388 | __set_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags); | |
389 | if (txrate->flags & IEEE80211_TX_RC_SHORT_GI) | |
390 | __set_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags); | |
391 | ||
392 | /* | |
393 | * Determine IFS values | |
394 | * - Use TXOP_BACKOFF for management frames except beacons | |
395 | * - Use TXOP_SIFS for fragment bursts | |
396 | * - Use TXOP_HTTXOP for everything else | |
397 | * | |
398 | * Note: rt2800 devices won't use CTS protection (if used) | |
399 | * for frames not transmitted with TXOP_HTTXOP | |
400 | */ | |
401 | if (ieee80211_is_mgmt(hdr->frame_control) && | |
402 | !ieee80211_is_beacon(hdr->frame_control)) | |
403 | txdesc->u.ht.txop = TXOP_BACKOFF; | |
404 | else if (!(tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)) | |
405 | txdesc->u.ht.txop = TXOP_SIFS; | |
406 | else | |
407 | txdesc->u.ht.txop = TXOP_HTTXOP; | |
408 | } | |
409 | ||
77b5621b GW |
410 | static void rt2x00queue_create_tx_descriptor(struct rt2x00_dev *rt2x00dev, |
411 | struct sk_buff *skb, | |
bd88a781 | 412 | struct txentry_desc *txdesc) |
7050ec82 | 413 | { |
77b5621b GW |
414 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
415 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
55b585e2 HS |
416 | struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0]; |
417 | struct ieee80211_rate *rate; | |
418 | const struct rt2x00_rate *hwrate = NULL; | |
7050ec82 ID |
419 | |
420 | memset(txdesc, 0, sizeof(*txdesc)); | |
421 | ||
9f166171 | 422 | /* |
df624ca5 | 423 | * Header and frame information. |
9f166171 | 424 | */ |
77b5621b GW |
425 | txdesc->length = skb->len; |
426 | txdesc->header_length = ieee80211_get_hdrlen_from_skb(skb); | |
9f166171 | 427 | |
7050ec82 ID |
428 | /* |
429 | * Check whether this frame is to be acked. | |
430 | */ | |
e039fa4a | 431 | if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK)) |
7050ec82 ID |
432 | __set_bit(ENTRY_TXD_ACK, &txdesc->flags); |
433 | ||
434 | /* | |
435 | * Check if this is a RTS/CTS frame | |
436 | */ | |
ac104462 ID |
437 | if (ieee80211_is_rts(hdr->frame_control) || |
438 | ieee80211_is_cts(hdr->frame_control)) { | |
7050ec82 | 439 | __set_bit(ENTRY_TXD_BURST, &txdesc->flags); |
ac104462 | 440 | if (ieee80211_is_rts(hdr->frame_control)) |
7050ec82 | 441 | __set_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags); |
e039fa4a | 442 | else |
7050ec82 | 443 | __set_bit(ENTRY_TXD_CTS_FRAME, &txdesc->flags); |
e039fa4a | 444 | if (tx_info->control.rts_cts_rate_idx >= 0) |
2e92e6f2 | 445 | rate = |
e039fa4a | 446 | ieee80211_get_rts_cts_rate(rt2x00dev->hw, tx_info); |
7050ec82 ID |
447 | } |
448 | ||
449 | /* | |
450 | * Determine retry information. | |
451 | */ | |
e6a9854b | 452 | txdesc->retry_limit = tx_info->control.rates[0].count - 1; |
42c82857 | 453 | if (txdesc->retry_limit >= rt2x00dev->long_retry) |
7050ec82 ID |
454 | __set_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags); |
455 | ||
456 | /* | |
457 | * Check if more fragments are pending | |
458 | */ | |
2606e422 | 459 | if (ieee80211_has_morefrags(hdr->frame_control)) { |
7050ec82 ID |
460 | __set_bit(ENTRY_TXD_BURST, &txdesc->flags); |
461 | __set_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags); | |
462 | } | |
463 | ||
2606e422 HS |
464 | /* |
465 | * Check if more frames (!= fragments) are pending | |
466 | */ | |
467 | if (tx_info->flags & IEEE80211_TX_CTL_MORE_FRAMES) | |
468 | __set_bit(ENTRY_TXD_BURST, &txdesc->flags); | |
469 | ||
7050ec82 ID |
470 | /* |
471 | * Beacons and probe responses require the tsf timestamp | |
1bce85cf | 472 | * to be inserted into the frame. |
7050ec82 | 473 | */ |
1bce85cf HS |
474 | if (ieee80211_is_beacon(hdr->frame_control) || |
475 | ieee80211_is_probe_resp(hdr->frame_control)) | |
7050ec82 ID |
476 | __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags); |
477 | ||
7b40982e | 478 | if ((tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) && |
2517794b | 479 | !test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)) |
7050ec82 | 480 | __set_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags); |
7050ec82 | 481 | |
076f9582 ID |
482 | /* |
483 | * Determine rate modulation. | |
484 | */ | |
55b585e2 HS |
485 | if (txrate->flags & IEEE80211_TX_RC_GREEN_FIELD) |
486 | txdesc->rate_mode = RATE_MODE_HT_GREENFIELD; | |
487 | else if (txrate->flags & IEEE80211_TX_RC_MCS) | |
488 | txdesc->rate_mode = RATE_MODE_HT_MIX; | |
489 | else { | |
490 | rate = ieee80211_get_tx_rate(rt2x00dev->hw, tx_info); | |
491 | hwrate = rt2x00_get_rate(rate->hw_value); | |
492 | if (hwrate->flags & DEV_RATE_OFDM) | |
493 | txdesc->rate_mode = RATE_MODE_OFDM; | |
494 | else | |
495 | txdesc->rate_mode = RATE_MODE_CCK; | |
496 | } | |
7050ec82 | 497 | |
7b40982e ID |
498 | /* |
499 | * Apply TX descriptor handling by components | |
500 | */ | |
77b5621b GW |
501 | rt2x00crypto_create_tx_descriptor(rt2x00dev, skb, txdesc); |
502 | rt2x00queue_create_tx_descriptor_seq(rt2x00dev, skb, txdesc); | |
26a1d07f | 503 | |
7dab73b3 | 504 | if (test_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags)) |
77b5621b GW |
505 | rt2x00queue_create_tx_descriptor_ht(rt2x00dev, skb, txdesc, |
506 | hwrate); | |
26a1d07f | 507 | else |
77b5621b GW |
508 | rt2x00queue_create_tx_descriptor_plcp(rt2x00dev, skb, txdesc, |
509 | hwrate); | |
7050ec82 | 510 | } |
7050ec82 | 511 | |
78eea11b GW |
512 | static int rt2x00queue_write_tx_data(struct queue_entry *entry, |
513 | struct txentry_desc *txdesc) | |
514 | { | |
515 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; | |
516 | ||
517 | /* | |
518 | * This should not happen, we already checked the entry | |
519 | * was ours. When the hardware disagrees there has been | |
520 | * a queue corruption! | |
521 | */ | |
522 | if (unlikely(rt2x00dev->ops->lib->get_entry_state && | |
523 | rt2x00dev->ops->lib->get_entry_state(entry))) { | |
524 | ERROR(rt2x00dev, | |
525 | "Corrupt queue %d, accessing entry which is not ours.\n" | |
526 | "Please file bug report to %s.\n", | |
527 | entry->queue->qid, DRV_PROJECT); | |
528 | return -EINVAL; | |
529 | } | |
530 | ||
531 | /* | |
532 | * Add the requested extra tx headroom in front of the skb. | |
533 | */ | |
534 | skb_push(entry->skb, rt2x00dev->ops->extra_tx_headroom); | |
535 | memset(entry->skb->data, 0, rt2x00dev->ops->extra_tx_headroom); | |
536 | ||
537 | /* | |
76dd5ddf | 538 | * Call the driver's write_tx_data function, if it exists. |
78eea11b | 539 | */ |
76dd5ddf GW |
540 | if (rt2x00dev->ops->lib->write_tx_data) |
541 | rt2x00dev->ops->lib->write_tx_data(entry, txdesc); | |
78eea11b GW |
542 | |
543 | /* | |
544 | * Map the skb to DMA. | |
545 | */ | |
7dab73b3 | 546 | if (test_bit(REQUIRE_DMA, &rt2x00dev->cap_flags)) |
fa69560f | 547 | rt2x00queue_map_txskb(entry); |
78eea11b GW |
548 | |
549 | return 0; | |
550 | } | |
551 | ||
bd88a781 ID |
552 | static void rt2x00queue_write_tx_descriptor(struct queue_entry *entry, |
553 | struct txentry_desc *txdesc) | |
7050ec82 | 554 | { |
b869767b | 555 | struct data_queue *queue = entry->queue; |
7050ec82 | 556 | |
93331458 | 557 | queue->rt2x00dev->ops->lib->write_tx_desc(entry, txdesc); |
7050ec82 ID |
558 | |
559 | /* | |
560 | * All processing on the frame has been completed, this means | |
561 | * it is now ready to be dumped to userspace through debugfs. | |
562 | */ | |
93331458 | 563 | rt2x00debug_dump_frame(queue->rt2x00dev, DUMP_FRAME_TX, entry->skb); |
6295d815 GW |
564 | } |
565 | ||
8be4eed0 | 566 | static void rt2x00queue_kick_tx_queue(struct data_queue *queue, |
6295d815 GW |
567 | struct txentry_desc *txdesc) |
568 | { | |
7050ec82 | 569 | /* |
b869767b | 570 | * Check if we need to kick the queue, there are however a few rules |
6295d815 | 571 | * 1) Don't kick unless this is the last in frame in a burst. |
b869767b ID |
572 | * When the burst flag is set, this frame is always followed |
573 | * by another frame which in some way are related to eachother. | |
574 | * This is true for fragments, RTS or CTS-to-self frames. | |
6295d815 | 575 | * 2) Rule 1 can be broken when the available entries |
b869767b | 576 | * in the queue are less then a certain threshold. |
7050ec82 | 577 | */ |
b869767b ID |
578 | if (rt2x00queue_threshold(queue) || |
579 | !test_bit(ENTRY_TXD_BURST, &txdesc->flags)) | |
dbba306f | 580 | queue->rt2x00dev->ops->lib->kick_queue(queue); |
7050ec82 | 581 | } |
7050ec82 | 582 | |
7351c6bd JB |
583 | int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb, |
584 | bool local) | |
6db3786a | 585 | { |
e6a9854b | 586 | struct ieee80211_tx_info *tx_info; |
77a861c4 | 587 | struct queue_entry *entry; |
6db3786a | 588 | struct txentry_desc txdesc; |
d74f5ba4 | 589 | struct skb_frame_desc *skbdesc; |
e6a9854b | 590 | u8 rate_idx, rate_flags; |
77a861c4 GW |
591 | int ret = 0; |
592 | ||
6db3786a ID |
593 | /* |
594 | * Copy all TX descriptor information into txdesc, | |
595 | * after that we are free to use the skb->cb array | |
596 | * for our information. | |
597 | */ | |
77b5621b | 598 | rt2x00queue_create_tx_descriptor(queue->rt2x00dev, skb, &txdesc); |
6db3786a | 599 | |
d74f5ba4 | 600 | /* |
e6a9854b | 601 | * All information is retrieved from the skb->cb array, |
2bb057d0 | 602 | * now we should claim ownership of the driver part of that |
e6a9854b | 603 | * array, preserving the bitrate index and flags. |
d74f5ba4 | 604 | */ |
e6a9854b JB |
605 | tx_info = IEEE80211_SKB_CB(skb); |
606 | rate_idx = tx_info->control.rates[0].idx; | |
607 | rate_flags = tx_info->control.rates[0].flags; | |
0e3de998 | 608 | skbdesc = get_skb_frame_desc(skb); |
d74f5ba4 | 609 | memset(skbdesc, 0, sizeof(*skbdesc)); |
e6a9854b JB |
610 | skbdesc->tx_rate_idx = rate_idx; |
611 | skbdesc->tx_rate_flags = rate_flags; | |
d74f5ba4 | 612 | |
7351c6bd JB |
613 | if (local) |
614 | skbdesc->flags |= SKBDESC_NOT_MAC80211; | |
615 | ||
2bb057d0 ID |
616 | /* |
617 | * When hardware encryption is supported, and this frame | |
618 | * is to be encrypted, we should strip the IV/EIV data from | |
3ad2f3fb | 619 | * the frame so we can provide it to the driver separately. |
2bb057d0 ID |
620 | */ |
621 | if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc.flags) && | |
dddfb478 | 622 | !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc.flags)) { |
7dab73b3 | 623 | if (test_bit(REQUIRE_COPY_IV, &queue->rt2x00dev->cap_flags)) |
9eb4e21e | 624 | rt2x00crypto_tx_copy_iv(skb, &txdesc); |
dddfb478 | 625 | else |
9eb4e21e | 626 | rt2x00crypto_tx_remove_iv(skb, &txdesc); |
dddfb478 | 627 | } |
2bb057d0 | 628 | |
93354cbb | 629 | /* |
25985edc | 630 | * When DMA allocation is required we should guarantee to the |
93354cbb | 631 | * driver that the DMA is aligned to a 4-byte boundary. |
93354cbb ID |
632 | * However some drivers require L2 padding to pad the payload |
633 | * rather then the header. This could be a requirement for | |
634 | * PCI and USB devices, while header alignment only is valid | |
635 | * for PCI devices. | |
636 | */ | |
7dab73b3 | 637 | if (test_bit(REQUIRE_L2PAD, &queue->rt2x00dev->cap_flags)) |
128f8f77 | 638 | rt2x00queue_insert_l2pad(skb, txdesc.header_length); |
7dab73b3 | 639 | else if (test_bit(REQUIRE_DMA, &queue->rt2x00dev->cap_flags)) |
128f8f77 GW |
640 | rt2x00queue_align_frame(skb); |
641 | ||
3780d038 SG |
642 | /* |
643 | * That function must be called with bh disabled. | |
644 | */ | |
128f8f77 GW |
645 | spin_lock(&queue->tx_lock); |
646 | ||
647 | if (unlikely(rt2x00queue_full(queue))) { | |
648 | ERROR(queue->rt2x00dev, | |
649 | "Dropping frame due to full tx queue %d.\n", queue->qid); | |
650 | ret = -ENOBUFS; | |
651 | goto out; | |
652 | } | |
653 | ||
654 | entry = rt2x00queue_get_entry(queue, Q_INDEX); | |
655 | ||
656 | if (unlikely(test_and_set_bit(ENTRY_OWNER_DEVICE_DATA, | |
657 | &entry->flags))) { | |
658 | ERROR(queue->rt2x00dev, | |
659 | "Arrived at non-free entry in the non-full queue %d.\n" | |
660 | "Please file bug report to %s.\n", | |
661 | queue->qid, DRV_PROJECT); | |
662 | ret = -EINVAL; | |
663 | goto out; | |
664 | } | |
665 | ||
666 | skbdesc->entry = entry; | |
667 | entry->skb = skb; | |
9f166171 | 668 | |
2bb057d0 ID |
669 | /* |
670 | * It could be possible that the queue was corrupted and this | |
0e3de998 ID |
671 | * call failed. Since we always return NETDEV_TX_OK to mac80211, |
672 | * this frame will simply be dropped. | |
2bb057d0 | 673 | */ |
78eea11b | 674 | if (unlikely(rt2x00queue_write_tx_data(entry, &txdesc))) { |
0262ab0d | 675 | clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags); |
2bb057d0 | 676 | entry->skb = NULL; |
77a861c4 GW |
677 | ret = -EIO; |
678 | goto out; | |
6db3786a ID |
679 | } |
680 | ||
0262ab0d | 681 | set_bit(ENTRY_DATA_PENDING, &entry->flags); |
6db3786a | 682 | |
75256f03 | 683 | rt2x00queue_index_inc(entry, Q_INDEX); |
6db3786a | 684 | rt2x00queue_write_tx_descriptor(entry, &txdesc); |
8be4eed0 | 685 | rt2x00queue_kick_tx_queue(queue, &txdesc); |
6db3786a | 686 | |
77a861c4 GW |
687 | out: |
688 | spin_unlock(&queue->tx_lock); | |
689 | return ret; | |
6db3786a ID |
690 | } |
691 | ||
69cf36a4 HS |
692 | int rt2x00queue_clear_beacon(struct rt2x00_dev *rt2x00dev, |
693 | struct ieee80211_vif *vif) | |
694 | { | |
695 | struct rt2x00_intf *intf = vif_to_intf(vif); | |
696 | ||
697 | if (unlikely(!intf->beacon)) | |
698 | return -ENOBUFS; | |
699 | ||
700 | mutex_lock(&intf->beacon_skb_mutex); | |
701 | ||
702 | /* | |
703 | * Clean up the beacon skb. | |
704 | */ | |
705 | rt2x00queue_free_skb(intf->beacon); | |
706 | ||
707 | /* | |
708 | * Clear beacon (single bssid devices don't need to clear the beacon | |
709 | * since the beacon queue will get stopped anyway). | |
710 | */ | |
711 | if (rt2x00dev->ops->lib->clear_beacon) | |
712 | rt2x00dev->ops->lib->clear_beacon(intf->beacon); | |
713 | ||
714 | mutex_unlock(&intf->beacon_skb_mutex); | |
715 | ||
716 | return 0; | |
717 | } | |
718 | ||
8414ff07 HS |
719 | int rt2x00queue_update_beacon_locked(struct rt2x00_dev *rt2x00dev, |
720 | struct ieee80211_vif *vif) | |
bd88a781 ID |
721 | { |
722 | struct rt2x00_intf *intf = vif_to_intf(vif); | |
723 | struct skb_frame_desc *skbdesc; | |
724 | struct txentry_desc txdesc; | |
bd88a781 ID |
725 | |
726 | if (unlikely(!intf->beacon)) | |
727 | return -ENOBUFS; | |
728 | ||
17512dc3 IP |
729 | /* |
730 | * Clean up the beacon skb. | |
731 | */ | |
fa69560f | 732 | rt2x00queue_free_skb(intf->beacon); |
17512dc3 | 733 | |
bd88a781 | 734 | intf->beacon->skb = ieee80211_beacon_get(rt2x00dev->hw, vif); |
8414ff07 | 735 | if (!intf->beacon->skb) |
bd88a781 ID |
736 | return -ENOMEM; |
737 | ||
738 | /* | |
739 | * Copy all TX descriptor information into txdesc, | |
740 | * after that we are free to use the skb->cb array | |
741 | * for our information. | |
742 | */ | |
77b5621b | 743 | rt2x00queue_create_tx_descriptor(rt2x00dev, intf->beacon->skb, &txdesc); |
bd88a781 | 744 | |
bd88a781 ID |
745 | /* |
746 | * Fill in skb descriptor | |
747 | */ | |
748 | skbdesc = get_skb_frame_desc(intf->beacon->skb); | |
749 | memset(skbdesc, 0, sizeof(*skbdesc)); | |
bd88a781 ID |
750 | skbdesc->entry = intf->beacon; |
751 | ||
bd88a781 | 752 | /* |
69cf36a4 | 753 | * Send beacon to hardware. |
bd88a781 | 754 | */ |
f224f4ef | 755 | rt2x00dev->ops->lib->write_beacon(intf->beacon, &txdesc); |
bd88a781 | 756 | |
8414ff07 HS |
757 | return 0; |
758 | ||
759 | } | |
760 | ||
761 | int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev, | |
762 | struct ieee80211_vif *vif) | |
763 | { | |
764 | struct rt2x00_intf *intf = vif_to_intf(vif); | |
765 | int ret; | |
766 | ||
767 | mutex_lock(&intf->beacon_skb_mutex); | |
768 | ret = rt2x00queue_update_beacon_locked(rt2x00dev, vif); | |
17512dc3 IP |
769 | mutex_unlock(&intf->beacon_skb_mutex); |
770 | ||
8414ff07 | 771 | return ret; |
bd88a781 ID |
772 | } |
773 | ||
10e11568 | 774 | bool rt2x00queue_for_each_entry(struct data_queue *queue, |
5eb7efe8 ID |
775 | enum queue_index start, |
776 | enum queue_index end, | |
10e11568 HS |
777 | void *data, |
778 | bool (*fn)(struct queue_entry *entry, | |
779 | void *data)) | |
5eb7efe8 ID |
780 | { |
781 | unsigned long irqflags; | |
782 | unsigned int index_start; | |
783 | unsigned int index_end; | |
784 | unsigned int i; | |
785 | ||
786 | if (unlikely(start >= Q_INDEX_MAX || end >= Q_INDEX_MAX)) { | |
787 | ERROR(queue->rt2x00dev, | |
788 | "Entry requested from invalid index range (%d - %d)\n", | |
789 | start, end); | |
10e11568 | 790 | return true; |
5eb7efe8 ID |
791 | } |
792 | ||
793 | /* | |
794 | * Only protect the range we are going to loop over, | |
795 | * if during our loop a extra entry is set to pending | |
796 | * it should not be kicked during this run, since it | |
797 | * is part of another TX operation. | |
798 | */ | |
813f0339 | 799 | spin_lock_irqsave(&queue->index_lock, irqflags); |
5eb7efe8 ID |
800 | index_start = queue->index[start]; |
801 | index_end = queue->index[end]; | |
813f0339 | 802 | spin_unlock_irqrestore(&queue->index_lock, irqflags); |
5eb7efe8 ID |
803 | |
804 | /* | |
25985edc | 805 | * Start from the TX done pointer, this guarantees that we will |
5eb7efe8 ID |
806 | * send out all frames in the correct order. |
807 | */ | |
808 | if (index_start < index_end) { | |
10e11568 HS |
809 | for (i = index_start; i < index_end; i++) { |
810 | if (fn(&queue->entries[i], data)) | |
811 | return true; | |
812 | } | |
5eb7efe8 | 813 | } else { |
10e11568 HS |
814 | for (i = index_start; i < queue->limit; i++) { |
815 | if (fn(&queue->entries[i], data)) | |
816 | return true; | |
817 | } | |
5eb7efe8 | 818 | |
10e11568 HS |
819 | for (i = 0; i < index_end; i++) { |
820 | if (fn(&queue->entries[i], data)) | |
821 | return true; | |
822 | } | |
5eb7efe8 | 823 | } |
10e11568 HS |
824 | |
825 | return false; | |
5eb7efe8 ID |
826 | } |
827 | EXPORT_SYMBOL_GPL(rt2x00queue_for_each_entry); | |
828 | ||
181d6902 ID |
829 | struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue, |
830 | enum queue_index index) | |
831 | { | |
832 | struct queue_entry *entry; | |
5f46c4d0 | 833 | unsigned long irqflags; |
181d6902 ID |
834 | |
835 | if (unlikely(index >= Q_INDEX_MAX)) { | |
836 | ERROR(queue->rt2x00dev, | |
837 | "Entry requested from invalid index type (%d)\n", index); | |
838 | return NULL; | |
839 | } | |
840 | ||
813f0339 | 841 | spin_lock_irqsave(&queue->index_lock, irqflags); |
181d6902 ID |
842 | |
843 | entry = &queue->entries[queue->index[index]]; | |
844 | ||
813f0339 | 845 | spin_unlock_irqrestore(&queue->index_lock, irqflags); |
181d6902 ID |
846 | |
847 | return entry; | |
848 | } | |
849 | EXPORT_SYMBOL_GPL(rt2x00queue_get_entry); | |
850 | ||
75256f03 | 851 | void rt2x00queue_index_inc(struct queue_entry *entry, enum queue_index index) |
181d6902 | 852 | { |
75256f03 | 853 | struct data_queue *queue = entry->queue; |
5f46c4d0 ID |
854 | unsigned long irqflags; |
855 | ||
181d6902 ID |
856 | if (unlikely(index >= Q_INDEX_MAX)) { |
857 | ERROR(queue->rt2x00dev, | |
858 | "Index change on invalid index type (%d)\n", index); | |
859 | return; | |
860 | } | |
861 | ||
813f0339 | 862 | spin_lock_irqsave(&queue->index_lock, irqflags); |
181d6902 ID |
863 | |
864 | queue->index[index]++; | |
865 | if (queue->index[index] >= queue->limit) | |
866 | queue->index[index] = 0; | |
867 | ||
75256f03 | 868 | entry->last_action = jiffies; |
652a9dd2 | 869 | |
10b6b801 ID |
870 | if (index == Q_INDEX) { |
871 | queue->length++; | |
872 | } else if (index == Q_INDEX_DONE) { | |
873 | queue->length--; | |
55887511 | 874 | queue->count++; |
10b6b801 | 875 | } |
181d6902 | 876 | |
813f0339 | 877 | spin_unlock_irqrestore(&queue->index_lock, irqflags); |
181d6902 | 878 | } |
181d6902 | 879 | |
0b7fde54 ID |
880 | void rt2x00queue_pause_queue(struct data_queue *queue) |
881 | { | |
882 | if (!test_bit(DEVICE_STATE_PRESENT, &queue->rt2x00dev->flags) || | |
883 | !test_bit(QUEUE_STARTED, &queue->flags) || | |
884 | test_and_set_bit(QUEUE_PAUSED, &queue->flags)) | |
885 | return; | |
886 | ||
887 | switch (queue->qid) { | |
f615e9a3 ID |
888 | case QID_AC_VO: |
889 | case QID_AC_VI: | |
0b7fde54 ID |
890 | case QID_AC_BE: |
891 | case QID_AC_BK: | |
0b7fde54 ID |
892 | /* |
893 | * For TX queues, we have to disable the queue | |
894 | * inside mac80211. | |
895 | */ | |
896 | ieee80211_stop_queue(queue->rt2x00dev->hw, queue->qid); | |
897 | break; | |
898 | default: | |
899 | break; | |
900 | } | |
901 | } | |
902 | EXPORT_SYMBOL_GPL(rt2x00queue_pause_queue); | |
903 | ||
904 | void rt2x00queue_unpause_queue(struct data_queue *queue) | |
905 | { | |
906 | if (!test_bit(DEVICE_STATE_PRESENT, &queue->rt2x00dev->flags) || | |
907 | !test_bit(QUEUE_STARTED, &queue->flags) || | |
908 | !test_and_clear_bit(QUEUE_PAUSED, &queue->flags)) | |
909 | return; | |
910 | ||
911 | switch (queue->qid) { | |
f615e9a3 ID |
912 | case QID_AC_VO: |
913 | case QID_AC_VI: | |
0b7fde54 ID |
914 | case QID_AC_BE: |
915 | case QID_AC_BK: | |
0b7fde54 ID |
916 | /* |
917 | * For TX queues, we have to enable the queue | |
918 | * inside mac80211. | |
919 | */ | |
920 | ieee80211_wake_queue(queue->rt2x00dev->hw, queue->qid); | |
921 | break; | |
5be65609 ID |
922 | case QID_RX: |
923 | /* | |
924 | * For RX we need to kick the queue now in order to | |
925 | * receive frames. | |
926 | */ | |
927 | queue->rt2x00dev->ops->lib->kick_queue(queue); | |
0b7fde54 ID |
928 | default: |
929 | break; | |
930 | } | |
931 | } | |
932 | EXPORT_SYMBOL_GPL(rt2x00queue_unpause_queue); | |
933 | ||
934 | void rt2x00queue_start_queue(struct data_queue *queue) | |
935 | { | |
936 | mutex_lock(&queue->status_lock); | |
937 | ||
938 | if (!test_bit(DEVICE_STATE_PRESENT, &queue->rt2x00dev->flags) || | |
939 | test_and_set_bit(QUEUE_STARTED, &queue->flags)) { | |
940 | mutex_unlock(&queue->status_lock); | |
941 | return; | |
942 | } | |
943 | ||
944 | set_bit(QUEUE_PAUSED, &queue->flags); | |
945 | ||
946 | queue->rt2x00dev->ops->lib->start_queue(queue); | |
947 | ||
948 | rt2x00queue_unpause_queue(queue); | |
949 | ||
950 | mutex_unlock(&queue->status_lock); | |
951 | } | |
952 | EXPORT_SYMBOL_GPL(rt2x00queue_start_queue); | |
953 | ||
954 | void rt2x00queue_stop_queue(struct data_queue *queue) | |
955 | { | |
956 | mutex_lock(&queue->status_lock); | |
957 | ||
958 | if (!test_and_clear_bit(QUEUE_STARTED, &queue->flags)) { | |
959 | mutex_unlock(&queue->status_lock); | |
960 | return; | |
961 | } | |
962 | ||
963 | rt2x00queue_pause_queue(queue); | |
964 | ||
965 | queue->rt2x00dev->ops->lib->stop_queue(queue); | |
966 | ||
967 | mutex_unlock(&queue->status_lock); | |
968 | } | |
969 | EXPORT_SYMBOL_GPL(rt2x00queue_stop_queue); | |
970 | ||
5be65609 ID |
971 | void rt2x00queue_flush_queue(struct data_queue *queue, bool drop) |
972 | { | |
5be65609 ID |
973 | bool started; |
974 | bool tx_queue = | |
f615e9a3 | 975 | (queue->qid == QID_AC_VO) || |
5be65609 | 976 | (queue->qid == QID_AC_VI) || |
f615e9a3 ID |
977 | (queue->qid == QID_AC_BE) || |
978 | (queue->qid == QID_AC_BK); | |
5be65609 ID |
979 | |
980 | mutex_lock(&queue->status_lock); | |
981 | ||
982 | /* | |
983 | * If the queue has been started, we must stop it temporarily | |
984 | * to prevent any new frames to be queued on the device. If | |
985 | * we are not dropping the pending frames, the queue must | |
986 | * only be stopped in the software and not the hardware, | |
987 | * otherwise the queue will never become empty on its own. | |
988 | */ | |
989 | started = test_bit(QUEUE_STARTED, &queue->flags); | |
990 | if (started) { | |
991 | /* | |
992 | * Pause the queue | |
993 | */ | |
994 | rt2x00queue_pause_queue(queue); | |
995 | ||
996 | /* | |
997 | * If we are not supposed to drop any pending | |
998 | * frames, this means we must force a start (=kick) | |
999 | * to the queue to make sure the hardware will | |
1000 | * start transmitting. | |
1001 | */ | |
1002 | if (!drop && tx_queue) | |
1003 | queue->rt2x00dev->ops->lib->kick_queue(queue); | |
1004 | } | |
1005 | ||
1006 | /* | |
152a5992 ID |
1007 | * Check if driver supports flushing, if that is the case we can |
1008 | * defer the flushing to the driver. Otherwise we must use the | |
1009 | * alternative which just waits for the queue to become empty. | |
5be65609 | 1010 | */ |
152a5992 ID |
1011 | if (likely(queue->rt2x00dev->ops->lib->flush_queue)) |
1012 | queue->rt2x00dev->ops->lib->flush_queue(queue, drop); | |
5be65609 ID |
1013 | |
1014 | /* | |
1015 | * The queue flush has failed... | |
1016 | */ | |
1017 | if (unlikely(!rt2x00queue_empty(queue))) | |
21957c31 | 1018 | WARNING(queue->rt2x00dev, "Queue %d failed to flush\n", queue->qid); |
5be65609 ID |
1019 | |
1020 | /* | |
1021 | * Restore the queue to the previous status | |
1022 | */ | |
1023 | if (started) | |
1024 | rt2x00queue_unpause_queue(queue); | |
1025 | ||
1026 | mutex_unlock(&queue->status_lock); | |
1027 | } | |
1028 | EXPORT_SYMBOL_GPL(rt2x00queue_flush_queue); | |
1029 | ||
0b7fde54 ID |
1030 | void rt2x00queue_start_queues(struct rt2x00_dev *rt2x00dev) |
1031 | { | |
1032 | struct data_queue *queue; | |
1033 | ||
1034 | /* | |
1035 | * rt2x00queue_start_queue will call ieee80211_wake_queue | |
1036 | * for each queue after is has been properly initialized. | |
1037 | */ | |
1038 | tx_queue_for_each(rt2x00dev, queue) | |
1039 | rt2x00queue_start_queue(queue); | |
1040 | ||
1041 | rt2x00queue_start_queue(rt2x00dev->rx); | |
1042 | } | |
1043 | EXPORT_SYMBOL_GPL(rt2x00queue_start_queues); | |
1044 | ||
1045 | void rt2x00queue_stop_queues(struct rt2x00_dev *rt2x00dev) | |
1046 | { | |
1047 | struct data_queue *queue; | |
1048 | ||
1049 | /* | |
1050 | * rt2x00queue_stop_queue will call ieee80211_stop_queue | |
1051 | * as well, but we are completely shutting doing everything | |
1052 | * now, so it is much safer to stop all TX queues at once, | |
1053 | * and use rt2x00queue_stop_queue for cleaning up. | |
1054 | */ | |
1055 | ieee80211_stop_queues(rt2x00dev->hw); | |
1056 | ||
1057 | tx_queue_for_each(rt2x00dev, queue) | |
1058 | rt2x00queue_stop_queue(queue); | |
1059 | ||
1060 | rt2x00queue_stop_queue(rt2x00dev->rx); | |
1061 | } | |
1062 | EXPORT_SYMBOL_GPL(rt2x00queue_stop_queues); | |
1063 | ||
5be65609 ID |
1064 | void rt2x00queue_flush_queues(struct rt2x00_dev *rt2x00dev, bool drop) |
1065 | { | |
1066 | struct data_queue *queue; | |
1067 | ||
1068 | tx_queue_for_each(rt2x00dev, queue) | |
1069 | rt2x00queue_flush_queue(queue, drop); | |
1070 | ||
1071 | rt2x00queue_flush_queue(rt2x00dev->rx, drop); | |
1072 | } | |
1073 | EXPORT_SYMBOL_GPL(rt2x00queue_flush_queues); | |
1074 | ||
181d6902 ID |
1075 | static void rt2x00queue_reset(struct data_queue *queue) |
1076 | { | |
5f46c4d0 | 1077 | unsigned long irqflags; |
652a9dd2 | 1078 | unsigned int i; |
5f46c4d0 | 1079 | |
813f0339 | 1080 | spin_lock_irqsave(&queue->index_lock, irqflags); |
181d6902 ID |
1081 | |
1082 | queue->count = 0; | |
1083 | queue->length = 0; | |
652a9dd2 | 1084 | |
75256f03 | 1085 | for (i = 0; i < Q_INDEX_MAX; i++) |
652a9dd2 | 1086 | queue->index[i] = 0; |
181d6902 | 1087 | |
813f0339 | 1088 | spin_unlock_irqrestore(&queue->index_lock, irqflags); |
181d6902 ID |
1089 | } |
1090 | ||
798b7adb | 1091 | void rt2x00queue_init_queues(struct rt2x00_dev *rt2x00dev) |
181d6902 ID |
1092 | { |
1093 | struct data_queue *queue; | |
1094 | unsigned int i; | |
1095 | ||
798b7adb | 1096 | queue_for_each(rt2x00dev, queue) { |
181d6902 ID |
1097 | rt2x00queue_reset(queue); |
1098 | ||
64e7d723 | 1099 | for (i = 0; i < queue->limit; i++) |
798b7adb | 1100 | rt2x00dev->ops->lib->clear_entry(&queue->entries[i]); |
181d6902 ID |
1101 | } |
1102 | } | |
1103 | ||
1104 | static int rt2x00queue_alloc_entries(struct data_queue *queue, | |
1105 | const struct data_queue_desc *qdesc) | |
1106 | { | |
1107 | struct queue_entry *entries; | |
1108 | unsigned int entry_size; | |
1109 | unsigned int i; | |
1110 | ||
1111 | rt2x00queue_reset(queue); | |
1112 | ||
1113 | queue->limit = qdesc->entry_num; | |
b869767b | 1114 | queue->threshold = DIV_ROUND_UP(qdesc->entry_num, 10); |
181d6902 ID |
1115 | queue->data_size = qdesc->data_size; |
1116 | queue->desc_size = qdesc->desc_size; | |
1117 | ||
1118 | /* | |
1119 | * Allocate all queue entries. | |
1120 | */ | |
1121 | entry_size = sizeof(*entries) + qdesc->priv_size; | |
baeb2ffa | 1122 | entries = kcalloc(queue->limit, entry_size, GFP_KERNEL); |
181d6902 ID |
1123 | if (!entries) |
1124 | return -ENOMEM; | |
1125 | ||
1126 | #define QUEUE_ENTRY_PRIV_OFFSET(__base, __index, __limit, __esize, __psize) \ | |
f8bfbc31 ME |
1127 | (((char *)(__base)) + ((__limit) * (__esize)) + \ |
1128 | ((__index) * (__psize))) | |
181d6902 ID |
1129 | |
1130 | for (i = 0; i < queue->limit; i++) { | |
1131 | entries[i].flags = 0; | |
1132 | entries[i].queue = queue; | |
1133 | entries[i].skb = NULL; | |
1134 | entries[i].entry_idx = i; | |
1135 | entries[i].priv_data = | |
1136 | QUEUE_ENTRY_PRIV_OFFSET(entries, i, queue->limit, | |
1137 | sizeof(*entries), qdesc->priv_size); | |
1138 | } | |
1139 | ||
1140 | #undef QUEUE_ENTRY_PRIV_OFFSET | |
1141 | ||
1142 | queue->entries = entries; | |
1143 | ||
1144 | return 0; | |
1145 | } | |
1146 | ||
fa69560f | 1147 | static void rt2x00queue_free_skbs(struct data_queue *queue) |
30caa6e3 GW |
1148 | { |
1149 | unsigned int i; | |
1150 | ||
1151 | if (!queue->entries) | |
1152 | return; | |
1153 | ||
1154 | for (i = 0; i < queue->limit; i++) { | |
fa69560f | 1155 | rt2x00queue_free_skb(&queue->entries[i]); |
30caa6e3 GW |
1156 | } |
1157 | } | |
1158 | ||
fa69560f | 1159 | static int rt2x00queue_alloc_rxskbs(struct data_queue *queue) |
30caa6e3 GW |
1160 | { |
1161 | unsigned int i; | |
1162 | struct sk_buff *skb; | |
1163 | ||
1164 | for (i = 0; i < queue->limit; i++) { | |
88211021 | 1165 | skb = rt2x00queue_alloc_rxskb(&queue->entries[i], GFP_KERNEL); |
30caa6e3 | 1166 | if (!skb) |
61243d8e | 1167 | return -ENOMEM; |
30caa6e3 GW |
1168 | queue->entries[i].skb = skb; |
1169 | } | |
1170 | ||
1171 | return 0; | |
30caa6e3 GW |
1172 | } |
1173 | ||
181d6902 ID |
1174 | int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev) |
1175 | { | |
1176 | struct data_queue *queue; | |
1177 | int status; | |
1178 | ||
181d6902 ID |
1179 | status = rt2x00queue_alloc_entries(rt2x00dev->rx, rt2x00dev->ops->rx); |
1180 | if (status) | |
1181 | goto exit; | |
1182 | ||
1183 | tx_queue_for_each(rt2x00dev, queue) { | |
1184 | status = rt2x00queue_alloc_entries(queue, rt2x00dev->ops->tx); | |
1185 | if (status) | |
1186 | goto exit; | |
1187 | } | |
1188 | ||
1189 | status = rt2x00queue_alloc_entries(rt2x00dev->bcn, rt2x00dev->ops->bcn); | |
1190 | if (status) | |
1191 | goto exit; | |
1192 | ||
7dab73b3 | 1193 | if (test_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags)) { |
e74df4a7 | 1194 | status = rt2x00queue_alloc_entries(rt2x00dev->atim, |
30caa6e3 GW |
1195 | rt2x00dev->ops->atim); |
1196 | if (status) | |
1197 | goto exit; | |
1198 | } | |
181d6902 | 1199 | |
fa69560f | 1200 | status = rt2x00queue_alloc_rxskbs(rt2x00dev->rx); |
181d6902 ID |
1201 | if (status) |
1202 | goto exit; | |
1203 | ||
1204 | return 0; | |
1205 | ||
1206 | exit: | |
1207 | ERROR(rt2x00dev, "Queue entries allocation failed.\n"); | |
1208 | ||
1209 | rt2x00queue_uninitialize(rt2x00dev); | |
1210 | ||
1211 | return status; | |
1212 | } | |
1213 | ||
1214 | void rt2x00queue_uninitialize(struct rt2x00_dev *rt2x00dev) | |
1215 | { | |
1216 | struct data_queue *queue; | |
1217 | ||
fa69560f | 1218 | rt2x00queue_free_skbs(rt2x00dev->rx); |
30caa6e3 | 1219 | |
181d6902 ID |
1220 | queue_for_each(rt2x00dev, queue) { |
1221 | kfree(queue->entries); | |
1222 | queue->entries = NULL; | |
1223 | } | |
1224 | } | |
1225 | ||
8f539276 ID |
1226 | static void rt2x00queue_init(struct rt2x00_dev *rt2x00dev, |
1227 | struct data_queue *queue, enum data_queue_qid qid) | |
1228 | { | |
0b7fde54 | 1229 | mutex_init(&queue->status_lock); |
77a861c4 | 1230 | spin_lock_init(&queue->tx_lock); |
813f0339 | 1231 | spin_lock_init(&queue->index_lock); |
8f539276 ID |
1232 | |
1233 | queue->rt2x00dev = rt2x00dev; | |
1234 | queue->qid = qid; | |
2af0a570 | 1235 | queue->txop = 0; |
8f539276 ID |
1236 | queue->aifs = 2; |
1237 | queue->cw_min = 5; | |
1238 | queue->cw_max = 10; | |
1239 | } | |
1240 | ||
181d6902 ID |
1241 | int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev) |
1242 | { | |
1243 | struct data_queue *queue; | |
1244 | enum data_queue_qid qid; | |
1245 | unsigned int req_atim = | |
7dab73b3 | 1246 | !!test_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags); |
181d6902 ID |
1247 | |
1248 | /* | |
1249 | * We need the following queues: | |
1250 | * RX: 1 | |
61448f88 | 1251 | * TX: ops->tx_queues |
181d6902 ID |
1252 | * Beacon: 1 |
1253 | * Atim: 1 (if required) | |
1254 | */ | |
61448f88 | 1255 | rt2x00dev->data_queues = 2 + rt2x00dev->ops->tx_queues + req_atim; |
181d6902 | 1256 | |
baeb2ffa | 1257 | queue = kcalloc(rt2x00dev->data_queues, sizeof(*queue), GFP_KERNEL); |
181d6902 ID |
1258 | if (!queue) { |
1259 | ERROR(rt2x00dev, "Queue allocation failed.\n"); | |
1260 | return -ENOMEM; | |
1261 | } | |
1262 | ||
1263 | /* | |
1264 | * Initialize pointers | |
1265 | */ | |
1266 | rt2x00dev->rx = queue; | |
1267 | rt2x00dev->tx = &queue[1]; | |
61448f88 | 1268 | rt2x00dev->bcn = &queue[1 + rt2x00dev->ops->tx_queues]; |
e74df4a7 | 1269 | rt2x00dev->atim = req_atim ? &queue[2 + rt2x00dev->ops->tx_queues] : NULL; |
181d6902 ID |
1270 | |
1271 | /* | |
1272 | * Initialize queue parameters. | |
1273 | * RX: qid = QID_RX | |
f615e9a3 | 1274 | * TX: qid = QID_AC_VO + index |
181d6902 ID |
1275 | * TX: cw_min: 2^5 = 32. |
1276 | * TX: cw_max: 2^10 = 1024. | |
565a019a ID |
1277 | * BCN: qid = QID_BEACON |
1278 | * ATIM: qid = QID_ATIM | |
181d6902 | 1279 | */ |
8f539276 | 1280 | rt2x00queue_init(rt2x00dev, rt2x00dev->rx, QID_RX); |
181d6902 | 1281 | |
f615e9a3 | 1282 | qid = QID_AC_VO; |
8f539276 ID |
1283 | tx_queue_for_each(rt2x00dev, queue) |
1284 | rt2x00queue_init(rt2x00dev, queue, qid++); | |
181d6902 | 1285 | |
e74df4a7 | 1286 | rt2x00queue_init(rt2x00dev, rt2x00dev->bcn, QID_BEACON); |
181d6902 | 1287 | if (req_atim) |
e74df4a7 | 1288 | rt2x00queue_init(rt2x00dev, rt2x00dev->atim, QID_ATIM); |
181d6902 ID |
1289 | |
1290 | return 0; | |
1291 | } | |
1292 | ||
1293 | void rt2x00queue_free(struct rt2x00_dev *rt2x00dev) | |
1294 | { | |
1295 | kfree(rt2x00dev->rx); | |
1296 | rt2x00dev->rx = NULL; | |
1297 | rt2x00dev->tx = NULL; | |
1298 | rt2x00dev->bcn = NULL; | |
1299 | } |