rt2x00: checkpatch.pl error fixes for rt73usb.c
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2x00queue.c
CommitLineData
181d6902 1/*
7e613e16
ID
2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2004 - 2009 Gertjan van Wingerde <gwingerde@gmail.com>
181d6902
ID
5 <http://rt2x00.serialmonkey.com>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the
19 Free Software Foundation, Inc.,
20 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22
23/*
24 Module: rt2x00lib
25 Abstract: rt2x00 queue specific routines.
26 */
27
5a0e3ad6 28#include <linux/slab.h>
181d6902
ID
29#include <linux/kernel.h>
30#include <linux/module.h>
c4da0048 31#include <linux/dma-mapping.h>
181d6902
ID
32
33#include "rt2x00.h"
34#include "rt2x00lib.h"
35
fa69560f 36struct sk_buff *rt2x00queue_alloc_rxskb(struct queue_entry *entry)
239c249d 37{
fa69560f 38 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
c4da0048
GW
39 struct sk_buff *skb;
40 struct skb_frame_desc *skbdesc;
2bb057d0
ID
41 unsigned int frame_size;
42 unsigned int head_size = 0;
43 unsigned int tail_size = 0;
239c249d
GW
44
45 /*
46 * The frame size includes descriptor size, because the
47 * hardware directly receive the frame into the skbuffer.
48 */
c4da0048 49 frame_size = entry->queue->data_size + entry->queue->desc_size;
239c249d
GW
50
51 /*
ff352391
ID
52 * The payload should be aligned to a 4-byte boundary,
53 * this means we need at least 3 bytes for moving the frame
54 * into the correct offset.
239c249d 55 */
2bb057d0
ID
56 head_size = 4;
57
58 /*
59 * For IV/EIV/ICV assembly we must make sure there is
60 * at least 8 bytes bytes available in headroom for IV/EIV
9c3444d3 61 * and 8 bytes for ICV data as tailroon.
2bb057d0 62 */
2bb057d0
ID
63 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
64 head_size += 8;
9c3444d3 65 tail_size += 8;
2bb057d0 66 }
239c249d
GW
67
68 /*
69 * Allocate skbuffer.
70 */
2bb057d0 71 skb = dev_alloc_skb(frame_size + head_size + tail_size);
239c249d
GW
72 if (!skb)
73 return NULL;
74
2bb057d0
ID
75 /*
76 * Make sure we not have a frame with the requested bytes
77 * available in the head and tail.
78 */
79 skb_reserve(skb, head_size);
239c249d
GW
80 skb_put(skb, frame_size);
81
c4da0048
GW
82 /*
83 * Populate skbdesc.
84 */
85 skbdesc = get_skb_frame_desc(skb);
86 memset(skbdesc, 0, sizeof(*skbdesc));
87 skbdesc->entry = entry;
88
89 if (test_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags)) {
90 skbdesc->skb_dma = dma_map_single(rt2x00dev->dev,
91 skb->data,
92 skb->len,
93 DMA_FROM_DEVICE);
94 skbdesc->flags |= SKBDESC_DMA_MAPPED_RX;
95 }
96
239c249d
GW
97 return skb;
98}
30caa6e3 99
fa69560f 100void rt2x00queue_map_txskb(struct queue_entry *entry)
30caa6e3 101{
fa69560f
ID
102 struct device *dev = entry->queue->rt2x00dev->dev;
103 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
c4da0048 104
3ee54a07 105 skbdesc->skb_dma =
fa69560f 106 dma_map_single(dev, entry->skb->data, entry->skb->len, DMA_TO_DEVICE);
c4da0048
GW
107 skbdesc->flags |= SKBDESC_DMA_MAPPED_TX;
108}
109EXPORT_SYMBOL_GPL(rt2x00queue_map_txskb);
110
fa69560f 111void rt2x00queue_unmap_skb(struct queue_entry *entry)
c4da0048 112{
fa69560f
ID
113 struct device *dev = entry->queue->rt2x00dev->dev;
114 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
c4da0048
GW
115
116 if (skbdesc->flags & SKBDESC_DMA_MAPPED_RX) {
fa69560f 117 dma_unmap_single(dev, skbdesc->skb_dma, entry->skb->len,
c4da0048
GW
118 DMA_FROM_DEVICE);
119 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_RX;
546adf29 120 } else if (skbdesc->flags & SKBDESC_DMA_MAPPED_TX) {
fa69560f 121 dma_unmap_single(dev, skbdesc->skb_dma, entry->skb->len,
c4da0048
GW
122 DMA_TO_DEVICE);
123 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_TX;
124 }
125}
0b8004aa 126EXPORT_SYMBOL_GPL(rt2x00queue_unmap_skb);
c4da0048 127
fa69560f 128void rt2x00queue_free_skb(struct queue_entry *entry)
c4da0048 129{
fa69560f 130 if (!entry->skb)
9a613195
ID
131 return;
132
fa69560f
ID
133 rt2x00queue_unmap_skb(entry);
134 dev_kfree_skb_any(entry->skb);
135 entry->skb = NULL;
30caa6e3 136}
239c249d 137
daee6c09 138void rt2x00queue_align_frame(struct sk_buff *skb)
9f166171 139{
9f166171 140 unsigned int frame_length = skb->len;
daee6c09 141 unsigned int align = ALIGN_SIZE(skb, 0);
9f166171
ID
142
143 if (!align)
144 return;
145
daee6c09
ID
146 skb_push(skb, align);
147 memmove(skb->data, skb->data + align, frame_length);
148 skb_trim(skb, frame_length);
149}
150
95d69aa0 151void rt2x00queue_align_payload(struct sk_buff *skb, unsigned int header_length)
daee6c09
ID
152{
153 unsigned int frame_length = skb->len;
95d69aa0 154 unsigned int align = ALIGN_SIZE(skb, header_length);
daee6c09
ID
155
156 if (!align)
157 return;
158
159 skb_push(skb, align);
160 memmove(skb->data, skb->data + align, frame_length);
161 skb_trim(skb, frame_length);
162}
163
164void rt2x00queue_insert_l2pad(struct sk_buff *skb, unsigned int header_length)
165{
2e331462 166 unsigned int payload_length = skb->len - header_length;
daee6c09
ID
167 unsigned int header_align = ALIGN_SIZE(skb, 0);
168 unsigned int payload_align = ALIGN_SIZE(skb, header_length);
e54be4e7 169 unsigned int l2pad = payload_length ? L2PAD_SIZE(header_length) : 0;
daee6c09 170
2e331462
GW
171 /*
172 * Adjust the header alignment if the payload needs to be moved more
173 * than the header.
174 */
175 if (payload_align > header_align)
176 header_align += 4;
177
178 /* There is nothing to do if no alignment is needed */
179 if (!header_align)
180 return;
daee6c09 181
2e331462
GW
182 /* Reserve the amount of space needed in front of the frame */
183 skb_push(skb, header_align);
184
185 /*
186 * Move the header.
187 */
188 memmove(skb->data, skb->data + header_align, header_length);
189
190 /* Move the payload, if present and if required */
191 if (payload_length && payload_align)
daee6c09 192 memmove(skb->data + header_length + l2pad,
a5186e99 193 skb->data + header_length + l2pad + payload_align,
2e331462
GW
194 payload_length);
195
196 /* Trim the skb to the correct size */
197 skb_trim(skb, header_length + l2pad + payload_length);
9f166171
ID
198}
199
daee6c09
ID
200void rt2x00queue_remove_l2pad(struct sk_buff *skb, unsigned int header_length)
201{
77e73d18 202 unsigned int l2pad = L2PAD_SIZE(header_length);
daee6c09 203
354e39db 204 if (!l2pad)
daee6c09
ID
205 return;
206
207 memmove(skb->data + l2pad, skb->data, header_length);
208 skb_pull(skb, l2pad);
209}
210
7b40982e
ID
211static void rt2x00queue_create_tx_descriptor_seq(struct queue_entry *entry,
212 struct txentry_desc *txdesc)
213{
214 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
215 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
216 struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
217 unsigned long irqflags;
218
219 if (!(tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) ||
220 unlikely(!tx_info->control.vif))
221 return;
222
223 /*
224 * Hardware should insert sequence counter.
225 * FIXME: We insert a software sequence counter first for
226 * hardware that doesn't support hardware sequence counting.
227 *
228 * This is wrong because beacons are not getting sequence
229 * numbers assigned properly.
230 *
231 * A secondary problem exists for drivers that cannot toggle
232 * sequence counting per-frame, since those will override the
233 * sequence counter given by mac80211.
234 */
235 spin_lock_irqsave(&intf->seqlock, irqflags);
236
237 if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags))
238 intf->seqno += 0x10;
239 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
240 hdr->seq_ctrl |= cpu_to_le16(intf->seqno);
241
242 spin_unlock_irqrestore(&intf->seqlock, irqflags);
243
244 __set_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags);
245}
246
247static void rt2x00queue_create_tx_descriptor_plcp(struct queue_entry *entry,
248 struct txentry_desc *txdesc,
249 const struct rt2x00_rate *hwrate)
250{
251 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
252 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
253 struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0];
254 unsigned int data_length;
255 unsigned int duration;
256 unsigned int residual;
257
258 /* Data length + CRC + Crypto overhead (IV/EIV/ICV/MIC) */
259 data_length = entry->skb->len + 4;
260 data_length += rt2x00crypto_tx_overhead(rt2x00dev, entry->skb);
261
262 /*
263 * PLCP setup
264 * Length calculation depends on OFDM/CCK rate.
265 */
266 txdesc->signal = hwrate->plcp;
267 txdesc->service = 0x04;
268
269 if (hwrate->flags & DEV_RATE_OFDM) {
270 txdesc->length_high = (data_length >> 6) & 0x3f;
271 txdesc->length_low = data_length & 0x3f;
272 } else {
273 /*
274 * Convert length to microseconds.
275 */
276 residual = GET_DURATION_RES(data_length, hwrate->bitrate);
277 duration = GET_DURATION(data_length, hwrate->bitrate);
278
279 if (residual != 0) {
280 duration++;
281
282 /*
283 * Check if we need to set the Length Extension
284 */
285 if (hwrate->bitrate == 110 && residual <= 30)
286 txdesc->service |= 0x80;
287 }
288
289 txdesc->length_high = (duration >> 8) & 0xff;
290 txdesc->length_low = duration & 0xff;
291
292 /*
293 * When preamble is enabled we should set the
294 * preamble bit for the signal.
295 */
296 if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
297 txdesc->signal |= 0x08;
298 }
299}
300
bd88a781
ID
301static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry,
302 struct txentry_desc *txdesc)
7050ec82 303{
2e92e6f2 304 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
e039fa4a 305 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
7050ec82 306 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
2e92e6f2 307 struct ieee80211_rate *rate =
e039fa4a 308 ieee80211_get_tx_rate(rt2x00dev->hw, tx_info);
7050ec82 309 const struct rt2x00_rate *hwrate;
7050ec82
ID
310
311 memset(txdesc, 0, sizeof(*txdesc));
312
9f166171 313 /*
df624ca5 314 * Header and frame information.
9f166171 315 */
df624ca5 316 txdesc->length = entry->skb->len;
9f166171 317 txdesc->header_length = ieee80211_get_hdrlen_from_skb(entry->skb);
9f166171 318
7050ec82
ID
319 /*
320 * Check whether this frame is to be acked.
321 */
e039fa4a 322 if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK))
7050ec82
ID
323 __set_bit(ENTRY_TXD_ACK, &txdesc->flags);
324
325 /*
326 * Check if this is a RTS/CTS frame
327 */
ac104462
ID
328 if (ieee80211_is_rts(hdr->frame_control) ||
329 ieee80211_is_cts(hdr->frame_control)) {
7050ec82 330 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
ac104462 331 if (ieee80211_is_rts(hdr->frame_control))
7050ec82 332 __set_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags);
e039fa4a 333 else
7050ec82 334 __set_bit(ENTRY_TXD_CTS_FRAME, &txdesc->flags);
e039fa4a 335 if (tx_info->control.rts_cts_rate_idx >= 0)
2e92e6f2 336 rate =
e039fa4a 337 ieee80211_get_rts_cts_rate(rt2x00dev->hw, tx_info);
7050ec82
ID
338 }
339
340 /*
341 * Determine retry information.
342 */
e6a9854b 343 txdesc->retry_limit = tx_info->control.rates[0].count - 1;
42c82857 344 if (txdesc->retry_limit >= rt2x00dev->long_retry)
7050ec82
ID
345 __set_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags);
346
347 /*
348 * Check if more fragments are pending
349 */
2606e422 350 if (ieee80211_has_morefrags(hdr->frame_control)) {
7050ec82
ID
351 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
352 __set_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags);
353 }
354
2606e422
HS
355 /*
356 * Check if more frames (!= fragments) are pending
357 */
358 if (tx_info->flags & IEEE80211_TX_CTL_MORE_FRAMES)
359 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
360
7050ec82
ID
361 /*
362 * Beacons and probe responses require the tsf timestamp
e81e0aef
AB
363 * to be inserted into the frame, except for a frame that has been injected
364 * through a monitor interface. This latter is needed for testing a
365 * monitor interface.
7050ec82 366 */
e81e0aef
AB
367 if ((ieee80211_is_beacon(hdr->frame_control) ||
368 ieee80211_is_probe_resp(hdr->frame_control)) &&
369 (!(tx_info->flags & IEEE80211_TX_CTL_INJECTED)))
7050ec82
ID
370 __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags);
371
372 /*
373 * Determine with what IFS priority this frame should be send.
374 * Set ifs to IFS_SIFS when the this is not the first fragment,
375 * or this fragment came after RTS/CTS.
376 */
7b40982e
ID
377 if ((tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) &&
378 !test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)) {
7050ec82
ID
379 __set_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags);
380 txdesc->ifs = IFS_BACKOFF;
7b40982e 381 } else
7050ec82 382 txdesc->ifs = IFS_SIFS;
7050ec82 383
076f9582
ID
384 /*
385 * Determine rate modulation.
386 */
7050ec82 387 hwrate = rt2x00_get_rate(rate->hw_value);
076f9582 388 txdesc->rate_mode = RATE_MODE_CCK;
7b40982e 389 if (hwrate->flags & DEV_RATE_OFDM)
076f9582 390 txdesc->rate_mode = RATE_MODE_OFDM;
7050ec82 391
7b40982e
ID
392 /*
393 * Apply TX descriptor handling by components
394 */
395 rt2x00crypto_create_tx_descriptor(entry, txdesc);
35f00cfc 396 rt2x00ht_create_tx_descriptor(entry, txdesc, hwrate);
7b40982e
ID
397 rt2x00queue_create_tx_descriptor_seq(entry, txdesc);
398 rt2x00queue_create_tx_descriptor_plcp(entry, txdesc, hwrate);
7050ec82 399}
7050ec82 400
78eea11b
GW
401static int rt2x00queue_write_tx_data(struct queue_entry *entry,
402 struct txentry_desc *txdesc)
403{
404 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
405
406 /*
407 * This should not happen, we already checked the entry
408 * was ours. When the hardware disagrees there has been
409 * a queue corruption!
410 */
411 if (unlikely(rt2x00dev->ops->lib->get_entry_state &&
412 rt2x00dev->ops->lib->get_entry_state(entry))) {
413 ERROR(rt2x00dev,
414 "Corrupt queue %d, accessing entry which is not ours.\n"
415 "Please file bug report to %s.\n",
416 entry->queue->qid, DRV_PROJECT);
417 return -EINVAL;
418 }
419
420 /*
421 * Add the requested extra tx headroom in front of the skb.
422 */
423 skb_push(entry->skb, rt2x00dev->ops->extra_tx_headroom);
424 memset(entry->skb->data, 0, rt2x00dev->ops->extra_tx_headroom);
425
426 /*
76dd5ddf 427 * Call the driver's write_tx_data function, if it exists.
78eea11b 428 */
76dd5ddf
GW
429 if (rt2x00dev->ops->lib->write_tx_data)
430 rt2x00dev->ops->lib->write_tx_data(entry, txdesc);
78eea11b
GW
431
432 /*
433 * Map the skb to DMA.
434 */
435 if (test_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags))
fa69560f 436 rt2x00queue_map_txskb(entry);
78eea11b
GW
437
438 return 0;
439}
440
bd88a781
ID
441static void rt2x00queue_write_tx_descriptor(struct queue_entry *entry,
442 struct txentry_desc *txdesc)
7050ec82 443{
b869767b 444 struct data_queue *queue = entry->queue;
7050ec82 445
93331458 446 queue->rt2x00dev->ops->lib->write_tx_desc(entry, txdesc);
7050ec82
ID
447
448 /*
449 * All processing on the frame has been completed, this means
450 * it is now ready to be dumped to userspace through debugfs.
451 */
93331458 452 rt2x00debug_dump_frame(queue->rt2x00dev, DUMP_FRAME_TX, entry->skb);
6295d815
GW
453}
454
455static void rt2x00queue_kick_tx_queue(struct queue_entry *entry,
456 struct txentry_desc *txdesc)
457{
458 struct data_queue *queue = entry->queue;
459 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
7050ec82
ID
460
461 /*
b869767b 462 * Check if we need to kick the queue, there are however a few rules
6295d815 463 * 1) Don't kick unless this is the last in frame in a burst.
b869767b
ID
464 * When the burst flag is set, this frame is always followed
465 * by another frame which in some way are related to eachother.
466 * This is true for fragments, RTS or CTS-to-self frames.
6295d815 467 * 2) Rule 1 can be broken when the available entries
b869767b 468 * in the queue are less then a certain threshold.
7050ec82 469 */
b869767b
ID
470 if (rt2x00queue_threshold(queue) ||
471 !test_bit(ENTRY_TXD_BURST, &txdesc->flags))
93331458 472 rt2x00dev->ops->lib->kick_tx_queue(queue);
7050ec82 473}
7050ec82 474
7351c6bd
JB
475int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
476 bool local)
6db3786a 477{
e6a9854b 478 struct ieee80211_tx_info *tx_info;
6db3786a
ID
479 struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX);
480 struct txentry_desc txdesc;
d74f5ba4 481 struct skb_frame_desc *skbdesc;
e6a9854b 482 u8 rate_idx, rate_flags;
6db3786a
ID
483
484 if (unlikely(rt2x00queue_full(queue)))
0e3de998 485 return -ENOBUFS;
6db3786a 486
c6084d5f
HS
487 if (unlikely(test_and_set_bit(ENTRY_OWNER_DEVICE_DATA,
488 &entry->flags))) {
6db3786a
ID
489 ERROR(queue->rt2x00dev,
490 "Arrived at non-free entry in the non-full queue %d.\n"
491 "Please file bug report to %s.\n",
492 queue->qid, DRV_PROJECT);
493 return -EINVAL;
494 }
495
496 /*
497 * Copy all TX descriptor information into txdesc,
498 * after that we are free to use the skb->cb array
499 * for our information.
500 */
501 entry->skb = skb;
502 rt2x00queue_create_tx_descriptor(entry, &txdesc);
503
d74f5ba4 504 /*
e6a9854b 505 * All information is retrieved from the skb->cb array,
2bb057d0 506 * now we should claim ownership of the driver part of that
e6a9854b 507 * array, preserving the bitrate index and flags.
d74f5ba4 508 */
e6a9854b
JB
509 tx_info = IEEE80211_SKB_CB(skb);
510 rate_idx = tx_info->control.rates[0].idx;
511 rate_flags = tx_info->control.rates[0].flags;
0e3de998 512 skbdesc = get_skb_frame_desc(skb);
d74f5ba4
ID
513 memset(skbdesc, 0, sizeof(*skbdesc));
514 skbdesc->entry = entry;
e6a9854b
JB
515 skbdesc->tx_rate_idx = rate_idx;
516 skbdesc->tx_rate_flags = rate_flags;
d74f5ba4 517
7351c6bd
JB
518 if (local)
519 skbdesc->flags |= SKBDESC_NOT_MAC80211;
520
2bb057d0
ID
521 /*
522 * When hardware encryption is supported, and this frame
523 * is to be encrypted, we should strip the IV/EIV data from
3ad2f3fb 524 * the frame so we can provide it to the driver separately.
2bb057d0
ID
525 */
526 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc.flags) &&
dddfb478 527 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc.flags)) {
3f787bd6 528 if (test_bit(DRIVER_REQUIRE_COPY_IV, &queue->rt2x00dev->flags))
9eb4e21e 529 rt2x00crypto_tx_copy_iv(skb, &txdesc);
dddfb478 530 else
9eb4e21e 531 rt2x00crypto_tx_remove_iv(skb, &txdesc);
dddfb478 532 }
2bb057d0 533
93354cbb
ID
534 /*
535 * When DMA allocation is required we should guarentee to the
536 * driver that the DMA is aligned to a 4-byte boundary.
93354cbb
ID
537 * However some drivers require L2 padding to pad the payload
538 * rather then the header. This could be a requirement for
539 * PCI and USB devices, while header alignment only is valid
540 * for PCI devices.
541 */
9f166171 542 if (test_bit(DRIVER_REQUIRE_L2PAD, &queue->rt2x00dev->flags))
daee6c09 543 rt2x00queue_insert_l2pad(entry->skb, txdesc.header_length);
93354cbb 544 else if (test_bit(DRIVER_REQUIRE_DMA, &queue->rt2x00dev->flags))
daee6c09 545 rt2x00queue_align_frame(entry->skb);
9f166171 546
2bb057d0
ID
547 /*
548 * It could be possible that the queue was corrupted and this
0e3de998
ID
549 * call failed. Since we always return NETDEV_TX_OK to mac80211,
550 * this frame will simply be dropped.
2bb057d0 551 */
78eea11b 552 if (unlikely(rt2x00queue_write_tx_data(entry, &txdesc))) {
0262ab0d 553 clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
2bb057d0 554 entry->skb = NULL;
0e3de998 555 return -EIO;
6db3786a
ID
556 }
557
0262ab0d 558 set_bit(ENTRY_DATA_PENDING, &entry->flags);
6db3786a
ID
559
560 rt2x00queue_index_inc(queue, Q_INDEX);
561 rt2x00queue_write_tx_descriptor(entry, &txdesc);
6295d815 562 rt2x00queue_kick_tx_queue(entry, &txdesc);
6db3786a
ID
563
564 return 0;
565}
566
bd88a781 567int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev,
a2c9b652
ID
568 struct ieee80211_vif *vif,
569 const bool enable_beacon)
bd88a781
ID
570{
571 struct rt2x00_intf *intf = vif_to_intf(vif);
572 struct skb_frame_desc *skbdesc;
573 struct txentry_desc txdesc;
bd88a781
ID
574
575 if (unlikely(!intf->beacon))
576 return -ENOBUFS;
577
17512dc3
IP
578 mutex_lock(&intf->beacon_skb_mutex);
579
580 /*
581 * Clean up the beacon skb.
582 */
fa69560f 583 rt2x00queue_free_skb(intf->beacon);
17512dc3 584
a2c9b652 585 if (!enable_beacon) {
93331458 586 rt2x00dev->ops->lib->kill_tx_queue(intf->beacon->queue);
17512dc3 587 mutex_unlock(&intf->beacon_skb_mutex);
a2c9b652
ID
588 return 0;
589 }
590
bd88a781 591 intf->beacon->skb = ieee80211_beacon_get(rt2x00dev->hw, vif);
17512dc3
IP
592 if (!intf->beacon->skb) {
593 mutex_unlock(&intf->beacon_skb_mutex);
bd88a781 594 return -ENOMEM;
17512dc3 595 }
bd88a781
ID
596
597 /*
598 * Copy all TX descriptor information into txdesc,
599 * after that we are free to use the skb->cb array
600 * for our information.
601 */
602 rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc);
603
bd88a781
ID
604 /*
605 * Fill in skb descriptor
606 */
607 skbdesc = get_skb_frame_desc(intf->beacon->skb);
608 memset(skbdesc, 0, sizeof(*skbdesc));
bd88a781
ID
609 skbdesc->entry = intf->beacon;
610
bd88a781 611 /*
d61cb266 612 * Send beacon to hardware and enable beacon genaration..
bd88a781 613 */
f224f4ef 614 rt2x00dev->ops->lib->write_beacon(intf->beacon, &txdesc);
bd88a781 615
17512dc3
IP
616 mutex_unlock(&intf->beacon_skb_mutex);
617
bd88a781
ID
618 return 0;
619}
620
5eb7efe8
ID
621void rt2x00queue_for_each_entry(struct data_queue *queue,
622 enum queue_index start,
623 enum queue_index end,
624 void (*fn)(struct queue_entry *entry))
625{
626 unsigned long irqflags;
627 unsigned int index_start;
628 unsigned int index_end;
629 unsigned int i;
630
631 if (unlikely(start >= Q_INDEX_MAX || end >= Q_INDEX_MAX)) {
632 ERROR(queue->rt2x00dev,
633 "Entry requested from invalid index range (%d - %d)\n",
634 start, end);
635 return;
636 }
637
638 /*
639 * Only protect the range we are going to loop over,
640 * if during our loop a extra entry is set to pending
641 * it should not be kicked during this run, since it
642 * is part of another TX operation.
643 */
644 spin_lock_irqsave(&queue->lock, irqflags);
645 index_start = queue->index[start];
646 index_end = queue->index[end];
647 spin_unlock_irqrestore(&queue->lock, irqflags);
648
649 /*
650 * Start from the TX done pointer, this guarentees that we will
651 * send out all frames in the correct order.
652 */
653 if (index_start < index_end) {
654 for (i = index_start; i < index_end; i++)
655 fn(&queue->entries[i]);
656 } else {
657 for (i = index_start; i < queue->limit; i++)
658 fn(&queue->entries[i]);
659
660 for (i = 0; i < index_end; i++)
661 fn(&queue->entries[i]);
662 }
663}
664EXPORT_SYMBOL_GPL(rt2x00queue_for_each_entry);
665
181d6902 666struct data_queue *rt2x00queue_get_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 667 const enum data_queue_qid queue)
181d6902
ID
668{
669 int atim = test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
670
a2c9b652
ID
671 if (queue == QID_RX)
672 return rt2x00dev->rx;
673
61448f88 674 if (queue < rt2x00dev->ops->tx_queues && rt2x00dev->tx)
181d6902
ID
675 return &rt2x00dev->tx[queue];
676
677 if (!rt2x00dev->bcn)
678 return NULL;
679
e58c6aca 680 if (queue == QID_BEACON)
181d6902 681 return &rt2x00dev->bcn[0];
e58c6aca 682 else if (queue == QID_ATIM && atim)
181d6902
ID
683 return &rt2x00dev->bcn[1];
684
685 return NULL;
686}
687EXPORT_SYMBOL_GPL(rt2x00queue_get_queue);
688
689struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue,
690 enum queue_index index)
691{
692 struct queue_entry *entry;
5f46c4d0 693 unsigned long irqflags;
181d6902
ID
694
695 if (unlikely(index >= Q_INDEX_MAX)) {
696 ERROR(queue->rt2x00dev,
697 "Entry requested from invalid index type (%d)\n", index);
698 return NULL;
699 }
700
5f46c4d0 701 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
702
703 entry = &queue->entries[queue->index[index]];
704
5f46c4d0 705 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902
ID
706
707 return entry;
708}
709EXPORT_SYMBOL_GPL(rt2x00queue_get_entry);
710
711void rt2x00queue_index_inc(struct data_queue *queue, enum queue_index index)
712{
5f46c4d0
ID
713 unsigned long irqflags;
714
181d6902
ID
715 if (unlikely(index >= Q_INDEX_MAX)) {
716 ERROR(queue->rt2x00dev,
717 "Index change on invalid index type (%d)\n", index);
718 return;
719 }
720
5f46c4d0 721 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
722
723 queue->index[index]++;
724 if (queue->index[index] >= queue->limit)
725 queue->index[index] = 0;
726
652a9dd2
ID
727 queue->last_action[index] = jiffies;
728
10b6b801
ID
729 if (index == Q_INDEX) {
730 queue->length++;
731 } else if (index == Q_INDEX_DONE) {
732 queue->length--;
55887511 733 queue->count++;
10b6b801 734 }
181d6902 735
5f46c4d0 736 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902 737}
181d6902
ID
738
739static void rt2x00queue_reset(struct data_queue *queue)
740{
5f46c4d0 741 unsigned long irqflags;
652a9dd2 742 unsigned int i;
5f46c4d0
ID
743
744 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
745
746 queue->count = 0;
747 queue->length = 0;
652a9dd2
ID
748
749 for (i = 0; i < Q_INDEX_MAX; i++) {
750 queue->index[i] = 0;
751 queue->last_action[i] = jiffies;
752 }
181d6902 753
5f46c4d0 754 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902
ID
755}
756
a2c9b652
ID
757void rt2x00queue_stop_queues(struct rt2x00_dev *rt2x00dev)
758{
759 struct data_queue *queue;
760
761 txall_queue_for_each(rt2x00dev, queue)
93331458 762 rt2x00dev->ops->lib->kill_tx_queue(queue);
a2c9b652
ID
763}
764
798b7adb 765void rt2x00queue_init_queues(struct rt2x00_dev *rt2x00dev)
181d6902
ID
766{
767 struct data_queue *queue;
768 unsigned int i;
769
798b7adb 770 queue_for_each(rt2x00dev, queue) {
181d6902
ID
771 rt2x00queue_reset(queue);
772
9c0ab712 773 for (i = 0; i < queue->limit; i++) {
798b7adb 774 rt2x00dev->ops->lib->clear_entry(&queue->entries[i]);
7e613e16
ID
775 if (queue->qid == QID_RX)
776 rt2x00queue_index_inc(queue, Q_INDEX);
9c0ab712 777 }
181d6902
ID
778 }
779}
780
781static int rt2x00queue_alloc_entries(struct data_queue *queue,
782 const struct data_queue_desc *qdesc)
783{
784 struct queue_entry *entries;
785 unsigned int entry_size;
786 unsigned int i;
787
788 rt2x00queue_reset(queue);
789
790 queue->limit = qdesc->entry_num;
b869767b 791 queue->threshold = DIV_ROUND_UP(qdesc->entry_num, 10);
181d6902
ID
792 queue->data_size = qdesc->data_size;
793 queue->desc_size = qdesc->desc_size;
794
795 /*
796 * Allocate all queue entries.
797 */
798 entry_size = sizeof(*entries) + qdesc->priv_size;
baeb2ffa 799 entries = kcalloc(queue->limit, entry_size, GFP_KERNEL);
181d6902
ID
800 if (!entries)
801 return -ENOMEM;
802
803#define QUEUE_ENTRY_PRIV_OFFSET(__base, __index, __limit, __esize, __psize) \
f8bfbc31
ME
804 (((char *)(__base)) + ((__limit) * (__esize)) + \
805 ((__index) * (__psize)))
181d6902
ID
806
807 for (i = 0; i < queue->limit; i++) {
808 entries[i].flags = 0;
809 entries[i].queue = queue;
810 entries[i].skb = NULL;
811 entries[i].entry_idx = i;
812 entries[i].priv_data =
813 QUEUE_ENTRY_PRIV_OFFSET(entries, i, queue->limit,
814 sizeof(*entries), qdesc->priv_size);
815 }
816
817#undef QUEUE_ENTRY_PRIV_OFFSET
818
819 queue->entries = entries;
820
821 return 0;
822}
823
fa69560f 824static void rt2x00queue_free_skbs(struct data_queue *queue)
30caa6e3
GW
825{
826 unsigned int i;
827
828 if (!queue->entries)
829 return;
830
831 for (i = 0; i < queue->limit; i++) {
fa69560f 832 rt2x00queue_free_skb(&queue->entries[i]);
30caa6e3
GW
833 }
834}
835
fa69560f 836static int rt2x00queue_alloc_rxskbs(struct data_queue *queue)
30caa6e3
GW
837{
838 unsigned int i;
839 struct sk_buff *skb;
840
841 for (i = 0; i < queue->limit; i++) {
fa69560f 842 skb = rt2x00queue_alloc_rxskb(&queue->entries[i]);
30caa6e3 843 if (!skb)
61243d8e 844 return -ENOMEM;
30caa6e3
GW
845 queue->entries[i].skb = skb;
846 }
847
848 return 0;
30caa6e3
GW
849}
850
181d6902
ID
851int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev)
852{
853 struct data_queue *queue;
854 int status;
855
181d6902
ID
856 status = rt2x00queue_alloc_entries(rt2x00dev->rx, rt2x00dev->ops->rx);
857 if (status)
858 goto exit;
859
860 tx_queue_for_each(rt2x00dev, queue) {
861 status = rt2x00queue_alloc_entries(queue, rt2x00dev->ops->tx);
862 if (status)
863 goto exit;
864 }
865
866 status = rt2x00queue_alloc_entries(rt2x00dev->bcn, rt2x00dev->ops->bcn);
867 if (status)
868 goto exit;
869
30caa6e3
GW
870 if (test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags)) {
871 status = rt2x00queue_alloc_entries(&rt2x00dev->bcn[1],
872 rt2x00dev->ops->atim);
873 if (status)
874 goto exit;
875 }
181d6902 876
fa69560f 877 status = rt2x00queue_alloc_rxskbs(rt2x00dev->rx);
181d6902
ID
878 if (status)
879 goto exit;
880
881 return 0;
882
883exit:
884 ERROR(rt2x00dev, "Queue entries allocation failed.\n");
885
886 rt2x00queue_uninitialize(rt2x00dev);
887
888 return status;
889}
890
891void rt2x00queue_uninitialize(struct rt2x00_dev *rt2x00dev)
892{
893 struct data_queue *queue;
894
fa69560f 895 rt2x00queue_free_skbs(rt2x00dev->rx);
30caa6e3 896
181d6902
ID
897 queue_for_each(rt2x00dev, queue) {
898 kfree(queue->entries);
899 queue->entries = NULL;
900 }
901}
902
8f539276
ID
903static void rt2x00queue_init(struct rt2x00_dev *rt2x00dev,
904 struct data_queue *queue, enum data_queue_qid qid)
905{
906 spin_lock_init(&queue->lock);
907
908 queue->rt2x00dev = rt2x00dev;
909 queue->qid = qid;
2af0a570 910 queue->txop = 0;
8f539276
ID
911 queue->aifs = 2;
912 queue->cw_min = 5;
913 queue->cw_max = 10;
914}
915
181d6902
ID
916int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
917{
918 struct data_queue *queue;
919 enum data_queue_qid qid;
920 unsigned int req_atim =
921 !!test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
922
923 /*
924 * We need the following queues:
925 * RX: 1
61448f88 926 * TX: ops->tx_queues
181d6902
ID
927 * Beacon: 1
928 * Atim: 1 (if required)
929 */
61448f88 930 rt2x00dev->data_queues = 2 + rt2x00dev->ops->tx_queues + req_atim;
181d6902 931
baeb2ffa 932 queue = kcalloc(rt2x00dev->data_queues, sizeof(*queue), GFP_KERNEL);
181d6902
ID
933 if (!queue) {
934 ERROR(rt2x00dev, "Queue allocation failed.\n");
935 return -ENOMEM;
936 }
937
938 /*
939 * Initialize pointers
940 */
941 rt2x00dev->rx = queue;
942 rt2x00dev->tx = &queue[1];
61448f88 943 rt2x00dev->bcn = &queue[1 + rt2x00dev->ops->tx_queues];
181d6902
ID
944
945 /*
946 * Initialize queue parameters.
947 * RX: qid = QID_RX
948 * TX: qid = QID_AC_BE + index
949 * TX: cw_min: 2^5 = 32.
950 * TX: cw_max: 2^10 = 1024.
565a019a
ID
951 * BCN: qid = QID_BEACON
952 * ATIM: qid = QID_ATIM
181d6902 953 */
8f539276 954 rt2x00queue_init(rt2x00dev, rt2x00dev->rx, QID_RX);
181d6902 955
8f539276
ID
956 qid = QID_AC_BE;
957 tx_queue_for_each(rt2x00dev, queue)
958 rt2x00queue_init(rt2x00dev, queue, qid++);
181d6902 959
565a019a 960 rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[0], QID_BEACON);
181d6902 961 if (req_atim)
565a019a 962 rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[1], QID_ATIM);
181d6902
ID
963
964 return 0;
965}
966
967void rt2x00queue_free(struct rt2x00_dev *rt2x00dev)
968{
969 kfree(rt2x00dev->rx);
970 rt2x00dev->rx = NULL;
971 rt2x00dev->tx = NULL;
972 rt2x00dev->bcn = NULL;
973}
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