rt2x00: Add support for RT3572/RT3592/RT3592+Bluetooth combo card
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2x00queue.c
CommitLineData
181d6902 1/*
7e613e16
ID
2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2004 - 2009 Gertjan van Wingerde <gwingerde@gmail.com>
181d6902
ID
5 <http://rt2x00.serialmonkey.com>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the
19 Free Software Foundation, Inc.,
20 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22
23/*
24 Module: rt2x00lib
25 Abstract: rt2x00 queue specific routines.
26 */
27
5a0e3ad6 28#include <linux/slab.h>
181d6902
ID
29#include <linux/kernel.h>
30#include <linux/module.h>
c4da0048 31#include <linux/dma-mapping.h>
181d6902
ID
32
33#include "rt2x00.h"
34#include "rt2x00lib.h"
35
fa69560f 36struct sk_buff *rt2x00queue_alloc_rxskb(struct queue_entry *entry)
239c249d 37{
fa69560f 38 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
c4da0048
GW
39 struct sk_buff *skb;
40 struct skb_frame_desc *skbdesc;
2bb057d0
ID
41 unsigned int frame_size;
42 unsigned int head_size = 0;
43 unsigned int tail_size = 0;
239c249d
GW
44
45 /*
46 * The frame size includes descriptor size, because the
47 * hardware directly receive the frame into the skbuffer.
48 */
c4da0048 49 frame_size = entry->queue->data_size + entry->queue->desc_size;
239c249d
GW
50
51 /*
ff352391
ID
52 * The payload should be aligned to a 4-byte boundary,
53 * this means we need at least 3 bytes for moving the frame
54 * into the correct offset.
239c249d 55 */
2bb057d0
ID
56 head_size = 4;
57
58 /*
59 * For IV/EIV/ICV assembly we must make sure there is
60 * at least 8 bytes bytes available in headroom for IV/EIV
9c3444d3 61 * and 8 bytes for ICV data as tailroon.
2bb057d0 62 */
7dab73b3 63 if (test_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags)) {
2bb057d0 64 head_size += 8;
9c3444d3 65 tail_size += 8;
2bb057d0 66 }
239c249d
GW
67
68 /*
69 * Allocate skbuffer.
70 */
2bb057d0 71 skb = dev_alloc_skb(frame_size + head_size + tail_size);
239c249d
GW
72 if (!skb)
73 return NULL;
74
2bb057d0
ID
75 /*
76 * Make sure we not have a frame with the requested bytes
77 * available in the head and tail.
78 */
79 skb_reserve(skb, head_size);
239c249d
GW
80 skb_put(skb, frame_size);
81
c4da0048
GW
82 /*
83 * Populate skbdesc.
84 */
85 skbdesc = get_skb_frame_desc(skb);
86 memset(skbdesc, 0, sizeof(*skbdesc));
87 skbdesc->entry = entry;
88
7dab73b3 89 if (test_bit(REQUIRE_DMA, &rt2x00dev->cap_flags)) {
c4da0048
GW
90 skbdesc->skb_dma = dma_map_single(rt2x00dev->dev,
91 skb->data,
92 skb->len,
93 DMA_FROM_DEVICE);
94 skbdesc->flags |= SKBDESC_DMA_MAPPED_RX;
95 }
96
239c249d
GW
97 return skb;
98}
30caa6e3 99
fa69560f 100void rt2x00queue_map_txskb(struct queue_entry *entry)
30caa6e3 101{
fa69560f
ID
102 struct device *dev = entry->queue->rt2x00dev->dev;
103 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
c4da0048 104
3ee54a07 105 skbdesc->skb_dma =
fa69560f 106 dma_map_single(dev, entry->skb->data, entry->skb->len, DMA_TO_DEVICE);
c4da0048
GW
107 skbdesc->flags |= SKBDESC_DMA_MAPPED_TX;
108}
109EXPORT_SYMBOL_GPL(rt2x00queue_map_txskb);
110
fa69560f 111void rt2x00queue_unmap_skb(struct queue_entry *entry)
c4da0048 112{
fa69560f
ID
113 struct device *dev = entry->queue->rt2x00dev->dev;
114 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
c4da0048
GW
115
116 if (skbdesc->flags & SKBDESC_DMA_MAPPED_RX) {
fa69560f 117 dma_unmap_single(dev, skbdesc->skb_dma, entry->skb->len,
c4da0048
GW
118 DMA_FROM_DEVICE);
119 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_RX;
546adf29 120 } else if (skbdesc->flags & SKBDESC_DMA_MAPPED_TX) {
fa69560f 121 dma_unmap_single(dev, skbdesc->skb_dma, entry->skb->len,
c4da0048
GW
122 DMA_TO_DEVICE);
123 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_TX;
124 }
125}
0b8004aa 126EXPORT_SYMBOL_GPL(rt2x00queue_unmap_skb);
c4da0048 127
fa69560f 128void rt2x00queue_free_skb(struct queue_entry *entry)
c4da0048 129{
fa69560f 130 if (!entry->skb)
9a613195
ID
131 return;
132
fa69560f
ID
133 rt2x00queue_unmap_skb(entry);
134 dev_kfree_skb_any(entry->skb);
135 entry->skb = NULL;
30caa6e3 136}
239c249d 137
daee6c09 138void rt2x00queue_align_frame(struct sk_buff *skb)
9f166171 139{
9f166171 140 unsigned int frame_length = skb->len;
daee6c09 141 unsigned int align = ALIGN_SIZE(skb, 0);
9f166171
ID
142
143 if (!align)
144 return;
145
daee6c09
ID
146 skb_push(skb, align);
147 memmove(skb->data, skb->data + align, frame_length);
148 skb_trim(skb, frame_length);
149}
150
daee6c09
ID
151void rt2x00queue_insert_l2pad(struct sk_buff *skb, unsigned int header_length)
152{
2e331462 153 unsigned int payload_length = skb->len - header_length;
daee6c09
ID
154 unsigned int header_align = ALIGN_SIZE(skb, 0);
155 unsigned int payload_align = ALIGN_SIZE(skb, header_length);
e54be4e7 156 unsigned int l2pad = payload_length ? L2PAD_SIZE(header_length) : 0;
daee6c09 157
2e331462
GW
158 /*
159 * Adjust the header alignment if the payload needs to be moved more
160 * than the header.
161 */
162 if (payload_align > header_align)
163 header_align += 4;
164
165 /* There is nothing to do if no alignment is needed */
166 if (!header_align)
167 return;
daee6c09 168
2e331462
GW
169 /* Reserve the amount of space needed in front of the frame */
170 skb_push(skb, header_align);
171
172 /*
173 * Move the header.
174 */
175 memmove(skb->data, skb->data + header_align, header_length);
176
177 /* Move the payload, if present and if required */
178 if (payload_length && payload_align)
daee6c09 179 memmove(skb->data + header_length + l2pad,
a5186e99 180 skb->data + header_length + l2pad + payload_align,
2e331462
GW
181 payload_length);
182
183 /* Trim the skb to the correct size */
184 skb_trim(skb, header_length + l2pad + payload_length);
9f166171
ID
185}
186
daee6c09
ID
187void rt2x00queue_remove_l2pad(struct sk_buff *skb, unsigned int header_length)
188{
a061a93b
GW
189 /*
190 * L2 padding is only present if the skb contains more than just the
191 * IEEE 802.11 header.
192 */
193 unsigned int l2pad = (skb->len > header_length) ?
194 L2PAD_SIZE(header_length) : 0;
daee6c09 195
354e39db 196 if (!l2pad)
daee6c09
ID
197 return;
198
a061a93b
GW
199 memmove(skb->data + l2pad, skb->data, header_length);
200 skb_pull(skb, l2pad);
daee6c09
ID
201}
202
7b40982e
ID
203static void rt2x00queue_create_tx_descriptor_seq(struct queue_entry *entry,
204 struct txentry_desc *txdesc)
205{
206 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
207 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
208 struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
209 unsigned long irqflags;
210
c262e08b 211 if (!(tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ))
7b40982e
ID
212 return;
213
7fe7ee77
HS
214 __set_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags);
215
7dab73b3 216 if (!test_bit(REQUIRE_SW_SEQNO, &entry->queue->rt2x00dev->cap_flags))
7fe7ee77
HS
217 return;
218
7b40982e 219 /*
7fe7ee77
HS
220 * The hardware is not able to insert a sequence number. Assign a
221 * software generated one here.
7b40982e
ID
222 *
223 * This is wrong because beacons are not getting sequence
224 * numbers assigned properly.
225 *
226 * A secondary problem exists for drivers that cannot toggle
227 * sequence counting per-frame, since those will override the
228 * sequence counter given by mac80211.
229 */
230 spin_lock_irqsave(&intf->seqlock, irqflags);
231
232 if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags))
233 intf->seqno += 0x10;
234 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
235 hdr->seq_ctrl |= cpu_to_le16(intf->seqno);
236
237 spin_unlock_irqrestore(&intf->seqlock, irqflags);
238
7b40982e
ID
239}
240
241static void rt2x00queue_create_tx_descriptor_plcp(struct queue_entry *entry,
242 struct txentry_desc *txdesc,
243 const struct rt2x00_rate *hwrate)
244{
245 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
246 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
247 struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0];
248 unsigned int data_length;
249 unsigned int duration;
250 unsigned int residual;
251
2517794b
HS
252 /*
253 * Determine with what IFS priority this frame should be send.
254 * Set ifs to IFS_SIFS when the this is not the first fragment,
255 * or this fragment came after RTS/CTS.
256 */
257 if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags))
258 txdesc->u.plcp.ifs = IFS_BACKOFF;
259 else
260 txdesc->u.plcp.ifs = IFS_SIFS;
261
7b40982e
ID
262 /* Data length + CRC + Crypto overhead (IV/EIV/ICV/MIC) */
263 data_length = entry->skb->len + 4;
264 data_length += rt2x00crypto_tx_overhead(rt2x00dev, entry->skb);
265
266 /*
267 * PLCP setup
268 * Length calculation depends on OFDM/CCK rate.
269 */
26a1d07f
HS
270 txdesc->u.plcp.signal = hwrate->plcp;
271 txdesc->u.plcp.service = 0x04;
7b40982e
ID
272
273 if (hwrate->flags & DEV_RATE_OFDM) {
26a1d07f
HS
274 txdesc->u.plcp.length_high = (data_length >> 6) & 0x3f;
275 txdesc->u.plcp.length_low = data_length & 0x3f;
7b40982e
ID
276 } else {
277 /*
278 * Convert length to microseconds.
279 */
280 residual = GET_DURATION_RES(data_length, hwrate->bitrate);
281 duration = GET_DURATION(data_length, hwrate->bitrate);
282
283 if (residual != 0) {
284 duration++;
285
286 /*
287 * Check if we need to set the Length Extension
288 */
289 if (hwrate->bitrate == 110 && residual <= 30)
26a1d07f 290 txdesc->u.plcp.service |= 0x80;
7b40982e
ID
291 }
292
26a1d07f
HS
293 txdesc->u.plcp.length_high = (duration >> 8) & 0xff;
294 txdesc->u.plcp.length_low = duration & 0xff;
7b40982e
ID
295
296 /*
297 * When preamble is enabled we should set the
298 * preamble bit for the signal.
299 */
300 if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
26a1d07f 301 txdesc->u.plcp.signal |= 0x08;
7b40982e
ID
302 }
303}
304
46a01ec0
GW
305static void rt2x00queue_create_tx_descriptor_ht(struct queue_entry *entry,
306 struct txentry_desc *txdesc,
307 const struct rt2x00_rate *hwrate)
308{
309 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
310 struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0];
311 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
312
313 if (tx_info->control.sta)
314 txdesc->u.ht.mpdu_density =
315 tx_info->control.sta->ht_cap.ampdu_density;
316
317 txdesc->u.ht.ba_size = 7; /* FIXME: What value is needed? */
318
319 /*
320 * Only one STBC stream is supported for now.
321 */
322 if (tx_info->flags & IEEE80211_TX_CTL_STBC)
323 txdesc->u.ht.stbc = 1;
324
325 /*
326 * If IEEE80211_TX_RC_MCS is set txrate->idx just contains the
327 * mcs rate to be used
328 */
329 if (txrate->flags & IEEE80211_TX_RC_MCS) {
330 txdesc->u.ht.mcs = txrate->idx;
331
332 /*
333 * MIMO PS should be set to 1 for STA's using dynamic SM PS
334 * when using more then one tx stream (>MCS7).
335 */
336 if (tx_info->control.sta && txdesc->u.ht.mcs > 7 &&
337 ((tx_info->control.sta->ht_cap.cap &
338 IEEE80211_HT_CAP_SM_PS) >>
339 IEEE80211_HT_CAP_SM_PS_SHIFT) ==
340 WLAN_HT_CAP_SM_PS_DYNAMIC)
341 __set_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags);
342 } else {
343 txdesc->u.ht.mcs = rt2x00_get_rate_mcs(hwrate->mcs);
344 if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
345 txdesc->u.ht.mcs |= 0x08;
346 }
347
348 /*
349 * This frame is eligible for an AMPDU, however, don't aggregate
350 * frames that are intended to probe a specific tx rate.
351 */
352 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU &&
353 !(tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE))
354 __set_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags);
355
356 /*
357 * Set 40Mhz mode if necessary (for legacy rates this will
358 * duplicate the frame to both channels).
359 */
360 if (txrate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH ||
361 txrate->flags & IEEE80211_TX_RC_DUP_DATA)
362 __set_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags);
363 if (txrate->flags & IEEE80211_TX_RC_SHORT_GI)
364 __set_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags);
365
366 /*
367 * Determine IFS values
368 * - Use TXOP_BACKOFF for management frames except beacons
369 * - Use TXOP_SIFS for fragment bursts
370 * - Use TXOP_HTTXOP for everything else
371 *
372 * Note: rt2800 devices won't use CTS protection (if used)
373 * for frames not transmitted with TXOP_HTTXOP
374 */
375 if (ieee80211_is_mgmt(hdr->frame_control) &&
376 !ieee80211_is_beacon(hdr->frame_control))
377 txdesc->u.ht.txop = TXOP_BACKOFF;
378 else if (!(tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT))
379 txdesc->u.ht.txop = TXOP_SIFS;
380 else
381 txdesc->u.ht.txop = TXOP_HTTXOP;
382}
383
bd88a781
ID
384static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry,
385 struct txentry_desc *txdesc)
7050ec82 386{
2e92e6f2 387 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
e039fa4a 388 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
7050ec82 389 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
55b585e2
HS
390 struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0];
391 struct ieee80211_rate *rate;
392 const struct rt2x00_rate *hwrate = NULL;
7050ec82
ID
393
394 memset(txdesc, 0, sizeof(*txdesc));
395
9f166171 396 /*
df624ca5 397 * Header and frame information.
9f166171 398 */
df624ca5 399 txdesc->length = entry->skb->len;
9f166171 400 txdesc->header_length = ieee80211_get_hdrlen_from_skb(entry->skb);
9f166171 401
7050ec82
ID
402 /*
403 * Check whether this frame is to be acked.
404 */
e039fa4a 405 if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK))
7050ec82
ID
406 __set_bit(ENTRY_TXD_ACK, &txdesc->flags);
407
408 /*
409 * Check if this is a RTS/CTS frame
410 */
ac104462
ID
411 if (ieee80211_is_rts(hdr->frame_control) ||
412 ieee80211_is_cts(hdr->frame_control)) {
7050ec82 413 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
ac104462 414 if (ieee80211_is_rts(hdr->frame_control))
7050ec82 415 __set_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags);
e039fa4a 416 else
7050ec82 417 __set_bit(ENTRY_TXD_CTS_FRAME, &txdesc->flags);
e039fa4a 418 if (tx_info->control.rts_cts_rate_idx >= 0)
2e92e6f2 419 rate =
e039fa4a 420 ieee80211_get_rts_cts_rate(rt2x00dev->hw, tx_info);
7050ec82
ID
421 }
422
423 /*
424 * Determine retry information.
425 */
e6a9854b 426 txdesc->retry_limit = tx_info->control.rates[0].count - 1;
42c82857 427 if (txdesc->retry_limit >= rt2x00dev->long_retry)
7050ec82
ID
428 __set_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags);
429
430 /*
431 * Check if more fragments are pending
432 */
2606e422 433 if (ieee80211_has_morefrags(hdr->frame_control)) {
7050ec82
ID
434 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
435 __set_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags);
436 }
437
2606e422
HS
438 /*
439 * Check if more frames (!= fragments) are pending
440 */
441 if (tx_info->flags & IEEE80211_TX_CTL_MORE_FRAMES)
442 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
443
7050ec82
ID
444 /*
445 * Beacons and probe responses require the tsf timestamp
1bce85cf 446 * to be inserted into the frame.
7050ec82 447 */
1bce85cf
HS
448 if (ieee80211_is_beacon(hdr->frame_control) ||
449 ieee80211_is_probe_resp(hdr->frame_control))
7050ec82
ID
450 __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags);
451
7b40982e 452 if ((tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) &&
2517794b 453 !test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags))
7050ec82 454 __set_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags);
7050ec82 455
076f9582
ID
456 /*
457 * Determine rate modulation.
458 */
55b585e2
HS
459 if (txrate->flags & IEEE80211_TX_RC_GREEN_FIELD)
460 txdesc->rate_mode = RATE_MODE_HT_GREENFIELD;
461 else if (txrate->flags & IEEE80211_TX_RC_MCS)
462 txdesc->rate_mode = RATE_MODE_HT_MIX;
463 else {
464 rate = ieee80211_get_tx_rate(rt2x00dev->hw, tx_info);
465 hwrate = rt2x00_get_rate(rate->hw_value);
466 if (hwrate->flags & DEV_RATE_OFDM)
467 txdesc->rate_mode = RATE_MODE_OFDM;
468 else
469 txdesc->rate_mode = RATE_MODE_CCK;
470 }
7050ec82 471
7b40982e
ID
472 /*
473 * Apply TX descriptor handling by components
474 */
475 rt2x00crypto_create_tx_descriptor(entry, txdesc);
476 rt2x00queue_create_tx_descriptor_seq(entry, txdesc);
26a1d07f 477
7dab73b3 478 if (test_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags))
46a01ec0 479 rt2x00queue_create_tx_descriptor_ht(entry, txdesc, hwrate);
26a1d07f
HS
480 else
481 rt2x00queue_create_tx_descriptor_plcp(entry, txdesc, hwrate);
7050ec82 482}
7050ec82 483
78eea11b
GW
484static int rt2x00queue_write_tx_data(struct queue_entry *entry,
485 struct txentry_desc *txdesc)
486{
487 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
488
489 /*
490 * This should not happen, we already checked the entry
491 * was ours. When the hardware disagrees there has been
492 * a queue corruption!
493 */
494 if (unlikely(rt2x00dev->ops->lib->get_entry_state &&
495 rt2x00dev->ops->lib->get_entry_state(entry))) {
496 ERROR(rt2x00dev,
497 "Corrupt queue %d, accessing entry which is not ours.\n"
498 "Please file bug report to %s.\n",
499 entry->queue->qid, DRV_PROJECT);
500 return -EINVAL;
501 }
502
503 /*
504 * Add the requested extra tx headroom in front of the skb.
505 */
506 skb_push(entry->skb, rt2x00dev->ops->extra_tx_headroom);
507 memset(entry->skb->data, 0, rt2x00dev->ops->extra_tx_headroom);
508
509 /*
76dd5ddf 510 * Call the driver's write_tx_data function, if it exists.
78eea11b 511 */
76dd5ddf
GW
512 if (rt2x00dev->ops->lib->write_tx_data)
513 rt2x00dev->ops->lib->write_tx_data(entry, txdesc);
78eea11b
GW
514
515 /*
516 * Map the skb to DMA.
517 */
7dab73b3 518 if (test_bit(REQUIRE_DMA, &rt2x00dev->cap_flags))
fa69560f 519 rt2x00queue_map_txskb(entry);
78eea11b
GW
520
521 return 0;
522}
523
bd88a781
ID
524static void rt2x00queue_write_tx_descriptor(struct queue_entry *entry,
525 struct txentry_desc *txdesc)
7050ec82 526{
b869767b 527 struct data_queue *queue = entry->queue;
7050ec82 528
93331458 529 queue->rt2x00dev->ops->lib->write_tx_desc(entry, txdesc);
7050ec82
ID
530
531 /*
532 * All processing on the frame has been completed, this means
533 * it is now ready to be dumped to userspace through debugfs.
534 */
93331458 535 rt2x00debug_dump_frame(queue->rt2x00dev, DUMP_FRAME_TX, entry->skb);
6295d815
GW
536}
537
8be4eed0 538static void rt2x00queue_kick_tx_queue(struct data_queue *queue,
6295d815
GW
539 struct txentry_desc *txdesc)
540{
7050ec82 541 /*
b869767b 542 * Check if we need to kick the queue, there are however a few rules
6295d815 543 * 1) Don't kick unless this is the last in frame in a burst.
b869767b
ID
544 * When the burst flag is set, this frame is always followed
545 * by another frame which in some way are related to eachother.
546 * This is true for fragments, RTS or CTS-to-self frames.
6295d815 547 * 2) Rule 1 can be broken when the available entries
b869767b 548 * in the queue are less then a certain threshold.
7050ec82 549 */
b869767b
ID
550 if (rt2x00queue_threshold(queue) ||
551 !test_bit(ENTRY_TXD_BURST, &txdesc->flags))
dbba306f 552 queue->rt2x00dev->ops->lib->kick_queue(queue);
7050ec82 553}
7050ec82 554
7351c6bd
JB
555int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
556 bool local)
6db3786a 557{
e6a9854b 558 struct ieee80211_tx_info *tx_info;
6db3786a
ID
559 struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX);
560 struct txentry_desc txdesc;
d74f5ba4 561 struct skb_frame_desc *skbdesc;
e6a9854b 562 u8 rate_idx, rate_flags;
6db3786a 563
6a4c499e
HS
564 if (unlikely(rt2x00queue_full(queue))) {
565 ERROR(queue->rt2x00dev,
566 "Dropping frame due to full tx queue %d.\n", queue->qid);
0e3de998 567 return -ENOBUFS;
6a4c499e 568 }
6db3786a 569
c6084d5f
HS
570 if (unlikely(test_and_set_bit(ENTRY_OWNER_DEVICE_DATA,
571 &entry->flags))) {
6db3786a
ID
572 ERROR(queue->rt2x00dev,
573 "Arrived at non-free entry in the non-full queue %d.\n"
574 "Please file bug report to %s.\n",
575 queue->qid, DRV_PROJECT);
576 return -EINVAL;
577 }
578
579 /*
580 * Copy all TX descriptor information into txdesc,
581 * after that we are free to use the skb->cb array
582 * for our information.
583 */
584 entry->skb = skb;
585 rt2x00queue_create_tx_descriptor(entry, &txdesc);
586
d74f5ba4 587 /*
e6a9854b 588 * All information is retrieved from the skb->cb array,
2bb057d0 589 * now we should claim ownership of the driver part of that
e6a9854b 590 * array, preserving the bitrate index and flags.
d74f5ba4 591 */
e6a9854b
JB
592 tx_info = IEEE80211_SKB_CB(skb);
593 rate_idx = tx_info->control.rates[0].idx;
594 rate_flags = tx_info->control.rates[0].flags;
0e3de998 595 skbdesc = get_skb_frame_desc(skb);
d74f5ba4
ID
596 memset(skbdesc, 0, sizeof(*skbdesc));
597 skbdesc->entry = entry;
e6a9854b
JB
598 skbdesc->tx_rate_idx = rate_idx;
599 skbdesc->tx_rate_flags = rate_flags;
d74f5ba4 600
7351c6bd
JB
601 if (local)
602 skbdesc->flags |= SKBDESC_NOT_MAC80211;
603
2bb057d0
ID
604 /*
605 * When hardware encryption is supported, and this frame
606 * is to be encrypted, we should strip the IV/EIV data from
3ad2f3fb 607 * the frame so we can provide it to the driver separately.
2bb057d0
ID
608 */
609 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc.flags) &&
dddfb478 610 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc.flags)) {
7dab73b3 611 if (test_bit(REQUIRE_COPY_IV, &queue->rt2x00dev->cap_flags))
9eb4e21e 612 rt2x00crypto_tx_copy_iv(skb, &txdesc);
dddfb478 613 else
9eb4e21e 614 rt2x00crypto_tx_remove_iv(skb, &txdesc);
dddfb478 615 }
2bb057d0 616
93354cbb 617 /*
25985edc 618 * When DMA allocation is required we should guarantee to the
93354cbb 619 * driver that the DMA is aligned to a 4-byte boundary.
93354cbb
ID
620 * However some drivers require L2 padding to pad the payload
621 * rather then the header. This could be a requirement for
622 * PCI and USB devices, while header alignment only is valid
623 * for PCI devices.
624 */
7dab73b3 625 if (test_bit(REQUIRE_L2PAD, &queue->rt2x00dev->cap_flags))
daee6c09 626 rt2x00queue_insert_l2pad(entry->skb, txdesc.header_length);
7dab73b3 627 else if (test_bit(REQUIRE_DMA, &queue->rt2x00dev->cap_flags))
daee6c09 628 rt2x00queue_align_frame(entry->skb);
9f166171 629
2bb057d0
ID
630 /*
631 * It could be possible that the queue was corrupted and this
0e3de998
ID
632 * call failed. Since we always return NETDEV_TX_OK to mac80211,
633 * this frame will simply be dropped.
2bb057d0 634 */
78eea11b 635 if (unlikely(rt2x00queue_write_tx_data(entry, &txdesc))) {
0262ab0d 636 clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
2bb057d0 637 entry->skb = NULL;
0e3de998 638 return -EIO;
6db3786a
ID
639 }
640
0262ab0d 641 set_bit(ENTRY_DATA_PENDING, &entry->flags);
6db3786a 642
75256f03 643 rt2x00queue_index_inc(entry, Q_INDEX);
6db3786a 644 rt2x00queue_write_tx_descriptor(entry, &txdesc);
8be4eed0 645 rt2x00queue_kick_tx_queue(queue, &txdesc);
6db3786a
ID
646
647 return 0;
648}
649
69cf36a4
HS
650int rt2x00queue_clear_beacon(struct rt2x00_dev *rt2x00dev,
651 struct ieee80211_vif *vif)
652{
653 struct rt2x00_intf *intf = vif_to_intf(vif);
654
655 if (unlikely(!intf->beacon))
656 return -ENOBUFS;
657
658 mutex_lock(&intf->beacon_skb_mutex);
659
660 /*
661 * Clean up the beacon skb.
662 */
663 rt2x00queue_free_skb(intf->beacon);
664
665 /*
666 * Clear beacon (single bssid devices don't need to clear the beacon
667 * since the beacon queue will get stopped anyway).
668 */
669 if (rt2x00dev->ops->lib->clear_beacon)
670 rt2x00dev->ops->lib->clear_beacon(intf->beacon);
671
672 mutex_unlock(&intf->beacon_skb_mutex);
673
674 return 0;
675}
676
8414ff07
HS
677int rt2x00queue_update_beacon_locked(struct rt2x00_dev *rt2x00dev,
678 struct ieee80211_vif *vif)
bd88a781
ID
679{
680 struct rt2x00_intf *intf = vif_to_intf(vif);
681 struct skb_frame_desc *skbdesc;
682 struct txentry_desc txdesc;
bd88a781
ID
683
684 if (unlikely(!intf->beacon))
685 return -ENOBUFS;
686
17512dc3
IP
687 /*
688 * Clean up the beacon skb.
689 */
fa69560f 690 rt2x00queue_free_skb(intf->beacon);
17512dc3 691
bd88a781 692 intf->beacon->skb = ieee80211_beacon_get(rt2x00dev->hw, vif);
8414ff07 693 if (!intf->beacon->skb)
bd88a781
ID
694 return -ENOMEM;
695
696 /*
697 * Copy all TX descriptor information into txdesc,
698 * after that we are free to use the skb->cb array
699 * for our information.
700 */
701 rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc);
702
bd88a781
ID
703 /*
704 * Fill in skb descriptor
705 */
706 skbdesc = get_skb_frame_desc(intf->beacon->skb);
707 memset(skbdesc, 0, sizeof(*skbdesc));
bd88a781
ID
708 skbdesc->entry = intf->beacon;
709
bd88a781 710 /*
69cf36a4 711 * Send beacon to hardware.
bd88a781 712 */
f224f4ef 713 rt2x00dev->ops->lib->write_beacon(intf->beacon, &txdesc);
bd88a781 714
8414ff07
HS
715 return 0;
716
717}
718
719int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev,
720 struct ieee80211_vif *vif)
721{
722 struct rt2x00_intf *intf = vif_to_intf(vif);
723 int ret;
724
725 mutex_lock(&intf->beacon_skb_mutex);
726 ret = rt2x00queue_update_beacon_locked(rt2x00dev, vif);
17512dc3
IP
727 mutex_unlock(&intf->beacon_skb_mutex);
728
8414ff07 729 return ret;
bd88a781
ID
730}
731
10e11568 732bool rt2x00queue_for_each_entry(struct data_queue *queue,
5eb7efe8
ID
733 enum queue_index start,
734 enum queue_index end,
10e11568
HS
735 void *data,
736 bool (*fn)(struct queue_entry *entry,
737 void *data))
5eb7efe8
ID
738{
739 unsigned long irqflags;
740 unsigned int index_start;
741 unsigned int index_end;
742 unsigned int i;
743
744 if (unlikely(start >= Q_INDEX_MAX || end >= Q_INDEX_MAX)) {
745 ERROR(queue->rt2x00dev,
746 "Entry requested from invalid index range (%d - %d)\n",
747 start, end);
10e11568 748 return true;
5eb7efe8
ID
749 }
750
751 /*
752 * Only protect the range we are going to loop over,
753 * if during our loop a extra entry is set to pending
754 * it should not be kicked during this run, since it
755 * is part of another TX operation.
756 */
813f0339 757 spin_lock_irqsave(&queue->index_lock, irqflags);
5eb7efe8
ID
758 index_start = queue->index[start];
759 index_end = queue->index[end];
813f0339 760 spin_unlock_irqrestore(&queue->index_lock, irqflags);
5eb7efe8
ID
761
762 /*
25985edc 763 * Start from the TX done pointer, this guarantees that we will
5eb7efe8
ID
764 * send out all frames in the correct order.
765 */
766 if (index_start < index_end) {
10e11568
HS
767 for (i = index_start; i < index_end; i++) {
768 if (fn(&queue->entries[i], data))
769 return true;
770 }
5eb7efe8 771 } else {
10e11568
HS
772 for (i = index_start; i < queue->limit; i++) {
773 if (fn(&queue->entries[i], data))
774 return true;
775 }
5eb7efe8 776
10e11568
HS
777 for (i = 0; i < index_end; i++) {
778 if (fn(&queue->entries[i], data))
779 return true;
780 }
5eb7efe8 781 }
10e11568
HS
782
783 return false;
5eb7efe8
ID
784}
785EXPORT_SYMBOL_GPL(rt2x00queue_for_each_entry);
786
181d6902
ID
787struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue,
788 enum queue_index index)
789{
790 struct queue_entry *entry;
5f46c4d0 791 unsigned long irqflags;
181d6902
ID
792
793 if (unlikely(index >= Q_INDEX_MAX)) {
794 ERROR(queue->rt2x00dev,
795 "Entry requested from invalid index type (%d)\n", index);
796 return NULL;
797 }
798
813f0339 799 spin_lock_irqsave(&queue->index_lock, irqflags);
181d6902
ID
800
801 entry = &queue->entries[queue->index[index]];
802
813f0339 803 spin_unlock_irqrestore(&queue->index_lock, irqflags);
181d6902
ID
804
805 return entry;
806}
807EXPORT_SYMBOL_GPL(rt2x00queue_get_entry);
808
75256f03 809void rt2x00queue_index_inc(struct queue_entry *entry, enum queue_index index)
181d6902 810{
75256f03 811 struct data_queue *queue = entry->queue;
5f46c4d0
ID
812 unsigned long irqflags;
813
181d6902
ID
814 if (unlikely(index >= Q_INDEX_MAX)) {
815 ERROR(queue->rt2x00dev,
816 "Index change on invalid index type (%d)\n", index);
817 return;
818 }
819
813f0339 820 spin_lock_irqsave(&queue->index_lock, irqflags);
181d6902
ID
821
822 queue->index[index]++;
823 if (queue->index[index] >= queue->limit)
824 queue->index[index] = 0;
825
75256f03 826 entry->last_action = jiffies;
652a9dd2 827
10b6b801
ID
828 if (index == Q_INDEX) {
829 queue->length++;
830 } else if (index == Q_INDEX_DONE) {
831 queue->length--;
55887511 832 queue->count++;
10b6b801 833 }
181d6902 834
813f0339 835 spin_unlock_irqrestore(&queue->index_lock, irqflags);
181d6902 836}
181d6902 837
0b7fde54
ID
838void rt2x00queue_pause_queue(struct data_queue *queue)
839{
840 if (!test_bit(DEVICE_STATE_PRESENT, &queue->rt2x00dev->flags) ||
841 !test_bit(QUEUE_STARTED, &queue->flags) ||
842 test_and_set_bit(QUEUE_PAUSED, &queue->flags))
843 return;
844
845 switch (queue->qid) {
f615e9a3
ID
846 case QID_AC_VO:
847 case QID_AC_VI:
0b7fde54
ID
848 case QID_AC_BE:
849 case QID_AC_BK:
0b7fde54
ID
850 /*
851 * For TX queues, we have to disable the queue
852 * inside mac80211.
853 */
854 ieee80211_stop_queue(queue->rt2x00dev->hw, queue->qid);
855 break;
856 default:
857 break;
858 }
859}
860EXPORT_SYMBOL_GPL(rt2x00queue_pause_queue);
861
862void rt2x00queue_unpause_queue(struct data_queue *queue)
863{
864 if (!test_bit(DEVICE_STATE_PRESENT, &queue->rt2x00dev->flags) ||
865 !test_bit(QUEUE_STARTED, &queue->flags) ||
866 !test_and_clear_bit(QUEUE_PAUSED, &queue->flags))
867 return;
868
869 switch (queue->qid) {
f615e9a3
ID
870 case QID_AC_VO:
871 case QID_AC_VI:
0b7fde54
ID
872 case QID_AC_BE:
873 case QID_AC_BK:
0b7fde54
ID
874 /*
875 * For TX queues, we have to enable the queue
876 * inside mac80211.
877 */
878 ieee80211_wake_queue(queue->rt2x00dev->hw, queue->qid);
879 break;
5be65609
ID
880 case QID_RX:
881 /*
882 * For RX we need to kick the queue now in order to
883 * receive frames.
884 */
885 queue->rt2x00dev->ops->lib->kick_queue(queue);
0b7fde54
ID
886 default:
887 break;
888 }
889}
890EXPORT_SYMBOL_GPL(rt2x00queue_unpause_queue);
891
892void rt2x00queue_start_queue(struct data_queue *queue)
893{
894 mutex_lock(&queue->status_lock);
895
896 if (!test_bit(DEVICE_STATE_PRESENT, &queue->rt2x00dev->flags) ||
897 test_and_set_bit(QUEUE_STARTED, &queue->flags)) {
898 mutex_unlock(&queue->status_lock);
899 return;
900 }
901
902 set_bit(QUEUE_PAUSED, &queue->flags);
903
904 queue->rt2x00dev->ops->lib->start_queue(queue);
905
906 rt2x00queue_unpause_queue(queue);
907
908 mutex_unlock(&queue->status_lock);
909}
910EXPORT_SYMBOL_GPL(rt2x00queue_start_queue);
911
912void rt2x00queue_stop_queue(struct data_queue *queue)
913{
914 mutex_lock(&queue->status_lock);
915
916 if (!test_and_clear_bit(QUEUE_STARTED, &queue->flags)) {
917 mutex_unlock(&queue->status_lock);
918 return;
919 }
920
921 rt2x00queue_pause_queue(queue);
922
923 queue->rt2x00dev->ops->lib->stop_queue(queue);
924
925 mutex_unlock(&queue->status_lock);
926}
927EXPORT_SYMBOL_GPL(rt2x00queue_stop_queue);
928
5be65609
ID
929void rt2x00queue_flush_queue(struct data_queue *queue, bool drop)
930{
5be65609
ID
931 bool started;
932 bool tx_queue =
f615e9a3 933 (queue->qid == QID_AC_VO) ||
5be65609 934 (queue->qid == QID_AC_VI) ||
f615e9a3
ID
935 (queue->qid == QID_AC_BE) ||
936 (queue->qid == QID_AC_BK);
5be65609
ID
937
938 mutex_lock(&queue->status_lock);
939
940 /*
941 * If the queue has been started, we must stop it temporarily
942 * to prevent any new frames to be queued on the device. If
943 * we are not dropping the pending frames, the queue must
944 * only be stopped in the software and not the hardware,
945 * otherwise the queue will never become empty on its own.
946 */
947 started = test_bit(QUEUE_STARTED, &queue->flags);
948 if (started) {
949 /*
950 * Pause the queue
951 */
952 rt2x00queue_pause_queue(queue);
953
954 /*
955 * If we are not supposed to drop any pending
956 * frames, this means we must force a start (=kick)
957 * to the queue to make sure the hardware will
958 * start transmitting.
959 */
960 if (!drop && tx_queue)
961 queue->rt2x00dev->ops->lib->kick_queue(queue);
962 }
963
964 /*
152a5992
ID
965 * Check if driver supports flushing, if that is the case we can
966 * defer the flushing to the driver. Otherwise we must use the
967 * alternative which just waits for the queue to become empty.
5be65609 968 */
152a5992
ID
969 if (likely(queue->rt2x00dev->ops->lib->flush_queue))
970 queue->rt2x00dev->ops->lib->flush_queue(queue, drop);
5be65609
ID
971
972 /*
973 * The queue flush has failed...
974 */
975 if (unlikely(!rt2x00queue_empty(queue)))
21957c31 976 WARNING(queue->rt2x00dev, "Queue %d failed to flush\n", queue->qid);
5be65609
ID
977
978 /*
979 * Restore the queue to the previous status
980 */
981 if (started)
982 rt2x00queue_unpause_queue(queue);
983
984 mutex_unlock(&queue->status_lock);
985}
986EXPORT_SYMBOL_GPL(rt2x00queue_flush_queue);
987
0b7fde54
ID
988void rt2x00queue_start_queues(struct rt2x00_dev *rt2x00dev)
989{
990 struct data_queue *queue;
991
992 /*
993 * rt2x00queue_start_queue will call ieee80211_wake_queue
994 * for each queue after is has been properly initialized.
995 */
996 tx_queue_for_each(rt2x00dev, queue)
997 rt2x00queue_start_queue(queue);
998
999 rt2x00queue_start_queue(rt2x00dev->rx);
1000}
1001EXPORT_SYMBOL_GPL(rt2x00queue_start_queues);
1002
1003void rt2x00queue_stop_queues(struct rt2x00_dev *rt2x00dev)
1004{
1005 struct data_queue *queue;
1006
1007 /*
1008 * rt2x00queue_stop_queue will call ieee80211_stop_queue
1009 * as well, but we are completely shutting doing everything
1010 * now, so it is much safer to stop all TX queues at once,
1011 * and use rt2x00queue_stop_queue for cleaning up.
1012 */
1013 ieee80211_stop_queues(rt2x00dev->hw);
1014
1015 tx_queue_for_each(rt2x00dev, queue)
1016 rt2x00queue_stop_queue(queue);
1017
1018 rt2x00queue_stop_queue(rt2x00dev->rx);
1019}
1020EXPORT_SYMBOL_GPL(rt2x00queue_stop_queues);
1021
5be65609
ID
1022void rt2x00queue_flush_queues(struct rt2x00_dev *rt2x00dev, bool drop)
1023{
1024 struct data_queue *queue;
1025
1026 tx_queue_for_each(rt2x00dev, queue)
1027 rt2x00queue_flush_queue(queue, drop);
1028
1029 rt2x00queue_flush_queue(rt2x00dev->rx, drop);
1030}
1031EXPORT_SYMBOL_GPL(rt2x00queue_flush_queues);
1032
181d6902
ID
1033static void rt2x00queue_reset(struct data_queue *queue)
1034{
5f46c4d0 1035 unsigned long irqflags;
652a9dd2 1036 unsigned int i;
5f46c4d0 1037
813f0339 1038 spin_lock_irqsave(&queue->index_lock, irqflags);
181d6902
ID
1039
1040 queue->count = 0;
1041 queue->length = 0;
652a9dd2 1042
75256f03 1043 for (i = 0; i < Q_INDEX_MAX; i++)
652a9dd2 1044 queue->index[i] = 0;
181d6902 1045
813f0339 1046 spin_unlock_irqrestore(&queue->index_lock, irqflags);
181d6902
ID
1047}
1048
798b7adb 1049void rt2x00queue_init_queues(struct rt2x00_dev *rt2x00dev)
181d6902
ID
1050{
1051 struct data_queue *queue;
1052 unsigned int i;
1053
798b7adb 1054 queue_for_each(rt2x00dev, queue) {
181d6902
ID
1055 rt2x00queue_reset(queue);
1056
64e7d723 1057 for (i = 0; i < queue->limit; i++)
798b7adb 1058 rt2x00dev->ops->lib->clear_entry(&queue->entries[i]);
181d6902
ID
1059 }
1060}
1061
1062static int rt2x00queue_alloc_entries(struct data_queue *queue,
1063 const struct data_queue_desc *qdesc)
1064{
1065 struct queue_entry *entries;
1066 unsigned int entry_size;
1067 unsigned int i;
1068
1069 rt2x00queue_reset(queue);
1070
1071 queue->limit = qdesc->entry_num;
b869767b 1072 queue->threshold = DIV_ROUND_UP(qdesc->entry_num, 10);
181d6902
ID
1073 queue->data_size = qdesc->data_size;
1074 queue->desc_size = qdesc->desc_size;
1075
1076 /*
1077 * Allocate all queue entries.
1078 */
1079 entry_size = sizeof(*entries) + qdesc->priv_size;
baeb2ffa 1080 entries = kcalloc(queue->limit, entry_size, GFP_KERNEL);
181d6902
ID
1081 if (!entries)
1082 return -ENOMEM;
1083
1084#define QUEUE_ENTRY_PRIV_OFFSET(__base, __index, __limit, __esize, __psize) \
f8bfbc31
ME
1085 (((char *)(__base)) + ((__limit) * (__esize)) + \
1086 ((__index) * (__psize)))
181d6902
ID
1087
1088 for (i = 0; i < queue->limit; i++) {
1089 entries[i].flags = 0;
1090 entries[i].queue = queue;
1091 entries[i].skb = NULL;
1092 entries[i].entry_idx = i;
1093 entries[i].priv_data =
1094 QUEUE_ENTRY_PRIV_OFFSET(entries, i, queue->limit,
1095 sizeof(*entries), qdesc->priv_size);
1096 }
1097
1098#undef QUEUE_ENTRY_PRIV_OFFSET
1099
1100 queue->entries = entries;
1101
1102 return 0;
1103}
1104
fa69560f 1105static void rt2x00queue_free_skbs(struct data_queue *queue)
30caa6e3
GW
1106{
1107 unsigned int i;
1108
1109 if (!queue->entries)
1110 return;
1111
1112 for (i = 0; i < queue->limit; i++) {
fa69560f 1113 rt2x00queue_free_skb(&queue->entries[i]);
30caa6e3
GW
1114 }
1115}
1116
fa69560f 1117static int rt2x00queue_alloc_rxskbs(struct data_queue *queue)
30caa6e3
GW
1118{
1119 unsigned int i;
1120 struct sk_buff *skb;
1121
1122 for (i = 0; i < queue->limit; i++) {
fa69560f 1123 skb = rt2x00queue_alloc_rxskb(&queue->entries[i]);
30caa6e3 1124 if (!skb)
61243d8e 1125 return -ENOMEM;
30caa6e3
GW
1126 queue->entries[i].skb = skb;
1127 }
1128
1129 return 0;
30caa6e3
GW
1130}
1131
181d6902
ID
1132int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev)
1133{
1134 struct data_queue *queue;
1135 int status;
1136
181d6902
ID
1137 status = rt2x00queue_alloc_entries(rt2x00dev->rx, rt2x00dev->ops->rx);
1138 if (status)
1139 goto exit;
1140
1141 tx_queue_for_each(rt2x00dev, queue) {
1142 status = rt2x00queue_alloc_entries(queue, rt2x00dev->ops->tx);
1143 if (status)
1144 goto exit;
1145 }
1146
1147 status = rt2x00queue_alloc_entries(rt2x00dev->bcn, rt2x00dev->ops->bcn);
1148 if (status)
1149 goto exit;
1150
7dab73b3 1151 if (test_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags)) {
e74df4a7 1152 status = rt2x00queue_alloc_entries(rt2x00dev->atim,
30caa6e3
GW
1153 rt2x00dev->ops->atim);
1154 if (status)
1155 goto exit;
1156 }
181d6902 1157
fa69560f 1158 status = rt2x00queue_alloc_rxskbs(rt2x00dev->rx);
181d6902
ID
1159 if (status)
1160 goto exit;
1161
1162 return 0;
1163
1164exit:
1165 ERROR(rt2x00dev, "Queue entries allocation failed.\n");
1166
1167 rt2x00queue_uninitialize(rt2x00dev);
1168
1169 return status;
1170}
1171
1172void rt2x00queue_uninitialize(struct rt2x00_dev *rt2x00dev)
1173{
1174 struct data_queue *queue;
1175
fa69560f 1176 rt2x00queue_free_skbs(rt2x00dev->rx);
30caa6e3 1177
181d6902
ID
1178 queue_for_each(rt2x00dev, queue) {
1179 kfree(queue->entries);
1180 queue->entries = NULL;
1181 }
1182}
1183
8f539276
ID
1184static void rt2x00queue_init(struct rt2x00_dev *rt2x00dev,
1185 struct data_queue *queue, enum data_queue_qid qid)
1186{
0b7fde54 1187 mutex_init(&queue->status_lock);
813f0339 1188 spin_lock_init(&queue->index_lock);
8f539276
ID
1189
1190 queue->rt2x00dev = rt2x00dev;
1191 queue->qid = qid;
2af0a570 1192 queue->txop = 0;
8f539276
ID
1193 queue->aifs = 2;
1194 queue->cw_min = 5;
1195 queue->cw_max = 10;
1196}
1197
181d6902
ID
1198int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
1199{
1200 struct data_queue *queue;
1201 enum data_queue_qid qid;
1202 unsigned int req_atim =
7dab73b3 1203 !!test_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags);
181d6902
ID
1204
1205 /*
1206 * We need the following queues:
1207 * RX: 1
61448f88 1208 * TX: ops->tx_queues
181d6902
ID
1209 * Beacon: 1
1210 * Atim: 1 (if required)
1211 */
61448f88 1212 rt2x00dev->data_queues = 2 + rt2x00dev->ops->tx_queues + req_atim;
181d6902 1213
baeb2ffa 1214 queue = kcalloc(rt2x00dev->data_queues, sizeof(*queue), GFP_KERNEL);
181d6902
ID
1215 if (!queue) {
1216 ERROR(rt2x00dev, "Queue allocation failed.\n");
1217 return -ENOMEM;
1218 }
1219
1220 /*
1221 * Initialize pointers
1222 */
1223 rt2x00dev->rx = queue;
1224 rt2x00dev->tx = &queue[1];
61448f88 1225 rt2x00dev->bcn = &queue[1 + rt2x00dev->ops->tx_queues];
e74df4a7 1226 rt2x00dev->atim = req_atim ? &queue[2 + rt2x00dev->ops->tx_queues] : NULL;
181d6902
ID
1227
1228 /*
1229 * Initialize queue parameters.
1230 * RX: qid = QID_RX
f615e9a3 1231 * TX: qid = QID_AC_VO + index
181d6902
ID
1232 * TX: cw_min: 2^5 = 32.
1233 * TX: cw_max: 2^10 = 1024.
565a019a
ID
1234 * BCN: qid = QID_BEACON
1235 * ATIM: qid = QID_ATIM
181d6902 1236 */
8f539276 1237 rt2x00queue_init(rt2x00dev, rt2x00dev->rx, QID_RX);
181d6902 1238
f615e9a3 1239 qid = QID_AC_VO;
8f539276
ID
1240 tx_queue_for_each(rt2x00dev, queue)
1241 rt2x00queue_init(rt2x00dev, queue, qid++);
181d6902 1242
e74df4a7 1243 rt2x00queue_init(rt2x00dev, rt2x00dev->bcn, QID_BEACON);
181d6902 1244 if (req_atim)
e74df4a7 1245 rt2x00queue_init(rt2x00dev, rt2x00dev->atim, QID_ATIM);
181d6902
ID
1246
1247 return 0;
1248}
1249
1250void rt2x00queue_free(struct rt2x00_dev *rt2x00dev)
1251{
1252 kfree(rt2x00dev->rx);
1253 rt2x00dev->rx = NULL;
1254 rt2x00dev->tx = NULL;
1255 rt2x00dev->bcn = NULL;
1256}
This page took 0.53898 seconds and 5 git commands to generate.