rt2x00: Move iv_len into tx descriptor data
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2x00queue.c
CommitLineData
181d6902 1/*
4e54c711 2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
181d6902
ID
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2x00lib
23 Abstract: rt2x00 queue specific routines.
24 */
25
26#include <linux/kernel.h>
27#include <linux/module.h>
c4da0048 28#include <linux/dma-mapping.h>
181d6902
ID
29
30#include "rt2x00.h"
31#include "rt2x00lib.h"
32
c4da0048
GW
33struct sk_buff *rt2x00queue_alloc_rxskb(struct rt2x00_dev *rt2x00dev,
34 struct queue_entry *entry)
239c249d 35{
c4da0048
GW
36 struct sk_buff *skb;
37 struct skb_frame_desc *skbdesc;
2bb057d0
ID
38 unsigned int frame_size;
39 unsigned int head_size = 0;
40 unsigned int tail_size = 0;
239c249d
GW
41
42 /*
43 * The frame size includes descriptor size, because the
44 * hardware directly receive the frame into the skbuffer.
45 */
c4da0048 46 frame_size = entry->queue->data_size + entry->queue->desc_size;
239c249d
GW
47
48 /*
ff352391
ID
49 * The payload should be aligned to a 4-byte boundary,
50 * this means we need at least 3 bytes for moving the frame
51 * into the correct offset.
239c249d 52 */
2bb057d0
ID
53 head_size = 4;
54
55 /*
56 * For IV/EIV/ICV assembly we must make sure there is
57 * at least 8 bytes bytes available in headroom for IV/EIV
9c3444d3 58 * and 8 bytes for ICV data as tailroon.
2bb057d0 59 */
2bb057d0
ID
60 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
61 head_size += 8;
9c3444d3 62 tail_size += 8;
2bb057d0 63 }
239c249d
GW
64
65 /*
66 * Allocate skbuffer.
67 */
2bb057d0 68 skb = dev_alloc_skb(frame_size + head_size + tail_size);
239c249d
GW
69 if (!skb)
70 return NULL;
71
2bb057d0
ID
72 /*
73 * Make sure we not have a frame with the requested bytes
74 * available in the head and tail.
75 */
76 skb_reserve(skb, head_size);
239c249d
GW
77 skb_put(skb, frame_size);
78
c4da0048
GW
79 /*
80 * Populate skbdesc.
81 */
82 skbdesc = get_skb_frame_desc(skb);
83 memset(skbdesc, 0, sizeof(*skbdesc));
84 skbdesc->entry = entry;
85
86 if (test_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags)) {
87 skbdesc->skb_dma = dma_map_single(rt2x00dev->dev,
88 skb->data,
89 skb->len,
90 DMA_FROM_DEVICE);
91 skbdesc->flags |= SKBDESC_DMA_MAPPED_RX;
92 }
93
239c249d
GW
94 return skb;
95}
30caa6e3 96
c4da0048 97void rt2x00queue_map_txskb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
30caa6e3 98{
c4da0048
GW
99 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
100
3ee54a07
ID
101 /*
102 * If device has requested headroom, we should make sure that
103 * is also mapped to the DMA so it can be used for transfering
104 * additional descriptor information to the hardware.
105 */
106 skb_push(skb, rt2x00dev->hw->extra_tx_headroom);
107
108 skbdesc->skb_dma =
109 dma_map_single(rt2x00dev->dev, skb->data, skb->len, DMA_TO_DEVICE);
110
111 /*
112 * Restore data pointer to original location again.
113 */
114 skb_pull(skb, rt2x00dev->hw->extra_tx_headroom);
115
c4da0048
GW
116 skbdesc->flags |= SKBDESC_DMA_MAPPED_TX;
117}
118EXPORT_SYMBOL_GPL(rt2x00queue_map_txskb);
119
120void rt2x00queue_unmap_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
121{
122 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
123
124 if (skbdesc->flags & SKBDESC_DMA_MAPPED_RX) {
125 dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma, skb->len,
126 DMA_FROM_DEVICE);
127 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_RX;
128 }
129
130 if (skbdesc->flags & SKBDESC_DMA_MAPPED_TX) {
3ee54a07
ID
131 /*
132 * Add headroom to the skb length, it has been removed
133 * by the driver, but it was actually mapped to DMA.
134 */
135 dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma,
136 skb->len + rt2x00dev->hw->extra_tx_headroom,
c4da0048
GW
137 DMA_TO_DEVICE);
138 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_TX;
139 }
140}
c4da0048
GW
141
142void rt2x00queue_free_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
143{
9a613195
ID
144 if (!skb)
145 return;
146
61243d8e 147 rt2x00queue_unmap_skb(rt2x00dev, skb);
30caa6e3
GW
148 dev_kfree_skb_any(skb);
149}
239c249d 150
7b40982e
ID
151static void rt2x00queue_create_tx_descriptor_seq(struct queue_entry *entry,
152 struct txentry_desc *txdesc)
153{
154 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
155 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
156 struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
157 unsigned long irqflags;
158
159 if (!(tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) ||
160 unlikely(!tx_info->control.vif))
161 return;
162
163 /*
164 * Hardware should insert sequence counter.
165 * FIXME: We insert a software sequence counter first for
166 * hardware that doesn't support hardware sequence counting.
167 *
168 * This is wrong because beacons are not getting sequence
169 * numbers assigned properly.
170 *
171 * A secondary problem exists for drivers that cannot toggle
172 * sequence counting per-frame, since those will override the
173 * sequence counter given by mac80211.
174 */
175 spin_lock_irqsave(&intf->seqlock, irqflags);
176
177 if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags))
178 intf->seqno += 0x10;
179 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
180 hdr->seq_ctrl |= cpu_to_le16(intf->seqno);
181
182 spin_unlock_irqrestore(&intf->seqlock, irqflags);
183
184 __set_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags);
185}
186
187static void rt2x00queue_create_tx_descriptor_plcp(struct queue_entry *entry,
188 struct txentry_desc *txdesc,
189 const struct rt2x00_rate *hwrate)
190{
191 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
192 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
193 struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0];
194 unsigned int data_length;
195 unsigned int duration;
196 unsigned int residual;
197
198 /* Data length + CRC + Crypto overhead (IV/EIV/ICV/MIC) */
199 data_length = entry->skb->len + 4;
200 data_length += rt2x00crypto_tx_overhead(rt2x00dev, entry->skb);
201
202 /*
203 * PLCP setup
204 * Length calculation depends on OFDM/CCK rate.
205 */
206 txdesc->signal = hwrate->plcp;
207 txdesc->service = 0x04;
208
209 if (hwrate->flags & DEV_RATE_OFDM) {
210 txdesc->length_high = (data_length >> 6) & 0x3f;
211 txdesc->length_low = data_length & 0x3f;
212 } else {
213 /*
214 * Convert length to microseconds.
215 */
216 residual = GET_DURATION_RES(data_length, hwrate->bitrate);
217 duration = GET_DURATION(data_length, hwrate->bitrate);
218
219 if (residual != 0) {
220 duration++;
221
222 /*
223 * Check if we need to set the Length Extension
224 */
225 if (hwrate->bitrate == 110 && residual <= 30)
226 txdesc->service |= 0x80;
227 }
228
229 txdesc->length_high = (duration >> 8) & 0xff;
230 txdesc->length_low = duration & 0xff;
231
232 /*
233 * When preamble is enabled we should set the
234 * preamble bit for the signal.
235 */
236 if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
237 txdesc->signal |= 0x08;
238 }
239}
240
bd88a781
ID
241static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry,
242 struct txentry_desc *txdesc)
7050ec82 243{
2e92e6f2 244 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
e039fa4a 245 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
7050ec82 246 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
2e92e6f2 247 struct ieee80211_rate *rate =
e039fa4a 248 ieee80211_get_tx_rate(rt2x00dev->hw, tx_info);
7050ec82 249 const struct rt2x00_rate *hwrate;
7050ec82
ID
250
251 memset(txdesc, 0, sizeof(*txdesc));
252
253 /*
254 * Initialize information from queue
255 */
256 txdesc->queue = entry->queue->qid;
257 txdesc->cw_min = entry->queue->cw_min;
258 txdesc->cw_max = entry->queue->cw_max;
259 txdesc->aifs = entry->queue->aifs;
260
7050ec82
ID
261 /*
262 * Check whether this frame is to be acked.
263 */
e039fa4a 264 if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK))
7050ec82
ID
265 __set_bit(ENTRY_TXD_ACK, &txdesc->flags);
266
267 /*
268 * Check if this is a RTS/CTS frame
269 */
ac104462
ID
270 if (ieee80211_is_rts(hdr->frame_control) ||
271 ieee80211_is_cts(hdr->frame_control)) {
7050ec82 272 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
ac104462 273 if (ieee80211_is_rts(hdr->frame_control))
7050ec82 274 __set_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags);
e039fa4a 275 else
7050ec82 276 __set_bit(ENTRY_TXD_CTS_FRAME, &txdesc->flags);
e039fa4a 277 if (tx_info->control.rts_cts_rate_idx >= 0)
2e92e6f2 278 rate =
e039fa4a 279 ieee80211_get_rts_cts_rate(rt2x00dev->hw, tx_info);
7050ec82
ID
280 }
281
282 /*
283 * Determine retry information.
284 */
e6a9854b 285 txdesc->retry_limit = tx_info->control.rates[0].count - 1;
42c82857 286 if (txdesc->retry_limit >= rt2x00dev->long_retry)
7050ec82
ID
287 __set_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags);
288
289 /*
290 * Check if more fragments are pending
291 */
8b7b1e05 292 if (ieee80211_has_morefrags(hdr->frame_control)) {
7050ec82
ID
293 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
294 __set_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags);
295 }
296
297 /*
298 * Beacons and probe responses require the tsf timestamp
299 * to be inserted into the frame.
300 */
ac104462
ID
301 if (ieee80211_is_beacon(hdr->frame_control) ||
302 ieee80211_is_probe_resp(hdr->frame_control))
7050ec82
ID
303 __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags);
304
305 /*
306 * Determine with what IFS priority this frame should be send.
307 * Set ifs to IFS_SIFS when the this is not the first fragment,
308 * or this fragment came after RTS/CTS.
309 */
7b40982e
ID
310 if ((tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) &&
311 !test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)) {
7050ec82
ID
312 __set_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags);
313 txdesc->ifs = IFS_BACKOFF;
7b40982e 314 } else
7050ec82 315 txdesc->ifs = IFS_SIFS;
7050ec82 316
076f9582
ID
317 /*
318 * Determine rate modulation.
319 */
7050ec82 320 hwrate = rt2x00_get_rate(rate->hw_value);
076f9582 321 txdesc->rate_mode = RATE_MODE_CCK;
7b40982e 322 if (hwrate->flags & DEV_RATE_OFDM)
076f9582 323 txdesc->rate_mode = RATE_MODE_OFDM;
7050ec82 324
7b40982e
ID
325 /*
326 * Apply TX descriptor handling by components
327 */
328 rt2x00crypto_create_tx_descriptor(entry, txdesc);
329 rt2x00queue_create_tx_descriptor_seq(entry, txdesc);
330 rt2x00queue_create_tx_descriptor_plcp(entry, txdesc, hwrate);
7050ec82 331}
7050ec82 332
bd88a781
ID
333static void rt2x00queue_write_tx_descriptor(struct queue_entry *entry,
334 struct txentry_desc *txdesc)
7050ec82 335{
b869767b
ID
336 struct data_queue *queue = entry->queue;
337 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
7050ec82
ID
338
339 rt2x00dev->ops->lib->write_tx_desc(rt2x00dev, entry->skb, txdesc);
340
341 /*
342 * All processing on the frame has been completed, this means
343 * it is now ready to be dumped to userspace through debugfs.
344 */
345 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_TX, entry->skb);
346
347 /*
b869767b
ID
348 * Check if we need to kick the queue, there are however a few rules
349 * 1) Don't kick beacon queue
350 * 2) Don't kick unless this is the last in frame in a burst.
351 * When the burst flag is set, this frame is always followed
352 * by another frame which in some way are related to eachother.
353 * This is true for fragments, RTS or CTS-to-self frames.
354 * 3) Rule 2 can be broken when the available entries
355 * in the queue are less then a certain threshold.
7050ec82 356 */
b869767b
ID
357 if (entry->queue->qid == QID_BEACON)
358 return;
359
360 if (rt2x00queue_threshold(queue) ||
361 !test_bit(ENTRY_TXD_BURST, &txdesc->flags))
362 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, queue->qid);
7050ec82 363}
7050ec82 364
6db3786a
ID
365int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb)
366{
e6a9854b 367 struct ieee80211_tx_info *tx_info;
6db3786a
ID
368 struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX);
369 struct txentry_desc txdesc;
d74f5ba4 370 struct skb_frame_desc *skbdesc;
e6a9854b 371 u8 rate_idx, rate_flags;
6db3786a
ID
372
373 if (unlikely(rt2x00queue_full(queue)))
0e3de998 374 return -ENOBUFS;
6db3786a 375
0262ab0d 376 if (test_and_set_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags)) {
6db3786a
ID
377 ERROR(queue->rt2x00dev,
378 "Arrived at non-free entry in the non-full queue %d.\n"
379 "Please file bug report to %s.\n",
380 queue->qid, DRV_PROJECT);
381 return -EINVAL;
382 }
383
384 /*
385 * Copy all TX descriptor information into txdesc,
386 * after that we are free to use the skb->cb array
387 * for our information.
388 */
389 entry->skb = skb;
390 rt2x00queue_create_tx_descriptor(entry, &txdesc);
391
d74f5ba4 392 /*
e6a9854b 393 * All information is retrieved from the skb->cb array,
2bb057d0 394 * now we should claim ownership of the driver part of that
e6a9854b 395 * array, preserving the bitrate index and flags.
d74f5ba4 396 */
e6a9854b
JB
397 tx_info = IEEE80211_SKB_CB(skb);
398 rate_idx = tx_info->control.rates[0].idx;
399 rate_flags = tx_info->control.rates[0].flags;
0e3de998 400 skbdesc = get_skb_frame_desc(skb);
d74f5ba4
ID
401 memset(skbdesc, 0, sizeof(*skbdesc));
402 skbdesc->entry = entry;
e6a9854b
JB
403 skbdesc->tx_rate_idx = rate_idx;
404 skbdesc->tx_rate_flags = rate_flags;
d74f5ba4 405
2bb057d0
ID
406 /*
407 * When hardware encryption is supported, and this frame
408 * is to be encrypted, we should strip the IV/EIV data from
409 * the frame so we can provide it to the driver seperately.
410 */
411 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc.flags) &&
dddfb478 412 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc.flags)) {
3f787bd6 413 if (test_bit(DRIVER_REQUIRE_COPY_IV, &queue->rt2x00dev->flags))
9eb4e21e 414 rt2x00crypto_tx_copy_iv(skb, &txdesc);
dddfb478 415 else
9eb4e21e 416 rt2x00crypto_tx_remove_iv(skb, &txdesc);
dddfb478 417 }
2bb057d0
ID
418
419 /*
420 * It could be possible that the queue was corrupted and this
0e3de998
ID
421 * call failed. Since we always return NETDEV_TX_OK to mac80211,
422 * this frame will simply be dropped.
2bb057d0 423 */
6db3786a 424 if (unlikely(queue->rt2x00dev->ops->lib->write_tx_data(entry))) {
0262ab0d 425 clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
2bb057d0 426 entry->skb = NULL;
0e3de998 427 return -EIO;
6db3786a
ID
428 }
429
d74f5ba4
ID
430 if (test_bit(DRIVER_REQUIRE_DMA, &queue->rt2x00dev->flags))
431 rt2x00queue_map_txskb(queue->rt2x00dev, skb);
432
0262ab0d 433 set_bit(ENTRY_DATA_PENDING, &entry->flags);
6db3786a
ID
434
435 rt2x00queue_index_inc(queue, Q_INDEX);
436 rt2x00queue_write_tx_descriptor(entry, &txdesc);
437
438 return 0;
439}
440
bd88a781 441int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev,
a2c9b652
ID
442 struct ieee80211_vif *vif,
443 const bool enable_beacon)
bd88a781
ID
444{
445 struct rt2x00_intf *intf = vif_to_intf(vif);
446 struct skb_frame_desc *skbdesc;
447 struct txentry_desc txdesc;
448 __le32 desc[16];
449
450 if (unlikely(!intf->beacon))
451 return -ENOBUFS;
452
a2c9b652
ID
453 if (!enable_beacon) {
454 rt2x00dev->ops->lib->kill_tx_queue(rt2x00dev, QID_BEACON);
455 return 0;
456 }
457
bd88a781
ID
458 intf->beacon->skb = ieee80211_beacon_get(rt2x00dev->hw, vif);
459 if (!intf->beacon->skb)
460 return -ENOMEM;
461
462 /*
463 * Copy all TX descriptor information into txdesc,
464 * after that we are free to use the skb->cb array
465 * for our information.
466 */
467 rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc);
468
469 /*
470 * For the descriptor we use a local array from where the
471 * driver can move it to the correct location required for
472 * the hardware.
473 */
474 memset(desc, 0, sizeof(desc));
475
476 /*
477 * Fill in skb descriptor
478 */
479 skbdesc = get_skb_frame_desc(intf->beacon->skb);
480 memset(skbdesc, 0, sizeof(*skbdesc));
481 skbdesc->desc = desc;
482 skbdesc->desc_len = intf->beacon->queue->desc_size;
483 skbdesc->entry = intf->beacon;
484
485 /*
486 * Write TX descriptor into reserved room in front of the beacon.
487 */
488 rt2x00queue_write_tx_descriptor(intf->beacon, &txdesc);
489
490 /*
491 * Send beacon to hardware.
492 * Also enable beacon generation, which might have been disabled
493 * by the driver during the config_beacon() callback function.
494 */
495 rt2x00dev->ops->lib->write_beacon(intf->beacon);
496 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, QID_BEACON);
497
498 return 0;
499}
500
181d6902 501struct data_queue *rt2x00queue_get_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 502 const enum data_queue_qid queue)
181d6902
ID
503{
504 int atim = test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
505
a2c9b652
ID
506 if (queue == QID_RX)
507 return rt2x00dev->rx;
508
61448f88 509 if (queue < rt2x00dev->ops->tx_queues && rt2x00dev->tx)
181d6902
ID
510 return &rt2x00dev->tx[queue];
511
512 if (!rt2x00dev->bcn)
513 return NULL;
514
e58c6aca 515 if (queue == QID_BEACON)
181d6902 516 return &rt2x00dev->bcn[0];
e58c6aca 517 else if (queue == QID_ATIM && atim)
181d6902
ID
518 return &rt2x00dev->bcn[1];
519
520 return NULL;
521}
522EXPORT_SYMBOL_GPL(rt2x00queue_get_queue);
523
524struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue,
525 enum queue_index index)
526{
527 struct queue_entry *entry;
5f46c4d0 528 unsigned long irqflags;
181d6902
ID
529
530 if (unlikely(index >= Q_INDEX_MAX)) {
531 ERROR(queue->rt2x00dev,
532 "Entry requested from invalid index type (%d)\n", index);
533 return NULL;
534 }
535
5f46c4d0 536 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
537
538 entry = &queue->entries[queue->index[index]];
539
5f46c4d0 540 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902
ID
541
542 return entry;
543}
544EXPORT_SYMBOL_GPL(rt2x00queue_get_entry);
545
546void rt2x00queue_index_inc(struct data_queue *queue, enum queue_index index)
547{
5f46c4d0
ID
548 unsigned long irqflags;
549
181d6902
ID
550 if (unlikely(index >= Q_INDEX_MAX)) {
551 ERROR(queue->rt2x00dev,
552 "Index change on invalid index type (%d)\n", index);
553 return;
554 }
555
5f46c4d0 556 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
557
558 queue->index[index]++;
559 if (queue->index[index] >= queue->limit)
560 queue->index[index] = 0;
561
10b6b801
ID
562 if (index == Q_INDEX) {
563 queue->length++;
564 } else if (index == Q_INDEX_DONE) {
565 queue->length--;
55887511 566 queue->count++;
10b6b801 567 }
181d6902 568
5f46c4d0 569 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902 570}
181d6902
ID
571
572static void rt2x00queue_reset(struct data_queue *queue)
573{
5f46c4d0
ID
574 unsigned long irqflags;
575
576 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
577
578 queue->count = 0;
579 queue->length = 0;
580 memset(queue->index, 0, sizeof(queue->index));
581
5f46c4d0 582 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902
ID
583}
584
a2c9b652
ID
585void rt2x00queue_stop_queues(struct rt2x00_dev *rt2x00dev)
586{
587 struct data_queue *queue;
588
589 txall_queue_for_each(rt2x00dev, queue)
590 rt2x00dev->ops->lib->kill_tx_queue(rt2x00dev, queue->qid);
591}
592
798b7adb 593void rt2x00queue_init_queues(struct rt2x00_dev *rt2x00dev)
181d6902
ID
594{
595 struct data_queue *queue;
596 unsigned int i;
597
798b7adb 598 queue_for_each(rt2x00dev, queue) {
181d6902
ID
599 rt2x00queue_reset(queue);
600
9c0ab712
ID
601 for (i = 0; i < queue->limit; i++) {
602 queue->entries[i].flags = 0;
603
798b7adb 604 rt2x00dev->ops->lib->clear_entry(&queue->entries[i]);
9c0ab712 605 }
181d6902
ID
606 }
607}
608
609static int rt2x00queue_alloc_entries(struct data_queue *queue,
610 const struct data_queue_desc *qdesc)
611{
612 struct queue_entry *entries;
613 unsigned int entry_size;
614 unsigned int i;
615
616 rt2x00queue_reset(queue);
617
618 queue->limit = qdesc->entry_num;
b869767b 619 queue->threshold = DIV_ROUND_UP(qdesc->entry_num, 10);
181d6902
ID
620 queue->data_size = qdesc->data_size;
621 queue->desc_size = qdesc->desc_size;
622
623 /*
624 * Allocate all queue entries.
625 */
626 entry_size = sizeof(*entries) + qdesc->priv_size;
627 entries = kzalloc(queue->limit * entry_size, GFP_KERNEL);
628 if (!entries)
629 return -ENOMEM;
630
631#define QUEUE_ENTRY_PRIV_OFFSET(__base, __index, __limit, __esize, __psize) \
231be4e9
AB
632 ( ((char *)(__base)) + ((__limit) * (__esize)) + \
633 ((__index) * (__psize)) )
181d6902
ID
634
635 for (i = 0; i < queue->limit; i++) {
636 entries[i].flags = 0;
637 entries[i].queue = queue;
638 entries[i].skb = NULL;
639 entries[i].entry_idx = i;
640 entries[i].priv_data =
641 QUEUE_ENTRY_PRIV_OFFSET(entries, i, queue->limit,
642 sizeof(*entries), qdesc->priv_size);
643 }
644
645#undef QUEUE_ENTRY_PRIV_OFFSET
646
647 queue->entries = entries;
648
649 return 0;
650}
651
c4da0048
GW
652static void rt2x00queue_free_skbs(struct rt2x00_dev *rt2x00dev,
653 struct data_queue *queue)
30caa6e3
GW
654{
655 unsigned int i;
656
657 if (!queue->entries)
658 return;
659
660 for (i = 0; i < queue->limit; i++) {
661 if (queue->entries[i].skb)
c4da0048 662 rt2x00queue_free_skb(rt2x00dev, queue->entries[i].skb);
30caa6e3
GW
663 }
664}
665
c4da0048
GW
666static int rt2x00queue_alloc_rxskbs(struct rt2x00_dev *rt2x00dev,
667 struct data_queue *queue)
30caa6e3
GW
668{
669 unsigned int i;
670 struct sk_buff *skb;
671
672 for (i = 0; i < queue->limit; i++) {
c4da0048 673 skb = rt2x00queue_alloc_rxskb(rt2x00dev, &queue->entries[i]);
30caa6e3 674 if (!skb)
61243d8e 675 return -ENOMEM;
30caa6e3
GW
676 queue->entries[i].skb = skb;
677 }
678
679 return 0;
30caa6e3
GW
680}
681
181d6902
ID
682int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev)
683{
684 struct data_queue *queue;
685 int status;
686
181d6902
ID
687 status = rt2x00queue_alloc_entries(rt2x00dev->rx, rt2x00dev->ops->rx);
688 if (status)
689 goto exit;
690
691 tx_queue_for_each(rt2x00dev, queue) {
692 status = rt2x00queue_alloc_entries(queue, rt2x00dev->ops->tx);
693 if (status)
694 goto exit;
695 }
696
697 status = rt2x00queue_alloc_entries(rt2x00dev->bcn, rt2x00dev->ops->bcn);
698 if (status)
699 goto exit;
700
30caa6e3
GW
701 if (test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags)) {
702 status = rt2x00queue_alloc_entries(&rt2x00dev->bcn[1],
703 rt2x00dev->ops->atim);
704 if (status)
705 goto exit;
706 }
181d6902 707
c4da0048 708 status = rt2x00queue_alloc_rxskbs(rt2x00dev, rt2x00dev->rx);
181d6902
ID
709 if (status)
710 goto exit;
711
712 return 0;
713
714exit:
715 ERROR(rt2x00dev, "Queue entries allocation failed.\n");
716
717 rt2x00queue_uninitialize(rt2x00dev);
718
719 return status;
720}
721
722void rt2x00queue_uninitialize(struct rt2x00_dev *rt2x00dev)
723{
724 struct data_queue *queue;
725
c4da0048 726 rt2x00queue_free_skbs(rt2x00dev, rt2x00dev->rx);
30caa6e3 727
181d6902
ID
728 queue_for_each(rt2x00dev, queue) {
729 kfree(queue->entries);
730 queue->entries = NULL;
731 }
732}
733
8f539276
ID
734static void rt2x00queue_init(struct rt2x00_dev *rt2x00dev,
735 struct data_queue *queue, enum data_queue_qid qid)
736{
737 spin_lock_init(&queue->lock);
738
739 queue->rt2x00dev = rt2x00dev;
740 queue->qid = qid;
2af0a570 741 queue->txop = 0;
8f539276
ID
742 queue->aifs = 2;
743 queue->cw_min = 5;
744 queue->cw_max = 10;
745}
746
181d6902
ID
747int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
748{
749 struct data_queue *queue;
750 enum data_queue_qid qid;
751 unsigned int req_atim =
752 !!test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
753
754 /*
755 * We need the following queues:
756 * RX: 1
61448f88 757 * TX: ops->tx_queues
181d6902
ID
758 * Beacon: 1
759 * Atim: 1 (if required)
760 */
61448f88 761 rt2x00dev->data_queues = 2 + rt2x00dev->ops->tx_queues + req_atim;
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ID
762
763 queue = kzalloc(rt2x00dev->data_queues * sizeof(*queue), GFP_KERNEL);
764 if (!queue) {
765 ERROR(rt2x00dev, "Queue allocation failed.\n");
766 return -ENOMEM;
767 }
768
769 /*
770 * Initialize pointers
771 */
772 rt2x00dev->rx = queue;
773 rt2x00dev->tx = &queue[1];
61448f88 774 rt2x00dev->bcn = &queue[1 + rt2x00dev->ops->tx_queues];
181d6902
ID
775
776 /*
777 * Initialize queue parameters.
778 * RX: qid = QID_RX
779 * TX: qid = QID_AC_BE + index
780 * TX: cw_min: 2^5 = 32.
781 * TX: cw_max: 2^10 = 1024.
565a019a
ID
782 * BCN: qid = QID_BEACON
783 * ATIM: qid = QID_ATIM
181d6902 784 */
8f539276 785 rt2x00queue_init(rt2x00dev, rt2x00dev->rx, QID_RX);
181d6902 786
8f539276
ID
787 qid = QID_AC_BE;
788 tx_queue_for_each(rt2x00dev, queue)
789 rt2x00queue_init(rt2x00dev, queue, qid++);
181d6902 790
565a019a 791 rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[0], QID_BEACON);
181d6902 792 if (req_atim)
565a019a 793 rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[1], QID_ATIM);
181d6902
ID
794
795 return 0;
796}
797
798void rt2x00queue_free(struct rt2x00_dev *rt2x00dev)
799{
800 kfree(rt2x00dev->rx);
801 rt2x00dev->rx = NULL;
802 rt2x00dev->tx = NULL;
803 rt2x00dev->bcn = NULL;
804}
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