rt2x00: Reverse calling order of bus write_tx_desc and driver write_tx_desc.
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2x00queue.c
CommitLineData
181d6902 1/*
9c9a0d14
GW
2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2004 - 2009 Gertjan van Wingerde <gwingerde@gmail.com>
181d6902
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4 <http://rt2x00.serialmonkey.com>
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the
18 Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22/*
23 Module: rt2x00lib
24 Abstract: rt2x00 queue specific routines.
25 */
26
5a0e3ad6 27#include <linux/slab.h>
181d6902
ID
28#include <linux/kernel.h>
29#include <linux/module.h>
c4da0048 30#include <linux/dma-mapping.h>
181d6902
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31
32#include "rt2x00.h"
33#include "rt2x00lib.h"
34
c4da0048
GW
35struct sk_buff *rt2x00queue_alloc_rxskb(struct rt2x00_dev *rt2x00dev,
36 struct queue_entry *entry)
239c249d 37{
c4da0048
GW
38 struct sk_buff *skb;
39 struct skb_frame_desc *skbdesc;
2bb057d0
ID
40 unsigned int frame_size;
41 unsigned int head_size = 0;
42 unsigned int tail_size = 0;
239c249d
GW
43
44 /*
45 * The frame size includes descriptor size, because the
46 * hardware directly receive the frame into the skbuffer.
47 */
c4da0048 48 frame_size = entry->queue->data_size + entry->queue->desc_size;
239c249d
GW
49
50 /*
ff352391
ID
51 * The payload should be aligned to a 4-byte boundary,
52 * this means we need at least 3 bytes for moving the frame
53 * into the correct offset.
239c249d 54 */
2bb057d0
ID
55 head_size = 4;
56
57 /*
58 * For IV/EIV/ICV assembly we must make sure there is
59 * at least 8 bytes bytes available in headroom for IV/EIV
9c3444d3 60 * and 8 bytes for ICV data as tailroon.
2bb057d0 61 */
2bb057d0
ID
62 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
63 head_size += 8;
9c3444d3 64 tail_size += 8;
2bb057d0 65 }
239c249d
GW
66
67 /*
68 * Allocate skbuffer.
69 */
2bb057d0 70 skb = dev_alloc_skb(frame_size + head_size + tail_size);
239c249d
GW
71 if (!skb)
72 return NULL;
73
2bb057d0
ID
74 /*
75 * Make sure we not have a frame with the requested bytes
76 * available in the head and tail.
77 */
78 skb_reserve(skb, head_size);
239c249d
GW
79 skb_put(skb, frame_size);
80
c4da0048
GW
81 /*
82 * Populate skbdesc.
83 */
84 skbdesc = get_skb_frame_desc(skb);
85 memset(skbdesc, 0, sizeof(*skbdesc));
86 skbdesc->entry = entry;
87
88 if (test_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags)) {
89 skbdesc->skb_dma = dma_map_single(rt2x00dev->dev,
90 skb->data,
91 skb->len,
92 DMA_FROM_DEVICE);
93 skbdesc->flags |= SKBDESC_DMA_MAPPED_RX;
94 }
95
239c249d
GW
96 return skb;
97}
30caa6e3 98
c4da0048 99void rt2x00queue_map_txskb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
30caa6e3 100{
c4da0048
GW
101 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
102
3ee54a07
ID
103 /*
104 * If device has requested headroom, we should make sure that
105 * is also mapped to the DMA so it can be used for transfering
106 * additional descriptor information to the hardware.
107 */
b59a52f1 108 skb_push(skb, rt2x00dev->ops->extra_tx_headroom);
3ee54a07
ID
109
110 skbdesc->skb_dma =
111 dma_map_single(rt2x00dev->dev, skb->data, skb->len, DMA_TO_DEVICE);
112
113 /*
114 * Restore data pointer to original location again.
115 */
b59a52f1 116 skb_pull(skb, rt2x00dev->ops->extra_tx_headroom);
3ee54a07 117
c4da0048
GW
118 skbdesc->flags |= SKBDESC_DMA_MAPPED_TX;
119}
120EXPORT_SYMBOL_GPL(rt2x00queue_map_txskb);
121
122void rt2x00queue_unmap_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
123{
124 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
125
126 if (skbdesc->flags & SKBDESC_DMA_MAPPED_RX) {
127 dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma, skb->len,
128 DMA_FROM_DEVICE);
129 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_RX;
130 }
131
132 if (skbdesc->flags & SKBDESC_DMA_MAPPED_TX) {
3ee54a07
ID
133 /*
134 * Add headroom to the skb length, it has been removed
135 * by the driver, but it was actually mapped to DMA.
136 */
137 dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma,
b59a52f1 138 skb->len + rt2x00dev->ops->extra_tx_headroom,
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GW
139 DMA_TO_DEVICE);
140 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_TX;
141 }
142}
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GW
143
144void rt2x00queue_free_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
145{
9a613195
ID
146 if (!skb)
147 return;
148
61243d8e 149 rt2x00queue_unmap_skb(rt2x00dev, skb);
30caa6e3
GW
150 dev_kfree_skb_any(skb);
151}
239c249d 152
daee6c09 153void rt2x00queue_align_frame(struct sk_buff *skb)
9f166171 154{
9f166171 155 unsigned int frame_length = skb->len;
daee6c09 156 unsigned int align = ALIGN_SIZE(skb, 0);
9f166171
ID
157
158 if (!align)
159 return;
160
daee6c09
ID
161 skb_push(skb, align);
162 memmove(skb->data, skb->data + align, frame_length);
163 skb_trim(skb, frame_length);
164}
165
95d69aa0 166void rt2x00queue_align_payload(struct sk_buff *skb, unsigned int header_length)
daee6c09
ID
167{
168 unsigned int frame_length = skb->len;
95d69aa0 169 unsigned int align = ALIGN_SIZE(skb, header_length);
daee6c09
ID
170
171 if (!align)
172 return;
173
174 skb_push(skb, align);
175 memmove(skb->data, skb->data + align, frame_length);
176 skb_trim(skb, frame_length);
177}
178
179void rt2x00queue_insert_l2pad(struct sk_buff *skb, unsigned int header_length)
180{
2e331462 181 unsigned int payload_length = skb->len - header_length;
daee6c09
ID
182 unsigned int header_align = ALIGN_SIZE(skb, 0);
183 unsigned int payload_align = ALIGN_SIZE(skb, header_length);
e54be4e7 184 unsigned int l2pad = payload_length ? L2PAD_SIZE(header_length) : 0;
daee6c09 185
2e331462
GW
186 /*
187 * Adjust the header alignment if the payload needs to be moved more
188 * than the header.
189 */
190 if (payload_align > header_align)
191 header_align += 4;
192
193 /* There is nothing to do if no alignment is needed */
194 if (!header_align)
195 return;
daee6c09 196
2e331462
GW
197 /* Reserve the amount of space needed in front of the frame */
198 skb_push(skb, header_align);
199
200 /*
201 * Move the header.
202 */
203 memmove(skb->data, skb->data + header_align, header_length);
204
205 /* Move the payload, if present and if required */
206 if (payload_length && payload_align)
daee6c09 207 memmove(skb->data + header_length + l2pad,
a5186e99 208 skb->data + header_length + l2pad + payload_align,
2e331462
GW
209 payload_length);
210
211 /* Trim the skb to the correct size */
212 skb_trim(skb, header_length + l2pad + payload_length);
9f166171
ID
213}
214
daee6c09
ID
215void rt2x00queue_remove_l2pad(struct sk_buff *skb, unsigned int header_length)
216{
77e73d18 217 unsigned int l2pad = L2PAD_SIZE(header_length);
daee6c09 218
354e39db 219 if (!l2pad)
daee6c09
ID
220 return;
221
222 memmove(skb->data + l2pad, skb->data, header_length);
223 skb_pull(skb, l2pad);
224}
225
7b40982e
ID
226static void rt2x00queue_create_tx_descriptor_seq(struct queue_entry *entry,
227 struct txentry_desc *txdesc)
228{
229 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
230 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
231 struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
232 unsigned long irqflags;
233
234 if (!(tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) ||
235 unlikely(!tx_info->control.vif))
236 return;
237
238 /*
239 * Hardware should insert sequence counter.
240 * FIXME: We insert a software sequence counter first for
241 * hardware that doesn't support hardware sequence counting.
242 *
243 * This is wrong because beacons are not getting sequence
244 * numbers assigned properly.
245 *
246 * A secondary problem exists for drivers that cannot toggle
247 * sequence counting per-frame, since those will override the
248 * sequence counter given by mac80211.
249 */
250 spin_lock_irqsave(&intf->seqlock, irqflags);
251
252 if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags))
253 intf->seqno += 0x10;
254 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
255 hdr->seq_ctrl |= cpu_to_le16(intf->seqno);
256
257 spin_unlock_irqrestore(&intf->seqlock, irqflags);
258
259 __set_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags);
260}
261
262static void rt2x00queue_create_tx_descriptor_plcp(struct queue_entry *entry,
263 struct txentry_desc *txdesc,
264 const struct rt2x00_rate *hwrate)
265{
266 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
267 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
268 struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0];
269 unsigned int data_length;
270 unsigned int duration;
271 unsigned int residual;
272
273 /* Data length + CRC + Crypto overhead (IV/EIV/ICV/MIC) */
274 data_length = entry->skb->len + 4;
275 data_length += rt2x00crypto_tx_overhead(rt2x00dev, entry->skb);
276
277 /*
278 * PLCP setup
279 * Length calculation depends on OFDM/CCK rate.
280 */
281 txdesc->signal = hwrate->plcp;
282 txdesc->service = 0x04;
283
284 if (hwrate->flags & DEV_RATE_OFDM) {
285 txdesc->length_high = (data_length >> 6) & 0x3f;
286 txdesc->length_low = data_length & 0x3f;
287 } else {
288 /*
289 * Convert length to microseconds.
290 */
291 residual = GET_DURATION_RES(data_length, hwrate->bitrate);
292 duration = GET_DURATION(data_length, hwrate->bitrate);
293
294 if (residual != 0) {
295 duration++;
296
297 /*
298 * Check if we need to set the Length Extension
299 */
300 if (hwrate->bitrate == 110 && residual <= 30)
301 txdesc->service |= 0x80;
302 }
303
304 txdesc->length_high = (duration >> 8) & 0xff;
305 txdesc->length_low = duration & 0xff;
306
307 /*
308 * When preamble is enabled we should set the
309 * preamble bit for the signal.
310 */
311 if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
312 txdesc->signal |= 0x08;
313 }
314}
315
bd88a781
ID
316static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry,
317 struct txentry_desc *txdesc)
7050ec82 318{
2e92e6f2 319 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
e039fa4a 320 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
7050ec82 321 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
2e92e6f2 322 struct ieee80211_rate *rate =
e039fa4a 323 ieee80211_get_tx_rate(rt2x00dev->hw, tx_info);
7050ec82 324 const struct rt2x00_rate *hwrate;
7050ec82
ID
325
326 memset(txdesc, 0, sizeof(*txdesc));
327
328 /*
329 * Initialize information from queue
330 */
331 txdesc->queue = entry->queue->qid;
332 txdesc->cw_min = entry->queue->cw_min;
333 txdesc->cw_max = entry->queue->cw_max;
334 txdesc->aifs = entry->queue->aifs;
335
9f166171 336 /*
df624ca5 337 * Header and frame information.
9f166171 338 */
df624ca5 339 txdesc->length = entry->skb->len;
9f166171 340 txdesc->header_length = ieee80211_get_hdrlen_from_skb(entry->skb);
9f166171 341
7050ec82
ID
342 /*
343 * Check whether this frame is to be acked.
344 */
e039fa4a 345 if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK))
7050ec82
ID
346 __set_bit(ENTRY_TXD_ACK, &txdesc->flags);
347
348 /*
349 * Check if this is a RTS/CTS frame
350 */
ac104462
ID
351 if (ieee80211_is_rts(hdr->frame_control) ||
352 ieee80211_is_cts(hdr->frame_control)) {
7050ec82 353 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
ac104462 354 if (ieee80211_is_rts(hdr->frame_control))
7050ec82 355 __set_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags);
e039fa4a 356 else
7050ec82 357 __set_bit(ENTRY_TXD_CTS_FRAME, &txdesc->flags);
e039fa4a 358 if (tx_info->control.rts_cts_rate_idx >= 0)
2e92e6f2 359 rate =
e039fa4a 360 ieee80211_get_rts_cts_rate(rt2x00dev->hw, tx_info);
7050ec82
ID
361 }
362
363 /*
364 * Determine retry information.
365 */
e6a9854b 366 txdesc->retry_limit = tx_info->control.rates[0].count - 1;
42c82857 367 if (txdesc->retry_limit >= rt2x00dev->long_retry)
7050ec82
ID
368 __set_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags);
369
370 /*
371 * Check if more fragments are pending
372 */
267e8987
ID
373 if (ieee80211_has_morefrags(hdr->frame_control) ||
374 (tx_info->flags & IEEE80211_TX_CTL_MORE_FRAMES)) {
7050ec82
ID
375 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
376 __set_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags);
377 }
378
379 /*
380 * Beacons and probe responses require the tsf timestamp
e81e0aef
AB
381 * to be inserted into the frame, except for a frame that has been injected
382 * through a monitor interface. This latter is needed for testing a
383 * monitor interface.
7050ec82 384 */
e81e0aef
AB
385 if ((ieee80211_is_beacon(hdr->frame_control) ||
386 ieee80211_is_probe_resp(hdr->frame_control)) &&
387 (!(tx_info->flags & IEEE80211_TX_CTL_INJECTED)))
7050ec82
ID
388 __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags);
389
390 /*
391 * Determine with what IFS priority this frame should be send.
392 * Set ifs to IFS_SIFS when the this is not the first fragment,
393 * or this fragment came after RTS/CTS.
394 */
7b40982e
ID
395 if ((tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) &&
396 !test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)) {
7050ec82
ID
397 __set_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags);
398 txdesc->ifs = IFS_BACKOFF;
7b40982e 399 } else
7050ec82 400 txdesc->ifs = IFS_SIFS;
7050ec82 401
076f9582
ID
402 /*
403 * Determine rate modulation.
404 */
7050ec82 405 hwrate = rt2x00_get_rate(rate->hw_value);
076f9582 406 txdesc->rate_mode = RATE_MODE_CCK;
7b40982e 407 if (hwrate->flags & DEV_RATE_OFDM)
076f9582 408 txdesc->rate_mode = RATE_MODE_OFDM;
7050ec82 409
7b40982e
ID
410 /*
411 * Apply TX descriptor handling by components
412 */
413 rt2x00crypto_create_tx_descriptor(entry, txdesc);
35f00cfc 414 rt2x00ht_create_tx_descriptor(entry, txdesc, hwrate);
7b40982e
ID
415 rt2x00queue_create_tx_descriptor_seq(entry, txdesc);
416 rt2x00queue_create_tx_descriptor_plcp(entry, txdesc, hwrate);
7050ec82 417}
7050ec82 418
bd88a781
ID
419static void rt2x00queue_write_tx_descriptor(struct queue_entry *entry,
420 struct txentry_desc *txdesc)
7050ec82 421{
b869767b
ID
422 struct data_queue *queue = entry->queue;
423 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
7050ec82
ID
424
425 rt2x00dev->ops->lib->write_tx_desc(rt2x00dev, entry->skb, txdesc);
426
427 /*
428 * All processing on the frame has been completed, this means
429 * it is now ready to be dumped to userspace through debugfs.
430 */
5c3b685c 431 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_TX, entry->skb);
6295d815
GW
432}
433
434static void rt2x00queue_kick_tx_queue(struct queue_entry *entry,
435 struct txentry_desc *txdesc)
436{
437 struct data_queue *queue = entry->queue;
438 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
7050ec82
ID
439
440 /*
b869767b 441 * Check if we need to kick the queue, there are however a few rules
6295d815 442 * 1) Don't kick unless this is the last in frame in a burst.
b869767b
ID
443 * When the burst flag is set, this frame is always followed
444 * by another frame which in some way are related to eachother.
445 * This is true for fragments, RTS or CTS-to-self frames.
6295d815 446 * 2) Rule 1 can be broken when the available entries
b869767b 447 * in the queue are less then a certain threshold.
7050ec82 448 */
b869767b
ID
449 if (rt2x00queue_threshold(queue) ||
450 !test_bit(ENTRY_TXD_BURST, &txdesc->flags))
451 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, queue->qid);
7050ec82 452}
7050ec82 453
7351c6bd
JB
454int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
455 bool local)
6db3786a 456{
e6a9854b 457 struct ieee80211_tx_info *tx_info;
6db3786a
ID
458 struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX);
459 struct txentry_desc txdesc;
d74f5ba4 460 struct skb_frame_desc *skbdesc;
e6a9854b 461 u8 rate_idx, rate_flags;
6db3786a
ID
462
463 if (unlikely(rt2x00queue_full(queue)))
0e3de998 464 return -ENOBUFS;
6db3786a 465
0262ab0d 466 if (test_and_set_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags)) {
6db3786a
ID
467 ERROR(queue->rt2x00dev,
468 "Arrived at non-free entry in the non-full queue %d.\n"
469 "Please file bug report to %s.\n",
470 queue->qid, DRV_PROJECT);
471 return -EINVAL;
472 }
473
474 /*
475 * Copy all TX descriptor information into txdesc,
476 * after that we are free to use the skb->cb array
477 * for our information.
478 */
479 entry->skb = skb;
480 rt2x00queue_create_tx_descriptor(entry, &txdesc);
481
d74f5ba4 482 /*
e6a9854b 483 * All information is retrieved from the skb->cb array,
2bb057d0 484 * now we should claim ownership of the driver part of that
e6a9854b 485 * array, preserving the bitrate index and flags.
d74f5ba4 486 */
e6a9854b
JB
487 tx_info = IEEE80211_SKB_CB(skb);
488 rate_idx = tx_info->control.rates[0].idx;
489 rate_flags = tx_info->control.rates[0].flags;
0e3de998 490 skbdesc = get_skb_frame_desc(skb);
d74f5ba4
ID
491 memset(skbdesc, 0, sizeof(*skbdesc));
492 skbdesc->entry = entry;
e6a9854b
JB
493 skbdesc->tx_rate_idx = rate_idx;
494 skbdesc->tx_rate_flags = rate_flags;
d74f5ba4 495
7351c6bd
JB
496 if (local)
497 skbdesc->flags |= SKBDESC_NOT_MAC80211;
498
2bb057d0
ID
499 /*
500 * When hardware encryption is supported, and this frame
501 * is to be encrypted, we should strip the IV/EIV data from
3ad2f3fb 502 * the frame so we can provide it to the driver separately.
2bb057d0
ID
503 */
504 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc.flags) &&
dddfb478 505 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc.flags)) {
3f787bd6 506 if (test_bit(DRIVER_REQUIRE_COPY_IV, &queue->rt2x00dev->flags))
9eb4e21e 507 rt2x00crypto_tx_copy_iv(skb, &txdesc);
dddfb478 508 else
9eb4e21e 509 rt2x00crypto_tx_remove_iv(skb, &txdesc);
dddfb478 510 }
2bb057d0 511
93354cbb
ID
512 /*
513 * When DMA allocation is required we should guarentee to the
514 * driver that the DMA is aligned to a 4-byte boundary.
93354cbb
ID
515 * However some drivers require L2 padding to pad the payload
516 * rather then the header. This could be a requirement for
517 * PCI and USB devices, while header alignment only is valid
518 * for PCI devices.
519 */
9f166171 520 if (test_bit(DRIVER_REQUIRE_L2PAD, &queue->rt2x00dev->flags))
daee6c09 521 rt2x00queue_insert_l2pad(entry->skb, txdesc.header_length);
93354cbb 522 else if (test_bit(DRIVER_REQUIRE_DMA, &queue->rt2x00dev->flags))
daee6c09 523 rt2x00queue_align_frame(entry->skb);
9f166171 524
2bb057d0
ID
525 /*
526 * It could be possible that the queue was corrupted and this
0e3de998
ID
527 * call failed. Since we always return NETDEV_TX_OK to mac80211,
528 * this frame will simply be dropped.
2bb057d0 529 */
41086693
HS
530 if (unlikely(queue->rt2x00dev->ops->lib->write_tx_data(entry,
531 &txdesc))) {
0262ab0d 532 clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
2bb057d0 533 entry->skb = NULL;
0e3de998 534 return -EIO;
6db3786a
ID
535 }
536
d74f5ba4
ID
537 if (test_bit(DRIVER_REQUIRE_DMA, &queue->rt2x00dev->flags))
538 rt2x00queue_map_txskb(queue->rt2x00dev, skb);
539
0262ab0d 540 set_bit(ENTRY_DATA_PENDING, &entry->flags);
6db3786a
ID
541
542 rt2x00queue_index_inc(queue, Q_INDEX);
543 rt2x00queue_write_tx_descriptor(entry, &txdesc);
6295d815 544 rt2x00queue_kick_tx_queue(entry, &txdesc);
6db3786a
ID
545
546 return 0;
547}
548
bd88a781 549int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev,
a2c9b652
ID
550 struct ieee80211_vif *vif,
551 const bool enable_beacon)
bd88a781
ID
552{
553 struct rt2x00_intf *intf = vif_to_intf(vif);
554 struct skb_frame_desc *skbdesc;
555 struct txentry_desc txdesc;
bd88a781
ID
556
557 if (unlikely(!intf->beacon))
558 return -ENOBUFS;
559
17512dc3
IP
560 mutex_lock(&intf->beacon_skb_mutex);
561
562 /*
563 * Clean up the beacon skb.
564 */
565 rt2x00queue_free_skb(rt2x00dev, intf->beacon->skb);
566 intf->beacon->skb = NULL;
567
a2c9b652
ID
568 if (!enable_beacon) {
569 rt2x00dev->ops->lib->kill_tx_queue(rt2x00dev, QID_BEACON);
17512dc3 570 mutex_unlock(&intf->beacon_skb_mutex);
a2c9b652
ID
571 return 0;
572 }
573
bd88a781 574 intf->beacon->skb = ieee80211_beacon_get(rt2x00dev->hw, vif);
17512dc3
IP
575 if (!intf->beacon->skb) {
576 mutex_unlock(&intf->beacon_skb_mutex);
bd88a781 577 return -ENOMEM;
17512dc3 578 }
bd88a781
ID
579
580 /*
581 * Copy all TX descriptor information into txdesc,
582 * after that we are free to use the skb->cb array
583 * for our information.
584 */
585 rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc);
586
bd88a781
ID
587 /*
588 * Fill in skb descriptor
589 */
590 skbdesc = get_skb_frame_desc(intf->beacon->skb);
591 memset(skbdesc, 0, sizeof(*skbdesc));
bd88a781
ID
592 skbdesc->entry = intf->beacon;
593
bd88a781 594 /*
d61cb266 595 * Send beacon to hardware and enable beacon genaration..
bd88a781 596 */
f224f4ef 597 rt2x00dev->ops->lib->write_beacon(intf->beacon, &txdesc);
bd88a781 598
17512dc3
IP
599 mutex_unlock(&intf->beacon_skb_mutex);
600
bd88a781
ID
601 return 0;
602}
603
181d6902 604struct data_queue *rt2x00queue_get_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 605 const enum data_queue_qid queue)
181d6902
ID
606{
607 int atim = test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
608
a2c9b652
ID
609 if (queue == QID_RX)
610 return rt2x00dev->rx;
611
61448f88 612 if (queue < rt2x00dev->ops->tx_queues && rt2x00dev->tx)
181d6902
ID
613 return &rt2x00dev->tx[queue];
614
615 if (!rt2x00dev->bcn)
616 return NULL;
617
e58c6aca 618 if (queue == QID_BEACON)
181d6902 619 return &rt2x00dev->bcn[0];
e58c6aca 620 else if (queue == QID_ATIM && atim)
181d6902
ID
621 return &rt2x00dev->bcn[1];
622
623 return NULL;
624}
625EXPORT_SYMBOL_GPL(rt2x00queue_get_queue);
626
627struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue,
628 enum queue_index index)
629{
630 struct queue_entry *entry;
5f46c4d0 631 unsigned long irqflags;
181d6902
ID
632
633 if (unlikely(index >= Q_INDEX_MAX)) {
634 ERROR(queue->rt2x00dev,
635 "Entry requested from invalid index type (%d)\n", index);
636 return NULL;
637 }
638
5f46c4d0 639 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
640
641 entry = &queue->entries[queue->index[index]];
642
5f46c4d0 643 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902
ID
644
645 return entry;
646}
647EXPORT_SYMBOL_GPL(rt2x00queue_get_entry);
648
649void rt2x00queue_index_inc(struct data_queue *queue, enum queue_index index)
650{
5f46c4d0
ID
651 unsigned long irqflags;
652
181d6902
ID
653 if (unlikely(index >= Q_INDEX_MAX)) {
654 ERROR(queue->rt2x00dev,
655 "Index change on invalid index type (%d)\n", index);
656 return;
657 }
658
5f46c4d0 659 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
660
661 queue->index[index]++;
662 if (queue->index[index] >= queue->limit)
663 queue->index[index] = 0;
664
10b6b801
ID
665 if (index == Q_INDEX) {
666 queue->length++;
667 } else if (index == Q_INDEX_DONE) {
668 queue->length--;
55887511 669 queue->count++;
10b6b801 670 }
181d6902 671
5f46c4d0 672 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902 673}
181d6902
ID
674
675static void rt2x00queue_reset(struct data_queue *queue)
676{
5f46c4d0
ID
677 unsigned long irqflags;
678
679 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
680
681 queue->count = 0;
682 queue->length = 0;
683 memset(queue->index, 0, sizeof(queue->index));
684
5f46c4d0 685 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902
ID
686}
687
a2c9b652
ID
688void rt2x00queue_stop_queues(struct rt2x00_dev *rt2x00dev)
689{
690 struct data_queue *queue;
691
692 txall_queue_for_each(rt2x00dev, queue)
693 rt2x00dev->ops->lib->kill_tx_queue(rt2x00dev, queue->qid);
694}
695
798b7adb 696void rt2x00queue_init_queues(struct rt2x00_dev *rt2x00dev)
181d6902
ID
697{
698 struct data_queue *queue;
699 unsigned int i;
700
798b7adb 701 queue_for_each(rt2x00dev, queue) {
181d6902
ID
702 rt2x00queue_reset(queue);
703
9c0ab712
ID
704 for (i = 0; i < queue->limit; i++) {
705 queue->entries[i].flags = 0;
706
798b7adb 707 rt2x00dev->ops->lib->clear_entry(&queue->entries[i]);
9c0ab712 708 }
181d6902
ID
709 }
710}
711
712static int rt2x00queue_alloc_entries(struct data_queue *queue,
713 const struct data_queue_desc *qdesc)
714{
715 struct queue_entry *entries;
716 unsigned int entry_size;
717 unsigned int i;
718
719 rt2x00queue_reset(queue);
720
721 queue->limit = qdesc->entry_num;
b869767b 722 queue->threshold = DIV_ROUND_UP(qdesc->entry_num, 10);
181d6902
ID
723 queue->data_size = qdesc->data_size;
724 queue->desc_size = qdesc->desc_size;
725
726 /*
727 * Allocate all queue entries.
728 */
729 entry_size = sizeof(*entries) + qdesc->priv_size;
730 entries = kzalloc(queue->limit * entry_size, GFP_KERNEL);
731 if (!entries)
732 return -ENOMEM;
733
734#define QUEUE_ENTRY_PRIV_OFFSET(__base, __index, __limit, __esize, __psize) \
231be4e9
AB
735 ( ((char *)(__base)) + ((__limit) * (__esize)) + \
736 ((__index) * (__psize)) )
181d6902
ID
737
738 for (i = 0; i < queue->limit; i++) {
739 entries[i].flags = 0;
740 entries[i].queue = queue;
741 entries[i].skb = NULL;
742 entries[i].entry_idx = i;
743 entries[i].priv_data =
744 QUEUE_ENTRY_PRIV_OFFSET(entries, i, queue->limit,
745 sizeof(*entries), qdesc->priv_size);
746 }
747
748#undef QUEUE_ENTRY_PRIV_OFFSET
749
750 queue->entries = entries;
751
752 return 0;
753}
754
c4da0048
GW
755static void rt2x00queue_free_skbs(struct rt2x00_dev *rt2x00dev,
756 struct data_queue *queue)
30caa6e3
GW
757{
758 unsigned int i;
759
760 if (!queue->entries)
761 return;
762
763 for (i = 0; i < queue->limit; i++) {
764 if (queue->entries[i].skb)
c4da0048 765 rt2x00queue_free_skb(rt2x00dev, queue->entries[i].skb);
30caa6e3
GW
766 }
767}
768
c4da0048
GW
769static int rt2x00queue_alloc_rxskbs(struct rt2x00_dev *rt2x00dev,
770 struct data_queue *queue)
30caa6e3
GW
771{
772 unsigned int i;
773 struct sk_buff *skb;
774
775 for (i = 0; i < queue->limit; i++) {
c4da0048 776 skb = rt2x00queue_alloc_rxskb(rt2x00dev, &queue->entries[i]);
30caa6e3 777 if (!skb)
61243d8e 778 return -ENOMEM;
30caa6e3
GW
779 queue->entries[i].skb = skb;
780 }
781
782 return 0;
30caa6e3
GW
783}
784
181d6902
ID
785int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev)
786{
787 struct data_queue *queue;
788 int status;
789
181d6902
ID
790 status = rt2x00queue_alloc_entries(rt2x00dev->rx, rt2x00dev->ops->rx);
791 if (status)
792 goto exit;
793
794 tx_queue_for_each(rt2x00dev, queue) {
795 status = rt2x00queue_alloc_entries(queue, rt2x00dev->ops->tx);
796 if (status)
797 goto exit;
798 }
799
800 status = rt2x00queue_alloc_entries(rt2x00dev->bcn, rt2x00dev->ops->bcn);
801 if (status)
802 goto exit;
803
30caa6e3
GW
804 if (test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags)) {
805 status = rt2x00queue_alloc_entries(&rt2x00dev->bcn[1],
806 rt2x00dev->ops->atim);
807 if (status)
808 goto exit;
809 }
181d6902 810
c4da0048 811 status = rt2x00queue_alloc_rxskbs(rt2x00dev, rt2x00dev->rx);
181d6902
ID
812 if (status)
813 goto exit;
814
815 return 0;
816
817exit:
818 ERROR(rt2x00dev, "Queue entries allocation failed.\n");
819
820 rt2x00queue_uninitialize(rt2x00dev);
821
822 return status;
823}
824
825void rt2x00queue_uninitialize(struct rt2x00_dev *rt2x00dev)
826{
827 struct data_queue *queue;
828
c4da0048 829 rt2x00queue_free_skbs(rt2x00dev, rt2x00dev->rx);
30caa6e3 830
181d6902
ID
831 queue_for_each(rt2x00dev, queue) {
832 kfree(queue->entries);
833 queue->entries = NULL;
834 }
835}
836
8f539276
ID
837static void rt2x00queue_init(struct rt2x00_dev *rt2x00dev,
838 struct data_queue *queue, enum data_queue_qid qid)
839{
840 spin_lock_init(&queue->lock);
841
842 queue->rt2x00dev = rt2x00dev;
843 queue->qid = qid;
2af0a570 844 queue->txop = 0;
8f539276
ID
845 queue->aifs = 2;
846 queue->cw_min = 5;
847 queue->cw_max = 10;
848}
849
181d6902
ID
850int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
851{
852 struct data_queue *queue;
853 enum data_queue_qid qid;
854 unsigned int req_atim =
855 !!test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
856
857 /*
858 * We need the following queues:
859 * RX: 1
61448f88 860 * TX: ops->tx_queues
181d6902
ID
861 * Beacon: 1
862 * Atim: 1 (if required)
863 */
61448f88 864 rt2x00dev->data_queues = 2 + rt2x00dev->ops->tx_queues + req_atim;
181d6902
ID
865
866 queue = kzalloc(rt2x00dev->data_queues * sizeof(*queue), GFP_KERNEL);
867 if (!queue) {
868 ERROR(rt2x00dev, "Queue allocation failed.\n");
869 return -ENOMEM;
870 }
871
872 /*
873 * Initialize pointers
874 */
875 rt2x00dev->rx = queue;
876 rt2x00dev->tx = &queue[1];
61448f88 877 rt2x00dev->bcn = &queue[1 + rt2x00dev->ops->tx_queues];
181d6902
ID
878
879 /*
880 * Initialize queue parameters.
881 * RX: qid = QID_RX
882 * TX: qid = QID_AC_BE + index
883 * TX: cw_min: 2^5 = 32.
884 * TX: cw_max: 2^10 = 1024.
565a019a
ID
885 * BCN: qid = QID_BEACON
886 * ATIM: qid = QID_ATIM
181d6902 887 */
8f539276 888 rt2x00queue_init(rt2x00dev, rt2x00dev->rx, QID_RX);
181d6902 889
8f539276
ID
890 qid = QID_AC_BE;
891 tx_queue_for_each(rt2x00dev, queue)
892 rt2x00queue_init(rt2x00dev, queue, qid++);
181d6902 893
565a019a 894 rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[0], QID_BEACON);
181d6902 895 if (req_atim)
565a019a 896 rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[1], QID_ATIM);
181d6902
ID
897
898 return 0;
899}
900
901void rt2x00queue_free(struct rt2x00_dev *rt2x00dev)
902{
903 kfree(rt2x00dev->rx);
904 rt2x00dev->rx = NULL;
905 rt2x00dev->tx = NULL;
906 rt2x00dev->bcn = NULL;
907}
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