rt2x00: only set TXDONE_FALLBACK in rt2800pci if the frame was retried
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2x00queue.c
CommitLineData
181d6902 1/*
9c9a0d14
GW
2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2004 - 2009 Gertjan van Wingerde <gwingerde@gmail.com>
181d6902
ID
4 <http://rt2x00.serialmonkey.com>
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the
18 Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22/*
23 Module: rt2x00lib
24 Abstract: rt2x00 queue specific routines.
25 */
26
5a0e3ad6 27#include <linux/slab.h>
181d6902
ID
28#include <linux/kernel.h>
29#include <linux/module.h>
c4da0048 30#include <linux/dma-mapping.h>
181d6902
ID
31
32#include "rt2x00.h"
33#include "rt2x00lib.h"
34
c4da0048
GW
35struct sk_buff *rt2x00queue_alloc_rxskb(struct rt2x00_dev *rt2x00dev,
36 struct queue_entry *entry)
239c249d 37{
c4da0048
GW
38 struct sk_buff *skb;
39 struct skb_frame_desc *skbdesc;
2bb057d0
ID
40 unsigned int frame_size;
41 unsigned int head_size = 0;
42 unsigned int tail_size = 0;
239c249d
GW
43
44 /*
45 * The frame size includes descriptor size, because the
46 * hardware directly receive the frame into the skbuffer.
47 */
c4da0048 48 frame_size = entry->queue->data_size + entry->queue->desc_size;
239c249d
GW
49
50 /*
ff352391
ID
51 * The payload should be aligned to a 4-byte boundary,
52 * this means we need at least 3 bytes for moving the frame
53 * into the correct offset.
239c249d 54 */
2bb057d0
ID
55 head_size = 4;
56
57 /*
58 * For IV/EIV/ICV assembly we must make sure there is
59 * at least 8 bytes bytes available in headroom for IV/EIV
9c3444d3 60 * and 8 bytes for ICV data as tailroon.
2bb057d0 61 */
2bb057d0
ID
62 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
63 head_size += 8;
9c3444d3 64 tail_size += 8;
2bb057d0 65 }
239c249d
GW
66
67 /*
68 * Allocate skbuffer.
69 */
2bb057d0 70 skb = dev_alloc_skb(frame_size + head_size + tail_size);
239c249d
GW
71 if (!skb)
72 return NULL;
73
2bb057d0
ID
74 /*
75 * Make sure we not have a frame with the requested bytes
76 * available in the head and tail.
77 */
78 skb_reserve(skb, head_size);
239c249d
GW
79 skb_put(skb, frame_size);
80
c4da0048
GW
81 /*
82 * Populate skbdesc.
83 */
84 skbdesc = get_skb_frame_desc(skb);
85 memset(skbdesc, 0, sizeof(*skbdesc));
86 skbdesc->entry = entry;
87
88 if (test_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags)) {
89 skbdesc->skb_dma = dma_map_single(rt2x00dev->dev,
90 skb->data,
91 skb->len,
92 DMA_FROM_DEVICE);
93 skbdesc->flags |= SKBDESC_DMA_MAPPED_RX;
94 }
95
239c249d
GW
96 return skb;
97}
30caa6e3 98
c4da0048 99void rt2x00queue_map_txskb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
30caa6e3 100{
c4da0048
GW
101 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
102
3ee54a07
ID
103 skbdesc->skb_dma =
104 dma_map_single(rt2x00dev->dev, skb->data, skb->len, DMA_TO_DEVICE);
c4da0048
GW
105 skbdesc->flags |= SKBDESC_DMA_MAPPED_TX;
106}
107EXPORT_SYMBOL_GPL(rt2x00queue_map_txskb);
108
109void rt2x00queue_unmap_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
110{
111 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
112
113 if (skbdesc->flags & SKBDESC_DMA_MAPPED_RX) {
114 dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma, skb->len,
115 DMA_FROM_DEVICE);
116 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_RX;
117 }
118
119 if (skbdesc->flags & SKBDESC_DMA_MAPPED_TX) {
0b8004aa 120 dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma, skb->len,
c4da0048
GW
121 DMA_TO_DEVICE);
122 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_TX;
123 }
124}
0b8004aa 125EXPORT_SYMBOL_GPL(rt2x00queue_unmap_skb);
c4da0048
GW
126
127void rt2x00queue_free_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
128{
9a613195
ID
129 if (!skb)
130 return;
131
61243d8e 132 rt2x00queue_unmap_skb(rt2x00dev, skb);
30caa6e3
GW
133 dev_kfree_skb_any(skb);
134}
239c249d 135
daee6c09 136void rt2x00queue_align_frame(struct sk_buff *skb)
9f166171 137{
9f166171 138 unsigned int frame_length = skb->len;
daee6c09 139 unsigned int align = ALIGN_SIZE(skb, 0);
9f166171
ID
140
141 if (!align)
142 return;
143
daee6c09
ID
144 skb_push(skb, align);
145 memmove(skb->data, skb->data + align, frame_length);
146 skb_trim(skb, frame_length);
147}
148
95d69aa0 149void rt2x00queue_align_payload(struct sk_buff *skb, unsigned int header_length)
daee6c09
ID
150{
151 unsigned int frame_length = skb->len;
95d69aa0 152 unsigned int align = ALIGN_SIZE(skb, header_length);
daee6c09
ID
153
154 if (!align)
155 return;
156
157 skb_push(skb, align);
158 memmove(skb->data, skb->data + align, frame_length);
159 skb_trim(skb, frame_length);
160}
161
162void rt2x00queue_insert_l2pad(struct sk_buff *skb, unsigned int header_length)
163{
2e331462 164 unsigned int payload_length = skb->len - header_length;
daee6c09
ID
165 unsigned int header_align = ALIGN_SIZE(skb, 0);
166 unsigned int payload_align = ALIGN_SIZE(skb, header_length);
e54be4e7 167 unsigned int l2pad = payload_length ? L2PAD_SIZE(header_length) : 0;
daee6c09 168
2e331462
GW
169 /*
170 * Adjust the header alignment if the payload needs to be moved more
171 * than the header.
172 */
173 if (payload_align > header_align)
174 header_align += 4;
175
176 /* There is nothing to do if no alignment is needed */
177 if (!header_align)
178 return;
daee6c09 179
2e331462
GW
180 /* Reserve the amount of space needed in front of the frame */
181 skb_push(skb, header_align);
182
183 /*
184 * Move the header.
185 */
186 memmove(skb->data, skb->data + header_align, header_length);
187
188 /* Move the payload, if present and if required */
189 if (payload_length && payload_align)
daee6c09 190 memmove(skb->data + header_length + l2pad,
a5186e99 191 skb->data + header_length + l2pad + payload_align,
2e331462
GW
192 payload_length);
193
194 /* Trim the skb to the correct size */
195 skb_trim(skb, header_length + l2pad + payload_length);
9f166171
ID
196}
197
daee6c09
ID
198void rt2x00queue_remove_l2pad(struct sk_buff *skb, unsigned int header_length)
199{
77e73d18 200 unsigned int l2pad = L2PAD_SIZE(header_length);
daee6c09 201
354e39db 202 if (!l2pad)
daee6c09
ID
203 return;
204
205 memmove(skb->data + l2pad, skb->data, header_length);
206 skb_pull(skb, l2pad);
207}
208
7b40982e
ID
209static void rt2x00queue_create_tx_descriptor_seq(struct queue_entry *entry,
210 struct txentry_desc *txdesc)
211{
212 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
213 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
214 struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
215 unsigned long irqflags;
216
217 if (!(tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) ||
218 unlikely(!tx_info->control.vif))
219 return;
220
221 /*
222 * Hardware should insert sequence counter.
223 * FIXME: We insert a software sequence counter first for
224 * hardware that doesn't support hardware sequence counting.
225 *
226 * This is wrong because beacons are not getting sequence
227 * numbers assigned properly.
228 *
229 * A secondary problem exists for drivers that cannot toggle
230 * sequence counting per-frame, since those will override the
231 * sequence counter given by mac80211.
232 */
233 spin_lock_irqsave(&intf->seqlock, irqflags);
234
235 if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags))
236 intf->seqno += 0x10;
237 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
238 hdr->seq_ctrl |= cpu_to_le16(intf->seqno);
239
240 spin_unlock_irqrestore(&intf->seqlock, irqflags);
241
242 __set_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags);
243}
244
245static void rt2x00queue_create_tx_descriptor_plcp(struct queue_entry *entry,
246 struct txentry_desc *txdesc,
247 const struct rt2x00_rate *hwrate)
248{
249 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
250 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
251 struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0];
252 unsigned int data_length;
253 unsigned int duration;
254 unsigned int residual;
255
256 /* Data length + CRC + Crypto overhead (IV/EIV/ICV/MIC) */
257 data_length = entry->skb->len + 4;
258 data_length += rt2x00crypto_tx_overhead(rt2x00dev, entry->skb);
259
260 /*
261 * PLCP setup
262 * Length calculation depends on OFDM/CCK rate.
263 */
264 txdesc->signal = hwrate->plcp;
265 txdesc->service = 0x04;
266
267 if (hwrate->flags & DEV_RATE_OFDM) {
268 txdesc->length_high = (data_length >> 6) & 0x3f;
269 txdesc->length_low = data_length & 0x3f;
270 } else {
271 /*
272 * Convert length to microseconds.
273 */
274 residual = GET_DURATION_RES(data_length, hwrate->bitrate);
275 duration = GET_DURATION(data_length, hwrate->bitrate);
276
277 if (residual != 0) {
278 duration++;
279
280 /*
281 * Check if we need to set the Length Extension
282 */
283 if (hwrate->bitrate == 110 && residual <= 30)
284 txdesc->service |= 0x80;
285 }
286
287 txdesc->length_high = (duration >> 8) & 0xff;
288 txdesc->length_low = duration & 0xff;
289
290 /*
291 * When preamble is enabled we should set the
292 * preamble bit for the signal.
293 */
294 if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
295 txdesc->signal |= 0x08;
296 }
297}
298
bd88a781
ID
299static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry,
300 struct txentry_desc *txdesc)
7050ec82 301{
2e92e6f2 302 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
e039fa4a 303 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
7050ec82 304 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
2e92e6f2 305 struct ieee80211_rate *rate =
e039fa4a 306 ieee80211_get_tx_rate(rt2x00dev->hw, tx_info);
7050ec82 307 const struct rt2x00_rate *hwrate;
7050ec82
ID
308
309 memset(txdesc, 0, sizeof(*txdesc));
310
311 /*
312 * Initialize information from queue
313 */
314 txdesc->queue = entry->queue->qid;
315 txdesc->cw_min = entry->queue->cw_min;
316 txdesc->cw_max = entry->queue->cw_max;
317 txdesc->aifs = entry->queue->aifs;
318
9f166171 319 /*
df624ca5 320 * Header and frame information.
9f166171 321 */
df624ca5 322 txdesc->length = entry->skb->len;
9f166171 323 txdesc->header_length = ieee80211_get_hdrlen_from_skb(entry->skb);
9f166171 324
7050ec82
ID
325 /*
326 * Check whether this frame is to be acked.
327 */
e039fa4a 328 if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK))
7050ec82
ID
329 __set_bit(ENTRY_TXD_ACK, &txdesc->flags);
330
331 /*
332 * Check if this is a RTS/CTS frame
333 */
ac104462
ID
334 if (ieee80211_is_rts(hdr->frame_control) ||
335 ieee80211_is_cts(hdr->frame_control)) {
7050ec82 336 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
ac104462 337 if (ieee80211_is_rts(hdr->frame_control))
7050ec82 338 __set_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags);
e039fa4a 339 else
7050ec82 340 __set_bit(ENTRY_TXD_CTS_FRAME, &txdesc->flags);
e039fa4a 341 if (tx_info->control.rts_cts_rate_idx >= 0)
2e92e6f2 342 rate =
e039fa4a 343 ieee80211_get_rts_cts_rate(rt2x00dev->hw, tx_info);
7050ec82
ID
344 }
345
346 /*
347 * Determine retry information.
348 */
e6a9854b 349 txdesc->retry_limit = tx_info->control.rates[0].count - 1;
42c82857 350 if (txdesc->retry_limit >= rt2x00dev->long_retry)
7050ec82
ID
351 __set_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags);
352
353 /*
354 * Check if more fragments are pending
355 */
267e8987
ID
356 if (ieee80211_has_morefrags(hdr->frame_control) ||
357 (tx_info->flags & IEEE80211_TX_CTL_MORE_FRAMES)) {
7050ec82
ID
358 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
359 __set_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags);
360 }
361
362 /*
363 * Beacons and probe responses require the tsf timestamp
e81e0aef
AB
364 * to be inserted into the frame, except for a frame that has been injected
365 * through a monitor interface. This latter is needed for testing a
366 * monitor interface.
7050ec82 367 */
e81e0aef
AB
368 if ((ieee80211_is_beacon(hdr->frame_control) ||
369 ieee80211_is_probe_resp(hdr->frame_control)) &&
370 (!(tx_info->flags & IEEE80211_TX_CTL_INJECTED)))
7050ec82
ID
371 __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags);
372
373 /*
374 * Determine with what IFS priority this frame should be send.
375 * Set ifs to IFS_SIFS when the this is not the first fragment,
376 * or this fragment came after RTS/CTS.
377 */
7b40982e
ID
378 if ((tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) &&
379 !test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)) {
7050ec82
ID
380 __set_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags);
381 txdesc->ifs = IFS_BACKOFF;
7b40982e 382 } else
7050ec82 383 txdesc->ifs = IFS_SIFS;
7050ec82 384
076f9582
ID
385 /*
386 * Determine rate modulation.
387 */
7050ec82 388 hwrate = rt2x00_get_rate(rate->hw_value);
076f9582 389 txdesc->rate_mode = RATE_MODE_CCK;
7b40982e 390 if (hwrate->flags & DEV_RATE_OFDM)
076f9582 391 txdesc->rate_mode = RATE_MODE_OFDM;
7050ec82 392
7b40982e
ID
393 /*
394 * Apply TX descriptor handling by components
395 */
396 rt2x00crypto_create_tx_descriptor(entry, txdesc);
35f00cfc 397 rt2x00ht_create_tx_descriptor(entry, txdesc, hwrate);
7b40982e
ID
398 rt2x00queue_create_tx_descriptor_seq(entry, txdesc);
399 rt2x00queue_create_tx_descriptor_plcp(entry, txdesc, hwrate);
7050ec82 400}
7050ec82 401
bd88a781
ID
402static void rt2x00queue_write_tx_descriptor(struct queue_entry *entry,
403 struct txentry_desc *txdesc)
7050ec82 404{
b869767b
ID
405 struct data_queue *queue = entry->queue;
406 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
7050ec82
ID
407
408 rt2x00dev->ops->lib->write_tx_desc(rt2x00dev, entry->skb, txdesc);
409
410 /*
411 * All processing on the frame has been completed, this means
412 * it is now ready to be dumped to userspace through debugfs.
413 */
5c3b685c 414 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_TX, entry->skb);
6295d815
GW
415}
416
417static void rt2x00queue_kick_tx_queue(struct queue_entry *entry,
418 struct txentry_desc *txdesc)
419{
420 struct data_queue *queue = entry->queue;
421 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
7050ec82
ID
422
423 /*
b869767b 424 * Check if we need to kick the queue, there are however a few rules
6295d815 425 * 1) Don't kick unless this is the last in frame in a burst.
b869767b
ID
426 * When the burst flag is set, this frame is always followed
427 * by another frame which in some way are related to eachother.
428 * This is true for fragments, RTS or CTS-to-self frames.
6295d815 429 * 2) Rule 1 can be broken when the available entries
b869767b 430 * in the queue are less then a certain threshold.
7050ec82 431 */
b869767b
ID
432 if (rt2x00queue_threshold(queue) ||
433 !test_bit(ENTRY_TXD_BURST, &txdesc->flags))
434 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, queue->qid);
7050ec82 435}
7050ec82 436
7351c6bd
JB
437int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
438 bool local)
6db3786a 439{
e6a9854b 440 struct ieee80211_tx_info *tx_info;
6db3786a
ID
441 struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX);
442 struct txentry_desc txdesc;
d74f5ba4 443 struct skb_frame_desc *skbdesc;
e6a9854b 444 u8 rate_idx, rate_flags;
6db3786a
ID
445
446 if (unlikely(rt2x00queue_full(queue)))
0e3de998 447 return -ENOBUFS;
6db3786a 448
0262ab0d 449 if (test_and_set_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags)) {
6db3786a
ID
450 ERROR(queue->rt2x00dev,
451 "Arrived at non-free entry in the non-full queue %d.\n"
452 "Please file bug report to %s.\n",
453 queue->qid, DRV_PROJECT);
454 return -EINVAL;
455 }
456
457 /*
458 * Copy all TX descriptor information into txdesc,
459 * after that we are free to use the skb->cb array
460 * for our information.
461 */
462 entry->skb = skb;
463 rt2x00queue_create_tx_descriptor(entry, &txdesc);
464
d74f5ba4 465 /*
e6a9854b 466 * All information is retrieved from the skb->cb array,
2bb057d0 467 * now we should claim ownership of the driver part of that
e6a9854b 468 * array, preserving the bitrate index and flags.
d74f5ba4 469 */
e6a9854b
JB
470 tx_info = IEEE80211_SKB_CB(skb);
471 rate_idx = tx_info->control.rates[0].idx;
472 rate_flags = tx_info->control.rates[0].flags;
0e3de998 473 skbdesc = get_skb_frame_desc(skb);
d74f5ba4
ID
474 memset(skbdesc, 0, sizeof(*skbdesc));
475 skbdesc->entry = entry;
e6a9854b
JB
476 skbdesc->tx_rate_idx = rate_idx;
477 skbdesc->tx_rate_flags = rate_flags;
d74f5ba4 478
7351c6bd
JB
479 if (local)
480 skbdesc->flags |= SKBDESC_NOT_MAC80211;
481
2bb057d0
ID
482 /*
483 * When hardware encryption is supported, and this frame
484 * is to be encrypted, we should strip the IV/EIV data from
3ad2f3fb 485 * the frame so we can provide it to the driver separately.
2bb057d0
ID
486 */
487 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc.flags) &&
dddfb478 488 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc.flags)) {
3f787bd6 489 if (test_bit(DRIVER_REQUIRE_COPY_IV, &queue->rt2x00dev->flags))
9eb4e21e 490 rt2x00crypto_tx_copy_iv(skb, &txdesc);
dddfb478 491 else
9eb4e21e 492 rt2x00crypto_tx_remove_iv(skb, &txdesc);
dddfb478 493 }
2bb057d0 494
93354cbb
ID
495 /*
496 * When DMA allocation is required we should guarentee to the
497 * driver that the DMA is aligned to a 4-byte boundary.
93354cbb
ID
498 * However some drivers require L2 padding to pad the payload
499 * rather then the header. This could be a requirement for
500 * PCI and USB devices, while header alignment only is valid
501 * for PCI devices.
502 */
9f166171 503 if (test_bit(DRIVER_REQUIRE_L2PAD, &queue->rt2x00dev->flags))
daee6c09 504 rt2x00queue_insert_l2pad(entry->skb, txdesc.header_length);
93354cbb 505 else if (test_bit(DRIVER_REQUIRE_DMA, &queue->rt2x00dev->flags))
daee6c09 506 rt2x00queue_align_frame(entry->skb);
9f166171 507
2bb057d0
ID
508 /*
509 * It could be possible that the queue was corrupted and this
0e3de998
ID
510 * call failed. Since we always return NETDEV_TX_OK to mac80211,
511 * this frame will simply be dropped.
2bb057d0 512 */
41086693
HS
513 if (unlikely(queue->rt2x00dev->ops->lib->write_tx_data(entry,
514 &txdesc))) {
0262ab0d 515 clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
2bb057d0 516 entry->skb = NULL;
0e3de998 517 return -EIO;
6db3786a
ID
518 }
519
0262ab0d 520 set_bit(ENTRY_DATA_PENDING, &entry->flags);
6db3786a
ID
521
522 rt2x00queue_index_inc(queue, Q_INDEX);
523 rt2x00queue_write_tx_descriptor(entry, &txdesc);
6295d815 524 rt2x00queue_kick_tx_queue(entry, &txdesc);
6db3786a
ID
525
526 return 0;
527}
528
bd88a781 529int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev,
a2c9b652
ID
530 struct ieee80211_vif *vif,
531 const bool enable_beacon)
bd88a781
ID
532{
533 struct rt2x00_intf *intf = vif_to_intf(vif);
534 struct skb_frame_desc *skbdesc;
535 struct txentry_desc txdesc;
bd88a781
ID
536
537 if (unlikely(!intf->beacon))
538 return -ENOBUFS;
539
17512dc3
IP
540 mutex_lock(&intf->beacon_skb_mutex);
541
542 /*
543 * Clean up the beacon skb.
544 */
545 rt2x00queue_free_skb(rt2x00dev, intf->beacon->skb);
546 intf->beacon->skb = NULL;
547
a2c9b652
ID
548 if (!enable_beacon) {
549 rt2x00dev->ops->lib->kill_tx_queue(rt2x00dev, QID_BEACON);
17512dc3 550 mutex_unlock(&intf->beacon_skb_mutex);
a2c9b652
ID
551 return 0;
552 }
553
bd88a781 554 intf->beacon->skb = ieee80211_beacon_get(rt2x00dev->hw, vif);
17512dc3
IP
555 if (!intf->beacon->skb) {
556 mutex_unlock(&intf->beacon_skb_mutex);
bd88a781 557 return -ENOMEM;
17512dc3 558 }
bd88a781
ID
559
560 /*
561 * Copy all TX descriptor information into txdesc,
562 * after that we are free to use the skb->cb array
563 * for our information.
564 */
565 rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc);
566
bd88a781
ID
567 /*
568 * Fill in skb descriptor
569 */
570 skbdesc = get_skb_frame_desc(intf->beacon->skb);
571 memset(skbdesc, 0, sizeof(*skbdesc));
bd88a781
ID
572 skbdesc->entry = intf->beacon;
573
bd88a781 574 /*
d61cb266 575 * Send beacon to hardware and enable beacon genaration..
bd88a781 576 */
f224f4ef 577 rt2x00dev->ops->lib->write_beacon(intf->beacon, &txdesc);
bd88a781 578
17512dc3
IP
579 mutex_unlock(&intf->beacon_skb_mutex);
580
bd88a781
ID
581 return 0;
582}
583
181d6902 584struct data_queue *rt2x00queue_get_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 585 const enum data_queue_qid queue)
181d6902
ID
586{
587 int atim = test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
588
a2c9b652
ID
589 if (queue == QID_RX)
590 return rt2x00dev->rx;
591
61448f88 592 if (queue < rt2x00dev->ops->tx_queues && rt2x00dev->tx)
181d6902
ID
593 return &rt2x00dev->tx[queue];
594
595 if (!rt2x00dev->bcn)
596 return NULL;
597
e58c6aca 598 if (queue == QID_BEACON)
181d6902 599 return &rt2x00dev->bcn[0];
e58c6aca 600 else if (queue == QID_ATIM && atim)
181d6902
ID
601 return &rt2x00dev->bcn[1];
602
603 return NULL;
604}
605EXPORT_SYMBOL_GPL(rt2x00queue_get_queue);
606
607struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue,
608 enum queue_index index)
609{
610 struct queue_entry *entry;
5f46c4d0 611 unsigned long irqflags;
181d6902
ID
612
613 if (unlikely(index >= Q_INDEX_MAX)) {
614 ERROR(queue->rt2x00dev,
615 "Entry requested from invalid index type (%d)\n", index);
616 return NULL;
617 }
618
5f46c4d0 619 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
620
621 entry = &queue->entries[queue->index[index]];
622
5f46c4d0 623 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902
ID
624
625 return entry;
626}
627EXPORT_SYMBOL_GPL(rt2x00queue_get_entry);
628
629void rt2x00queue_index_inc(struct data_queue *queue, enum queue_index index)
630{
5f46c4d0
ID
631 unsigned long irqflags;
632
181d6902
ID
633 if (unlikely(index >= Q_INDEX_MAX)) {
634 ERROR(queue->rt2x00dev,
635 "Index change on invalid index type (%d)\n", index);
636 return;
637 }
638
5f46c4d0 639 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
640
641 queue->index[index]++;
642 if (queue->index[index] >= queue->limit)
643 queue->index[index] = 0;
644
10b6b801
ID
645 if (index == Q_INDEX) {
646 queue->length++;
647 } else if (index == Q_INDEX_DONE) {
648 queue->length--;
55887511 649 queue->count++;
10b6b801 650 }
181d6902 651
5f46c4d0 652 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902 653}
181d6902
ID
654
655static void rt2x00queue_reset(struct data_queue *queue)
656{
5f46c4d0
ID
657 unsigned long irqflags;
658
659 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
660
661 queue->count = 0;
662 queue->length = 0;
663 memset(queue->index, 0, sizeof(queue->index));
664
5f46c4d0 665 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902
ID
666}
667
a2c9b652
ID
668void rt2x00queue_stop_queues(struct rt2x00_dev *rt2x00dev)
669{
670 struct data_queue *queue;
671
672 txall_queue_for_each(rt2x00dev, queue)
673 rt2x00dev->ops->lib->kill_tx_queue(rt2x00dev, queue->qid);
674}
675
798b7adb 676void rt2x00queue_init_queues(struct rt2x00_dev *rt2x00dev)
181d6902
ID
677{
678 struct data_queue *queue;
679 unsigned int i;
680
798b7adb 681 queue_for_each(rt2x00dev, queue) {
181d6902
ID
682 rt2x00queue_reset(queue);
683
9c0ab712
ID
684 for (i = 0; i < queue->limit; i++) {
685 queue->entries[i].flags = 0;
686
798b7adb 687 rt2x00dev->ops->lib->clear_entry(&queue->entries[i]);
9c0ab712 688 }
181d6902
ID
689 }
690}
691
692static int rt2x00queue_alloc_entries(struct data_queue *queue,
693 const struct data_queue_desc *qdesc)
694{
695 struct queue_entry *entries;
696 unsigned int entry_size;
697 unsigned int i;
698
699 rt2x00queue_reset(queue);
700
701 queue->limit = qdesc->entry_num;
b869767b 702 queue->threshold = DIV_ROUND_UP(qdesc->entry_num, 10);
181d6902
ID
703 queue->data_size = qdesc->data_size;
704 queue->desc_size = qdesc->desc_size;
705
706 /*
707 * Allocate all queue entries.
708 */
709 entry_size = sizeof(*entries) + qdesc->priv_size;
710 entries = kzalloc(queue->limit * entry_size, GFP_KERNEL);
711 if (!entries)
712 return -ENOMEM;
713
714#define QUEUE_ENTRY_PRIV_OFFSET(__base, __index, __limit, __esize, __psize) \
231be4e9
AB
715 ( ((char *)(__base)) + ((__limit) * (__esize)) + \
716 ((__index) * (__psize)) )
181d6902
ID
717
718 for (i = 0; i < queue->limit; i++) {
719 entries[i].flags = 0;
720 entries[i].queue = queue;
721 entries[i].skb = NULL;
722 entries[i].entry_idx = i;
723 entries[i].priv_data =
724 QUEUE_ENTRY_PRIV_OFFSET(entries, i, queue->limit,
725 sizeof(*entries), qdesc->priv_size);
726 }
727
728#undef QUEUE_ENTRY_PRIV_OFFSET
729
730 queue->entries = entries;
731
732 return 0;
733}
734
c4da0048
GW
735static void rt2x00queue_free_skbs(struct rt2x00_dev *rt2x00dev,
736 struct data_queue *queue)
30caa6e3
GW
737{
738 unsigned int i;
739
740 if (!queue->entries)
741 return;
742
743 for (i = 0; i < queue->limit; i++) {
744 if (queue->entries[i].skb)
c4da0048 745 rt2x00queue_free_skb(rt2x00dev, queue->entries[i].skb);
30caa6e3
GW
746 }
747}
748
c4da0048
GW
749static int rt2x00queue_alloc_rxskbs(struct rt2x00_dev *rt2x00dev,
750 struct data_queue *queue)
30caa6e3
GW
751{
752 unsigned int i;
753 struct sk_buff *skb;
754
755 for (i = 0; i < queue->limit; i++) {
c4da0048 756 skb = rt2x00queue_alloc_rxskb(rt2x00dev, &queue->entries[i]);
30caa6e3 757 if (!skb)
61243d8e 758 return -ENOMEM;
30caa6e3
GW
759 queue->entries[i].skb = skb;
760 }
761
762 return 0;
30caa6e3
GW
763}
764
181d6902
ID
765int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev)
766{
767 struct data_queue *queue;
768 int status;
769
181d6902
ID
770 status = rt2x00queue_alloc_entries(rt2x00dev->rx, rt2x00dev->ops->rx);
771 if (status)
772 goto exit;
773
774 tx_queue_for_each(rt2x00dev, queue) {
775 status = rt2x00queue_alloc_entries(queue, rt2x00dev->ops->tx);
776 if (status)
777 goto exit;
778 }
779
780 status = rt2x00queue_alloc_entries(rt2x00dev->bcn, rt2x00dev->ops->bcn);
781 if (status)
782 goto exit;
783
30caa6e3
GW
784 if (test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags)) {
785 status = rt2x00queue_alloc_entries(&rt2x00dev->bcn[1],
786 rt2x00dev->ops->atim);
787 if (status)
788 goto exit;
789 }
181d6902 790
c4da0048 791 status = rt2x00queue_alloc_rxskbs(rt2x00dev, rt2x00dev->rx);
181d6902
ID
792 if (status)
793 goto exit;
794
795 return 0;
796
797exit:
798 ERROR(rt2x00dev, "Queue entries allocation failed.\n");
799
800 rt2x00queue_uninitialize(rt2x00dev);
801
802 return status;
803}
804
805void rt2x00queue_uninitialize(struct rt2x00_dev *rt2x00dev)
806{
807 struct data_queue *queue;
808
c4da0048 809 rt2x00queue_free_skbs(rt2x00dev, rt2x00dev->rx);
30caa6e3 810
181d6902
ID
811 queue_for_each(rt2x00dev, queue) {
812 kfree(queue->entries);
813 queue->entries = NULL;
814 }
815}
816
8f539276
ID
817static void rt2x00queue_init(struct rt2x00_dev *rt2x00dev,
818 struct data_queue *queue, enum data_queue_qid qid)
819{
820 spin_lock_init(&queue->lock);
821
822 queue->rt2x00dev = rt2x00dev;
823 queue->qid = qid;
2af0a570 824 queue->txop = 0;
8f539276
ID
825 queue->aifs = 2;
826 queue->cw_min = 5;
827 queue->cw_max = 10;
828}
829
181d6902
ID
830int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
831{
832 struct data_queue *queue;
833 enum data_queue_qid qid;
834 unsigned int req_atim =
835 !!test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
836
837 /*
838 * We need the following queues:
839 * RX: 1
61448f88 840 * TX: ops->tx_queues
181d6902
ID
841 * Beacon: 1
842 * Atim: 1 (if required)
843 */
61448f88 844 rt2x00dev->data_queues = 2 + rt2x00dev->ops->tx_queues + req_atim;
181d6902
ID
845
846 queue = kzalloc(rt2x00dev->data_queues * sizeof(*queue), GFP_KERNEL);
847 if (!queue) {
848 ERROR(rt2x00dev, "Queue allocation failed.\n");
849 return -ENOMEM;
850 }
851
852 /*
853 * Initialize pointers
854 */
855 rt2x00dev->rx = queue;
856 rt2x00dev->tx = &queue[1];
61448f88 857 rt2x00dev->bcn = &queue[1 + rt2x00dev->ops->tx_queues];
181d6902
ID
858
859 /*
860 * Initialize queue parameters.
861 * RX: qid = QID_RX
862 * TX: qid = QID_AC_BE + index
863 * TX: cw_min: 2^5 = 32.
864 * TX: cw_max: 2^10 = 1024.
565a019a
ID
865 * BCN: qid = QID_BEACON
866 * ATIM: qid = QID_ATIM
181d6902 867 */
8f539276 868 rt2x00queue_init(rt2x00dev, rt2x00dev->rx, QID_RX);
181d6902 869
8f539276
ID
870 qid = QID_AC_BE;
871 tx_queue_for_each(rt2x00dev, queue)
872 rt2x00queue_init(rt2x00dev, queue, qid++);
181d6902 873
565a019a 874 rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[0], QID_BEACON);
181d6902 875 if (req_atim)
565a019a 876 rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[1], QID_ATIM);
181d6902
ID
877
878 return 0;
879}
880
881void rt2x00queue_free(struct rt2x00_dev *rt2x00dev)
882{
883 kfree(rt2x00dev->rx);
884 rt2x00dev->rx = NULL;
885 rt2x00dev->tx = NULL;
886 rt2x00dev->bcn = NULL;
887}
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