Commit | Line | Data |
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181d6902 ID |
1 | /* |
2 | Copyright (C) 2004 - 2008 rt2x00 SourceForge Project | |
3 | <http://rt2x00.serialmonkey.com> | |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the | |
17 | Free Software Foundation, Inc., | |
18 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | */ | |
20 | ||
21 | /* | |
22 | Module: rt2x00lib | |
23 | Abstract: rt2x00 queue specific routines. | |
24 | */ | |
25 | ||
26 | #include <linux/kernel.h> | |
27 | #include <linux/module.h> | |
28 | ||
29 | #include "rt2x00.h" | |
30 | #include "rt2x00lib.h" | |
31 | ||
7050ec82 | 32 | void rt2x00queue_create_tx_descriptor(struct queue_entry *entry, |
e039fa4a | 33 | struct txentry_desc *txdesc) |
7050ec82 | 34 | { |
2e92e6f2 | 35 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; |
e039fa4a | 36 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb); |
7050ec82 | 37 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data; |
2e92e6f2 | 38 | struct ieee80211_rate *rate = |
e039fa4a | 39 | ieee80211_get_tx_rate(rt2x00dev->hw, tx_info); |
7050ec82 ID |
40 | const struct rt2x00_rate *hwrate; |
41 | unsigned int data_length; | |
42 | unsigned int duration; | |
43 | unsigned int residual; | |
44 | u16 frame_control; | |
45 | ||
46 | memset(txdesc, 0, sizeof(*txdesc)); | |
47 | ||
48 | /* | |
49 | * Initialize information from queue | |
50 | */ | |
51 | txdesc->queue = entry->queue->qid; | |
52 | txdesc->cw_min = entry->queue->cw_min; | |
53 | txdesc->cw_max = entry->queue->cw_max; | |
54 | txdesc->aifs = entry->queue->aifs; | |
55 | ||
56 | /* Data length should be extended with 4 bytes for CRC */ | |
57 | data_length = entry->skb->len + 4; | |
58 | ||
59 | /* | |
60 | * Read required fields from ieee80211 header. | |
61 | */ | |
62 | frame_control = le16_to_cpu(hdr->frame_control); | |
63 | ||
64 | /* | |
65 | * Check whether this frame is to be acked. | |
66 | */ | |
e039fa4a | 67 | if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK)) |
7050ec82 ID |
68 | __set_bit(ENTRY_TXD_ACK, &txdesc->flags); |
69 | ||
70 | /* | |
71 | * Check if this is a RTS/CTS frame | |
72 | */ | |
73 | if (is_rts_frame(frame_control) || is_cts_frame(frame_control)) { | |
74 | __set_bit(ENTRY_TXD_BURST, &txdesc->flags); | |
e039fa4a | 75 | if (is_rts_frame(frame_control)) |
7050ec82 | 76 | __set_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags); |
e039fa4a | 77 | else |
7050ec82 | 78 | __set_bit(ENTRY_TXD_CTS_FRAME, &txdesc->flags); |
e039fa4a | 79 | if (tx_info->control.rts_cts_rate_idx >= 0) |
2e92e6f2 | 80 | rate = |
e039fa4a | 81 | ieee80211_get_rts_cts_rate(rt2x00dev->hw, tx_info); |
7050ec82 ID |
82 | } |
83 | ||
84 | /* | |
85 | * Determine retry information. | |
86 | */ | |
e039fa4a JB |
87 | txdesc->retry_limit = tx_info->control.retry_limit; |
88 | if (tx_info->flags & IEEE80211_TX_CTL_LONG_RETRY_LIMIT) | |
7050ec82 ID |
89 | __set_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags); |
90 | ||
91 | /* | |
92 | * Check if more fragments are pending | |
93 | */ | |
94 | if (ieee80211_get_morefrag(hdr)) { | |
95 | __set_bit(ENTRY_TXD_BURST, &txdesc->flags); | |
96 | __set_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags); | |
97 | } | |
98 | ||
99 | /* | |
100 | * Beacons and probe responses require the tsf timestamp | |
101 | * to be inserted into the frame. | |
102 | */ | |
103 | if (txdesc->queue == QID_BEACON || is_probe_resp(frame_control)) | |
104 | __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags); | |
105 | ||
106 | /* | |
107 | * Determine with what IFS priority this frame should be send. | |
108 | * Set ifs to IFS_SIFS when the this is not the first fragment, | |
109 | * or this fragment came after RTS/CTS. | |
110 | */ | |
111 | if (test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)) { | |
112 | txdesc->ifs = IFS_SIFS; | |
e039fa4a | 113 | } else if (tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) { |
7050ec82 ID |
114 | __set_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags); |
115 | txdesc->ifs = IFS_BACKOFF; | |
116 | } else { | |
117 | txdesc->ifs = IFS_SIFS; | |
118 | } | |
119 | ||
120 | /* | |
121 | * PLCP setup | |
122 | * Length calculation depends on OFDM/CCK rate. | |
123 | */ | |
124 | hwrate = rt2x00_get_rate(rate->hw_value); | |
125 | txdesc->signal = hwrate->plcp; | |
126 | txdesc->service = 0x04; | |
127 | ||
128 | if (hwrate->flags & DEV_RATE_OFDM) { | |
129 | __set_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags); | |
130 | ||
131 | txdesc->length_high = (data_length >> 6) & 0x3f; | |
132 | txdesc->length_low = data_length & 0x3f; | |
133 | } else { | |
134 | /* | |
135 | * Convert length to microseconds. | |
136 | */ | |
137 | residual = get_duration_res(data_length, hwrate->bitrate); | |
138 | duration = get_duration(data_length, hwrate->bitrate); | |
139 | ||
140 | if (residual != 0) { | |
141 | duration++; | |
142 | ||
143 | /* | |
144 | * Check if we need to set the Length Extension | |
145 | */ | |
146 | if (hwrate->bitrate == 110 && residual <= 30) | |
147 | txdesc->service |= 0x80; | |
148 | } | |
149 | ||
150 | txdesc->length_high = (duration >> 8) & 0xff; | |
151 | txdesc->length_low = duration & 0xff; | |
152 | ||
153 | /* | |
154 | * When preamble is enabled we should set the | |
155 | * preamble bit for the signal. | |
156 | */ | |
157 | if (rt2x00_get_rate_preamble(rate->hw_value)) | |
158 | txdesc->signal |= 0x08; | |
159 | } | |
160 | } | |
161 | EXPORT_SYMBOL_GPL(rt2x00queue_create_tx_descriptor); | |
162 | ||
163 | void rt2x00queue_write_tx_descriptor(struct queue_entry *entry, | |
164 | struct txentry_desc *txdesc) | |
165 | { | |
166 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; | |
167 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); | |
168 | ||
169 | rt2x00dev->ops->lib->write_tx_desc(rt2x00dev, entry->skb, txdesc); | |
170 | ||
171 | /* | |
172 | * All processing on the frame has been completed, this means | |
173 | * it is now ready to be dumped to userspace through debugfs. | |
174 | */ | |
175 | rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_TX, entry->skb); | |
176 | ||
177 | /* | |
178 | * We are done writing the frame to the queue entry, | |
e039fa4a JB |
179 | * also kick the queue in case the correct flags are set, |
180 | * note that this will automatically filter beacons and | |
181 | * RTS/CTS frames since those frames don't have this flag | |
182 | * set. | |
7050ec82 ID |
183 | */ |
184 | if (rt2x00dev->ops->lib->kick_tx_queue && | |
185 | !(skbdesc->flags & FRAME_DESC_DRIVER_GENERATED)) | |
186 | rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, | |
187 | entry->queue->qid); | |
188 | } | |
189 | EXPORT_SYMBOL_GPL(rt2x00queue_write_tx_descriptor); | |
190 | ||
181d6902 | 191 | struct data_queue *rt2x00queue_get_queue(struct rt2x00_dev *rt2x00dev, |
e58c6aca | 192 | const enum data_queue_qid queue) |
181d6902 ID |
193 | { |
194 | int atim = test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags); | |
195 | ||
61448f88 | 196 | if (queue < rt2x00dev->ops->tx_queues && rt2x00dev->tx) |
181d6902 ID |
197 | return &rt2x00dev->tx[queue]; |
198 | ||
199 | if (!rt2x00dev->bcn) | |
200 | return NULL; | |
201 | ||
e58c6aca | 202 | if (queue == QID_BEACON) |
181d6902 | 203 | return &rt2x00dev->bcn[0]; |
e58c6aca | 204 | else if (queue == QID_ATIM && atim) |
181d6902 ID |
205 | return &rt2x00dev->bcn[1]; |
206 | ||
207 | return NULL; | |
208 | } | |
209 | EXPORT_SYMBOL_GPL(rt2x00queue_get_queue); | |
210 | ||
211 | struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue, | |
212 | enum queue_index index) | |
213 | { | |
214 | struct queue_entry *entry; | |
5f46c4d0 | 215 | unsigned long irqflags; |
181d6902 ID |
216 | |
217 | if (unlikely(index >= Q_INDEX_MAX)) { | |
218 | ERROR(queue->rt2x00dev, | |
219 | "Entry requested from invalid index type (%d)\n", index); | |
220 | return NULL; | |
221 | } | |
222 | ||
5f46c4d0 | 223 | spin_lock_irqsave(&queue->lock, irqflags); |
181d6902 ID |
224 | |
225 | entry = &queue->entries[queue->index[index]]; | |
226 | ||
5f46c4d0 | 227 | spin_unlock_irqrestore(&queue->lock, irqflags); |
181d6902 ID |
228 | |
229 | return entry; | |
230 | } | |
231 | EXPORT_SYMBOL_GPL(rt2x00queue_get_entry); | |
232 | ||
233 | void rt2x00queue_index_inc(struct data_queue *queue, enum queue_index index) | |
234 | { | |
5f46c4d0 ID |
235 | unsigned long irqflags; |
236 | ||
181d6902 ID |
237 | if (unlikely(index >= Q_INDEX_MAX)) { |
238 | ERROR(queue->rt2x00dev, | |
239 | "Index change on invalid index type (%d)\n", index); | |
240 | return; | |
241 | } | |
242 | ||
5f46c4d0 | 243 | spin_lock_irqsave(&queue->lock, irqflags); |
181d6902 ID |
244 | |
245 | queue->index[index]++; | |
246 | if (queue->index[index] >= queue->limit) | |
247 | queue->index[index] = 0; | |
248 | ||
10b6b801 ID |
249 | if (index == Q_INDEX) { |
250 | queue->length++; | |
251 | } else if (index == Q_INDEX_DONE) { | |
252 | queue->length--; | |
253 | queue->count ++; | |
254 | } | |
181d6902 | 255 | |
5f46c4d0 | 256 | spin_unlock_irqrestore(&queue->lock, irqflags); |
181d6902 ID |
257 | } |
258 | EXPORT_SYMBOL_GPL(rt2x00queue_index_inc); | |
259 | ||
260 | static void rt2x00queue_reset(struct data_queue *queue) | |
261 | { | |
5f46c4d0 ID |
262 | unsigned long irqflags; |
263 | ||
264 | spin_lock_irqsave(&queue->lock, irqflags); | |
181d6902 ID |
265 | |
266 | queue->count = 0; | |
267 | queue->length = 0; | |
268 | memset(queue->index, 0, sizeof(queue->index)); | |
269 | ||
5f46c4d0 | 270 | spin_unlock_irqrestore(&queue->lock, irqflags); |
181d6902 ID |
271 | } |
272 | ||
273 | void rt2x00queue_init_rx(struct rt2x00_dev *rt2x00dev) | |
274 | { | |
275 | struct data_queue *queue = rt2x00dev->rx; | |
276 | unsigned int i; | |
277 | ||
278 | rt2x00queue_reset(queue); | |
279 | ||
280 | if (!rt2x00dev->ops->lib->init_rxentry) | |
281 | return; | |
282 | ||
283 | for (i = 0; i < queue->limit; i++) | |
284 | rt2x00dev->ops->lib->init_rxentry(rt2x00dev, | |
285 | &queue->entries[i]); | |
286 | } | |
287 | ||
288 | void rt2x00queue_init_tx(struct rt2x00_dev *rt2x00dev) | |
289 | { | |
290 | struct data_queue *queue; | |
291 | unsigned int i; | |
292 | ||
293 | txall_queue_for_each(rt2x00dev, queue) { | |
294 | rt2x00queue_reset(queue); | |
295 | ||
296 | if (!rt2x00dev->ops->lib->init_txentry) | |
297 | continue; | |
298 | ||
299 | for (i = 0; i < queue->limit; i++) | |
300 | rt2x00dev->ops->lib->init_txentry(rt2x00dev, | |
301 | &queue->entries[i]); | |
302 | } | |
303 | } | |
304 | ||
305 | static int rt2x00queue_alloc_entries(struct data_queue *queue, | |
306 | const struct data_queue_desc *qdesc) | |
307 | { | |
308 | struct queue_entry *entries; | |
309 | unsigned int entry_size; | |
310 | unsigned int i; | |
311 | ||
312 | rt2x00queue_reset(queue); | |
313 | ||
314 | queue->limit = qdesc->entry_num; | |
315 | queue->data_size = qdesc->data_size; | |
316 | queue->desc_size = qdesc->desc_size; | |
317 | ||
318 | /* | |
319 | * Allocate all queue entries. | |
320 | */ | |
321 | entry_size = sizeof(*entries) + qdesc->priv_size; | |
322 | entries = kzalloc(queue->limit * entry_size, GFP_KERNEL); | |
323 | if (!entries) | |
324 | return -ENOMEM; | |
325 | ||
326 | #define QUEUE_ENTRY_PRIV_OFFSET(__base, __index, __limit, __esize, __psize) \ | |
231be4e9 AB |
327 | ( ((char *)(__base)) + ((__limit) * (__esize)) + \ |
328 | ((__index) * (__psize)) ) | |
181d6902 ID |
329 | |
330 | for (i = 0; i < queue->limit; i++) { | |
331 | entries[i].flags = 0; | |
332 | entries[i].queue = queue; | |
333 | entries[i].skb = NULL; | |
334 | entries[i].entry_idx = i; | |
335 | entries[i].priv_data = | |
336 | QUEUE_ENTRY_PRIV_OFFSET(entries, i, queue->limit, | |
337 | sizeof(*entries), qdesc->priv_size); | |
338 | } | |
339 | ||
340 | #undef QUEUE_ENTRY_PRIV_OFFSET | |
341 | ||
342 | queue->entries = entries; | |
343 | ||
344 | return 0; | |
345 | } | |
346 | ||
347 | int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev) | |
348 | { | |
349 | struct data_queue *queue; | |
350 | int status; | |
351 | ||
352 | ||
353 | status = rt2x00queue_alloc_entries(rt2x00dev->rx, rt2x00dev->ops->rx); | |
354 | if (status) | |
355 | goto exit; | |
356 | ||
357 | tx_queue_for_each(rt2x00dev, queue) { | |
358 | status = rt2x00queue_alloc_entries(queue, rt2x00dev->ops->tx); | |
359 | if (status) | |
360 | goto exit; | |
361 | } | |
362 | ||
363 | status = rt2x00queue_alloc_entries(rt2x00dev->bcn, rt2x00dev->ops->bcn); | |
364 | if (status) | |
365 | goto exit; | |
366 | ||
367 | if (!test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags)) | |
368 | return 0; | |
369 | ||
370 | status = rt2x00queue_alloc_entries(&rt2x00dev->bcn[1], | |
371 | rt2x00dev->ops->atim); | |
372 | if (status) | |
373 | goto exit; | |
374 | ||
375 | return 0; | |
376 | ||
377 | exit: | |
378 | ERROR(rt2x00dev, "Queue entries allocation failed.\n"); | |
379 | ||
380 | rt2x00queue_uninitialize(rt2x00dev); | |
381 | ||
382 | return status; | |
383 | } | |
384 | ||
385 | void rt2x00queue_uninitialize(struct rt2x00_dev *rt2x00dev) | |
386 | { | |
387 | struct data_queue *queue; | |
388 | ||
389 | queue_for_each(rt2x00dev, queue) { | |
390 | kfree(queue->entries); | |
391 | queue->entries = NULL; | |
392 | } | |
393 | } | |
394 | ||
8f539276 ID |
395 | static void rt2x00queue_init(struct rt2x00_dev *rt2x00dev, |
396 | struct data_queue *queue, enum data_queue_qid qid) | |
397 | { | |
398 | spin_lock_init(&queue->lock); | |
399 | ||
400 | queue->rt2x00dev = rt2x00dev; | |
401 | queue->qid = qid; | |
402 | queue->aifs = 2; | |
403 | queue->cw_min = 5; | |
404 | queue->cw_max = 10; | |
405 | } | |
406 | ||
181d6902 ID |
407 | int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev) |
408 | { | |
409 | struct data_queue *queue; | |
410 | enum data_queue_qid qid; | |
411 | unsigned int req_atim = | |
412 | !!test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags); | |
413 | ||
414 | /* | |
415 | * We need the following queues: | |
416 | * RX: 1 | |
61448f88 | 417 | * TX: ops->tx_queues |
181d6902 ID |
418 | * Beacon: 1 |
419 | * Atim: 1 (if required) | |
420 | */ | |
61448f88 | 421 | rt2x00dev->data_queues = 2 + rt2x00dev->ops->tx_queues + req_atim; |
181d6902 ID |
422 | |
423 | queue = kzalloc(rt2x00dev->data_queues * sizeof(*queue), GFP_KERNEL); | |
424 | if (!queue) { | |
425 | ERROR(rt2x00dev, "Queue allocation failed.\n"); | |
426 | return -ENOMEM; | |
427 | } | |
428 | ||
429 | /* | |
430 | * Initialize pointers | |
431 | */ | |
432 | rt2x00dev->rx = queue; | |
433 | rt2x00dev->tx = &queue[1]; | |
61448f88 | 434 | rt2x00dev->bcn = &queue[1 + rt2x00dev->ops->tx_queues]; |
181d6902 ID |
435 | |
436 | /* | |
437 | * Initialize queue parameters. | |
438 | * RX: qid = QID_RX | |
439 | * TX: qid = QID_AC_BE + index | |
440 | * TX: cw_min: 2^5 = 32. | |
441 | * TX: cw_max: 2^10 = 1024. | |
565a019a ID |
442 | * BCN: qid = QID_BEACON |
443 | * ATIM: qid = QID_ATIM | |
181d6902 | 444 | */ |
8f539276 | 445 | rt2x00queue_init(rt2x00dev, rt2x00dev->rx, QID_RX); |
181d6902 | 446 | |
8f539276 ID |
447 | qid = QID_AC_BE; |
448 | tx_queue_for_each(rt2x00dev, queue) | |
449 | rt2x00queue_init(rt2x00dev, queue, qid++); | |
181d6902 | 450 | |
565a019a | 451 | rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[0], QID_BEACON); |
181d6902 | 452 | if (req_atim) |
565a019a | 453 | rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[1], QID_ATIM); |
181d6902 ID |
454 | |
455 | return 0; | |
456 | } | |
457 | ||
458 | void rt2x00queue_free(struct rt2x00_dev *rt2x00dev) | |
459 | { | |
460 | kfree(rt2x00dev->rx); | |
461 | rt2x00dev->rx = NULL; | |
462 | rt2x00dev->tx = NULL; | |
463 | rt2x00dev->bcn = NULL; | |
464 | } |