rt2800usb: read TX_STA_FIFO asynchronously
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2x00queue.h
CommitLineData
181d6902 1/*
7e613e16 2 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
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3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2x00
23 Abstract: rt2x00 queue datastructures and routines
24 */
25
26#ifndef RT2X00QUEUE_H
27#define RT2X00QUEUE_H
28
29#include <linux/prefetch.h>
30
31/**
49513481 32 * DOC: Entry frame size
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33 *
34 * Ralink PCI devices demand the Frame size to be a multiple of 128 bytes,
35 * for USB devices this restriction does not apply, but the value of
36 * 2432 makes sense since it is big enough to contain the maximum fragment
37 * size according to the ieee802.11 specs.
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38 * The aggregation size depends on support from the driver, but should
39 * be something around 3840 bytes.
181d6902 40 */
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41#define DATA_FRAME_SIZE 2432
42#define MGMT_FRAME_SIZE 256
43#define AGGREGATION_SIZE 3840
181d6902 44
181d6902
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45/**
46 * enum data_queue_qid: Queue identification
e58c6aca 47 *
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48 * @QID_AC_VO: AC VO queue
49 * @QID_AC_VI: AC VI queue
e58c6aca
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50 * @QID_AC_BE: AC BE queue
51 * @QID_AC_BK: AC BK queue
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52 * @QID_HCCA: HCCA queue
53 * @QID_MGMT: MGMT queue (prio queue)
54 * @QID_RX: RX queue
55 * @QID_OTHER: None of the above (don't use, only present for completeness)
56 * @QID_BEACON: Beacon queue (value unspecified, don't send it to device)
57 * @QID_ATIM: Atim queue (value unspeficied, don't send it to device)
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58 */
59enum data_queue_qid {
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60 QID_AC_VO = 0,
61 QID_AC_VI = 1,
62 QID_AC_BE = 2,
63 QID_AC_BK = 3,
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64 QID_HCCA = 4,
65 QID_MGMT = 13,
66 QID_RX = 14,
67 QID_OTHER = 15,
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68 QID_BEACON,
69 QID_ATIM,
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70};
71
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72/**
73 * enum skb_frame_desc_flags: Flags for &struct skb_frame_desc
74 *
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75 * @SKBDESC_DMA_MAPPED_RX: &skb_dma field has been mapped for RX
76 * @SKBDESC_DMA_MAPPED_TX: &skb_dma field has been mapped for TX
9f166171 77 * @SKBDESC_IV_STRIPPED: Frame contained a IV/EIV provided by
2bb057d0 78 * mac80211 but was stripped for processing by the driver.
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JB
79 * @SKBDESC_NOT_MAC80211: Frame didn't originate from mac80211,
80 * don't try to pass it back.
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GW
81 * @SKBDESC_DESC_IN_SKB: The descriptor is at the start of the
82 * skb, instead of in the desc field.
baf26a7e 83 */
c4da0048 84enum skb_frame_desc_flags {
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85 SKBDESC_DMA_MAPPED_RX = 1 << 0,
86 SKBDESC_DMA_MAPPED_TX = 1 << 1,
9f166171 87 SKBDESC_IV_STRIPPED = 1 << 2,
354e39db 88 SKBDESC_NOT_MAC80211 = 1 << 3,
fd76f148 89 SKBDESC_DESC_IN_SKB = 1 << 4,
c4da0048 90};
baf26a7e 91
181d6902
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92/**
93 * struct skb_frame_desc: Descriptor information for the skb buffer
94 *
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JB
95 * This structure is placed over the driver_data array, this means that
96 * this structure should not exceed the size of that array (40 bytes).
181d6902 97 *
baf26a7e 98 * @flags: Frame flags, see &enum skb_frame_desc_flags.
c4da0048 99 * @desc_len: Length of the frame descriptor.
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100 * @tx_rate_idx: the index of the TX rate, used for TX status reporting
101 * @tx_rate_flags: the TX rate flags, used for TX status reporting
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102 * @desc: Pointer to descriptor part of the frame.
103 * Note that this pointer could point to something outside
104 * of the scope of the skb->data pointer.
1ce9cdac 105 * @iv: IV/EIV data used during encryption/decryption.
c4da0048 106 * @skb_dma: (PCI-only) the DMA address associated with the sk buffer.
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107 * @entry: The entry to which this sk buffer belongs.
108 */
109struct skb_frame_desc {
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JB
110 u8 flags;
111
112 u8 desc_len;
113 u8 tx_rate_idx;
114 u8 tx_rate_flags;
181d6902 115
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GW
116 void *desc;
117
1ce9cdac 118 __le32 iv[2];
2bb057d0 119
c4da0048 120 dma_addr_t skb_dma;
181d6902 121
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122 struct queue_entry *entry;
123};
124
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125/**
126 * get_skb_frame_desc - Obtain the rt2x00 frame descriptor from a sk_buff.
127 * @skb: &struct sk_buff from where we obtain the &struct skb_frame_desc
128 */
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129static inline struct skb_frame_desc* get_skb_frame_desc(struct sk_buff *skb)
130{
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JB
131 BUILD_BUG_ON(sizeof(struct skb_frame_desc) >
132 IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
133 return (struct skb_frame_desc *)&IEEE80211_SKB_CB(skb)->driver_data;
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134}
135
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136/**
137 * enum rxdone_entry_desc_flags: Flags for &struct rxdone_entry_desc
138 *
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139 * @RXDONE_SIGNAL_PLCP: Signal field contains the plcp value.
140 * @RXDONE_SIGNAL_BITRATE: Signal field contains the bitrate value.
35f00cfc 141 * @RXDONE_SIGNAL_MCS: Signal field contains the mcs value.
19d30e02 142 * @RXDONE_MY_BSS: Does this frame originate from device's BSS.
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143 * @RXDONE_CRYPTO_IV: Driver provided IV/EIV data.
144 * @RXDONE_CRYPTO_ICV: Driver provided ICV data.
9f166171 145 * @RXDONE_L2PAD: 802.11 payload has been padded to 4-byte boundary.
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146 */
147enum rxdone_entry_desc_flags {
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148 RXDONE_SIGNAL_PLCP = BIT(0),
149 RXDONE_SIGNAL_BITRATE = BIT(1),
150 RXDONE_SIGNAL_MCS = BIT(2),
151 RXDONE_MY_BSS = BIT(3),
152 RXDONE_CRYPTO_IV = BIT(4),
153 RXDONE_CRYPTO_ICV = BIT(5),
154 RXDONE_L2PAD = BIT(6),
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155};
156
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157/**
158 * RXDONE_SIGNAL_MASK - Define to mask off all &rxdone_entry_desc_flags flags
159 * except for the RXDONE_SIGNAL_* flags. This is useful to convert the dev_flags
160 * from &rxdone_entry_desc to a signal value type.
161 */
162#define RXDONE_SIGNAL_MASK \
35f00cfc 163 ( RXDONE_SIGNAL_PLCP | RXDONE_SIGNAL_BITRATE | RXDONE_SIGNAL_MCS )
b30dd5c0 164
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165/**
166 * struct rxdone_entry_desc: RX Entry descriptor
167 *
168 * Summary of information that has been read from the RX frame descriptor.
169 *
ae73e58e 170 * @timestamp: RX Timestamp
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171 * @signal: Signal of the received frame.
172 * @rssi: RSSI of the received frame.
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173 * @size: Data size of the received frame.
174 * @flags: MAC80211 receive flags (See &enum mac80211_rx_flags).
19d30e02 175 * @dev_flags: Ralink receive flags (See &enum rxdone_entry_desc_flags).
35f00cfc 176 * @rate_mode: Rate mode (See @enum rate_modulation).
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177 * @cipher: Cipher type used during decryption.
178 * @cipher_status: Decryption status.
1ce9cdac 179 * @iv: IV/EIV data used during decryption.
2bb057d0 180 * @icv: ICV data used during decryption.
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181 */
182struct rxdone_entry_desc {
ae73e58e 183 u64 timestamp;
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184 int signal;
185 int rssi;
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186 int size;
187 int flags;
19d30e02 188 int dev_flags;
35f00cfc 189 u16 rate_mode;
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190 u8 cipher;
191 u8 cipher_status;
192
1ce9cdac 193 __le32 iv[2];
2bb057d0 194 __le32 icv;
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195};
196
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197/**
198 * enum txdone_entry_desc_flags: Flags for &struct txdone_entry_desc
199 *
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HS
200 * Every txdone report has to contain the basic result of the
201 * transmission, either &TXDONE_UNKNOWN, &TXDONE_SUCCESS or
202 * &TXDONE_FAILURE. The flag &TXDONE_FALLBACK can be used in
203 * conjunction with all of these flags but should only be set
204 * if retires > 0. The flag &TXDONE_EXCESSIVE_RETRY can only be used
205 * in conjunction with &TXDONE_FAILURE.
206 *
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207 * @TXDONE_UNKNOWN: Hardware could not determine success of transmission.
208 * @TXDONE_SUCCESS: Frame was successfully send
46678b19 209 * @TXDONE_FALLBACK: Hardware used fallback rates for retries
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210 * @TXDONE_FAILURE: Frame was not successfully send
211 * @TXDONE_EXCESSIVE_RETRY: In addition to &TXDONE_FAILURE, the
212 * frame transmission failed due to excessive retries.
213 */
214enum txdone_entry_desc_flags {
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215 TXDONE_UNKNOWN,
216 TXDONE_SUCCESS,
92ed48e5 217 TXDONE_FALLBACK,
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218 TXDONE_FAILURE,
219 TXDONE_EXCESSIVE_RETRY,
f16d2db7 220 TXDONE_AMPDU,
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ID
221};
222
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223/**
224 * struct txdone_entry_desc: TX done entry descriptor
225 *
226 * Summary of information that has been read from the TX frame descriptor
227 * after the device is done with transmission.
228 *
fb55f4d1 229 * @flags: TX done flags (See &enum txdone_entry_desc_flags).
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230 * @retry: Retry count.
231 */
232struct txdone_entry_desc {
fb55f4d1 233 unsigned long flags;
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234 int retry;
235};
236
237/**
238 * enum txentry_desc_flags: Status flags for TX entry descriptor
239 *
240 * @ENTRY_TXD_RTS_FRAME: This frame is a RTS frame.
7050ec82 241 * @ENTRY_TXD_CTS_FRAME: This frame is a CTS-to-self frame.
5adf6d63 242 * @ENTRY_TXD_GENERATE_SEQ: This frame requires sequence counter.
61486e0f 243 * @ENTRY_TXD_FIRST_FRAGMENT: This is the first frame.
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244 * @ENTRY_TXD_MORE_FRAG: This frame is followed by another fragment.
245 * @ENTRY_TXD_REQ_TIMESTAMP: Require timestamp to be inserted.
246 * @ENTRY_TXD_BURST: This frame belongs to the same burst event.
247 * @ENTRY_TXD_ACK: An ACK is required for this frame.
61486e0f 248 * @ENTRY_TXD_RETRY_MODE: When set, the long retry count is used.
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249 * @ENTRY_TXD_ENCRYPT: This frame should be encrypted.
250 * @ENTRY_TXD_ENCRYPT_PAIRWISE: Use pairwise key table (instead of shared).
251 * @ENTRY_TXD_ENCRYPT_IV: Generate IV/EIV in hardware.
252 * @ENTRY_TXD_ENCRYPT_MMIC: Generate MIC in hardware.
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ID
253 * @ENTRY_TXD_HT_AMPDU: This frame is part of an AMPDU.
254 * @ENTRY_TXD_HT_BW_40: Use 40MHz Bandwidth.
255 * @ENTRY_TXD_HT_SHORT_GI: Use short GI.
84804cdc 256 * @ENTRY_TXD_HT_MIMO_PS: The receiving STA is in dynamic SM PS mode.
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257 */
258enum txentry_desc_flags {
259 ENTRY_TXD_RTS_FRAME,
7050ec82 260 ENTRY_TXD_CTS_FRAME,
5adf6d63 261 ENTRY_TXD_GENERATE_SEQ,
61486e0f 262 ENTRY_TXD_FIRST_FRAGMENT,
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263 ENTRY_TXD_MORE_FRAG,
264 ENTRY_TXD_REQ_TIMESTAMP,
265 ENTRY_TXD_BURST,
266 ENTRY_TXD_ACK,
61486e0f 267 ENTRY_TXD_RETRY_MODE,
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268 ENTRY_TXD_ENCRYPT,
269 ENTRY_TXD_ENCRYPT_PAIRWISE,
270 ENTRY_TXD_ENCRYPT_IV,
271 ENTRY_TXD_ENCRYPT_MMIC,
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272 ENTRY_TXD_HT_AMPDU,
273 ENTRY_TXD_HT_BW_40,
274 ENTRY_TXD_HT_SHORT_GI,
84804cdc 275 ENTRY_TXD_HT_MIMO_PS,
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276};
277
278/**
279 * struct txentry_desc: TX Entry descriptor
280 *
281 * Summary of information for the frame descriptor before sending a TX frame.
282 *
283 * @flags: Descriptor flags (See &enum queue_entry_flags).
df624ca5 284 * @length: Length of the entire frame.
9f166171 285 * @header_length: Length of 802.11 header.
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286 * @length_high: PLCP length high word.
287 * @length_low: PLCP length low word.
288 * @signal: PLCP signal.
289 * @service: PLCP service.
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290 * @msc: MCS.
291 * @stbc: STBC.
292 * @ba_size: BA size.
076f9582 293 * @rate_mode: Rate mode (See @enum rate_modulation).
35f00cfc 294 * @mpdu_density: MDPU density.
61486e0f 295 * @retry_limit: Max number of retries.
181d6902 296 * @ifs: IFS value.
1affa091 297 * @txop: IFS value for 11n capable chips.
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298 * @cipher: Cipher type used for encryption.
299 * @key_idx: Key index used for encryption.
300 * @iv_offset: Position where IV should be inserted by hardware.
9eb4e21e 301 * @iv_len: Length of IV data.
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302 */
303struct txentry_desc {
304 unsigned long flags;
305
df624ca5 306 u16 length;
9f166171 307 u16 header_length;
9f166171 308
26a1d07f
HS
309 union {
310 struct {
311 u16 length_high;
312 u16 length_low;
313 u16 signal;
314 u16 service;
2517794b 315 enum ifs ifs;
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HS
316 } plcp;
317
318 struct {
319 u16 mcs;
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ID
320 u8 stbc;
321 u8 ba_size;
322 u8 mpdu_density;
323 enum txop txop;
26a1d07f
HS
324 } ht;
325 } u;
181d6902 326
4df10c8c 327 enum rate_modulation rate_mode;
076f9582 328
61486e0f 329 short retry_limit;
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330
331 enum cipher cipher;
332 u16 key_idx;
333 u16 iv_offset;
9eb4e21e 334 u16 iv_len;
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335};
336
337/**
338 * enum queue_entry_flags: Status flags for queue entry
339 *
340 * @ENTRY_BCN_ASSIGNED: This entry has been assigned to an interface.
341 * As long as this bit is set, this entry may only be touched
342 * through the interface structure.
343 * @ENTRY_OWNER_DEVICE_DATA: This entry is owned by the device for data
344 * transfer (either TX or RX depending on the queue). The entry should
345 * only be touched after the device has signaled it is done with it.
f019d514
ID
346 * @ENTRY_DATA_PENDING: This entry contains a valid frame and is waiting
347 * for the signal to start sending.
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ID
348 * @ENTRY_DATA_IO_FAILED: Hardware indicated that an IO error occured
349 * while transfering the data to the hardware. No TX status report will
350 * be expected from the hardware.
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ID
351 * @ENTRY_DATA_STATUS_PENDING: The entry has been send to the device and
352 * returned. It is now waiting for the status reporting before the
353 * entry can be reused again.
181d6902 354 */
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355enum queue_entry_flags {
356 ENTRY_BCN_ASSIGNED,
357 ENTRY_OWNER_DEVICE_DATA,
f019d514 358 ENTRY_DATA_PENDING,
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ID
359 ENTRY_DATA_IO_FAILED,
360 ENTRY_DATA_STATUS_PENDING,
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361};
362
363/**
364 * struct queue_entry: Entry inside the &struct data_queue
365 *
366 * @flags: Entry flags, see &enum queue_entry_flags.
367 * @queue: The data queue (&struct data_queue) to which this entry belongs.
368 * @skb: The buffer which is currently being transmitted (for TX queue),
369 * or used to directly recieve data in (for RX queue).
370 * @entry_idx: The entry index number.
371 * @priv_data: Private data belonging to this queue entry. The pointer
372 * points to data specific to a particular driver and queue type.
373 */
374struct queue_entry {
375 unsigned long flags;
376
377 struct data_queue *queue;
378
379 struct sk_buff *skb;
380
381 unsigned int entry_idx;
382
383 void *priv_data;
384};
385
386/**
387 * enum queue_index: Queue index type
388 *
389 * @Q_INDEX: Index pointer to the current entry in the queue, if this entry is
390 * owned by the hardware then the queue is considered to be full.
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ID
391 * @Q_INDEX_DMA_DONE: Index pointer for the next entry which will have been
392 * transfered to the hardware.
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393 * @Q_INDEX_DONE: Index pointer to the next entry which will be completed by
394 * the hardware and for which we need to run the txdone handler. If this
395 * entry is not owned by the hardware the queue is considered to be empty.
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ID
396 * @Q_INDEX_MAX: Keep last, used in &struct data_queue to determine the size
397 * of the index array.
398 */
399enum queue_index {
400 Q_INDEX,
652a9dd2 401 Q_INDEX_DMA_DONE,
181d6902 402 Q_INDEX_DONE,
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ID
403 Q_INDEX_MAX,
404};
405
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ID
406/**
407 * enum data_queue_flags: Status flags for data queues
408 *
409 * @QUEUE_STARTED: The queue has been started. Fox RX queues this means the
410 * device might be DMA'ing skbuffers. TX queues will accept skbuffers to
411 * be transmitted and beacon queues will start beaconing the configured
412 * beacons.
413 * @QUEUE_PAUSED: The queue has been started but is currently paused.
414 * When this bit is set, the queue has been stopped in mac80211,
415 * preventing new frames to be enqueued. However, a few frames
416 * might still appear shortly after the pausing...
417 */
418enum data_queue_flags {
419 QUEUE_STARTED,
420 QUEUE_PAUSED,
421};
422
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423/**
424 * struct data_queue: Data queue
425 *
426 * @rt2x00dev: Pointer to main &struct rt2x00dev where this queue belongs to.
427 * @entries: Base address of the &struct queue_entry which are
428 * part of this queue.
429 * @qid: The queue identification, see &enum data_queue_qid.
0b7fde54
ID
430 * @flags: Entry flags, see &enum queue_entry_flags.
431 * @status_lock: The mutex for protecting the start/stop/flush
432 * handling on this queue.
813f0339 433 * @index_lock: Spinlock to protect index handling. Whenever @index, @index_done or
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434 * @index_crypt needs to be changed this lock should be grabbed to prevent
435 * index corruption due to concurrency.
436 * @count: Number of frames handled in the queue.
437 * @limit: Maximum number of entries in the queue.
b869767b 438 * @threshold: Minimum number of free entries before queue is kicked by force.
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439 * @length: Number of frames in queue.
440 * @index: Index pointers to entry positions in the queue,
441 * use &enum queue_index to get a specific index field.
2af0a570 442 * @txop: maximum burst time.
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443 * @aifs: The aifs value for outgoing frames (field ignored in RX queue).
444 * @cw_min: The cw min value for outgoing frames (field ignored in RX queue).
445 * @cw_max: The cw max value for outgoing frames (field ignored in RX queue).
446 * @data_size: Maximum data size for the frames in this queue.
447 * @desc_size: Hardware descriptor size for the data in this queue.
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448 * @usb_endpoint: Device endpoint used for communication (USB only)
449 * @usb_maxpacket: Max packet size for given endpoint (USB only)
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450 */
451struct data_queue {
452 struct rt2x00_dev *rt2x00dev;
453 struct queue_entry *entries;
454
455 enum data_queue_qid qid;
0b7fde54 456 unsigned long flags;
181d6902 457
0b7fde54 458 struct mutex status_lock;
813f0339 459 spinlock_t index_lock;
0b7fde54 460
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461 unsigned int count;
462 unsigned short limit;
b869767b 463 unsigned short threshold;
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464 unsigned short length;
465 unsigned short index[Q_INDEX_MAX];
652a9dd2 466 unsigned long last_action[Q_INDEX_MAX];
181d6902 467
2af0a570 468 unsigned short txop;
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469 unsigned short aifs;
470 unsigned short cw_min;
471 unsigned short cw_max;
472
473 unsigned short data_size;
474 unsigned short desc_size;
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475
476 unsigned short usb_endpoint;
477 unsigned short usb_maxpacket;
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478};
479
480/**
481 * struct data_queue_desc: Data queue description
482 *
483 * The information in this structure is used by drivers
484 * to inform rt2x00lib about the creation of the data queue.
485 *
486 * @entry_num: Maximum number of entries for a queue.
487 * @data_size: Maximum data size for the frames in this queue.
488 * @desc_size: Hardware descriptor size for the data in this queue.
489 * @priv_size: Size of per-queue_entry private data.
490 */
491struct data_queue_desc {
492 unsigned short entry_num;
493 unsigned short data_size;
494 unsigned short desc_size;
495 unsigned short priv_size;
496};
497
498/**
499 * queue_end - Return pointer to the last queue (HELPER MACRO).
500 * @__dev: Pointer to &struct rt2x00_dev
501 *
502 * Using the base rx pointer and the maximum number of available queues,
503 * this macro will return the address of 1 position beyond the end of the
504 * queues array.
505 */
506#define queue_end(__dev) \
507 &(__dev)->rx[(__dev)->data_queues]
508
509/**
510 * tx_queue_end - Return pointer to the last TX queue (HELPER MACRO).
511 * @__dev: Pointer to &struct rt2x00_dev
512 *
513 * Using the base tx pointer and the maximum number of available TX
514 * queues, this macro will return the address of 1 position beyond
515 * the end of the TX queue array.
516 */
517#define tx_queue_end(__dev) \
61448f88 518 &(__dev)->tx[(__dev)->ops->tx_queues]
181d6902 519
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ID
520/**
521 * queue_next - Return pointer to next queue in list (HELPER MACRO).
522 * @__queue: Current queue for which we need the next queue
523 *
524 * Using the current queue address we take the address directly
525 * after the queue to take the next queue. Note that this macro
526 * should be used carefully since it does not protect against
527 * moving past the end of the list. (See macros &queue_end and
528 * &tx_queue_end for determining the end of the queue).
529 */
530#define queue_next(__queue) \
531 &(__queue)[1]
532
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533/**
534 * queue_loop - Loop through the queues within a specific range (HELPER MACRO).
535 * @__entry: Pointer where the current queue entry will be stored in.
536 * @__start: Start queue pointer.
537 * @__end: End queue pointer.
538 *
539 * This macro will loop through all queues between &__start and &__end.
540 */
541#define queue_loop(__entry, __start, __end) \
542 for ((__entry) = (__start); \
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ID
543 prefetch(queue_next(__entry)), (__entry) != (__end);\
544 (__entry) = queue_next(__entry))
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ID
545
546/**
547 * queue_for_each - Loop through all queues
548 * @__dev: Pointer to &struct rt2x00_dev
549 * @__entry: Pointer where the current queue entry will be stored in.
550 *
551 * This macro will loop through all available queues.
552 */
553#define queue_for_each(__dev, __entry) \
554 queue_loop(__entry, (__dev)->rx, queue_end(__dev))
555
556/**
557 * tx_queue_for_each - Loop through the TX queues
558 * @__dev: Pointer to &struct rt2x00_dev
559 * @__entry: Pointer where the current queue entry will be stored in.
560 *
561 * This macro will loop through all TX related queues excluding
562 * the Beacon and Atim queues.
563 */
564#define tx_queue_for_each(__dev, __entry) \
565 queue_loop(__entry, (__dev)->tx, tx_queue_end(__dev))
566
567/**
568 * txall_queue_for_each - Loop through all TX related queues
569 * @__dev: Pointer to &struct rt2x00_dev
570 * @__entry: Pointer where the current queue entry will be stored in.
571 *
572 * This macro will loop through all TX related queues including
573 * the Beacon and Atim queues.
574 */
575#define txall_queue_for_each(__dev, __entry) \
576 queue_loop(__entry, (__dev)->tx, queue_end(__dev))
577
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578/**
579 * rt2x00queue_for_each_entry - Loop through all entries in the queue
580 * @queue: Pointer to @data_queue
581 * @start: &enum queue_index Pointer to start index
582 * @end: &enum queue_index Pointer to end index
10e11568 583 * @data: Data to pass to the callback function
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584 * @fn: The function to call for each &struct queue_entry
585 *
586 * This will walk through all entries in the queue, in chronological
587 * order. This means it will start at the current @start pointer
588 * and will walk through the queue until it reaches the @end pointer.
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589 *
590 * If fn returns true for an entry rt2x00queue_for_each_entry will stop
591 * processing and return true as well.
5eb7efe8 592 */
10e11568 593bool rt2x00queue_for_each_entry(struct data_queue *queue,
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594 enum queue_index start,
595 enum queue_index end,
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596 void *data,
597 bool (*fn)(struct queue_entry *entry,
598 void *data));
5eb7efe8 599
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600/**
601 * rt2x00queue_empty - Check if the queue is empty.
602 * @queue: Queue to check if empty.
603 */
604static inline int rt2x00queue_empty(struct data_queue *queue)
605{
606 return queue->length == 0;
607}
608
609/**
610 * rt2x00queue_full - Check if the queue is full.
611 * @queue: Queue to check if full.
612 */
613static inline int rt2x00queue_full(struct data_queue *queue)
614{
615 return queue->length == queue->limit;
616}
617
618/**
619 * rt2x00queue_free - Check the number of available entries in queue.
620 * @queue: Queue to check.
621 */
622static inline int rt2x00queue_available(struct data_queue *queue)
623{
624 return queue->limit - queue->length;
625}
626
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627/**
628 * rt2x00queue_threshold - Check if the queue is below threshold
629 * @queue: Queue to check.
630 */
631static inline int rt2x00queue_threshold(struct data_queue *queue)
632{
633 return rt2x00queue_available(queue) < queue->threshold;
634}
635
c965c74b 636/**
7225ce1e 637 * rt2x00queue_status_timeout - Check if a timeout occured for STATUS reports
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638 * @queue: Queue to check.
639 */
7225ce1e 640static inline int rt2x00queue_status_timeout(struct data_queue *queue)
c965c74b 641{
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642 return time_after(queue->last_action[Q_INDEX_DMA_DONE],
643 queue->last_action[Q_INDEX_DONE] + (HZ / 10));
644}
645
646/**
647 * rt2x00queue_timeout - Check if a timeout occured for DMA transfers
648 * @queue: Queue to check.
649 */
650static inline int rt2x00queue_dma_timeout(struct data_queue *queue)
651{
652 return time_after(queue->last_action[Q_INDEX],
653 queue->last_action[Q_INDEX_DMA_DONE] + (HZ / 10));
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654}
655
181d6902 656/**
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657 * _rt2x00_desc_read - Read a word from the hardware descriptor.
658 * @desc: Base descriptor address
659 * @word: Word index from where the descriptor should be read.
660 * @value: Address where the descriptor value should be written into.
661 */
662static inline void _rt2x00_desc_read(__le32 *desc, const u8 word, __le32 *value)
663{
664 *value = desc[word];
665}
666
667/**
668 * rt2x00_desc_read - Read a word from the hardware descriptor, this
669 * function will take care of the byte ordering.
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670 * @desc: Base descriptor address
671 * @word: Word index from where the descriptor should be read.
672 * @value: Address where the descriptor value should be written into.
673 */
674static inline void rt2x00_desc_read(__le32 *desc, const u8 word, u32 *value)
675{
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676 __le32 tmp;
677 _rt2x00_desc_read(desc, word, &tmp);
678 *value = le32_to_cpu(tmp);
679}
680
681/**
682 * rt2x00_desc_write - write a word to the hardware descriptor, this
683 * function will take care of the byte ordering.
684 * @desc: Base descriptor address
685 * @word: Word index from where the descriptor should be written.
686 * @value: Value that should be written into the descriptor.
687 */
688static inline void _rt2x00_desc_write(__le32 *desc, const u8 word, __le32 value)
689{
690 desc[word] = value;
181d6902
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691}
692
693/**
2bb057d0 694 * rt2x00_desc_write - write a word to the hardware descriptor.
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695 * @desc: Base descriptor address
696 * @word: Word index from where the descriptor should be written.
697 * @value: Value that should be written into the descriptor.
698 */
699static inline void rt2x00_desc_write(__le32 *desc, const u8 word, u32 value)
700{
2bb057d0 701 _rt2x00_desc_write(desc, word, cpu_to_le32(value));
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702}
703
704#endif /* RT2X00QUEUE_H */
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