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95ea3627 | 1 | /* |
9c9a0d14 | 2 | Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com> |
95ea3627 ID |
3 | <http://rt2x00.serialmonkey.com> |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the | |
17 | Free Software Foundation, Inc., | |
18 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | */ | |
20 | ||
21 | /* | |
22 | Module: rt2x00 | |
23 | Abstract: rt2x00 generic register information. | |
24 | */ | |
25 | ||
26 | #ifndef RT2X00REG_H | |
27 | #define RT2X00REG_H | |
28 | ||
2bb057d0 ID |
29 | /* |
30 | * RX crypto status | |
31 | */ | |
32 | enum rx_crypto { | |
33 | RX_CRYPTO_SUCCESS = 0, | |
34 | RX_CRYPTO_FAIL_ICV = 1, | |
35 | RX_CRYPTO_FAIL_MIC = 2, | |
36 | RX_CRYPTO_FAIL_KEY = 3, | |
37 | }; | |
38 | ||
95ea3627 ID |
39 | /* |
40 | * Antenna values | |
41 | */ | |
42 | enum antenna { | |
43 | ANTENNA_SW_DIVERSITY = 0, | |
44 | ANTENNA_A = 1, | |
45 | ANTENNA_B = 2, | |
46 | ANTENNA_HW_DIVERSITY = 3, | |
47 | }; | |
48 | ||
49 | /* | |
50 | * Led mode values. | |
51 | */ | |
52 | enum led_mode { | |
53 | LED_MODE_DEFAULT = 0, | |
54 | LED_MODE_TXRX_ACTIVITY = 1, | |
55 | LED_MODE_SIGNAL_STRENGTH = 2, | |
56 | LED_MODE_ASUS = 3, | |
57 | LED_MODE_ALPHA = 4, | |
58 | }; | |
59 | ||
feb24691 ID |
60 | /* |
61 | * TSF sync values | |
62 | */ | |
63 | enum tsf_sync { | |
64 | TSF_SYNC_NONE = 0, | |
65 | TSF_SYNC_INFRA = 1, | |
ab8966dd HS |
66 | TSF_SYNC_ADHOC = 2, |
67 | TSF_SYNC_AP_NONE = 3, | |
feb24691 ID |
68 | }; |
69 | ||
95ea3627 ID |
70 | /* |
71 | * Device states | |
72 | */ | |
73 | enum dev_state { | |
74 | STATE_DEEP_SLEEP = 0, | |
75 | STATE_SLEEP = 1, | |
76 | STATE_STANDBY = 2, | |
77 | STATE_AWAKE = 3, | |
78 | ||
79 | /* | |
80 | * Additional device states, these values are | |
81 | * not strict since they are not directly passed | |
82 | * into the device. | |
83 | */ | |
84 | STATE_RADIO_ON, | |
85 | STATE_RADIO_OFF, | |
95ea3627 ID |
86 | STATE_RADIO_IRQ_ON, |
87 | STATE_RADIO_IRQ_OFF, | |
88 | }; | |
89 | ||
90 | /* | |
91 | * IFS backoff values | |
92 | */ | |
93 | enum ifs { | |
94 | IFS_BACKOFF = 0, | |
95 | IFS_SIFS = 1, | |
96 | IFS_NEW_BACKOFF = 2, | |
97 | IFS_NONE = 3, | |
98 | }; | |
99 | ||
1affa091 HS |
100 | /* |
101 | * IFS backoff values for HT devices | |
102 | */ | |
103 | enum txop { | |
104 | TXOP_HTTXOP = 0, | |
105 | TXOP_PIFS = 1, | |
106 | TXOP_SIFS = 2, | |
107 | TXOP_BACKOFF = 3, | |
108 | }; | |
109 | ||
95ea3627 ID |
110 | /* |
111 | * Cipher types for hardware encryption | |
112 | */ | |
113 | enum cipher { | |
114 | CIPHER_NONE = 0, | |
115 | CIPHER_WEP64 = 1, | |
116 | CIPHER_WEP128 = 2, | |
117 | CIPHER_TKIP = 3, | |
118 | CIPHER_AES = 4, | |
119 | /* | |
120 | * The following fields were added by rt61pci and rt73usb. | |
121 | */ | |
122 | CIPHER_CKIP64 = 5, | |
123 | CIPHER_CKIP128 = 6, | |
2bb057d0 ID |
124 | CIPHER_TKIP_NO_MIC = 7, /* Don't send to device */ |
125 | ||
126 | /* | |
127 | * Max cipher type. | |
128 | * Note that CIPHER_NONE isn't counted, and CKIP64 and CKIP128 | |
129 | * are excluded due to limitations in mac80211. | |
130 | */ | |
131 | CIPHER_MAX = 4, | |
95ea3627 ID |
132 | }; |
133 | ||
076f9582 ID |
134 | /* |
135 | * Rate modulations | |
136 | */ | |
137 | enum rate_modulation { | |
138 | RATE_MODE_CCK = 0, | |
139 | RATE_MODE_OFDM = 1, | |
140 | RATE_MODE_HT_MIX = 2, | |
141 | RATE_MODE_HT_GREENFIELD = 3, | |
142 | }; | |
143 | ||
0cbe0064 ID |
144 | /* |
145 | * Firmware validation error codes | |
146 | */ | |
147 | enum firmware_errors { | |
148 | FW_OK, | |
149 | FW_BAD_CRC, | |
150 | FW_BAD_LENGTH, | |
151 | FW_BAD_VERSION, | |
152 | }; | |
153 | ||
95ea3627 ID |
154 | /* |
155 | * Register handlers. | |
156 | * We store the position of a register field inside a field structure, | |
157 | * This will simplify the process of setting and reading a certain field | |
158 | * inside the register while making sure the process remains byte order safe. | |
159 | */ | |
160 | struct rt2x00_field8 { | |
161 | u8 bit_offset; | |
162 | u8 bit_mask; | |
163 | }; | |
164 | ||
165 | struct rt2x00_field16 { | |
166 | u16 bit_offset; | |
167 | u16 bit_mask; | |
168 | }; | |
169 | ||
170 | struct rt2x00_field32 { | |
171 | u32 bit_offset; | |
172 | u32 bit_mask; | |
173 | }; | |
174 | ||
175 | /* | |
176 | * Power of two check, this will check | |
9dad92b9 ID |
177 | * if the mask that has been given contains and contiguous set of bits. |
178 | * Note that we cannot use the is_power_of_2() function since this | |
179 | * check must be done at compile-time. | |
95ea3627 ID |
180 | */ |
181 | #define is_power_of_two(x) ( !((x) & ((x)-1)) ) | |
182 | #define low_bit_mask(x) ( ((x)-1) & ~(x) ) | |
445df54f | 183 | #define is_valid_mask(x) is_power_of_two(1LU + (x) + low_bit_mask(x)) |
95ea3627 | 184 | |
9dad92b9 | 185 | /* |
49513481 LC |
186 | * Macros to find first set bit in a variable. |
187 | * These macros behave the same as the __ffs() functions but | |
9dad92b9 ID |
188 | * the most important difference that this is done during |
189 | * compile-time rather then run-time. | |
190 | */ | |
191 | #define compile_ffs2(__x) \ | |
4ae11681 | 192 | __builtin_choose_expr(((__x) & 0x1), 0, 1) |
9dad92b9 ID |
193 | |
194 | #define compile_ffs4(__x) \ | |
4ae11681 ID |
195 | __builtin_choose_expr(((__x) & 0x3), \ |
196 | (compile_ffs2((__x))), \ | |
197 | (compile_ffs2((__x) >> 2) + 2)) | |
9dad92b9 ID |
198 | |
199 | #define compile_ffs8(__x) \ | |
4ae11681 ID |
200 | __builtin_choose_expr(((__x) & 0xf), \ |
201 | (compile_ffs4((__x))), \ | |
202 | (compile_ffs4((__x) >> 4) + 4)) | |
9dad92b9 ID |
203 | |
204 | #define compile_ffs16(__x) \ | |
4ae11681 ID |
205 | __builtin_choose_expr(((__x) & 0xff), \ |
206 | (compile_ffs8((__x))), \ | |
207 | (compile_ffs8((__x) >> 8) + 8)) | |
9dad92b9 ID |
208 | |
209 | #define compile_ffs32(__x) \ | |
4ae11681 ID |
210 | __builtin_choose_expr(((__x) & 0xffff), \ |
211 | (compile_ffs16((__x))), \ | |
212 | (compile_ffs16((__x) >> 16) + 16)) | |
9dad92b9 ID |
213 | |
214 | /* | |
215 | * This macro will check the requirements for the FIELD{8,16,32} macros | |
216 | * The mask should be a constant non-zero contiguous set of bits which | |
217 | * does not exceed the given typelimit. | |
218 | */ | |
219 | #define FIELD_CHECK(__mask, __type) \ | |
445df54f | 220 | BUILD_BUG_ON(!(__mask) || \ |
9dad92b9 ID |
221 | !is_valid_mask(__mask) || \ |
222 | (__mask) != (__type)(__mask)) \ | |
223 | ||
95ea3627 ID |
224 | #define FIELD8(__mask) \ |
225 | ({ \ | |
9dad92b9 | 226 | FIELD_CHECK(__mask, u8); \ |
95ea3627 | 227 | (struct rt2x00_field8) { \ |
9dad92b9 | 228 | compile_ffs8(__mask), (__mask) \ |
95ea3627 ID |
229 | }; \ |
230 | }) | |
231 | ||
232 | #define FIELD16(__mask) \ | |
233 | ({ \ | |
9dad92b9 | 234 | FIELD_CHECK(__mask, u16); \ |
95ea3627 | 235 | (struct rt2x00_field16) { \ |
9dad92b9 | 236 | compile_ffs16(__mask), (__mask) \ |
95ea3627 ID |
237 | }; \ |
238 | }) | |
239 | ||
240 | #define FIELD32(__mask) \ | |
241 | ({ \ | |
9dad92b9 | 242 | FIELD_CHECK(__mask, u32); \ |
95ea3627 | 243 | (struct rt2x00_field32) { \ |
9dad92b9 | 244 | compile_ffs32(__mask), (__mask) \ |
95ea3627 ID |
245 | }; \ |
246 | }) | |
247 | ||
c483bb4c ID |
248 | #define SET_FIELD(__reg, __type, __field, __value)\ |
249 | ({ \ | |
250 | typecheck(__type, __field); \ | |
251 | *(__reg) &= ~((__field).bit_mask); \ | |
252 | *(__reg) |= ((__value) << \ | |
253 | ((__field).bit_offset)) & \ | |
254 | ((__field).bit_mask); \ | |
255 | }) | |
256 | ||
257 | #define GET_FIELD(__reg, __type, __field) \ | |
258 | ({ \ | |
259 | typecheck(__type, __field); \ | |
260 | ((__reg) & ((__field).bit_mask)) >> \ | |
261 | ((__field).bit_offset); \ | |
262 | }) | |
263 | ||
264 | #define rt2x00_set_field32(__reg, __field, __value) \ | |
265 | SET_FIELD(__reg, struct rt2x00_field32, __field, __value) | |
266 | #define rt2x00_get_field32(__reg, __field) \ | |
267 | GET_FIELD(__reg, struct rt2x00_field32, __field) | |
268 | ||
269 | #define rt2x00_set_field16(__reg, __field, __value) \ | |
270 | SET_FIELD(__reg, struct rt2x00_field16, __field, __value) | |
271 | #define rt2x00_get_field16(__reg, __field) \ | |
272 | GET_FIELD(__reg, struct rt2x00_field16, __field) | |
273 | ||
274 | #define rt2x00_set_field8(__reg, __field, __value) \ | |
275 | SET_FIELD(__reg, struct rt2x00_field8, __field, __value) | |
276 | #define rt2x00_get_field8(__reg, __field) \ | |
277 | GET_FIELD(__reg, struct rt2x00_field8, __field) | |
95ea3627 | 278 | |
95ea3627 | 279 | #endif /* RT2X00REG_H */ |